Display device

Abstract

The invention discloses a display device which comprises a substrate, a plurality of first wafer connecting line structures, a plurality of light-emitting elements, a first insulating layer, a failure microchip, a plurality of second wafer connecting line structures and a repair microchip. The first wafer connecting line structure is located on the substrate and extends outwards from the wafer placing area. The first insulating layer is located on the substrate and transversely surrounds the failed microchip, and the failed microchip is at least partially connected to the first chip connecting line structure. The second wafer connection line structure is located on the first insulating layer, and at least part of the second wafer connection line structure is electrically connected to the first wafer connection line structure. The repair microchip is located on the first insulating layer. The repair microchip at least partially overlaps the failed microchip. The repair microchip is electrically connected to the light-emitting element through the second chip connecting line.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a display device comprising a repair microchip. Background Art

[0002] Micro light emitting diode (μLED) display panels are display technologies composed of tens of thousands of micro light emitting diodes. These micro light emitting diodes serve as the light source for each pixel and have higher brightness, lower power consumption and longer life than traditional organic light emitting diode display panels or liquid crystal display panels.

[0003] In micro-LED display panels, the driving method of micro-LEDs is a key challenge, because each micro-LED requires precise signal control. Using microchip technology, micro-control chips can be set in the display area of ​​the display panel. These microchips directly provide signals to the micro-LEDs to drive and control the pixels. This technology greatly improves the accuracy and efficiency of signal transmission, while reducing the layout complexity of the driving circuit, which is conducive to the realization of miniaturization and high-resolution display panels. Summary of the invention

[0004] The invention provides a display device which can repair a failed microchip.

[0005] At least one embodiment of the present invention provides a display device, which includes a substrate, a plurality of first chip connection line structures, a plurality of light-emitting elements, a first insulating layer, a failed microchip, a plurality of second chip connection line structures, and a repair microchip. The first chip connection line structure is located on the substrate and extends outward from the chip placement area. The light-emitting elements are respectively arranged in the pixel area. The first insulating layer is located on the substrate. The failed microchip is located in the chip placement area. The first insulating layer laterally surrounds the failed microchip, and the failed microchip is at least partially connected to the first chip connection line structure. The second chip connection line structure is located on the first insulating layer and is at least partially electrically connected to the first chip connection line structure. The repair microchip is located on the first insulating layer. The repair microchip is located in the chip placement area and at least partially overlaps the failed microchip. The repair microchip is electrically connected to the light-emitting element through the second chip connection line. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A , 2A , 3A, 4A, 5A and 6A are top views of various stages of manufacturing a display device according to an embodiment of the present invention.

[0007] Figure 1B , 2B, 3B, 4B, 5B and 6B respectively Figure 1A , 2A , schematic cross-sectional views of lines AA' and BB' of 3A, 4A, 5A and 6A.

[0008] Fig. 7A , 8A 9A is a top view schematically showing various stages of manufacturing a display device according to an embodiment of the present invention.

[0009] Figure 7B , 8B and 9B are Fig. 7A , 8A And the cross-sectional schematic diagrams along the line AA' and the line BB' of 9A.

[0010] Fig. 10A , 11A 12A, 13A, 14A and 15A are top views of various stages of manufacturing a display device according to an embodiment of the present invention.

[0011] Fig. 10B , 11B , 12B, 13B, 14B and 15B are Fig. 10A , 11A , schematic cross-sectional views of lines AA' and BB' of 12A, 13A, 14A and 15A.

[0012] Fig.16 It is a cross-sectional schematic diagram of a manufacturing display device according to an embodiment of the present invention.

[0013] Wherein, the reference numerals are:

[0014] 10A, 10B, 10C, 10D: Display device

[0015] 100:Substrate

[0016] 102: Buffer layer

[0017] 104,202: Adhesive layer

[0018] 110A, 110B: First microchip

[0019] 113: First chip pad

[0020] 115,215,S: Connection structure

[0021] 120A, 120D: First chip connection line structure

[0022] 120A-1, 120D-1: Part 1

[0023] 120A-2, 120D-2: Part 2

[0024] 120B,120E: Signal input structure

[0025] 122A, 122D: first chip bonding pad

[0026] 122B, 122E: Second chip bonding pad

[0027] 123A, 123D: First connection line

[0028] 123B, 123E: Signal input line

[0029] 124A, 124D: First connection pad

[0030] 124B, 124E: Second connection pad

[0031] 125B,125E:Connecting wire

[0032] 130A, 130C, 130D: Second chip connection line structure

[0033] 130B,130E: Bridge structure

[0034] 132A, 132C: First repair pad

[0035] 132B, 132E: Second repair pad

[0036] 133A, 133C: Second connection line

[0037] 133B, 133E: Third connection line

[0038] 134A, 134C: first conductive filling portion

[0039] 134B, 134E: second conductive filling portion

[0040] 135A,176:Signal output line

[0041] 138C: Third connection pad

[0042] 139C:Signal transmission line

[0043] 140: first insulating layer

[0044] 152, 182: First light emitting diode bonding pad

[0045] 154,184: Second light emitting diode bonding pad

[0046] 160: Second insulation layer

[0047] 170:Signal output line

[0048] 174: third conductive filling portion

[0049] 210: Repair microchip

[0050] 213: Second chip pad

[0051] 310,320,330: Light emitting element

[0052] CA: Chip placement area

[0053] E: Electrode

[0054] H1,H2,X1,X2: Depth

[0055] O1: First opening

[0056] O2: Second opening

[0057] O3: The third opening

[0058] PA: Pixel Area

[0059] V1, V2: Open

[0060] W1,W2,Y1,Y2: Width DETAILED DESCRIPTION

[0061] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention.

[0062] Figure 1A , 2A , 3A, 4A, 5A and 6A are top views of various stages of manufacturing a display device 10A according to an embodiment of the present invention. Figure 1B , 2B , 3B, 4B, 5B and 6B respectively Figure 1A , 2A , 3A, 4A, 5A and 6A along the lines AA' and BB'. Figure 1A as well as Figure 1B, providing a substrate 100. In some embodiments, the substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, an organic polymer, or an opaque / reflective material (e.g., a conductive material, a metal, a wafer, a ceramic, or other applicable materials) or other applicable materials. However, the present invention is not limited thereto, and in other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane PU) or other suitable materials. In some embodiments, the substrate 100 is a transparent substrate, which is suitable for a transparent display device.

[0063] The substrate 100 includes a plurality of chip placement areas CA and a plurality of pixel areas PA. The chip placement area CA is an area for setting microchips in subsequent processes. The pixel area PA is an area for setting light-emitting elements in subsequent processes. The pixel areas PA are respectively located around the corresponding chip placement areas CA. In some embodiments, the chip placement areas CA and the pixel areas PA are both arranged in the display area of ​​the display device. By arranging the chip placement areas CA in the display area, it is helpful to reduce the frame size of the display device.

[0064] A plurality of first chip connection line structures 120A and a plurality of signal input structures 120B are located on the substrate 100. In the present embodiment, the buffer layer 102 is located between the first chip connection line structure 120A and the substrate 100 and between the signal input structure 120B and the substrate 100. In some embodiments, other insulating layers and / or conductive layers are also included between the buffer layer 102 and the substrate 100. The first chip connection line structure 120A and the signal input structure 120B extend outward from the chip placement area CA. In some embodiments, the signal input structure 120B extends outward from the chip placement area CA to the signal source area (not shown). In some embodiments, the signal source area is disposed in the border area of ​​the display device, but the present invention is not limited thereto.

[0065] In some embodiments, the first chip connection line structure 120A includes a first chip bonding pad 122A, a first connection line 123A, and a first connection pad 124A. The first chip bonding pad 122A is disposed in the chip placement area CA. In some embodiments, the first connection pad 124A is located outside the chip placement area CA, and the first connection line 123A extends outward from the chip placement area CA to connect the first chip bonding pad 122A to the first connection pad 124A.

[0066] In some embodiments, part of the first chip connection line structure 120A extends from one side of the chip placement area CA (eg, Figure 1A The first chip connection line structure 120A extends outward from the chip placement area CA, and another portion of the first chip connection line structure 120A extends from the other side of the chip placement area CA (eg Figure 1A The lower side of the wafer extends outwardly to form a chip placement area CA.

[0067] The signal input structure 120B includes a second chip bonding pad 122B, a signal input line 123B, a second connection pad 124B, and a connection line 125B connecting the second chip bonding pad 122B and the second connection pad 124B. The second chip bonding pad 122B is disposed in the chip placement area CA, and is electrically connected to the signal input line 123B through the connection line 125B and the second connection pad 124B. In some embodiments, the second connection pad 124B is located outside the chip placement area CA, and the signal input line 123B extends outward from the chip placement area CA to connect the second chip bonding pad 122B to the second connection pad 124B.

[0068] Please refer to Figure 2A and Figure 2B , the first microchips 110A and 110B are respectively arranged in the chip placement area CA with the active surface facing downward. In some embodiments, the first microchips 110A and 110B include a driving circuit. The first microchips 110A and 110B each include a plurality of first chip pads 113. In some embodiments, the first chip pads 113 are located on a side of the first microchips 110A and 110B close to the substrate 100. In some embodiments, the first chip pads 113 include a metal bump structure. For example, the first chip pads 113 include gold, copper, tin, silver, lead, indium or other metal materials or a combination of the above materials. The first chip pads 113 are arranged on the active surface of the first microchips 110A and 110B.

[0069] The first microchips 110A and 110B are respectively bonded to the corresponding first chip connection line structure 120A and the signal input structure 120B through the connection structure 115. Specifically, the first chip pads 113 of each of the first microchips 110A and 110B are bonded to the first chip bonding pad 122A of the corresponding first chip connection line structure 120A and the second chip bonding pad 122B of the corresponding signal input structure 120B through the connection structure 115. The connection structure 115 includes, for example, solder (such as indium, tin or other suitable metal materials or a combination of the above materials), conductive glue or other conductive connection materials. In some embodiments, the signal input structure 120B is configured to provide input signals to the first microchips 110A and 110B.

[0070] The first connection pads 124A of the first chip connection wire structure 120A and the second connection pads 124B of the signal input structure 120B do not overlap the first microchips 110A and 110B in the normal direction of the top surface of the substrate 100 .

[0071] Please refer to Figure 3A as well as Figure 3B , the first microchip 110A, 110B is tested to confirm whether the first microchip 110A, 110B can operate normally. In this embodiment, the first microchip 110A cannot operate normally, while the first microchip 110B can operate normally. For example, the first microchip 110A is offset when placed on the substrate 100, or has internal defects, resulting in the first microchip 110A being unable to output and / or receive the expected signal. The first microchip 110A can also be called a failed microchip. In this embodiment, the failed microchip (i.e., the first microchip 110A) is located in the chip placement area CA. The failed microchip is at least partially connected to the first chip connection line structure 120A and the signal input structure 120B. In some embodiments, because the failed microchip is offset when placed, part of the first chip pads 113 of the failed microchip are not bonded to the first chip connection line structure 120A and the signal input structure 120B.

[0072] In some embodiments, after confirming that the first microchip 110A is a failed microchip, the first chip connection line structure 120A corresponding to the first microchip 110A is cut through a cutting process (such as laser cutting or other suitable cutting methods) to cut the first connection line 123A between the first chip bonding pad 122A and the first connection pad 124A. This ensures that the first microchip 110A cannot output signals to the light-emitting element that will be subsequently transferred to the substrate 100 through the first chip connection line structure 120A. On the other hand, the connection line 125B corresponding to the first microchip 110A can also be cut to ensure that the signal input line 123B does not transmit signals to the first microchip 110A.

[0073] In some embodiments, at least one of the first chip connection wire structures 120A is cut to have a first portion 120A-1 (e.g., including a first chip bonding pad 122A and a portion of a first connection wire 123A connected to the first chip bonding pad 122A) and a second portion 120A-2 (e.g., including a first connection pad 124A and a portion of a first connection wire 123A connected to the first connection pad 124A) separated from each other. In some embodiments, the failed microchip (i.e., the first microchip 110A) is electrically connected to the first portion 120A-1.

[0074] Please refer to Figure 4A as well as Figure 4B , a first insulating layer 140 is formed on the substrate 100. The first insulating layer 140 is located on the first chip connection line structure 120A and the signal input structure 120B, and the first chip connection line structure 120A and the signal input structure 120B are located between the first insulating layer 140 and the substrate 100. The first insulating layer 140 laterally surrounds the first microchips 110A and 110B.

[0075] In some embodiments, the material of the first insulating layer 140 includes photoresist (eg, positive photoresist or negative photoresist), polyimide (eg, PI ), acrylic material or other insulating materials. In some embodiments, the thickness of the first insulating layer 140 is 5 micrometers to 25 micrometers.

[0076] The first insulating layer 140 has a plurality of first openings O1 and a plurality of second openings O2. The first openings O1 expose the first connection pads 124A at the bottom thereof, and the second openings O2 expose the second connection pads 124B at the bottom thereof. In some embodiments, the depth H1 of the first openings O1 and the second openings O2 is 5 micrometers to 25 micrometers, and the width W1 is 5 micrometers to 35 micrometers.

[0077] Please refer to Figure 5A as well as Figure 5B , forming a plurality of second chip connection wire structures 130A, a plurality of bridge structures 130B, a plurality of first LED bonding pads 152, and a plurality of second LED bonding pads 154 on the first insulating layer 140. The second chip connection wire structures 130A are at least partially electrically connected to the first chip connection wire structures 120A. For example, the second chip connection wire structures 130A are respectively filled into the first openings O1 of the first insulating layer 140 to connect to the corresponding first chip connection wire structures 120A. The bridge structures 130B are respectively filled into the second openings O2 of the first insulating layer 140 to connect to the signal input structures 120B.

[0078] In some embodiments, the second chip connection line structure 130A includes a first repair pad 132A, a second connection line 133A, a first conductive filling portion 134A, and a signal output line 135A. The first repair pad 132A is disposed in the chip placement area CA. In some embodiments, the first conductive filling portion 134A is located outside the chip placement area CA, and is filled into the first opening O1 of the first insulating layer 140, and is connected to the corresponding first connection pad 124A through the first opening O1. The second connection line 133A extends outward from the chip placement area CA to connect the first repair pad 132A to the first conductive filling portion 134A. The signal output line 135A extends into the pixel area PA and is connected to the first light-emitting diode bonding pad 152 in the pixel area PA. In some embodiments, each pixel area PA also includes one or more second light-emitting diode bonding pads 154. In some embodiments, a plurality of second light-emitting diode bonding pads 154 are connected to each other and electrically connected to a common voltage.

[0079] In some embodiments, the bridge structure 130B includes a second repair pad 132B, a third connection line 133B, and a second conductive filling portion 134B. The second repair pad 132B is disposed in the wafer placement area CA. In some embodiments, the second conductive filling portion 134B is located outside the wafer placement area CA and is filled into the second opening O2 of the first insulating layer 140, and is connected to the corresponding second connection pad 124B through the second opening O2. The third connection line 133B extends outward from the wafer placement area CA to connect the second repair pad 132B to the second conductive filling portion 134B.

[0080] Please refer to Fig. 6A and Figure 6B, the repair microchip 210 is arranged in the chip placement area CA corresponding to the failed microchip. In the present embodiment, the repair microchip 210 is located in the chip placement area CA and at least partially overlaps the failed microchip (i.e., the first microchip 110A). The repair microchip 210 is not arranged in the chip placement area CA corresponding to the first microchip 110B that can function normally. In the present embodiment, the repair microchip 210 is arranged in the chip placement area CA in an active face-down manner. The repair microchip 210 includes a plurality of second chip pads 213. In some embodiments, the second chip pads 213 are located on a side of the repair microchip 210 close to the substrate 100. In some embodiments, the repair microchip 210 has the same structural design as the first microchips 110A and 110B, so it is not necessary to redesign the microchip for the repair process. For example, the relative positions of the second chip pads 213 on the repair microchip 210 are equal to the relative positions of the first chip pads 113 on the first microchips 110A and 110B. In some embodiments, the second chip pad 213 includes a metal bump structure. For example, the second chip pad 213 includes gold, copper, tin, silver, lead, indium or other metal materials or a combination of the above materials.

[0081] The repair microchip 210 is located on the first insulating layer 140 and is bonded to the corresponding second chip connection line 130A and the bridge structure 130B through the connection structure 215. Specifically, the second chip pad 213 of the repair microchip 210 is bonded to the first repair pad 132A of the corresponding second chip connection line 130A and the second repair pad 132B of the corresponding bridge structure 130B through the connection structure 215. The connection structure 215, for example, includes solder (such as indium, tin or other suitable metal materials or a combination of the above materials), conductive glue or other conductive connection materials. The repair microchip 210 is electrically connected to the signal input structure 120B through the bridge structure 130B corresponding to the failed microchip. For example, the second chip connection line structure 130A is configured to provide a data signal from the microchip to the light-emitting elements 310, 320, 330, and the signal input structure 120B is configured to provide an input signal to the microchip.

[0082] In some embodiments, after the repair microchip 210 is bonded to the corresponding second chip connection wires 130A and the bridge structures 130B and before the light emitting elements 310 , 320 , 330 are disposed in the pixel area PA, the repair microchip 210 is tested to confirm whether the repair microchip 210 can operate normally.

[0083] The light-emitting elements 310, 320, 330 are respectively disposed in the pixel area PA. The light-emitting elements 310, 320, 330 are located above the first insulating layer 140, and the electrodes E of the light-emitting elements 310, 320, 330 are bonded to the first LED bonding pad 152 and the second LED bonding pad 154 through the connection structure S. The connection structure S includes, for example, solder (such as indium, tin or other suitable metal materials or a combination of the above materials), conductive glue or other conductive connection materials. In some embodiments, the light-emitting elements 310, 320, 330 include micro light-emitting diodes. For example, the light-emitting elements 310, 320, 330 are respectively red micro light-emitting diodes, green micro light-emitting diodes, and blue micro light-emitting diodes.

[0084] In some embodiments, the connection structure 215,S is first formed on the substrate 100 by evaporation or other suitable methods, and then the repair microchip 210 and the light-emitting elements 310, 320, 330 are bonded to the connection structure 215,S, but the present invention is not limited thereto. In other embodiments, the connection structure 215,S is formed on the repair microchip 210 and the light-emitting elements 310, 320, 330, respectively, and then the repair microchip 210 and the light-emitting elements 310, 320, 330 are disposed on the substrate 100.

[0085] The repair microchip 210 is electrically connected to the light emitting elements 310, 320, 330 via the second chip connection wire structure 130A corresponding to the failed microchip (i.e., the first microchip 110A). The repair microchip 210 outputs data signals to the corresponding light emitting elements 310, 320, 330 via the corresponding second chip connection wire 130A. In some embodiments, the repair microchip 210 is electrically connected to a portion (e.g., the second portion 120A-2) of the first chip connection wire structure 120A via the second chip connection wire 130A. In this embodiment, at least one of the second chip connection wire structures 130A corresponding to the first microchip 110A (i.e., the failed microchip) is electrically connected to the second portion 120A-2 of the first chip connection wire structure 120A, and is electrically independent of the first portion 120A-1 of the corresponding first chip connection wire structure 120A. Since the first chip connection wire structure 120A corresponding to the first microchip 110A is cut off, the first microchip 110A cannot output data signals to the corresponding light emitting elements 310, 320, 330. In addition, since the first chip connection wire structure 120A corresponding to the first microchip 110B is not cut off, the first microchip 110B can output data signals to the corresponding light emitting elements 310, 320, 330 through the first chip connection wire structure 120A and the second chip connection wire structure 130A.

[0086] Based on the above, in the display device 10A, the repaired microchip 210 can replace the failed first microchip 110A to output data signals to the corresponding light emitting elements 310 , 320 , 330 , thereby improving the yield of the display device 10A.

[0087] Fig. 7A , 8A 9A is a top view schematically showing various stages of manufacturing a display device 10B according to an embodiment of the present invention. Figure 7B , 8B and 9B are Fig. 7A , 8A And the cross-sectional schematic diagrams along the line AA' and the line BB' of 9A.

[0088] It must be pointed out here that 7A to 9B The implementation examples are used Figures 1A to 6B The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0089] Please refer to Fig. 7A as well as Figure 7B , continued Figure 4A as well as Figure 4B The steps of forming a plurality of second chip connection line structures 130C and a plurality of bridge structures 130B on the first insulating layer 140. The second chip connection line structures 130C are at least partially electrically connected to the first chip connection line structures 120A. For example, the second chip connection line structures 130C are respectively filled into the first openings O1 to connect to the corresponding first chip connection line structures 120A. The bridge structures 130B are respectively filled into the second openings O2 to connect to the signal input structures 120B.

[0090] In some embodiments, the second chip connection line structure 130C includes a first repair pad 132C, a second connection line 133C, a first conductive filling portion 134C, a third connection pad 138C, and a signal transmission line 139C. The first repair pad 132C is disposed in the chip placement area CA. In some embodiments, the first conductive filling portion 134C is located outside the chip placement area CA, is filled in the first opening O1, and is connected to the corresponding first connection pad 124A through the first opening O1. The second connection line 133C extends outward from the chip placement area CA to connect the first repair pad 132C to the first conductive filling portion 134C. The signal transmission line 139C connects the first conductive filling portion 134C and the third connection pad 138C.

[0091] The repair microchip 210 is arranged in the chip placement area CA corresponding to the failed microchip. The repair microchip 210 is not arranged in the chip placement area CA corresponding to the first microchip 110B that can function normally. The repair microchip 210 is located on the first insulating layer 140 and is bonded to the corresponding second chip connection line 130C and the bridge structure 130B through the connection structure 215. Specifically, the second chip pad 213 of the repair microchip 210 is bonded to the first repair pad 132C of the corresponding second chip connection line 130C and the second repair pad 132B of the corresponding bridge structure 130B through the connection structure 215. The repair microchip 210 is electrically connected to the signal input structure 120B through the bridge structure 130B corresponding to the failed microchip. For example, the signal input structure 120B is configured to provide an input signal to the microchip.

[0092] In this embodiment, the repair microchip 210 is located in the chip placement area CA and at least partially overlaps the failed microchip (i.e., the first microchip 110A). In some embodiments, the repair microchip 210 is electrically connected to a portion of the first chip connection line structure 120A (e.g., the second portion 120A-2) through the second chip connection line 130C.

[0093] Please refer to Fig. 8A as well as Figure 8B The second insulating layer 160 is formed on the first insulating layer 140, the second chip connection line 130C and the bridge structure 130B. The second chip connection line 130C and the bridge structure 130B are located between the first insulating layer 140 and the second insulating layer 160. The second insulating layer 160 surrounds the repair microchip 210 in a transverse direction.

[0094] A plurality of signal output lines 170, a plurality of first light emitting diode bonding pads 182, and a plurality of second light emitting diode bonding pads 184 are formed on the second insulating layer 160. The signal output lines 170 are electrically connected to the second chip connection line structure 130C. For example, the signal output lines 170 are respectively filled into the third openings O3 in the second insulating layer 160 to connect the corresponding second chip connection lines 130C. In some embodiments, the depth H2 of the third openings O3 is 5 microns to 25 microns, and the width W2 is 5 microns to 35 microns.

[0095] In some embodiments, the signal output line 170 includes a third conductive filling portion 174 and a signal output line 176. The third conductive filling portion 174 is filled in the third opening O3 and connected to the corresponding third connection pad 138C through the third opening O3. The signal output line 176 extends from the third conductive filling portion 174 to the pixel area PA and is connected to the first light-emitting diode bonding pad 182 in the pixel area PA. In some embodiments, each pixel area PA also includes one or more second light-emitting diode bonding pads 184. In some embodiments, the plurality of second light-emitting diode bonding pads 184 are connected to each other and electrically connected to a common voltage.

[0096] Please refer to Fig.9A as well as Fig. 9B The light emitting elements 310 , 320 , 330 are respectively disposed in the pixel area PA. The light emitting elements 310 , 320 , 330 are located above the second insulating layer 160 , and the electrodes E of the light emitting elements 310 , 320 , 330 are respectively bonded to the first LED bonding pad 182 and the second LED bonding pad 184 through the connection structure S.

[0097] The light emitting elements 310, 320, 330 are electrically connected to the signal output structure 170, respectively. The repair microchip 210 is electrically connected to the signal output structure 170 through the second chip connection line structure 130C, thereby providing data signals to the light emitting elements 310, 320, 330. Since the first chip connection line structure 120A corresponding to the first microchip 110A is cut off, the first microchip 110A cannot transmit data signals to the corresponding light emitting elements 310, 320, 330. In addition, since the first chip connection line structure 120A corresponding to the first microchip 110B is not cut off, the first microchip 110B can transmit data signals to the corresponding light emitting elements 310, 320, 330 through the first chip connection line structure 120A, the second chip connection line structure 130C and the signal output structure 170.

[0098] Based on the above, in the display device 10B, the repaired microchip 210 can replace the failed first microchip 110A to output data signals to the corresponding light emitting elements 310 , 320 , 330 , thereby improving the yield of the display device 10B.

[0099] Fig. 10A , 11A 12A, 13A, 14A and 15A are top views of various stages of manufacturing a display device 10C according to an embodiment of the present invention. Fig. 10B , 11B , 12B, 13B, 14B and 15B are Fig. 10A , 11A, schematic cross-sectional views of lines AA' and BB' of 12A, 13A, 14A and 15A.

[0100] Please refer to Fig. 10A as well as Fig. 10B , the first microchips 110A and 110B are disposed on the substrate 100. For example, the first microchips 110A and 110B are attached to the substrate 100 through the adhesive layer 104. The first microchips 110A and 110B are respectively disposed in different chip placement areas CA. In some embodiments, after the first microchips 110A and 110B are placed in the chip placement areas CA, an automated optical inspection (AOI) is performed to detect the positions of the first microchips 110A and 110B.

[0101] In this embodiment, the first microchips 110A and 110B are attached to the top surface of the substrate 100 through the adhesive layer 104, but the present invention is not limited thereto. In other embodiments, the top surface of the substrate 100 includes a circuit structure (not shown), and the first microchips 110A and 110B are attached to the circuit structure through the adhesive layer 104.

[0102] In this embodiment, a whole adhesive layer 104 is formed on the substrate 100, and a portion of the adhesive layer 104 does not overlap the first microchips 110A and 110B, but the present invention is not limited thereto. In other embodiments, multiple separate adhesive layers 104 respectively attach the first microchips 110A and 110B to the substrate 100.

[0103] In this embodiment, the first microchips 110A and 110B are both disposed in the chip placement area CA with their active surfaces facing upward. The first microchips 110A and 110B each include a plurality of first chip pads 113. The first chip pads 113 are disposed on the active surface and are located on the side of the first microchips 110A and 110B facing away from the substrate 100.

[0104] Please refer to Fig.11A as well as Fig. 11B A first insulating layer 140 is formed on the substrate 100 . The first insulating layer 140 surrounds the first microchips 110A and 110B in a transverse direction. The first chip pads 113 of the first microchips 110A and 110B are exposed by the first insulating layer 140 .

[0105] A plurality of first chip connection line structures 120D and a plurality of signal input structures 120E are formed on the first insulating layer 140. The first chip connection line structures 120D extend outward from the chip placement area CA, and the signal input structures 120E extend from the chip placement area CA to the signal source area (not shown). In some embodiments, the signal source area is disposed in the frame area of ​​the display device, but the present invention is not limited thereto.

[0106] In some embodiments, the first chip connection line structure 120D includes a first chip bonding pad 122D, a first connection line 123D, and a first connection pad 124D. The first chip bonding pad 122D is disposed in the chip placement area CA. In some embodiments, the first connection pad 124D is located outside the chip placement area CA, and the first connection line 123D extends outward from the chip placement area CA to connect the first chip bonding pad 122D to the first connection pad 124D.

[0107] In some embodiments, a portion of the first chip connection line structure 120D extends from one side of the chip placement area CA (eg, Fig.11A The first chip connection line structure 120D extends outward from the chip placement area CA, and another portion of the first chip connection line structure 120D extends from the other side of the chip placement area CA (eg Fig.11A The lower side of the wafer extends outwardly to form a chip placement area CA.

[0108] The signal input structure 120E includes a second chip bonding pad 122E, a signal input line 123E, a second connection pad 124E, and a connection line 125E connecting the second chip bonding pad 122E and the second connection pad 124E. The second chip bonding pad 122E is disposed in the chip placement area CA, and is electrically connected to the signal input line 123E through the connection line 125E and the second connection pad 124B. In some embodiments, the second connection pad 124E is located outside the chip placement area CA, and the signal input line 123E extends outward from the chip placement area CA to connect the second chip bonding pad 122E to the second connection pad 124E.

[0109] In some embodiments, the first chip bonding pads 122D and the second chip bonding pads 122E are directly formed on the first chip bonding pads 113 of the first microchips 110A and 110B, and directly contact at least a portion of the first chip bonding pads 113 of the first microchips 110A and 110B. In some embodiments, the first microchip 110A is offset when placed, resulting in that part or all of the first chip bonding pads 113 of the first microchip 110A are not aligned with the first chip bonding pads 122D and / or the second chip bonding pads 122E.

[0110] Please refer to Fig. 12A as well as Fig. 12B, the first microchips 110A and 110B are tested to confirm whether the first microchips 110A and 110B can operate normally. For example, the first microchips 110A and 110B are tested by a full contact test. In this embodiment, the first microchip 110A cannot operate normally, while the first microchip 110B can operate normally. For example, the first microchip 110A is offset when placed on the substrate 100, or has internal defects, resulting in the first microchip 110A being unable to output and / or receive expected signals. The first microchip 110A may also be referred to as a failed microchip. In this embodiment, the failed microchip (i.e., the first microchip 110A) is located in the chip placement area CA. The failed microchip is at least partially connected to the first chip connection line structure 120D and the signal input structure 120E. In some embodiments, because the failed microchip is offset when placed, part of the first chip pads 113 of the failed microchip are not bonded to the first chip connection line structure 120D and the signal input structure 120E.

[0111] In some embodiments, after confirming that the first microchip 110A is a failed microchip, the first chip connection line structure 120D corresponding to the first microchip 110A is cut through a cutting process (such as laser cutting or other suitable cutting methods) to cut the first connection line 123D between the first chip bonding pad 122D and the first connection pad 124D. This ensures that the first microchip 110A no longer outputs signals to the light-emitting element that will be subsequently transferred to the substrate 100 through the first chip connection line structure 120D. On the other hand, the connection line 125E corresponding to the first microchip 110A can also be cut to ensure that the signal input line 123E does not transmit signals to the first microchip 110A.

[0112] In some embodiments, at least one of the first chip connection wire structures 120D is cut to have a first portion 120D-1 (e.g., including a first chip bonding pad 122D and a portion of a first connection wire 123D connected to the first chip bonding pad 122D) and a second portion 120D-2 (e.g., including a first connection pad 124D and a portion of a first connection wire 123D connected to the first connection pad 124D) separated from each other. The failed microchip (i.e., the first microchip 110A) is electrically connected to the first portion 120D-1.

[0113] Please refer to Fig.13A as well as Fig. 13B, the repair microchip 210 is arranged in the chip placement area CA corresponding to the failed microchip. The repair microchip 210 is not arranged in the chip placement area CA corresponding to the first microchip 110B that can operate normally. For example, the repair microchip 210 is placed in the chip placement area CA by a pick and place (PNP) method. In this embodiment, the repair microchip 210 is arranged in the chip placement area CA with the active surface facing up. The repair microchip 210 includes a plurality of second chip pads 213. In some embodiments, the second chip pads 213 are located on the side of the repair microchip 210 facing away from the substrate 100. In some embodiments, the repair microchip 210 has the same structural design as the first microchips 110A and 110B, so it is not necessary to redesign the microchip for the repair process. For example, the relative positions of the second chip pads 213 on the repair microchip 210 are equal to the relative positions of the first chip pads 113 of the first microchips 110A and 110B.

[0114] In some embodiments, the repair microchip 210 is bonded to the first insulating layer 140 via the adhesive layer 202. In some embodiments, the repair microchip 210 is bonded to the first portion 120D-1 in the first chip connection wire structure 120D via the adhesive layer 202. The first chip connection wire structure 120D portion (e.g., the first portion 120D-1) is located between the repair microchip 210 and the failed microchip (i.e., the first microchip 110A).

[0115] Please refer to Fig.14A as well as Fig. 14B The second insulating layer 160 is formed on the first insulating layer 140, the first chip connection line 130D and the signal input structure 120E. The first chip connection line 130D and the signal input structure 120E are located between the first insulating layer 140 and the second insulating layer 160. The second insulating layer 160 surrounds the repair microchip 210 in a transverse direction.

[0116] The second insulating layer 160 has a plurality of first openings O1 and a plurality of second openings O2. The first openings O1 expose the first connection pads 124D at the bottom thereof, and the second openings O2 expose the second connection pads 124E at the bottom thereof.

[0117] A plurality of second chip connection wire structures 130D, a plurality of bridge structures 130E, a plurality of first LED bonding pads 182, and a plurality of second LED bonding pads 184 are formed on the second insulating layer 160. The second chip connection wire structures 130D are at least partially electrically connected to the first chip connection wire structures 120D. For example, the second chip connection wire structures 130D are respectively filled into the first openings O1 of the second insulating layer 160 to connect to the corresponding first chip connection wire structures 120D. The bridge structures 130E are respectively filled into the second openings O2 of the second insulating layer 160 to connect to the signal input structures 120E.

[0118] In some embodiments, the second chip connection line structure 130D includes a first repair pad 132D, a second connection line 133D, a first conductive filling portion 134D, and a signal output line 135D. The first repair pad 132D is disposed in the chip placement area CA. In some embodiments, the first repair pad 132D is directly formed on the second chip pad 213 of the repair microchip 210. In some embodiments, the first conductive filling portion 134D is located outside the chip placement area CA, and is filled in the first opening O1 of the second insulating layer 160, and is connected to the corresponding first connection pad 124D through the first opening O1. The second connection line 133D extends outward from the chip placement area CA to connect the first repair pad 132D to the first conductive filling portion 134D. The signal output line 135D extends into the pixel area PA and is connected to the first light-emitting diode bonding pad 182 in the pixel area PA. In some embodiments, each pixel area PA also includes one or more second light-emitting diode bonding pads 184. In some embodiments, a plurality of second light-emitting diode bonding pads 184 are connected to each other and electrically connected to a common voltage.

[0119] In some embodiments, the bridge structure 130E includes a second repair pad 132E, a third connection line 133E, and a second conductive filling portion 134E. The second repair pad 132E is disposed in the wafer placement area CA. In some embodiments, the second repair pad 132E is directly formed on the second wafer pad 213 of the repair microchip 210. In some embodiments, the second conductive filling portion 134E is located outside the wafer placement area CA and is filled into the second opening O2 of the second insulating layer 160, and is connected to the corresponding second connection pad 124E through the second opening O2. The third connection line 133E extends outward from the wafer placement area CA to connect the second repair pad 132E to the second conductive filling portion 134E.

[0120] Please refer to Fig.15A as well as Fig. 15BThe light emitting elements 310 , 320 , 330 are respectively disposed in the pixel area PA. The light emitting elements 310 , 320 , 330 are located above the second insulating layer 160 , and the electrodes E of the light emitting elements 310 , 320 , 330 are respectively bonded to the first LED bonding pad 182 and the second LED bonding pad 184 through the connection structure S.

[0121] In some embodiments, the connection structure S is first formed on the substrate 100 by evaporation or other suitable methods, and then the light-emitting elements 310, 320, 330 are bonded to the connection structure S, but the present invention is not limited thereto. In other embodiments, the connection structure S is formed on the light-emitting elements 310, 320, 330, respectively, and then the light-emitting elements 310, 320, 330 are disposed on the substrate 100.

[0122] The repaired microchip 210 is electrically connected to the corresponding light emitting elements 310, 320, 330 through the corresponding second chip connection wires 130D. In the present embodiment, at least one of the second chip connection wire structures 130D corresponding to the first microchip 110A (i.e., the failed microchip) is electrically connected to the second portion 120D-2 of the first chip connection wire structure 120D, and is electrically independent of the first portion 120D-1 of the corresponding first chip connection wire structure 120D. Since the first chip connection wire structure 120D corresponding to the first microchip 110A is cut off, the first microchip 110A cannot transmit data signals to the corresponding light emitting elements 310, 320, 330. In addition, since the first chip connection wire structure 120D corresponding to the first microchip 110B is not cut off, the first microchip 110B can transmit data signals to the corresponding light emitting elements 310, 320, 330 through the first chip connection wire structure 120D and the second chip connection wire structure 130D.

[0123] Based on the above, in the display device 10C, the repaired microchip 210 can replace the failed first microchip 110C to output data signals to the corresponding light emitting elements 310 , 320 , 330 , thereby improving the yield of the display device 10C.

[0124] Fig.16 FIG. 1 is a cross-sectional schematic diagram of a display device 10D manufactured according to an embodiment of the present invention. It must be noted that: Fig.16 The implementation examples are used FIG. 10A to FIG. 15B The component numbers and partial contents of the embodiments are the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the above embodiments, which will not be repeated here. Please refer to Fig.16In this embodiment, the top surface of the first insulating layer 140 is higher than the top surface of the first chip pad 113. The first chip connection line structure 120D fills the opening V1 of the first insulating layer 140 on the first chip pad 113 to connect the first chip pad 113. In some embodiments, the depth X1 of the opening V1 is 0.1 micrometers to 20 micrometers, and the width Y1 is 3 micrometers to 100 micrometers.

[0125] In addition, in the present embodiment, the height of the top surface of the second insulating layer 160 is higher than the height of the top surface of the second chip pad 213. The second chip connection line structure 130D fills the opening V2 of the second insulating layer 160 located on the second chip pad 113 to connect the second chip pad 213. In some embodiments, the depth X2 of the opening V2 is 0.1 micrometers to 20 micrometers, and the width Y2 is 3 micrometers to 100 micrometers.

[0126] In some embodiments, in addition to the opening V2 at the location where the repair microchip 210 is disposed, the area corresponding to the first microchip 110B (e.g., directly above the first microchip 110B) that does not include the repair microchip 210 also includes the opening V2. By providing the opening V2 in all wafer placement areas, no matter in which wafer placement area the repair microchip 210 is to be placed, it is not necessary to readjust the pattern of the mask used when etching the second insulating layer 160.

[0127] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A display device, characterized in that: include: a substrate; A plurality of first chip connection line structures are located on the substrate and extend outward from a chip placement area; A plurality of light emitting elements are respectively arranged in a plurality of pixel areas around the chip placement area; a first insulating layer, located on the substrate; A failed microchip is located in the chip placement area, wherein the first insulating layer laterally surrounds the failed microchip, and the failed microchip is at least partially connected to the first chip connection line structures; a plurality of second chip connection line structures, located on the first insulating layer and at least partially electrically connected to the first chip connection line structures; and A repair microchip is located on the first insulating layer, wherein the repair microchip is located in the chip placement area and at least partially overlaps the failed microchip, wherein the repair microchip is electrically connected to the light-emitting elements through the second chip connection lines.

2. The display device according to claim 1, wherein: The first chip connection line structures are located between the first insulating layer and the substrate, and the second chip connection line structures are located on the first insulating layer. The second chip connection line structures are respectively filled into a plurality of first openings in the first insulating layer to connect the first chip connection structures.

3. The display device according to claim 2, wherein: Also includes: a second insulating layer located on the first insulating layer, wherein the light emitting elements are located on the second insulating layer, and the second chip connecting wire structures are located between the first insulating layer and the second insulating layer; and A plurality of signal output structures are located on the second insulating layer, wherein the light emitting elements are respectively electrically connected to the signal output structures, and the signal output structures are respectively filled into a plurality of second openings in the second insulating layer to connect to the second chip connection structures.

4. The display device according to claim 1, wherein: Also includes: A second insulating layer is located on the first insulating layer and laterally surrounds the repair microchip, wherein the second chip connection line structures are located on the second insulating layer.

5. The display device according to claim 1, wherein: At least one of the first chip connection wire structures is cut to have a first portion and a second portion separated from each other, wherein the failed microchip is electrically connected to the first portion, and at least one of the second chip connection wire structures is electrically connected to the second portion.

6. The display device according to claim 1, wherein: The failed microchip includes a plurality of first chip pads, and the repaired microchip includes a plurality of second chip pads, wherein the first chip pads are located on a side of the failed microchip close to the substrate, and the second chip pads are located on a side of the repaired microchip close to the substrate.

7. The display device according to claim 1, wherein: The failed microchip includes a plurality of first chip pads, and the repaired microchip includes a plurality of second chip pads, wherein the first chip pads are located on the side of the failed microchip facing away from the substrate, and the second chip pads are located on the side of the repaired microchip facing away from the substrate.

8. The display device according to claim 1, wherein: Also includes: A plurality of signal input structures extending outward from the chip placement area, wherein the signal input structures and the first chip connection line structures are located between the first insulating layer and the substrate; a second insulating layer located on the first insulating layer and the second chip connection line structures, wherein the second insulating layer laterally surrounds the repair microchip; a plurality of bridge structures, wherein the bridge structures and the second chip connection line structures are located between the first insulating layer and the second insulating layer, and the repair microchip is electrically connected to the signal input structures through the bridge structures; and A plurality of signal output structures are located on the second insulating layer, wherein the light emitting elements are electrically connected to the signal output structures respectively, and the repair microchip is electrically connected to the signal output structures through the second chip connection line structures.

9. The display device according to claim 1, wherein: Also includes: A second insulating layer, located on the first insulating layer, and the second chip connection line structures are located on the second insulating layer; A plurality of signal input structures extending outward from the chip placement area, wherein the signal input structures and the first chip connection line structures are located between the first insulating layer and the second insulating layer; and A plurality of bridge structures are located on the second insulating layer, and the repair microchip is electrically connected to the signal input structures through the bridge structures.

10. The display device according to claim 1, wherein: The first chip connection line structures are partially located between the repaired microchip and the failed microchip.

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