High-temperature superconducting quantum voltage chip and preparation method thereof

Abstract

The invention discloses the technical field of high-temperature superconducting quantum voltage, and particularly relates to a high-temperature superconducting quantum voltage chip, which comprises a Josephson junction array, and the Josephson junction array comprises a plurality of Josephson junctions. The Josephson junction comprises a polycrystal substrate with different crystal orientation areas, a first superconducting element and a second superconducting element, the first superconducting element and the second superconducting element are distributed on the surfaces of the different crystal orientation areas on the polycrystal substrate, and one end of the first superconducting element is in contact connection with one end of the second superconducting element through a microbridge. The first superconducting element, the second superconducting element and the microbridge are composed of a high-temperature superconducting film which is epitaxially grown on the upper surface of the polycrystal substrate at a time. According to the prepared high-temperature superconducting quantum voltage chip, the two-dimensional thin film only needs to be epitaxially grown for one time to form the high-temperature superconducting Josephson junction array, the integration process is greatly simplified in structure, the characteristic consistency is good, the yield is high, the chip can work at high temperature and is miniaturized and easy to transplant, and real-time voltage calibration is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-temperature superconducting quantum voltage, and in particular to a high-temperature superconducting quantum voltage chip and a preparation method thereof. Background Art

[0002] Compared with the traditional physical standard based on the Weston standard cell, the quantum voltage standard has the advantages of high precision, high reproducibility and easy storage. The core device of the quantum voltage standard is the large-scale integrated Josephson junction array device. The Josephson junction is an electronic circuit consisting of two superconducting layers tightly connected to a weak connection layer or an insulating layer or a semiconductor layer, and the thickness of the weak connection layer is generally in the order of nanometers. When the temperature is low enough, the superconductor can exchange pairs of electrons through a potential barrier at a very fast speed. The integrated Josephson junction array chip is the core chip required for the quantum voltage base standard and related precision measurement systems. It is the core component of many superconducting devices and circuits and has been successfully applied in superconducting quantum interference devices (SQUIDs), superconducting tunnel mixers (SIS mixers), quantum bits (Qubits), single flux quantum circuits (SFQ), Josephson voltage standards and other devices. The Josephson voltage standard realized by connecting thousands of Josephson junctions in series can output a voltage of up to 10V, with a relative uncertainty of less than 10 - 10 , Josephson voltage references are used in routine DC calibration and related applications in more than 60 laboratories around the world.

[0003] The Josephson voltage standard is a measurement standard based on the Josephson effect to reproduce the voltage value. The current superconducting quantum voltage standard is based on the Josephson junction array of the SIS sandwich structure of low-temperature superconducting materials. It is a three-dimensional structure with its central axis perpendicular to the substrate. The core film evaporation requires at least three processes, including the lower superconducting film, the middle dielectric, and the upper superconducting film. The materials used for superconducting Josephson junctions are currently mainly aluminum nitride, titanium nitride, niobium nitride (NbN), niobium, aluminum oxide, magnesium oxide, silicon nitride, silicon dioxide, etc. For example, patent CN201511018443.4 provides a method for preparing high-quality niobium nitride film, using niobium nitride (NbN) as an electrode material and aluminum nitride (AlN) as an insulating layer of the Josephson junction. Patent CN202010021481.X provides a method for preparing a Josephson junction array, a Josephson junction array, and an electronic device. However, the above two types of Josephson junction arrays still use SIS sandwich structures, which have the problems of cumbersome and complicated preparation process and poor stability of finished products. In addition, niobium nitride and other materials are used as superconducting films, which are still low-temperature superconductors and require liquid helium refrigeration. They have high operating costs, large size, poor mobility, and are not easy to miniaturize and transplant. In addition, the superconducting properties of the upper superconducting film are often worse than those of the lower layer. The prepared Josephson junction array is required to work in liquid helium (4.2K) or lower temperature zones. The refrigeration equipment for this low-temperature environment is large and complex. If the liquid helium Dewar system is used directly, it will be more fragile and can only be used in laboratories with better conditions as a fixed laboratory equipment. Although the accuracy of the low-temperature quantum voltage standard can reach 10 -10 , while the accuracy of traditional provincial voltage standards is only 10 -4 to 10 -6 Even if the accuracy is between the above two, if the quantum voltage standard can work at high temperature (such as liquid nitrogen temperature zone), achieve miniaturization and easy transplantation, it will bring revolutionary breakthroughs to the seamless embedding of quantum voltage standards into devices or instruments. Summary of the invention

[0004] In view of the above shortcomings, the present invention provides a high-temperature superconducting quantum voltage chip, which works at high temperature (such as liquid nitrogen temperature range), is miniaturized and easy to transplant, and is conducive to realizing real-time voltage calibration. The specific technical solution is as follows:

[0005] A high-temperature superconducting quantum voltage chip comprises a Josephson junction array, wherein the Josephson junction array comprises a plurality of Josephson junctions, wherein the Josephson junctions comprise a polycrystalline substrate having regions with different crystal orientations, a first superconducting element and a second superconducting element distributed on the surface of the regions with different crystal orientations on the polycrystalline substrate, wherein one end of the first superconducting element is contact-connected with one end of the second superconducting element via a first microbridge, and the first superconducting element, the second superconducting element and the first microbridge are composed of a high-temperature superconducting thin film epitaxially grown once on the upper surface of the polycrystalline substrate.

[0006] In the high-temperature superconducting quantum voltage chip of the present invention, a polycrystalline substrate with pre-designed crystal orientation regions is used, and a high-temperature superconducting thin film is obtained by epitaxial growth on the substrate once. Due to the induction of the polycrystalline substrate, the orientation of the epitaxial film grown thereon is also different, so that a grain boundary is formed at the interface thereof, forming a Josephson junction in the form of a polycrystalline boundary junction. A plurality of Josephson junctions form a Josephson junction array, and the Josephson junction array completely exists in the two-dimensional thin film grown once, which greatly simplifies the integration process in terms of structure and has good characteristic consistency.

[0007] Preferably, in the above-mentioned high-temperature superconducting quantum voltage chip, a plurality of Josephson junctions in the Josephson junction array are arranged at periodic intervals, a second superconducting element in the Josephson junction is connected to a second superconducting element in an adjacent Josephson junction through a second connector, and the first superconducting element is connected to a first superconducting element in an adjacent Josephson junction through a first connector, and the plurality of Josephson junctions form a series structure, a first superconducting element in the Josephson junction at the head end and a second superconducting element in the Josephson junction at the end end are respectively connected to electrodes, and the second connector and the first connector are composed of the high-temperature superconducting film.

[0008] Preferably, in the above-mentioned high-temperature superconducting quantum voltage chip, the width of the microbridge is 5 μm, and the length of the microbridge is 20 μm.

[0009] Preferably, in the above-mentioned high-temperature superconducting quantum voltage chip, the Josephson junction also includes a third superconducting element, the crystal orientation of the polycrystalline substrate region corresponding to the third superconducting element is different from the crystal orientation of the regions corresponding to the first superconducting element and the second superconducting element, and the two ends of the third superconducting element of the same Josephson junction are respectively connected to the second superconducting element and one end of the first superconducting element through the second microbridge and the third microbridge, and in the Josephson junction array, the first superconducting element in one Josephson junction is connected to the first superconducting element in the adjacent Josephson junction through the first connecting piece, and several Josephson junctions form a series structure, and the first superconducting element in the Josephson junction at the head end and the first superconducting element in the Josephson junction at the end are respectively connected to electrodes, and the second microbridge, the third microbridge and the first connecting piece are composed of the high-temperature superconducting film.

[0010] On the other hand, the present invention also provides a method for preparing the above-mentioned high-temperature superconducting quantum voltage chip, comprising the following steps:

[0011] S1. Producing a polycrystalline substrate with different crystal orientation regions;

[0012] S2. Preparing a high temperature superconducting thin film on the polycrystalline substrate obtained in step S1;

[0013] S3. Coating a glue layer on the high-temperature superconducting film prepared in step S2, etching and processing a plurality of superconducting elements, microbridges and connectors to obtain a plurality of serially connected Josephson junctions to form a Josephson junction array;

[0014] S4. Prepare electrodes on the first superconducting element in the Josephson junction at the head end and the first superconducting element in the Josephson junction at the end to form a high-temperature superconducting quantum voltage chip.

[0015] Preferably, in the above-mentioned method for preparing a high-temperature superconducting quantum voltage chip, in step S1, two or more substrates with parallel c-axes and b-axes having a certain angle are treated at high temperature and high pressure to obtain substrates with different crystal orientation regions.

[0016] Preferably, in the above-mentioned method for preparing a high-temperature superconducting quantum voltage chip, the angle is -24 to 48°.

[0017] Preferably, in the above-mentioned method for preparing a high-temperature superconducting quantum voltage chip, in step S2, the high-temperature superconducting thin film is prepared by laser pulse deposition, magnetron sputtering, molecular beam epitaxy or laser molecular beam epitaxy.

[0018] Preferably, in the above-mentioned method for preparing a high-temperature superconducting quantum voltage chip, the high-temperature superconducting film is a YBCO film, and the thickness of the film is 150-200 nm. 7-δ The superconducting temperature of thin film can reach above 93K and it can be cooled by liquid nitrogen. It is an ideal material for manufacturing Josephson junction of high-temperature quantum voltage standard system.

[0019] Preferably, in the above-mentioned method for preparing the high-temperature superconducting quantum voltage chip, the substrate is an STO substrate, a LAO substrate or a SYZ substrate; the LAO substrate is further preferred, and the LAO substrate is a lanthanum aluminate (LaAlO3) polycrystalline substrate. Lanthanum aluminate single crystal has the advantages of large size, good thermal sensitivity, low microwave loss, strong chemical stability, etc., and has good lattice matching with YBCO material. The polycrystalline substrate is a twin-crystal substrate, a tri-crystal substrate or a tetra-crystal substrate.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] 1. In the high-temperature superconducting quantum voltage chip of the present invention, only one epitaxial growth of a two-dimensional thin film is required, and the prepared high-temperature superconducting Josephson junction array exists entirely in the one-time two-dimensional thin film, which greatly simplifies the integration process in structure, has a simple preparation process, small material differences, good property consistency, high yield, and can work at high temperatures (such as liquid nitrogen temperature range), be miniaturized and easy to transplant, and can even be directly embedded in the device to achieve real-time voltage calibration.

[0022] 2. In the present invention, by designing the crystal orientation of the substrate region, a twin crystal substrate with different crystal orientations is formed after appropriate heat treatment. Due to the induction of the twin crystal substrate, the orientations of the epitaxial films grown in different crystal orientation regions of the substrate are also different, thereby forming a grain boundary at the interface thereof. After etching the microbridge in a direction perpendicular to the grain boundary, a twin crystal grain boundary junction can be obtained, that is, a twin crystal or polycrystalline Josephson junction is formed. A number of Josephson junctions are arranged to form a Josephson junction array. By designing the array structure parameters, the working stability and standard accuracy of the high-temperature superconducting quantum voltage chip are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 This is a schematic diagram of the structure of the quantum voltage standard superconducting chip in Example 1 of the present invention;

[0025] Figure 2 Schematic diagram of the Josephson junction structure in Example 1 of the present invention;

[0026] Figure 3 Schematic diagram of the crystal orientation of the polycrystalline substrate in Example 1 of the present invention;

[0027] Figure 4 Schematic diagram of the Josephson junction structure in Example 2 of the present invention;

[0028] Figure 5 Schematic diagram of the crystal orientation of the polycrystalline substrate in Example 2 of the present invention;

[0029] Figure 6 Schematic diagram of the Josephson junction array structure in Example 2 of the present invention;

[0030] Figure 7 Schematic diagram of the structure of the Josephson junction array in Example 4 of the present invention;

[0031] Figure 8 Schematic diagram of the crystal orientation of the polycrystalline substrate in Example 4 of the present invention;

[0032] Main legend:

[0033] 1-first superconducting element, 2-second superconducting element, 3-polycrystalline substrate, 3-1-first region of polycrystalline substrate, 3-2-second region of polycrystalline substrate, 3-3-third region of polycrystalline substrate, 4-electrode, 5-second connecting piece, 6-first connecting piece, 7-first grain boundary, 8-first microbridge, 9-second microbridge, 10-second grain boundary, 11-third superconducting element, 12-third microbridge, 13-third grain boundary. DETAILED DESCRIPTION

[0034] The specific embodiments of the present invention are described in detail below, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments. Unless otherwise defined, all professional terms used hereinafter have the same meaning as those generally understood by those skilled in the art. The professional terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the protection scope of the present invention. Unless otherwise specifically stated, various raw materials, reagents, instruments and equipment used in the present invention, etc. can be purchased from the market or can be prepared by existing methods.

[0035] Example 1

[0036] This embodiment provides a quantum voltage standard superconducting chip based on a Josephson junction array, including a Josephson junction array such as Figure 1 As shown, the Josephson junction array includes several Josephson junctions. Figure 2 As shown, it includes a polycrystalline substrate 3, a first superconducting element 1, and a second superconducting element 2. Specifically, the polycrystalline substrate 3 of this embodiment is a double crystal substrate. The polycrystalline substrate 3 is composed of a first region 3-1 and a second region 3-2 with different crystal orientations. The crystal c axes of the first region 3-1 and the second region 3-2 are parallel, and the crystal b axis of the second region 3-2 is rotated 24° clockwise relative to the b axis of the first region 3-1. The angle between the b axes of the two regions is 24°. Figure 3 As shown; the first superconducting element 1 and the second superconducting element 2 are respectively located on the upper surfaces of the first region 3-1 and the second region 3-2, and one end of the first superconducting element 1 is connected to one end of the second superconducting element 2 through a first microbridge 8 to form a twin-crystal Josephson junction.

[0037] like Figure 1 As shown, the Josephson junction array of this embodiment includes a plurality of Josephson junctions periodically arranged on the same polycrystalline substrate 3, the second superconducting element 2 of the Josephson junction is connected to the second superconducting element 2 of the adjacent Josephson junction through a second connector 5, the first superconducting element 1 is connected to the first superconducting element 1 in the adjacent Josephson junction through a first connector 6, and the plurality of Josephson junctions form a series structure, the first superconducting element 1 in the head Josephson junction and the first superconducting element 1 in the terminal Josephson junction in the Josephson junction array are electrically connected to the electrode 4 to form a quantum voltage standard superconducting chip.

[0038] Specifically, the first superconducting element 1 , the first superconducting element 2 , the first microbridge 8 , the first connecting member 6 and the second connecting member 5 are composed of a high-temperature superconducting thin film that is epitaxially grown once on the surface of the polycrystalline substrate 3 .

[0039] The polycrystalline substrate 3 in this embodiment is a LAO twin crystal substrate, and the high temperature superconducting film is a YBCO film. The YBCO film is directly epitaxially grown on the LAO substrate by coherent lattice. Since the crystal (b axis) orientations of the substrate regions where the first superconducting element 1 and the second superconducting element 2 are located are different, the crystal orientations of the YBCO high temperature superconducting film induced by epitaxial growth are also different, and a grain boundary 7 is formed at the junction (the center of the microbridge), and a twin crystal Josephson junction is obtained. More specifically, the first superconducting element 1, the second superconducting element 2 and the microbridge 8 in this embodiment are rectangular, the first superconducting element 1 and the second superconducting element 2 are 15 μm wide and 300 μm long respectively, the microbridge 8 is 5 μm wide and 20 μm long; the thickness of the high temperature superconducting film is 200 nm. The spacing between adjacent Josephson junctions is 15 μm.

[0040] In this embodiment, under the conditions of an operating temperature of 77K and an applied microwave frequency of 75GHz, a standard superconducting chip that generates a quantum voltage of 1V includes 6666 twin-crystal Josephson junctions.

[0041] Example 2

[0042] The Josephson junction of this embodiment is as follows Figure 4 and Figure 6 As shown, it includes a polycrystalline substrate 3, a first superconducting element 1 at the head end and a second superconducting element 2, and a third superconducting element 11 at the end. The first superconducting element 1, the second superconducting element 2, and the third superconducting element 11 are respectively located on the upper surfaces of the first region 3-1, the second region 3-2, and the third region 3-3. The polycrystalline substrate 3 of this embodiment is a three-crystal substrate. Figure 5 As shown, the polycrystalline substrate 3 is composed of a first region 3-1, a second region 3-2, and a third region 3-3 with different crystal orientations. The crystal c axes of the first region 3-1, the second region 3-2, and the third region 3-3 are parallel, the b axis of the second region 3-2 rotates 24° clockwise relative to the b axis of the first region 3-1, and the angle between the b axes of the two regions is 24°; the b axis of the third region 3-3 rotates 24° counterclockwise relative to the b axis of the first region 3-1, and the angle between the b axes of the two regions is -24°; the angle between the second region 3-2 and the third region 3-3 is 48°. In the Josephson junction, one end of the first superconducting element 1 at the head end is connected to one end of the second superconducting element 2 through the first microbridge 8, the other end of the second superconducting element 2 is connected to one end of the third superconducting element 11 through the second microbridge 9, and the other end of the third superconducting element 11 is connected to one end of the first superconducting element 1 at the end through the third microbridge 13, forming a three-crystal Josephson junction.

[0043] The Josephson junction array of the present embodiment includes a plurality of periodically arranged Josephson junctions, wherein one end of a first superconducting element 1 at a head end of a Josephson junction in the Josephson junction array is connected to the first superconducting element 1 at the end end of an adjacent Josephson junction through a first connector 6, and one end of the first superconducting element 1 at the end end of another adjacent Josephson junction is connected to the first superconducting element 1 at the head end of another adjacent Josephson junction through a first connector 6, forming a series structure, and a plurality of Josephson junctions are connected in series to form a Josephson junction array, one end of the first superconducting element 1 at the head end of the first Josephson junction in the Josephson junction array and one end of the first superconducting element 1 at the end end of the last Josephson junction in the Josephson junction array are respectively connected to an electrode 4, and the first superconducting element 1, the second superconducting element 2, the third superconducting element 11, the first microbridge 8, the second microbridge 9, the third microbridge 12 and the first connector 6 in the Josephson junction array are composed of a high-temperature superconducting thin film epitaxially grown on a polycrystalline substrate 3.

[0044] Specifically, in this embodiment, the polycrystalline substrate 3 is a LAO three-crystal substrate, and the high-temperature superconducting thin film is a YBCO thin film. The YBCO thin film is coherently directly epitaxially grown on the LAO substrate. Since the crystal (b-axis) orientations of the substrate regions where the first superconducting element 1, the second superconducting element 2, the third superconducting element 11, the first microbridge 8, the second microbridge 9, and the third microbridge 12 are located are different, the crystal orientations of the YBCO high-temperature superconducting thin film induced to grow epitaxially are also different, and the first grain boundary 7, the second grain boundary 10, and the third grain boundary 13 are formed at the center of the first microbridge 8, the second microbridge 9, and the third microbridge 12 to obtain a three-crystal Josephson junction. In the Josephson junction array of this embodiment, the first superconducting element 1 of the Josephson junction is rectangular, the first microbridge 8, the second microbridge 9, and the third microbridge 12 are rectangular, the first superconducting element 1 is 15 μm wide and 300 μm long respectively, the first microbridge 8, the second microbridge 9, and the third microbridge 12 are 5 μm wide and 20 μm long; the thickness of the high-temperature superconducting film is 200 nm. The second superconducting element 2 and the third superconducting element 11 are of the same shape, L-shaped, and the width of the two corner lines is 15 μm. The length of the two lines of the second superconducting element 2 and the third superconducting element 11 of the first Josephson junction in the Josephson junction array is 75 μm, and the lengths of the second superconducting element 2 and the third superconducting element 11 of adjacent Josephson junctions are increased in sequence, with an increment of 15 μm, and the Josephson junction interval is 15 μm.

[0045] In this embodiment, under the conditions of an operating temperature of 77K and an applied microwave frequency of 75GHz, a standard superconducting chip that generates a quantum voltage of 1V includes 2270 three-crystal Josephson junctions.

[0046] Example 3

[0047] This embodiment provides a method for preparing a quantum voltage standard superconducting chip based on a Josephson junction array, comprising the following steps:

[0048] S1. Making polycrystalline substrates with different crystal orientation regions: according to the design requirements, take two or more substrates with parallel c-axes and b-axes having a certain angle, polish the surfaces to be spliced, and then perform pressurized heat treatment at high temperature, the temperature is 1400-1600°C, the pressurized pressure is 8-10MPa, and the treatment time is 2-4h, specifically, the temperature is 1500°C, the pressurized pressure is 10MPa, and the treatment time is 2h, to obtain substrates with different crystal orientation regions;

[0049] S2. A high-temperature superconducting film is prepared from the substrate obtained in step S1 by laser molecular beam epitaxy, the film thickness being 150-200nm;

[0050] S3. Coating a photoresist layer on the high-temperature superconducting film prepared in step S2, and using an Ar ion source to etch and process superconducting elements, microbridges, and connectors to obtain a plurality of serially connected Josephson junctions to form a Josephson junction array;

[0051] S4. Prepare electrodes on the first superconducting element in the Josephson junction at the head end and the first superconducting element in the Josephson junction at the end to form a high-temperature superconducting quantum voltage chip.

[0052] Example 4

[0053] The Josephson junction array of this embodiment is as follows Figure 7 and Figure 8 As shown, it includes a polycrystalline substrate 3 and a plurality of Josephson junctions. The polycrystalline substrate 3 is composed of two first regions 3-1 and a second region 3-2 with different crystal orientations, which are spliced ​​at intervals. Figure 8 The crystal c-axis of the first region 3-1 and the second region 3-2 are parallel, the crystal b-axis of the second region 3-2 is rotated 24° clockwise relative to the b-axis of the first region, and the included angle of the b-axes of the two regions is 24°, as shown in FIG. Figure 8 As shown; the Josephson junction includes a first superconducting element 1, a second superconducting element 2, and a first microbridge 8. The first superconducting element 1 and the second superconducting element 2 are respectively located on the upper surfaces of the first region 3-1 and the second region 3-2, and one end of the first superconducting element 1 is connected to one end of the second superconducting element 2 through the first microbridge 8.

[0054] The Josephson junction array of this embodiment includes a plurality of Josephson junctions periodically arranged on the same polycrystalline substrate 3, the second superconducting element 2 of the Josephson junction is connected to the second superconducting element 2 of the adjacent Josephson junction through a second connector 5, the first superconducting element is connected to the first superconducting element in the adjacent Josephson junction through a first connector 6, and the plurality of Josephson junctions form a series structure, the first superconducting element 1 in the head Josephson junction and the second superconducting element 2 in the terminal Josephson junction in the Josephson junction array are electrically connected to an electrode 4 to form a quantum voltage standard superconducting chip.

[0055] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and demonstration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different selections and changes. The scope of the present invention is intended to be limited by the claims and their equivalents.

Claims

1. A high-temperature superconducting quantum voltage chip, characterized in that: The invention comprises a Josephson junction array, wherein the Josephson junction array comprises a plurality of Josephson junctions, wherein the Josephson junction comprises a polycrystalline substrate (3) having different crystal orientation regions, a first superconducting element (1) and a second superconducting element (2) distributed on the surface of the polycrystalline substrate (3) having different crystal orientation regions, wherein one end of the first superconducting element (1) is contact-connected with one end of the second superconducting element (2) via a first microbridge (8), and the first superconducting element (1), the second superconducting element (2) and the first microbridge (8) are composed of a high-temperature superconducting thin film epitaxially grown once on the upper surface of the polycrystalline substrate (3).

2. The high temperature superconducting quantum voltage chip according to claim 1, characterized in that: A plurality of Josephson junctions in the Josephson junction array are arranged at intervals in a periodic manner; a second superconducting element (2) in the Josephson junction is connected to a second superconducting element (2) in an adjacent Josephson junction via a second connecting member (5); and the first superconducting element (1) is connected to a first superconducting element (1) in an adjacent Josephson junction via a first connecting member (6); the plurality of Josephson junctions form a series structure; the first superconducting element (1) in the Josephson junction at the head end and the first superconducting element (1) in the Josephson junction at the end are respectively connected to an electrode (4); and the second connecting member (5) and the first connecting member (6) are composed of the high-temperature superconducting film.

3. The high temperature superconducting quantum voltage chip according to claim 1, characterized in that: The Josephson junction further comprises a third superconducting element (11), wherein the crystal orientation of the polycrystalline substrate (3) region corresponding to the third superconducting element (11) is different from the crystal orientation of the regions corresponding to the first superconducting element (1) and the second superconducting element (2), and the two ends of the third superconducting element (11) of the same Josephson junction are respectively connected to the second superconducting element (2) and one end of the first superconducting element (1) through a second microbridge (9) and a third microbridge (12), and in the Josephson junction array, the first superconducting element (1) in a Josephson junction is connected to the first superconducting element (1) in an adjacent Josephson junction through a first connector (6), and a plurality of Josephson junctions form a series structure, wherein the first superconducting element (1) in the Josephson junction at the head end and the first superconducting element (1) in the Josephson junction at the end are respectively connected to electrodes (4), and the second microbridge (9), the third microbridge (11) and the first connector (6) are composed of the high-temperature superconducting film.

4. A method for preparing a high temperature superconducting quantum voltage chip as claimed in claims 1 to 3, characterized in that: The following steps are involved: S1. Producing a polycrystalline substrate with different crystal orientation regions; S2. Preparing a high temperature superconducting thin film on the polycrystalline substrate obtained in step S1; S3. coating a glue layer on the high-temperature superconducting film prepared in step S2, etching and processing a plurality of superconducting elements, microbridges and connectors to obtain a plurality of serially connected Josephson junctions to form a Josephson junction array; S4. Prepare electrodes on the first superconducting element in the Josephson junction at the head end and the first superconducting element in the Josephson junction at the end to form a high-temperature superconducting quantum voltage chip.

5. The method for preparing a high temperature superconducting quantum voltage chip according to claim 4, characterized in that: In the step S1, two or more substrates with parallel c-axes and b-axes having a certain angle are processed under high temperature and high pressure conditions to obtain a polycrystalline substrate with different crystal orientation regions.

6. The method for preparing a high temperature superconducting quantum voltage chip according to claim 5, characterized in that: The angle is -24 to 48 degrees.

7. The method for preparing a high temperature superconducting quantum voltage chip according to claim 4, characterized in that: In the step S2, the high temperature superconducting thin film is prepared by laser pulse deposition, magnetron sputtering, molecular beam epitaxy or laser molecular beam epitaxy.

8. The method for preparing a high temperature superconducting quantum voltage chip according to claim 4, characterized in that: The high temperature superconducting film is a YBCO film, and the thickness of the film is 150-200 nm.

9. The method for preparing a high temperature superconducting quantum voltage chip according to claim 4, characterized in that: The substrate is an STO substrate, a LAO substrate or a SYZ substrate.

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