Wiring board

Abstract

The purpose of the present invention is to prevent disconnection between a wiring layer provided on a glass substrate and a TGV provided on the glass substrate. A wiring board (1) is provided with: a glass substrate (10) having a first surface and a second surface (S1, S2) and provided with a through-hole; a first conductor layer (20) which includes a first copper layer (24) facing the first surface and a hydrofluoric acid-resistant metal layer (21) interposed therebetween, and which covers the first-surface-side opening of the through-hole, the glass-substrate-side surface having recesses at the positions of the through-holes, and the opening of each recess having a larger profile than and surrounding the first-surface-side opening of the through-hole corresponding thereto; and a second conductor layer (70) including an adhesion layer (72) covering a side wall of the through-hole, an inner surface of the recess, and a region of the second surface surrounding an opening of the through-hole on the second surface side, a seed layer (73) provided on the adhesion layer, and a second copper layer (74) provided on the seed layer. The sum (T1 + T2) of the thickness (T1) of the adhesion layer and the thickness (T2) of the seed layer is equal to or greater than the thickness (T3) of the hydrofluoric acid-resistant metal layer.

Description

Technical Field

[0001] The present invention relates to a wiring substrate. Background Art

[0002] Conventionally, for example, as a large-scale integrated circuit (LSI) mounting technology, a mounting technology using through silicon vias (TSV) is known. A silicon substrate provided with TSV, i.e., a silicon interposer, is a wiring substrate for relaying components with different distances between terminals, such as an integrated circuit (IC) chip and a printed circuit board having different wiring design rules.

[0003] In the silicon interposer, it is necessary to electrically insulate the silicon as a semiconductor from the through-electrode. Specifically, after the through-hole is formed, the silicon substrate needs to be insulated. In addition, the silicon substrate itself is expensive. Therefore, the silicon interposer has the problem of high manufacturing cost. Therefore, the glass interposer obtained by forming a glass through-electrode (TGV) on a cheap and large-area glass substrate and monolithicizing it has attracted much attention.

[0004] In the TGV technology, it is necessary to form a through hole on a glass substrate. The through hole can be formed on a glass substrate by various methods.

[0005] For example, as described in Patent Document 1, there is known a technique for forming a through hole in a glass substrate by laser irradiation using a pulsed YAG laser.

[0006] Patent document 2 describes a method for forming microscopic holes on a photosensitive glass substrate. In this method, ultraviolet rays are first irradiated onto the photosensitive glass substrate through a photomask to form a latent image on the photosensitive glass substrate. Next, the photosensitive glass substrate is subjected to a heat treatment to cause crystallization at the portion where the latent image is formed. Next, a hole smaller than the latent image is formed in the center of the portion where the latent image is formed by laser irradiation. Then, etching is performed using hydrofluoric acid to selectively etch the crystallized portion. In this way, a hole larger than the hole formed by laser irradiation is produced.

[0007] Patent Document 3 describes a method of drilling holes in a plate glass using a pair of core drills that are coaxially arranged and face each other with the plate glass interposed therebetween.

[0008] Patent Document 4 describes a method for simultaneously forming a through hole in a glass substrate and thinning the glass substrate by etching. In this method, a laser is first irradiated onto the glass substrate to generate a modified portion. Next, one surface of the glass substrate is etched with hydrofluoric acid to remove the modified portion while thinning the glass substrate, thereby forming a through hole.

[0009] An inductor or capacitor may also be provided in the glass interlayer. Patent document 5 describes a glass core wiring substrate with a built-in LC filter, which is a combination of an inductor and a capacitor. In this wiring substrate, the capacitor has a structure called MIM (Metal / Insulator / Metal) in which a metal layer, a dielectric layer, and a metal layer are overlapped in the thickness direction of the glass core substrate. In addition, in this wiring substrate, the inductor has a structure in which the spiral axis is parallel to the main surface of the glass core substrate and extends in a spiral shape through two rows of through holes provided in the glass core substrate.

[0010] Prior art literature

[0011] Patent Literature

[0012] Patent Document 1: Japanese Patent Application Publication No. 2000-61667

[0013] Patent Document 2: Japanese Patent Application Publication No. 2001-105398

[0014] Patent Document 3: Japanese Patent Application Laid-Open No. 54-126215

[0015] Patent Document 4: International Publication No. 2019 / 235617

[0016] Patent Document 5: Japanese Patent Application Publication No. 2021-166257 Summary of the invention

[0017] An object of the present invention is to provide a technology that can make disconnection between a wiring layer provided on a glass substrate and a TGV provided in the glass substrate less likely to occur.

[0018] According to one aspect of the present invention, there is provided a wiring substrate, comprising: a glass substrate having a first surface and a second surface as the back surface thereof, and provided with one or more first through holes extending from the first surface to the second surface respectively; a first conductor layer, comprising a first copper layer opposite to the first surface, and a hydrofluoric acid-resistant metal layer interposed between the first copper layer and the glass substrate, and covering the openings of the one or more first through holes on the first surface side, wherein the surface on the glass substrate side has a recessed portion at the position of the one or more first through holes, and the openings of the recessed portions are respectively The contour is larger than and surrounds the opening on the first surface side of the corresponding first through hole; and a second conductor layer, which includes a bonding layer, a seed layer arranged on the bonding layer, and a second copper layer arranged on the seed layer, wherein the bonding layer covers the side walls of the one or more first through holes, the inner surface of the recess, and the area of ​​the second surface surrounding the opening on the second surface side of the one or more first through holes, and the sum T1+T2 of the thickness T1 of the bonding layer and the thickness T2 of the seed layer is equal to or greater than the thickness T3 of the hydrofluoric acid resistant metal layer.

[0019] According to other aspects of the present invention, a wiring substrate involved in the above-mentioned aspect is provided, wherein, in the hydrofluoric acid-resistant metal layer, one or more second through holes are respectively arranged at the positions of the one or more first through holes, and the one or more second through holes form the recessed portion on the surface of the glass substrate side of the first conductor layer.

[0020] According to still another aspect of the present invention, there is provided a wiring substrate according to any one of the above aspects, wherein the thickness T1 is equal to or greater than the thickness T3.

[0021] According to still another aspect of the present invention, there is provided a wiring substrate according to any one of the above aspects, wherein the thickness T2 is equal to or greater than the sum T1+T3 of the thickness T1 and the thickness T3.

[0022] According to still another aspect of the present invention, there is provided a wiring substrate according to any one of the above aspects, wherein the thickness T2 is 0.5 μm or less.

[0023] According to yet another aspect of the present invention, there is provided a wiring substrate according to any one of the above aspects, wherein the thickness T1 is in the range of 10 nm to 0.5 μm, the thickness T2 is in the range of 100 nm to 0.5 μm, and the thickness T3 is in the range of 10 nm to 0.5 μm.

[0024] According to still another aspect of the present invention, there is provided a wiring substrate involved in any one of the above aspects, further comprising: a dielectric layer arranged on the first conductor layer, and an upper electrode arranged on the dielectric layer, wherein a portion of the first conductor layer opposite to the upper electrode is a lower electrode, and the upper electrode, the dielectric layer and the lower electrode constitute a capacitor.

[0025] According to still another aspect of the present invention, there is provided the wiring substrate according to the above aspect, wherein the lower electrode covers the opening on the first surface side of at least one of the one or more first through holes.

[0026] According to still another aspect of the present invention, there is provided a wiring substrate according to any one of the above aspects, wherein the one or more first through holes are a plurality of first through holes, and a portion of the first conductor layer and a portion of the second conductor layer constitute a solenoid coil.

[0027] According to still another aspect of the present invention, there is provided a wiring substrate involved in any one of the above aspects, further comprising: a dielectric layer arranged on the first conductor layer, and an upper electrode arranged on the dielectric layer, the portion of the first conductor layer opposite to the upper electrode being a lower electrode, the upper electrode, the dielectric layer and the lower electrode forming a capacitor, the one or more first through holes being a plurality of first through holes, a portion of the first conductor layer and a portion of the second conductor layer forming a solenoid coil, and the capacitor and the solenoid coil forming an LC filter.

[0028] It should be noted that LC filter is also called LC frequency filter. LC filter has a structure composed of an inductor (L) and a capacitor (C). LC filter uses the resonance phenomenon to allow electrical signals to flow through the circuit at a specific frequency and block other frequencies. It is a device that functions as a bandpass filter, low-pass filter, high-pass filter, or duplexer.

[0029] According to still another aspect of the present invention, there is provided a wiring substrate according to any one of the above aspects, wherein the hydrofluoric acid-resistant metal layer is made of a material selected from the group consisting of chromium, nickel, and a nickel-chromium alloy.

[0030] According to still another aspect of the present invention, there is provided a wiring substrate according to any one of the above aspects, wherein the adhesion layer is composed of one or more materials selected from the group consisting of titanium, chromium, and nickel, or oxides thereof, and the seed layer is composed of copper.

[0031] According to still another aspect of the present invention, there is provided a wiring substrate according to any one of the above aspects, which is an interposer.

[0032] According to still another aspect of the present invention, there is provided a packaging device including the wiring substrate according to any one of the above aspects, and a functional device mounted on the wiring substrate.

[0033] Here, a "functional device" is a device that operates by supplying at least one of power and an electric signal, a device that outputs at least one of power and an electric signal by external stimulation, or a device that operates by supplying at least one of power and an electric signal and outputs at least one of power and an electric signal by external stimulation. The functional device has a chip form such as a semiconductor chip or a chip having a circuit or element formed on a substrate made of a material other than a semiconductor such as a glass substrate. The functional device may include, for example, one or more of LSI, a memory, an imaging element, a light-emitting element, and MEMS (Micro Electro Mechanical Systems). MEMS is, for example, one or more of a pressure sensor, an acceleration sensor, a gyroscope sensor, a tilt sensor, a microphone, and an acoustic sensor. According to one example, the functional device is a semiconductor chip including an LSI.

[0034] According to still another aspect of the present invention, there is provided a method for manufacturing a wiring substrate, comprising: preparing a glass substrate having a first surface and a second surface as the back surface thereof; irradiating the glass substrate with a laser to form one or more modified portions on the glass substrate; forming a first conductor layer on the first surface in a manner covering the one or more modified portions, the first conductor layer comprising a first copper layer opposite to the first surface, and a hydrofluoric acid-resistant metal layer between the first copper layer and the glass substrate; etching the second surface with an etching solution containing hydrogen fluoride to cause the second surface to retreat and to form one or more modified portions at the positions of the one or more modified portions, respectively. The invention relates to a method for forming a first through hole in the first conductor layer; wet-etching a portion of the hydrofluoric acid-resistant metal layer exposed in the one or more first through holes to form a recess on the surface of the first conductor layer on the glass substrate side; forming a bonding layer, which covers the side walls of the one or more first through holes, the inner surface of the recess, and the second surface; forming a seed layer on the bonding layer; and forming a second copper layer on the seed layer, wherein the bonding layer, the seed layer, and the hydrofluoric acid-resistant metal layer are formed in such a manner that the sum T1+T2 of the thickness T1 of the bonding layer and the thickness T2 of the seed layer is equal to or greater than the thickness T3 of the hydrofluoric acid-resistant metal layer.

[0035] According to yet another aspect of the present invention, a method for manufacturing a wiring substrate involved in the above aspect is provided, further comprising: before irradiating the glass substrate with the laser, supporting the glass substrate on the first support body in a manner in which the second surface is opposite to the first support body; and after forming the first conductor layer and before forming the one or more first through holes, removing the first support body from the glass substrate.

[0036] According to still another aspect of the present invention, there is provided a method for manufacturing a wiring substrate according to any one of the above aspects, wherein the wet etching of the hydrofluoric acid-resistant metal layer is performed in a manner to form one or more second through holes in the hydrofluoric acid-resistant metal layer.

[0037] According to yet another aspect of the present invention, a method for manufacturing a wiring substrate involved in any one of the above aspects is provided, further comprising: after forming the first conductor layer and before forming the one or more first through holes, supporting a composite body including the glass substrate and the first conductor layer on the second support body in a manner such that the first conductor layer is opposite to the second support body.

[0038] According to the present invention, there is provided a technology capable of making disconnection between a wiring layer provided on a glass substrate and a TGV provided on the glass substrate less likely to occur. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] [ Figure 1 ] Figure 1 It is a cross-sectional view of a wiring substrate according to the first embodiment of the present invention.

[0040] [ Figure 2 ] Figure 2 Yes Figure 1 A cross-sectional view showing an enlarged portion of a wiring substrate shown in FIG.

[0041] [ Figure 3 ] Figure 3 It is shown Figure 1 A cross-sectional view showing a process step in a method for manufacturing a wiring substrate shown in FIG.

[0042] [ Figure 4 ] Figure 4 It is shown Figure 1 A cross-sectional view of other steps in the method for manufacturing a wiring substrate shown.

[0043] [ Figure 5 ] Figure 5 It is shown Figure 1 A cross-sectional view showing still another step in the method for manufacturing a wiring substrate shown.

[0044] [ Figure 6 ] Figure 6It is shown Figure 1 A cross-sectional view showing still another step in the method for manufacturing a wiring substrate shown.

[0045] [ Figure 7 ] Figure 7 It is shown Figure 1 A cross-sectional view showing still another step in the method for manufacturing a wiring substrate shown.

[0046] [ Figure 8 ] Figure 8 It is shown Figure 1 A cross-sectional view showing still another step in the method for manufacturing a wiring substrate shown.

[0047] [ Fig. 9 ] Fig. 9 It is shown Figure 1 A cross-sectional view showing still another step in the method for manufacturing a wiring substrate shown.

[0048] [ Fig.10 ] Fig.10 It is shown Figure 1 A cross-sectional view showing still another step in the method for manufacturing a wiring substrate shown.

[0049] [ Fig.11 ] Fig.11 It is shown Figure 1 A cross-sectional view showing still another step in the method for manufacturing a wiring substrate shown.

[0050] [ Fig.12 ] Fig.12 It shows that you can use Figure 1 A cross-sectional view of an example of a packaged device manufactured using a wiring substrate shown.

[0051] [ Fig.13 ] Fig.13 It is a cross-sectional view showing a part of a wiring substrate according to a comparative example.

[0052] [ Fig.14 ] Fig.14 This is a cross-sectional view showing a through hole provided in a glass substrate of a wiring substrate according to a first modification.

[0053] [ Fig.15 ] Fig.15 It is a cross-sectional view showing a through hole provided in a glass substrate of a wiring substrate according to a second modification.

[0054] [ Fig.16 ] Fig.16 This is a perspective view showing a portion of a wiring substrate according to a third modification.

[0055] [ Fig.17 ] Fig.17This is a cross-sectional view showing a portion of a wiring substrate according to a fourth variation.

[0056] [ Fig.18 ] Fig.18 This is a cross-sectional view showing a portion of a wiring substrate according to a fifth variation.

[0057] [ Fig.19 ] Fig.19 This is a cross-sectional view showing a portion of a wiring substrate involved in the sixth variation.

[0058] [ Fig. 20 ] Fig. 20 This is a cross-sectional view showing one step in the method for manufacturing a wiring substrate according to the second embodiment of the present invention.

[0059] [ Fig.21 ] Fig.21 It is a cross-sectional view showing other steps in the method for manufacturing the wiring substrate according to the second embodiment of the present invention.

[0060] [ Fig. 22 ] Fig. 22 This is a cross-sectional view showing one step in the method for manufacturing a wiring substrate according to the third embodiment of the present invention.

[0061] [ Fig.23 ] Fig.23 It is a cross-sectional view showing other steps in the method for manufacturing the wiring substrate according to the third embodiment of the present invention.

[0062] [ Fig.24 ] Fig.24 This is a cross-sectional view showing a step in the method for manufacturing a wiring substrate according to the fourth embodiment of the present invention.

[0063] [ Fig.25 ] Fig.25 It is a cross-sectional view showing other steps in the method for manufacturing the wiring substrate according to the fourth embodiment of the present invention. DETAILED DESCRIPTION

[0064] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are embodiments that further specify any of the above aspects. The matters described below may be incorporated into the above aspects individually or in combination.

[0065] In addition, the embodiments shown below illustrate the configuration for embodying the technical concept of the present invention, and the technical concept of the present invention is not limited by the material, shape, structure, etc. of the following components. In the technical concept of the present invention, various changes can be made within the technical scope specified by the claims described in the claims.

[0066] It should be noted that, for elements having the same or similar functions, the same reference symbols are marked in the drawings referred to below, and repeated descriptions are omitted. In addition, the drawings are schematic, and the relationship between the dimensions in one direction and the dimensions in another direction, and the relationship between the dimensions of a certain component and the dimensions of other components, etc. may be different from the actual situation.

[0067] <1> First Embodiment

[0068] <1.1> Wiring board

[0069] Figure 1 It is a cross-sectional view of a wiring substrate according to the first embodiment of the present invention. Figure 2 Yes Figure 1 A cross-sectional view showing an enlarged portion of a wiring substrate.

[0070] Figure 1 The wiring substrate 1 shown is a glass core wiring substrate. According to one example, the wiring substrate 1 is a wiring substrate used as an interposer, that is, a glass interposer.

[0071] The wiring substrate 1 includes a glass substrate 10 , a first conductor layer 20 , a dielectric layer 31 , an upper electrode 32 , an interlayer insulating film 40 , a conductor layer 50 , an insulating layer 60 , a second conductor layer 70 , an interlayer insulating film 80 , a conductor layer 90 , and an insulating layer 100 .

[0072] The glass substrate 10 has a first surface S1 and a second surface S2 which is the back surface thereof. The first surface S1 and the second surface S2 are parallel to each other.

[0073] One or more first through holes extending from the first surface S1 to the second surface S2 are provided in the glass substrate 10. Here, a plurality of first through holes are provided. Each first through hole tapers gradually from the second surface S2 to the front end of the first surface S1.

[0074] The first conductor layer 20 is a conductor pattern provided on the first surface S1. The conductor pattern includes a land portion, a wiring portion, and a lower electrode of a capacitor 30 described later. The first conductor layer 20 is a first wiring layer.

[0075] The first conductor layer 20 has a multi-layer structure. Specifically, the first conductor layer 20 includes: a first copper layer 24 facing the first surface S1, and a hydrofluoric acid resistant metal layer 21 between the first copper layer 24 and the glass substrate 10. Figure 2 As shown, the first conductor layer 20 further includes an adhesion layer 22 between the hydrofluoric acid resistant metal layer 21 and the first copper layer 24 , and a seed layer 23 between the adhesion layer 22 and the first copper layer 24 .

[0076] The first conductor layer 20 covers the opening of the first through hole on the first surface S1 side. The surface of the first conductor layer 20 on the glass substrate 10 side has a recessed portion at the position of the first through hole. Here, in the hydrofluoric acid-resistant metal layer 21, second through holes are provided at the positions of the first through holes. These second through holes form the above-mentioned recessed portion on the surface of the first conductor layer 20 on the glass substrate 10 side.

[0077] The contour of each opening (hereinafter sometimes referred to as the first opening) provided in the concave portion of the above-mentioned surface of the first conductor layer 20 is larger than and surrounds the opening (hereinafter sometimes referred to as the second opening) on ​​the first surface S1 side of the corresponding first through hole. That is, the contour of the orthographic projection of the first opening onto the plane perpendicular to the thickness direction of the wiring substrate 1 is larger than and surrounds the orthographic projection of the second opening onto the plane. The distance from the orthographic projection contour of the first opening onto the above-mentioned plane to the orthographic projection of the second opening onto the plane, that is, the width of the undercut portion (undercut) generated by the side etching described later, is in the range of 1 μm to 10 μm according to one example, and in the range of 0.1 μm to 5 μm according to another example.

[0078] The hydrofluoric acid-resistant metal layer 21 is composed of a metal material having excellent resistance to hydrofluoric acid etching compared to the glass substrate 10. The hydrofluoric acid-resistant metal layer 21 is composed of, for example, a material selected from the group consisting of chromium, nickel, and a nickel-chromium alloy. The thickness T3 of the hydrofluoric acid-resistant metal layer 21 is preferably in the range of 10 nm to 500 nm, more preferably in the range of 0.02 μm to 0.08 μm.

[0079] The adhesion layer 22 and the seed layer 23 are sequentially stacked on the hydrofluoric acid-resistant metal layer 21. The adhesion layer 22 and the seed layer 23 can use the materials exemplified for the adhesion layer 72 and the seed layer 73 described later, respectively. In the case where the first copper layer 24 is formed by electroplating, the adhesion layer 72 and the seed layer 73 are provided. The adhesion layer 72 can also be omitted. In addition, in the case where the first copper layer 24 is formed by other methods such as electroless plating or sputtering, both the adhesion layer 22 and the seed layer 23 can also be omitted.

[0080] The dielectric layer 31 and the upper electrode 32 are sequentially stacked on a portion of the first conductor layer 20. The portion of the first conductor layer 20 facing the upper electrode 32 is the lower electrode. The upper electrode 32, the dielectric layer 31, and the lower electrode constitute the capacitor 30, specifically, a MIM capacitor.

[0081] exist Figure 1 In the example shown, the lower electrode covers the opening on the first surface S1 side of the first through hole. The lower electrode may be away from the first through hole, but when it is arranged in a manner covering the opening on the first surface S1 side of the first through hole, the resistance caused by the wiring can be reduced and the wiring length can be shortened.

[0082] It should be noted that, here, the capacitor 30 is provided in a manner opposite to the first surface S1, but the capacitor may be provided on the second surface S2 side. Alternatively, the capacitor 30 may be provided in a manner opposite to the first surface S1, and another capacitor may be further provided on the second surface S2 side. The capacitor 30 may be omitted.

[0083] The interlayer insulating film 40 covers the first surface S1 and buries the first conductor layer 20, the dielectric layer 31, and the upper electrode 32. The interlayer insulating film 40 is provided with through holes at the positions of the soldering lands included in the first conductor layer 20 and the positions of the upper electrodes 32. According to one example, the interlayer insulating film 40 is an insulating resin layer.

[0084] The conductor layer 50 is a conductor pattern provided on the interlayer insulating film 40. The conductor pattern includes a pad portion provided on the main surface of the interlayer insulating film 40, and a through hole portion covering the side wall of the through hole provided in the interlayer insulating film 40. The pad portion is an external connection terminal. Each through hole portion connects the welding land portion or the upper electrode 32 included in the first conductor layer 20 to the pad portion.

[0085] The conductor layer 50 includes a seed layer 53 and a copper layer 54. The seed layer 53 and the copper layer 54 are sequentially stacked on the interlayer insulating film 40. The conductor layer 50 may further include a bonding layer between the interlayer insulating film 40 and the seed layer 53. The bonding layer and the seed layer 53 included in the conductor layer 50 may use the materials exemplified for the bonding layer 72 and the seed layer 73 described later, respectively. The seed layer 53 may also be omitted.

[0086] The insulating layer 60 at least partially covers the interlayer insulating film 40 and buries the conductive layer 50. The insulating layer 60 is provided with through holes at the positions of the pads included in the conductive layer 50. The insulating layer 60 is made of, for example, a solder resist.

[0087] The second conductor layer 70 is a conductor pattern including a portion covering the second surface S2 of the glass substrate 10, a portion covering the side wall of the first through hole provided in the glass substrate 10, and a portion covering the inner surface of the recess provided in the first conductor layer 20. The conductor pattern includes a welding area, a wiring portion, and a through hole portion. The portion covering the second surface S2 of the second conductor layer 70 is a second wiring layer, including a welding area and a wiring portion. The through hole portion is composed of a portion covering the side wall of the first through hole provided in the glass substrate 10, and a portion covering the inner surface of the recess provided in the first conductor layer 20.

[0088] The second conductor layer 70 has a multi-layer structure. Figure 2As shown, the second conductor layer 70 includes an adhesion layer 72, a seed layer 73, and a second copper layer 74. The adhesion layer 72, the seed layer 73, and the second copper layer 74 are sequentially stacked on the glass substrate 10.

[0089] The adhesive layer 72 covers the sidewall of the first through hole provided in the glass substrate 10, the inner surface of the recess provided in the first conductor layer 20, and the opening region of the second surface S2 surrounding the first through hole on the second surface S2 side. The adhesive layer 72 is conformal to these surfaces.

[0090] The adhesion layer 72 improves the adhesion of the seed layer 73 to the glass substrate 10. The adhesion layer 72 is preferably composed of one or more materials selected from the group consisting of titanium, chromium and nickel or their oxides, and more preferably composed of titanium or titanium oxide. The thickness T1 of the adhesion layer 72 is preferably in the range of 10nm to 0.5μm, and more preferably in the range of 20nm to 0.08μm. Here, the thickness T1 of the adhesion layer 72 is the thickness of the portion of the adhesion layer 72 provided on the second surface S2.

[0091] In order to increase the sum T1+T2 of the thickness T1 of the adhesion layer 72 and the thickness T2 of the seed layer 73, it is advantageous to increase the thickness T1. However, when the thickness T1 is increased, the connection resistance between the first conductor layer 20 and the second conductor layer 70 increases.

[0092] The seed layer 73 is disposed on the adhesion layer 72. The seed layer 73 is conformal to the adhesion layer 72. The seed layer 73 serves as a power supply layer in electroplating. The seed layer 73 is composed of, for example, copper. The thickness T2 of the seed layer 73 is preferably in the range of 100 nm to 0.5 μm, more preferably in the range of 200 nm to 0.4 μm. Here, the thickness T2 of the seed layer 73 is the thickness of the portion of the seed layer 73 disposed on the second surface S2.

[0093] In consideration of the role of the power supply layer, the seed layer 73 is preferably thicker. When the thickness T2 is increased, when the second conductor layer 70 is formed by the semi-additive method, unnecessary portions such as the seed layer 73 formed in a continuous film are removed by full-surface etching, and the surface area of ​​the second copper layer 74 is also removed. Therefore, when the thickness T2 is increased, the shape accuracy and dimensional accuracy of the wiring included in the second conductor layer 70 are reduced.

[0094] The second copper layer 74 is disposed on the seed layer 73. The second copper layer 74 is conformal with the seed layer 73. The thickness of the second copper layer 74 is, for example, in the range of 2 μm to 10 μm.

[0095] The sum T1+T2 of the thickness T1 of the adhesion layer 72 and the thickness T2 of the seed layer 73 is equal to or greater than the thickness T3 of the hydrofluoric acid resistant metal layer 21. That is, the thicknesses T1 to T3 satisfy the relationship shown in the following inequality (1).

[0096] T3 ≤ T1 + T2 … (1)

[0097] The sum T1+T2 is preferably greater than the thickness T3, more preferably at least twice the thickness T3, and further preferably at least six times the thickness T3. The thicknesses T2 and T3 may satisfy the relationship shown in the following inequality (1).

[0098] T3≤ T1… (2)

[0099] As described later, when the thicknesses T1 to T3 satisfy the above relationship, the seed layer 73 is unlikely to have a discontinuous portion due to undercutting between the bottom surface of the recess provided in the first conductor layer 20 and the side wall of the first through hole. Therefore, in the electroplating for forming the second copper layer 74, the deposition of copper in the recess provided in the first conductor layer 20 is unlikely to become insufficient.

[0100] The sum T1+T2 is preferably 20 times or less of the thickness T3, and more preferably 8 times or less of the thickness T3. When the second conductor layer 70 is formed by a semi-additive method, unnecessary portions such as the adhesion layer 72 and the seed layer 73 formed in a continuous film are removed by full-surface etching. When the sum T1+T2 is increased, the time required to remove these unnecessary portions becomes longer.

[0101] The thickness T2 is preferably equal to or greater than the sum T1 + T3 of the thickness T1 and the thickness T3. That is, the thicknesses T1 to T3 preferably satisfy the relationship shown in the following inequality (3).

[0102] T1 + T3 ≤ T2… (3)

[0103] When thicknesses T1 to T3 satisfy the above relationship, seed layer 73 is thicker than hydrofluoric acid resistant metal layer 21 and adhesion layer 72. With this configuration, seed layer 73 can function particularly well as a power supply layer during electroplating to form second copper layer 74.

[0104] The interlayer insulating film 80 covers the second surface S2 and buries the second conductor layer 70. Through holes are provided in the interlayer insulating film 80 at the positions of the pads included in the second conductor layer 70. According to one example, the interlayer insulating film 40 is an insulating resin layer.

[0105] The conductor layer 90 is a conductor pattern provided on the interlayer insulating film 80. The conductor pattern includes a pad portion provided on the main surface of the interlayer insulating film 80 and a through hole portion covering the side wall of the through hole provided in the interlayer insulating film 80. The pad portion is an external connection terminal. Each through hole portion connects the welding land portion included in the second conductor layer 70 to the pad portion.

[0106] The conductor layer 90 includes a seed layer 93 and a copper layer 94. The seed layer 93 and the copper layer 94 are sequentially stacked on the interlayer insulating film 80. The conductor layer 90 may further include a bonding layer between the interlayer insulating film 80 and the seed layer 93. The bonding layer and the seed layer 93 included in the conductor layer 90 may use the materials exemplified for the bonding layer 72 and the seed layer 73, respectively. The seed layer 93 may also be omitted.

[0107] The insulating layer 100 at least partially covers the interlayer insulating film 80 and buries the conductive layer 90. The insulating layer 100 is provided with through holes at the positions of the pads included in the conductive layer 90. The insulating layer 100 is made of, for example, a solder resist.

[0108] <1.2> Method for manufacturing wiring substrate

[0109] The wiring substrate 1 can be manufactured, for example, by the following method.

[0110] Figures 3 to 11 It is shown Figure 1 A cross-sectional view showing a method for manufacturing a wiring substrate.

[0111] <1.2.1>1st step

[0112] In this method, first, a glass substrate 10 having a first surface S1 and a second surface S2 as the back thereof is prepared. For example, contaminants are removed from the surface of an alkali-free glass plate having a thickness of 500 μm by ultrasonic cleaning or the like to obtain the glass substrate 10. It should be noted that the glass substrate 10 at this stage is thicker than the glass substrate 10 included in the wiring substrate 1. In addition, the glass substrate 10 at this stage is a large glass substrate having a larger size in a direction perpendicular to the thickness direction than the glass substrate 10 included in the packaging device described later.

[0113] <1.2.2> Second process

[0114] Next, the glass substrate 10 is irradiated with laser light from the first surface S1 toward the second surface S2. Figure 3As shown, one or more modified portions 11 are formed in the glass substrate 10. The modified portion 11 is, for example, a portion that has a difference in crystallinity, etc. between the portion not irradiated with the laser due to heating by laser irradiation. The modified portion 11 is formed at a position corresponding to the first through hole. The modified portion 11 extends from the first surface S1 to the second surface S2, for example, in the thickness direction of the glass substrate 10. The laser light amount is preferably adjusted so that the modified portion 11 extending from the first surface S1 does not reach the second surface S2.

[0115] The wavelength of the laser used here is below 535nm. The preferred wavelength of the laser is above 355nm and below 535nm. When the wavelength of the laser is less than 355nm, it is difficult to obtain sufficient laser output power, and it may be difficult to perform stable laser modification. On the other hand, when the wavelength of the laser is greater than 535nm, the irradiation spot becomes larger, and it is difficult to perform laser modification in a small range. In addition, due to the influence of heat, micro cracks are generated, and the glass substrate 10 is easily broken.

[0116] When using a pulse laser, the laser pulse width is preferably in the range of picoseconds to femtoseconds. When the laser pulse width is nanoseconds or longer, it is difficult to control the energy per pulse, microcracks are generated, and the glass substrate 10 is easily broken.

[0117] The energy of the laser pulse is preferably selected according to the glass composition and the type of laser modification to be produced, and is preferably in the range of 5 μJ to 150 μJ. By increasing the energy of the laser pulse, the length of the modified portion 11 can be increased proportionally.

[0118] <1.2.3>3rd process

[0119] Next, the first conductor layer 20 including the first copper layer 24 facing the first surface S1 and the hydrofluoric acid-resistant metal layer 21 interposed between the first copper layer 24 and the glass substrate 10 is formed on the first surface S1 to cover the modified portion 11 .

[0120] For example, first, Figure 4 As shown, a hydrofluoric acid resistant metal layer 21 and a seed layer 23 are sequentially formed on the first surface S1. Here, the hydrofluoric acid resistant metal layer 21 and the seed layer 23 are respectively formed in the form of continuous films. The hydrofluoric acid resistant metal layer 21 is formed, for example, by sputtering. The seed layer 23 is formed, for example, by sputtering or electroless plating. Before forming the seed layer 23, a hydrofluoric acid resistant metal layer 21 may be formed. Figure 2 The adhesion layer 22 is shown. The adhesion layer 22 is formed as a continuous film by, for example, sputtering or electroless plating. When the adhesion layer 22 is formed, the adhesion between the hydrofluoric acid resistant metal layer 21 and the seed layer 23 is improved.

[0121] Next, a mask pattern composed of an insulator and having an opening at a position corresponding to the first copper layer 24 is formed on the seed layer 23. The mask pattern is formed, for example, by providing a photoresist layer on the seed layer 23, and pattern-exposing and developing the photoresist layer. According to one example, a dry photoresist RD1225 manufactured by Showa Denko Materials Co., Ltd. is laminated on the seed layer 23, and the dry photoresist is pattern-exposed and developed in sequence, thereby obtaining a mask pattern composed of a resin.

[0122] Next, copper electroplating is performed using the seed layer 23 as a power supply layer. Thus, copper is deposited on the seed layer 23 at the position of the opening of the mask pattern, and a Figure 5 The first copper layer 24 is shown.

[0123] Then, the mask pattern is removed. For example, the dry film resist is dissolved and peeled off. Next, the entire surface of the first copper layer 24 side of the composite body including the first copper layer 24 and the glass substrate 10 is etched until the exposed portion of the seed layer 23 is removed. In addition, in the case where the adhesion layer 22 exists between the seed layer 23 and the hydrofluoric acid-resistant metal layer 21, the entire surface of the first copper layer 24 side of the composite body is further etched until the portion exposed by removing the exposed portion of the seed layer 23 in the adhesion layer 22 is also removed.

[0124] Through the above, we get Figure 5 The first conductor layer 20 shown. It should be noted that, as described above, the first conductor layer 20 includes a pad portion, a wiring portion, and a lower electrode.

[0125] <1.2.4> Step 4

[0126] Next, a dielectric layer 31 and an upper electrode 32 are sequentially formed on the lower electrode included in the first conductive layer 20 to obtain Figure 5 The capacitor 30 shown in FIG. 1 can be formed by the same method as the seed layer 23 and the first copper layer 24 included in the first conductor layer 20. The upper electrode 32 has a multilayer structure including a seed layer and a copper layer.

[0127] <1.2.5> Fifth step

[0128] Next, an insulating resin layer is provided on the surface of the capacitor 30 side of the composite body including the capacitor 30 and the glass substrate 10. According to one example, an insulating resin film ABF-GXT31 (32.5 μm thick) manufactured by Ajinomoto Fine-Techno Co., Inc. is laminated on the above surface and pre-cured. Next, blind holes are formed in the insulating resin layer by laser processing. Then, a desmear treatment is performed to remove the residue generated by the laser processing. By the above, Figure 6 An interlayer insulating film 40 is shown.

[0129] Next, a seed layer 53 is formed by sputtering or electroless plating. Here, the seed layer 53 is formed to cover the top of the interlayer insulating film 40, the side walls of the through holes provided therein, and the exposed portions of the first conductor layer 20 and the upper electrode 32 at the positions of the through holes.

[0130] Next, a mask pattern composed of an insulator and having an opening at a position corresponding to the copper layer 54 is formed on the seed layer 53. The mask pattern is formed, for example, by providing a photoresist layer on the seed layer 53, and pattern-exposing and developing the photoresist layer. According to one example, a dry film resist RD1225 manufactured by Showa Denko Materials Co., Ltd. is laminated on the seed layer 53, and the dry film resist is pattern-exposed and developed in sequence, thereby obtaining a mask pattern composed of a resin.

[0131] Next, copper electroplating is performed using the seed layer 53 as a power supply layer. Thus, copper is deposited on the seed layer 53 at the position of the opening of the mask pattern, and a Figure 6 Copper layer 54 is shown.

[0132] Then, the mask pattern is removed. For example, the dry film resist is dissolved and peeled off. Next, the entire surface of the copper layer 54 side of the composite body including the copper layer 54 and the glass substrate 10 is etched until the exposed portion of the seed layer 53 is removed. Through the above, the conductor layer 50 is obtained.

[0133] Next, a layer is provided on the interlayer insulating film 40. Figure 6 For example, a solder resist is provided on the interlayer insulating film 40 and patterned using photolithography or the like. Figure 6 structure.

[0134] <1.2.6> Step 6

[0135] Then, if Figure 7As shown in the figure, the composite body including the glass substrate 10 and the insulating layer 60 is supported on the second support 141 in such a manner that the insulating layer 60 faces the second support 141. Here, the second support 141 is attached to the composite body via an adhesive 142 for temporary attachment. The second support 141 is less likely to be damaged as the glass substrate 10 is thinned in the next process, and the composite body including the glass substrate 10 is easily handled.

[0136] As the adhesive 142, for example, REVALPHA (registered trademark) manufactured by Nitto Denko Corporation is used. As the second support 141, for example, a thin plate-shaped glass carrier is used. The second support 141 may not be made of glass, but may be made of metal, resin, or the like.

[0137] In view of the transportability of the thinned glass substrate 10 , the thickness of the second support 141 is preferably in the range of 0.7 mm to 10 mm. The thickness of the second support 141 can be appropriately set according to the thickness of the glass substrate 10 .

[0138] <1.2.7> Step 7

[0139] Next, the second surface S2 of the composite body supported by the second support 141 is etched using an etching solution containing hydrogen fluoride. Figure 8 As shown in the figure, the second surface S2 is retreated and the first through holes 12 are formed at the positions of the modified portions 11. When the second surface S2 is etched, the glass substrate 10 becomes thinner and the modified portions 11 are exposed. The modified portions 11 in the glass substrate 10 have a higher etching rate than other portions. Therefore, by this etching, the glass substrate 10 can be thinned and the first through holes 12 can be formed at the same time.

[0140] It should be noted that, in this etching, the hydrofluoric acid resistant metal layer 21 acts as an etching stopper film. Figure 8 In the embodiment, the first through hole 12 obtained by the etching has a truncated cone shape in which the diameter (or cross-sectional area) on the second surface S2 side is larger than the diameter (or cross-sectional area) on the first surface S1 side.

[0141] The etching amount of the glass substrate 10 can be appropriately set according to the thickness of the wiring substrate 1. For example, when the thickness of the glass substrate 10 before etching is 400 μm, the etching amount is preferably set in the range of 100 μm to 350 μm. The thickness of the glass substrate 10 after thinning is preferably set in the range of 50 μm to 300 μm.

[0142] The etching solution containing hydrogen fluoride is, for example, an aqueous solution of hydrogen fluoride. The etching solution may further contain one or more inorganic acids selected from the group consisting of nitric acid, hydrochloric acid, and sulfuric acid.

[0143] The concentration of hydrogen fluoride in the etching solution is, for example, in the range of 1.0 mass % to 6.0 mass %, preferably in the range of 2.0 mass % to 5.0 mass %. The concentration of the inorganic acid is, for example, in the range of 1.0 mass % to 20.0 mass %, preferably in the range of 3.0 mass % to 16.0 mass %. Preferably, etching is performed at an etching rate of 1.0 μm / min or less using an etching solution in which the concentrations of the components are set within the above ranges. The temperature of the etching solution during etching is preferably set in the range of 10° C. to 40° C.

[0144] <1.2.8> Step 8

[0145] Next, the portion of the hydrofluoric acid resistant metal layer 21 exposed in the first through hole 12 is subjected to wet etching, such as Fig. 9 As shown, a recessed portion is formed on the surface of the first conductor layer 20 on the glass substrate 10 side. Here, the hydrofluoric acid-resistant metal layer 21 is subjected to the above-mentioned wet etching to form a second through hole in the hydrofluoric acid-resistant metal layer 21.

[0146] Any etching solution may be used for the wet etching as long as it can remove the exposed portion of the hydrofluoric acid-resistant metal layer 21. As the etching solution, a chromium etching solution is preferably used.

[0147] According to one example, as the above-mentioned etching solution, an alkaline chromium etching solution manufactured by Nippon Chemical Industry Co., Ltd. containing potassium ferrocyanide and potassium hydroxide is used. Then, wet etching is performed for 1.5 minutes at a temperature of 40° C. According to such wet etching, only the exposed portion of the hydrofluoric acid-resistant metal layer 21 can be removed without damaging components other than the hydrofluoric acid-resistant metal layer 21, such as the glass substrate 10, the first copper layer 24, and the interlayer insulating film 40.

[0148] Here, as described above, the first through hole 12 has a truncated cone shape in which the diameter (or cross-sectional area) on the second surface S2 side is larger than the diameter (or cross-sectional area) on the first surface S1 side. Such a shape can promote the circulation of the etching liquid between the inside and outside of the first through hole 12, and effectively perform etching.

[0149] Before the wet etching, plasma treatment or ultrasonic cleaning using, for example, CF4 gas, oxygen, argon gas, or hydrogen gas is preferably performed to improve the wettability of the exposed portion of the hydrofluoric acid-resistant metal layer 21 to the etching solution. It is more preferable to perform both plasma treatment and ultrasonic cleaning. In this case, the wettability improvement effect is further improved.

[0150] <1.2.9> Step 9

[0151] Then, form Figure 2The adhesion layer 72 is shown. Here, the adhesion layer 72 is formed in the form of a continuous film, and the continuous film covers the side wall of the first through hole 12, the inner surface of the recessed portion formed in the first conductor layer 20, and the second surface S2. The adhesion layer 72 is formed in the form of a continuous film by, for example, sputtering or electroless plating. In order to deposit the metal on the undercut portion described later, the adhesion layer 72 is preferably formed by electroless plating.

[0152] Next, a layer is formed on the adhesion layer 72. Fig.10 Seed layer 73 is shown. Seed layer 73 is formed in a continuous film by sputtering or electroless plating, for example. In order to deposit metal toward the undercut portion, seed layer 73 is preferably formed by electroless plating.

[0153] The adhesion layer 72 and the seed layer 73 are formed so that the thickness T1 of the adhesion layer 72 , the thickness T2 of the seed layer 73 , and the thickness T3 of the hydrofluoric acid-resistant metal layer satisfy the above relationship.

[0154] <1.2.10> Step 10

[0155] Then, if Fig.10 As shown, a second copper layer 74 is formed on the seed layer 73 .

[0156] For example, first, a mask pattern composed of an insulator and having an opening at a position corresponding to the second copper layer 74 is formed on the seed layer 73. The mask pattern is formed, for example, by providing a photoresist layer on the seed layer 73, and pattern-exposing and developing the photoresist layer. According to one example, a dry photoresist RD1225 manufactured by Showa Denko Materials Co., Ltd. is laminated on the seed layer 73, and the dry photoresist is pattern-exposed and developed in sequence, thereby obtaining a mask pattern composed of a resin.

[0157] Next, copper electroplating is performed using the seed layer 73 as a power supply layer. Thus, copper is deposited on the seed layer 73 at the position of the opening of the mask pattern, and a Fig.10 The second copper layer 74 is shown.

[0158] Then, the mask pattern is removed. For example, the dry film resist is dissolved and peeled off. Next, the entire surface of the second copper layer 74 side of the composite body including the second copper layer 74 and the glass substrate 10 is etched to remove the exposed portion of the seed layer 73. Next, the entire surface of the second copper layer 74 side of the composite body is further etched until the exposed portion of the seed layer 73 in the adhesion layer 72 is also removed.

[0159] Through the above, we get Fig.10 The second conductor layer 70 is shown. It should be noted that, as described above, the second conductor layer 70 includes a pad portion and a wiring portion.

[0160] <1.2.11>Step 11

[0161] Next, the surface of the composite body including the second conductor layer 70 and the glass substrate 10 on the second conductor layer 70 side is subjected to the same treatment as in the fifth step to provide Fig.11 An interlayer insulating film 80 , a conductive layer 90 and an insulating layer 100 are shown.

[0162] <1.2.12> Step 12

[0163] Then, the second support 141 and the adhesive 142 are removed from the composite body including the glass substrate 10, the first conductor layer 20, and the second conductor layer 70. Figure 1 The wiring substrate 1 is shown.

[0164] <1.3>Packaging device

[0165] The wiring substrate 1 described above can be used for manufacturing a packaged device.

[0166] Fig.12 It shows that you can use Figure 1 A cross-sectional view of an example of a packaged device manufactured using a wiring substrate shown. Fig.12 The packaged device shown is, for example, a high-frequency device equipped with an LC filter. Fig.12 The package device shown includes a wiring substrate 1 , a functional device 2 , a chip component 3 , and conductors 4 and 5 for bonding.

[0167] The wiring substrate 1 is a reference Figure 1 The wiring substrate 1 may further include at least one of the conductors 4 and 5 for bonding.

[0168] The bonding conductors 4 and 5 are solder balls here. The bonding conductor 4 is provided on the pad portion included in the conductor layer 50. The bonding conductor 4 bonds the functional device 2 to the wiring substrate 1. The bonding conductor 5 is provided on the pad portion included in the conductor layer 90. The bonding conductor 5 can bond the packaged device to other wiring substrates such as a main board.

[0169] As described above, the functional device 2 is a device that works by supplying at least one of power and an electric signal; a device that outputs at least one of power and an electric signal by external stimulation; or a device that works by supplying at least one of power and an electric signal and outputs at least one of power and an electric signal by external stimulation. The functional device 2 has a chip form such as a semiconductor chip or a chip having a circuit or element formed on a substrate made of a material other than a semiconductor such as a glass substrate. The functional device 2 may include, for example, one or more of an LSI, a memory, an imaging element, a light-emitting element, and a MEMS. MEMS is, for example, one or more of a pressure sensor, an acceleration sensor, a gyro sensor, a tilt sensor, a microphone, and an acoustic sensor. According to one example, the functional device is a semiconductor chip including an LSI.

[0170] The functional device 2 is mounted on the wiring substrate 1. Here, the functional device 2 is mounted on the wiring substrate 1 by flip-chip bonding. The functional device 2 may also be mounted on the wiring substrate 1 by other surface mounting techniques. The packaged device may include two or more functional devices 2.

[0171] The chip component 3 is a passive component that can be surface mounted, such as a chip resistor, a chip capacitor, and a chip inductor. The chip component 3 is mounted on the wiring substrate 1. Here, the chip component 3 is mounted on the wiring substrate 1 by die bonding and wire bonding. The chip component 3 can also be mounted on the wiring substrate 1 by other surface mounting techniques. The packaging device may include more than two chip components 3. The chip component 3 may also be omitted. Here, as an example, the chip component 3 is a chip inductor, which together with the capacitor 30 constitutes an LC filter.

[0172] <1.4>Effect

[0173] The above-mentioned technology exerts the effects described below, for example.

[0174] <1.4.1> Processability

[0175] According to the above-mentioned manufacturing method, the glass substrate 10 is less likely to be damaged, and excellent handling properties can be achieved. This will be described below.

[0176] When through holes are formed in a glass substrate, its mechanical strength may be reduced. In addition, a glass substrate with a small thickness, for example, a glass substrate with a thickness of 300 μm or less, is easily cracked during transportation for forming a conductive part such as a circuit, and is difficult to handle.

[0177] In the above method, when the first conductor layer 20 is formed on the first surface S1, the glass substrate 10 is relatively thick and is therefore less likely to be damaged. In addition, the composite body including the glass substrate 10 and the first conductor layer 20 has high strength even after the glass substrate 10 is thinned and the first through hole 12 is formed. Therefore, it is difficult for the glass substrate 10 to be damaged in the subsequent process. Moreover, the second support body 141 makes it more difficult for the glass substrate 10 to be damaged. In addition, by forming the second conductor layer 70 before removing the second support body 141, the strength of the composite body is improved, so it is difficult for the glass substrate 10 to be damaged even after the second support body 141 is removed from the composite body. Therefore, according to the above manufacturing method, it is difficult for the glass substrate 10 to be damaged, and the operation is easy.

[0178] <1.4.2>Productivity

[0179] Furthermore, according to the above-mentioned manufacturing method, high productivity can be achieved as described below.

[0180] In TSV technology, methods such as the Bosch process using dry etching have been established as methods for forming through holes in silicon substrates. However, it takes a long time to form through holes in glass substrates using dry etching, and it is not practical.

[0181] In the above manufacturing method, the first through hole 12 is also formed by wet etching for thinning the glass substrate 10. In addition, the first through hole 12 is formed at the position of the modified portion 11 generated by laser irradiation. In the glass substrate 10, the modified portion 11 can be etched at a higher etching rate than other portions. Therefore, according to the above manufacturing method, high productivity can be achieved.

[0182] <1.4.3>Electrical characteristics

[0183] Furthermore, the wiring substrate 1 obtained by the above method has excellent electrical characteristics at the connection portion between the wiring layer provided on the glass substrate 10 and the TGV provided on the glass substrate.

[0184] Fig.13 It is a cross-sectional view showing a part of a wiring substrate according to a comparative example.

[0185] In reference Figures 1 to 11 In the method described above, in the seventh step, etching is performed using an etching solution containing hydrogen fluoride to form the first through hole 12 in the glass substrate 10. The structure immediately after etching is as shown in FIG. Fig.13 As shown, in the first through hole 12, there may be etching residue 10ER (also referred to as glass residue) of the glass substrate 10 on the hydrofluoric acid resistant metal layer 21. Fig.13As shown, when the second conductor layer 70 is formed without removing the etching residue 10ER, the etching residue 10ER will hinder the electrical connection between the first conductor layer 20 and the second conductor layer 70 .

[0186] In the above method, in the eighth step after the seventh step, the portion of the hydrofluoric acid-resistant metal layer 21 exposed at the position of the first through hole 12 is removed by wet etching. Since wet etching is isotropic etching, when this etching is performed, the portion of the hydrofluoric acid-resistant metal layer 21 located directly below the etching residue 10ER is also removed by side etching. Therefore, when this etching is performed, the etching residue 10ER is also removed. In addition, generally speaking, the resistivity of the material of the hydrofluoric acid-resistant metal layer 21 is larger than that of copper or the like. Therefore, when the portion of the hydrofluoric acid-resistant metal layer 21 exposed at the position of the first through hole 12 is removed, the connection resistance between the first conductor layer 20 and the second conductor layer 70 can be reduced.

[0187] In the above method, the portion of the hydrofluoric acid-resistant metal layer 21 exposed at the position of the first through hole 12 is removed by isotropic etching, that is, wet etching. Figure 2 As shown, not only the portion of the hydrofluoric acid resistant metal layer 21 corresponding to the opening on the first surface S1 side of the first through hole 12 is removed, but also the portion around the opening is removed by side etching. That is, an undercut portion is generated in the hydrofluoric acid resistant metal layer 21. The undercut portion increases the contact area between the first conductor layer 20 and the second conductor layer 70.

[0188] Therefore, the wiring substrate 1 obtained by the above method has excellent electrical characteristics at the connection portion between the wiring layer provided on the glass substrate 10 and the TGV provided on the glass substrate.

[0189] <1.4.4> Connection reliability

[0190] Furthermore, the wiring substrate 1 obtained by the above method has excellent connection reliability between the wiring layer provided on the glass substrate 10 and the TGV provided on the glass substrate.

[0191] Fig.13 The etching residue 10ER shown reduces the adhesion between the hydrofluoric acid-resistant metal layer 21 and the second conductor layer 70, and thus may reduce the connection reliability between the first conductor layer 20 and the second conductor layer 70. In the above method, in the eighth step after the seventh step, the portion of the hydrofluoric acid-resistant metal layer 21 exposed at the position of the first through hole 12 is removed by wet etching. When the portion of the hydrofluoric acid-resistant metal layer 21 exposed at the position of the first through hole 12 is removed, the etching residue 10ER located on the portion is also removed.

[0192] Furthermore, in the above-described wiring substrate 1, stress is concentrated on the connection portion between the first conductor layer 20 and the second conductor layer 70. Therefore, disconnection of the connection portion greatly affects the connection reliability.

[0193] In the wiring substrate 1, the hydrofluoric acid-resistant metal layer 21 has an undercut portion, and the undercut portion is at least partially buried by the second conductor layer 70. When a force in a direction of pulling the portion of the composite layer of the seed layer 73 and the second copper layer 74 located in the first through hole 12 is applied to the portion of the composite layer 70 located in the first through hole 12, it is difficult to cause the above-mentioned portion located in the first through hole 12 to move.

[0194] Therefore, the wiring substrate 1 obtained by the above method has excellent connection reliability between the wiring layer provided on the glass substrate 10 and the TGV provided on the glass substrate.

[0195] <1.4.5> Yield

[0196] Furthermore, according to the above method, disconnection between the wiring layer provided on the glass substrate 10 and the TGV provided on the glass substrate can be made less likely to occur, and thus a high yield can be achieved. This will be described below.

[0197] As described above, by the wet etching performed in the eighth step, Figure 2 As shown, an undercut portion is generated in the hydrofluoric acid resistant metal layer 21. In the ninth step of forming the adhesion layer 72 and the seed layer 73, the material of the adhesion layer 72 and the material of the seed layer 73 are difficult to be deposited in the undercut portion, compared with the area corresponding to the opening on the first surface S1 side of the first through hole 12 among the side walls of the first through hole 12 and the bottom surface of the recess formed in the first conductor layer 20. Therefore, in the case where the sum T1+T2 of the thickness T1 of the adhesion layer 72 and the thickness T2 of the seed layer 73 is less than the thickness T3 of the hydrofluoric acid resistant metal layer 21, the seed layer 73 having a discontinuous portion may be formed near the undercut portion. For example, the seed layer 73 having an annular discontinuous portion surrounding the opening on the first surface S1 side of the first through hole 12 may be formed.

[0198] When the seed layer 73 has such a discontinuous portion, power cannot be supplied to the portion of the seed layer 73 surrounded by the annular discontinuous portion during the copper electroplating performed in the tenth step. As a result, a gap may be generated between the second copper layer 74 and the portion of the seed layer 73 surrounded by the annular discontinuous portion at the position of the recess formed in the first conductor layer 20. That is, a disconnection occurs between the wiring layer provided on the glass substrate 10 and the TGV provided on the glass substrate.

[0199] In reference Figures 1 to 11In the method described, the sum T1+T2 of the thickness T1 of the adhesion layer 72 and the thickness T2 of the seed layer 73 is made equal to or greater than the thickness T3 of the hydrofluoric acid resistant metal layer 21. When the adhesion layer 72 and the seed layer 73 are formed in a manner satisfying this relationship, the above-mentioned discontinuous portion can be reliably prevented from being generated in the seed layer 73. Therefore, the above-mentioned void can be prevented from being generated. Therefore, it is difficult for the wiring layer provided on the glass substrate 10 and the TGV provided on the glass substrate to be disconnected, and a high yield can be achieved.

[0200] In this method, thickness T1 is preferably equal to or greater than thickness T3. When adhesion layer 72 is formed so as to satisfy this relationship, the above-mentioned discontinuous portion can be more reliably prevented from being generated in seed layer 73.

[0201] In addition, in this method, the thickness T2 is preferably equal to or greater than the sum of the thickness T1 and the thickness T3, T1+T3. During the electroplating for forming the second copper layer 74, when the portion of the seed layer 73 located in the first through hole 12 is insufficiently supplied with power, the deposition of copper in the first through hole 12 becomes insufficient, and thus, a disconnection may occur between the wiring layer provided on the glass substrate 10 and the TGV provided on the glass substrate. When the adhesion layer 72 and the seed layer 73 are formed in a manner satisfying the above relationship, the above disconnection caused by insufficient power supply is unlikely to occur.

[0202] <1.5> Modification

[0203] Various modifications can be made to the above-described wiring substrate 1 and packaging device.

[0204] <1.5.1>First through hole

[0205] Fig.14 It is a cross-sectional view showing a through hole provided in a glass substrate of a wiring substrate according to a first modification. Fig.15 1 is a cross-sectional view showing a through hole provided in a glass substrate of a wiring substrate according to a second modification. The wiring substrates according to the first and second modifications each adopt a through hole 12, except that the first through hole 12 is Fig.14 and Fig.15 Except for the structure, it is the same as the above-mentioned wiring substrate 1.

[0206] In the above wiring substrate 1, the first through hole 12 provided in the glass substrate 10 gradually tapers from the second surface S2 to the front end of the first surface S1. That is, the first through hole 12 is a positive taper. Fig.14 and Fig.15 As shown, the first through hole 12 may include a forward tapered portion tapering from the second surface S2 toward the first surface S1 , and an inverse tapered portion tapering from the first surface S1 toward the second surface S2 .

[0207] Here, the forward tapered portion extends from the second surface S2 to the first surface S1 and decreases in diameter from the second surface S2 to the first surface S1. In addition, the reverse tapered portion extends from the first surface S1 to the second surface S2 and increases in diameter from the first surface S1 to the second surface S2.

[0208] exist Fig.14 In the structure, the position where the first through hole 12 has the minimum diameter is located at a distance from the first surface S1 that is 0.4 to 0.6 times the thickness T of the glass substrate 10. Fig.15 In the structure, the position where the first through hole 12 has the minimum diameter is at a distance from the first surface S1 that is not more than 0.2 times the thickness T of the glass substrate 10 .

[0209] exist Fig.14 and Fig.15 In the structure shown, the position where the first through hole 12 has a minimum diameter (or the position where the area of ​​the cross section parallel to the first surface S1 has a minimum value) is away from the first surface S1. Fig.14 or Fig.15 In the case of a structure with Figure 2 Compared with the structure of , the stress applied to the connection portion between the first conductor layer 20 and the second conductor layer 70 can be reduced, so the connection reliability between the wiring layer provided on the glass substrate 10 and the TGV provided on the glass substrate can be further improved.

[0210] <1.5.2> Inductors

[0211] The package device described above includes an inductor as the chip component 3. As described above, the inductor and the capacitor 30 can be combined to form an LC filter.

[0212] The inductor may be built in the wiring substrate 1. When the inductor is built in the wiring substrate 1, for example, the wiring length can be shortened, the electrical characteristics and transmission characteristics can be improved accordingly, or the package device can be miniaturized or reduced in height.

[0213] The inductor built into the wiring substrate 1 is, for example, a spiral coil. The wiring substrate 1 may include a portion of the first conductor layer 20 as a spiral coil, and may include a portion of the second conductor 70 as a spiral coil. Alternatively, the wiring substrate 1 may include a portion of the first conductor 20 as a spiral coil and a portion of the second conductor 70 as another spiral coil.

[0214] The wiring substrate 1 may include a solenoid coil described below as an inductor.

[0215] Fig.16 FIG. 1 is a perspective view showing a portion of a wiring substrate according to a third variant. Fig.16In the above description, the solenoid coil 110 is described as an example of an inductor that can be built in the wiring substrate 1. The wiring substrate according to the third modification is the same as the above-described wiring substrate 1 except that the solenoid coil 110 is included.

[0216] The solenoid coil 110 is constituted by a part of the first conductor layer 20 and a part of the second conductor layer 70. Specifically, the solenoid coil 110 includes a first conductor path 20A, a second conductor path 70A, and a third conductor path 70B.

[0217] Each first conductor path 20A is a part of the first conductor layer 20. The first conductor paths 20A have a shape extending in a first direction parallel to the first surface S1, and are arranged at a certain pitch in a second direction parallel to the first surface S1 and intersecting the first direction. Each first conductor path 20A has a first end and a second end. In the glass substrate 10, first through holes 12 are provided at the positions of the first end and the second end.

[0218] Each second conductor path 70A is a part of the second conductor layer 70 located on the second surface S2. The second conductor paths 70A have a shape extending in a third direction parallel to the second surface S2 and intersecting the first and second directions, and are arranged at a certain pitch in the second direction. Each second conductor path 70A has a third end opposite to the first end of a certain first conductor path 20A, and a third end opposite to the second end of the first conductor path 20A adjacent to the preceding first conductor path 20A.

[0219] Each third conductor path 70B is a portion of the second conductor layer 70 located in the first through hole 12. The third conductor path 70B connects the third end and the fourth end of each second conductor path 70A to the first end of a first conductor path 20A and the second end of the adjacent first conductor path 20A, respectively.

[0220] The solenoid coil 110 has a structure in which a plurality of segments are connected in series, and each of the plurality of segments includes the first conductor path 20A, the third conductor path 70B, the second conductor path 70A, and the third conductor path 70B in sequence. In addition, the spiral axis of the solenoid coil 110 is parallel to the second direction. The solenoid coil 110 can be combined with the capacitor 30 to form an LC filter.

[0221] As mentioned above, in reference Fig.13 In the structure described above, the connection resistance between the first conductor layer 20 and the second conductor layer 70 is large. Therefore, the connection portion between the first conductor path 20A and the third conductor path 70B has a Fig.13In the case of the above-described structure, the connection resistance between the first conductor path 20A and the third conductor path 70B is large. Therefore, in this case, it is difficult to realize an LC filter having excellent electrical characteristics and transmission characteristics, especially transmission characteristics in a high frequency region.

[0222] In contrast, in the above-mentioned solenoid coil 110, the connection portion between the first conductor path 20A and the third conductor path 70B has a reference Figure 2 The structure of the description. Figure 2 In the structure, the connection resistance between the first conductor layer 20 and the second conductor layer 70 is small. Therefore, in the solenoid coil 110, the connection resistance between the first conductor path 20A and the third conductor path 70B is small. Therefore, when the solenoid coil 110 is combined with the capacitor 30, an LC filter with excellent electrical characteristics and transmission characteristics can be realized.

[0223] The solenoid coil 110 is formed by a part of the first conductor layer 20 and a part of the second conductor layer 70. A solenoid coil having the same structure may be formed by a part of the first conductor layer 20 and a part of the conductor layer 50 or by a part of the second conductor layer 70 and a part of the conductor layer 90.

[0224] <1.5.3>Thickness T1 to T3

[0225] Fig.17 1 is a cross-sectional view showing a portion of a wiring board according to a fourth modification. The wiring board according to the fourth modification is the same as the above-described wiring board 1 except that thicknesses T1 to T3 satisfy the relationship described below.

[0226] In reference Figures 1 to 11 In the method described, in the tenth step, the second copper layer 74 is formed, and then the entire surface of the second copper layer 74 side of the composite body including the second copper layer 74 and the glass substrate 10 is etched to remove the exposed portion of the seed layer 73. When this etching is performed, the surface area of ​​the second copper layer 74 is also removed. As a result, not only the thickness of the portion constituting the wiring in the second copper layer 74 is reduced, but also the width of the portion is reduced. Therefore, when the second copper layer 74 is formed thicker, the shape and dimensional accuracy of the wiring included in the second conductor layer 70 are reduced.

[0227] exist Figure 2 In the structure, the thickness T1 of the adhesion layer 72 is less than the thickness T3 of the hydrofluoric acid resistant metal layer 21. Therefore, the seed layer 73 needs to be formed thicker so that the sum T1+T2 of the thickness T1 of the adhesion layer 72 and the thickness T2 of the seed layer 73 is greater than the thickness T3.

[0228] In contrast, Fig.17In the structure, the thickness T1 is greater than the thickness T3 of the hydrofluoric acid-resistant metal layer 21. When the thickness T1 of the adhesion layer 72 is made equal to or greater than the thickness T3 of the hydrofluoric acid-resistant metal layer 21, the sum T1+T2 of the thickness T1 of the adhesion layer 72 and the thickness T2 of the seed layer 73 can be made equal to or greater than the thickness T3 of the hydrofluoric acid-resistant metal layer 21 without increasing the thickness T2 of the seed layer 73. That is, it is possible to suppress the reduction in the shape and dimensional accuracy of the wiring included in the second conductor layer 70, and therefore, it is possible to suppress the reduction in electrical characteristics caused by them.

[0229] <1.5.4>Copper layer

[0230] Fig.18 1 is a cross-sectional view showing a part of a wiring board according to a fifth modification. The wiring board according to the fifth modification is the same as the above-described wiring board 1 except that the second copper layer 74 has a structure described later.

[0231] exist Figure 2 In the structure of , at the position of the first through hole 12, the second copper layer 74 is conformal to the seed layer 73. Fig.18 In the structure of , the second copper layer 74 buries the entire first through hole 12 whose sidewalls are formed with the adhesion layer 72 and the seed layer 73. That is, the former structure is a conformal form, and the latter structure is a filling form.

[0232] In each through hole, the copper layer may be in a conformal form or a filled form. However, in the case of a filled form, the electrical characteristics and transmission characteristics of the connection between the wiring layer provided on the glass substrate 10 and the TGV provided on the glass substrate can be improved compared to the case of a conformal form.

[0233] <1.5.5> Hydrofluoric acid resistant metal layer

[0234] Fig.19 1 is a cross-sectional view showing a part of a wiring board according to a sixth modification. The wiring board according to the sixth modification is the same as the above-described wiring board 1 except that the first conductor layer 20 has the following structure.

[0235] exist Figure 2 In the structure of , the second through hole is formed in the hydrofluoric acid resistant metal layer 21 at the position of the first through hole 12, thereby forming a recess in the first conductor layer 20 at the position of the first through hole 12. Fig.19 In the structure of FIG. 1 , the hydrofluoric acid-resistant metal layer 21 has a recessed portion at the position of the first through hole 12 . The recessed portion constitutes a recessed portion of the first conductor layer 20 .

[0236] If you can remove the reference Fig.13The etching residue 10ER described above can also be used to complete the etching of the hydrofluoric acid-resistant metal layer 21 at the position of the first through hole 12 before the through hole is formed in the hydrofluoric acid-resistant metal layer 21. Fig.19 In the case of a structure of, in order to reliably remove the etching residue 10ER, the average depth D of the recessed portion provided in the hydrofluoric acid-resistant metal layer 21 is preferably set to be 50% or more of the thickness T3 of the portion of the hydrofluoric acid-resistant metal layer 21 where the recessed portion is not provided. Here, the average depth D of the recessed portion provided in the hydrofluoric acid-resistant metal layer 21 is a value obtained by connecting the end portions of the first surface S1 on both sides of the first through hole 12 with a line when observing the cross section at a position passing through the midpoint of the first through hole 12 using an electron microscope, and setting the distance from the recessed portion of the hydrofluoric acid-resistant metal layer 21 located directly above the end portions to be the depth of the recessed portion, and averaging the lowest 10 measured values ​​between the end portions of the first surface S1 on both sides of the first through hole 12 with equal measurement intervals.

[0237] In addition, when the portion of the hydrofluoric acid-resistant metal layer 21 corresponding to the first through hole 12 is not completely removed, the portion of the hydrofluoric acid-resistant metal layer 21 remaining at the position of the first through hole 12 may reduce the above-mentioned electrical characteristics and transmission characteristics. From the viewpoint of electrical characteristics or transmission characteristics, the average depth D is preferably set to 70% or more of the thickness T3.

[0238] When the etching is terminated before a through hole is formed in the hydrofluoric acid-resistant metal layer 21, the time required for etching can be shortened. In consideration of this effect, the average depth D is preferably set to 90% or less of the thickness T3.

[0239] <1.5.6> Other variations

[0240] The above-mentioned wiring substrate 1 and packaging device may also be subjected to other modifications.

[0241] For example, Figure 1 The wiring substrate 1 includes only one laminate of the interlayer insulating film 40 and the conductor layer 50 on the first surface S1. Two or more laminates may be laminated on the first surface S1. Alternatively, the laminate may be omitted.

[0242] Likewise, Figure 1 The wiring substrate 1 includes only one laminate of the interlayer insulating film 80 and the conductor layer 90 on the second surface S2. Two or more laminates may be laminated on the second surface S2. Alternatively, the laminate may be omitted.

[0243] <2> Second Embodiment

[0244] The second embodiment of the present invention is the same as the first embodiment except that the wiring substrate is manufactured by the following method.

[0245] <2.1> Method for manufacturing wiring substrate

[0246] Fig. 20 This is a cross-sectional view showing one step in the method for manufacturing a wiring substrate according to the second embodiment of the present invention. Fig.21 It is a cross-sectional view showing other steps in the method for manufacturing the wiring substrate according to the second embodiment of the present invention.

[0247] As described below, the manufacturing method according to the second embodiment implements the 13th and 14th steps instead of the 1st and 2nd steps, and implements the 15th step between the 6th and 7th steps, and is the same as the reference 1. Figures 1 to 11 The manufacturing method described is the same.

[0248] <2.1.1>Step 13

[0249] In this method, first, a glass substrate 10 having a first surface S1 and a second surface S2 as the back thereof is prepared. The thickness of the glass substrate 10 is preferably smaller than the thickness of the glass substrate used in the first step. For example, the glass substrate 10 is obtained by removing contaminants from the surface of an alkali-free glass plate having a thickness of 130 μm by ultrasonic cleaning or the like. It should be noted that the glass substrate 10 at this stage is a large glass substrate having a larger size in a direction perpendicular to the thickness direction than the glass substrate 10 included in the packaging device.

[0250] Then, if Fig. 20 As shown, the first support 151 is adhered to the second surface S2 via an adhesive 152 for temporary adhesion. As the first support 151, for example, a thin plate-shaped glass carrier is used. The first support 151 may not be made of glass, but may be made of metal or resin, etc. In view of the transportability of the glass substrate 10, the thickness of the first support 151 is preferably in the range of 0.7 mm to 10 mm. The thickness of the first support 151 can be appropriately set according to the thickness of the glass substrate 10.

[0251] <2.1.2> Step 14

[0252] Next, the glass substrate 10 is irradiated with laser light from the first surface S1 toward the second surface S2. Fig. 20 As shown, one or more modified portions 11 are formed in the glass substrate 10. The modified portion 11 is formed at a position corresponding to the first through hole. The modified portion 11 extends from the first surface S1 to the second surface S2, for example, in the thickness direction of the glass substrate 10. The laser light intensity is preferably adjusted so that the modified portion 11 extending from the first surface S1 reaches the second surface S2 but does not reach the back side of the surface of the first support 151 opposite to the second surface S2.

[0253] <2.1.3> Steps 3 to 6

[0254] Next, the glass substrate 10 supported by the first support 151 is subjected to the third to sixth steps in sequence. Fig.21 The structure shown.

[0255] <2.1.4> Step 15

[0256] Then, the first support 151 and the adhesive 152 are removed from the composite body including the glass substrate 10 , the first conductive layer 20 , the second support 141 , and the like.

[0257] <2.1.5> Steps 7 to 12

[0258] Furthermore, the composite body including the glass substrate 10 and the first conductor layer 20 is sequentially subjected to the seventh to twelfth steps. Figure 1 The wiring substrate 1 is shown.

[0259] <2.2>Effect

[0260] The second embodiment achieves the same effects as those of the first embodiment.

[0261] In the second embodiment, the modified portion 11 is formed so as to extend from the first surface S1 to the second surface S2. Therefore, there is no variation in the length of the modified portion 11 in the glass substrate 10. Therefore, according to the second embodiment, it is easy to reduce the variation in the diameter of the first through hole 12 compared to the first embodiment, and achieve higher processing accuracy.

[0262] <2.3> Modification

[0263] The above-mentioned manufacturing method, the wiring substrate obtained by the manufacturing method, and the package device including the wiring substrate may be modified in the same manner as described in the first embodiment, for example.

[0264] <3> Third Embodiment

[0265] The third embodiment of the present invention is the same as the first embodiment except that the wiring board is manufactured by the following method.

[0266] <3.1> Method for manufacturing wiring substrate

[0267] Fig. 22 This is a cross-sectional view showing one step in the method for manufacturing a wiring substrate according to the third embodiment of the present invention. Fig.23 It is a cross-sectional view showing other steps in the method for manufacturing the wiring substrate according to the third embodiment of the present invention.

[0268] As described below, the manufacturing method according to the third embodiment is the same as that of the reference embodiment except that the second step is omitted and the sixteenth step is performed between the sixth step and the seventh step. Figures 1 to 11 The manufacturing method described is the same.

[0269] <3.1.1> Steps 1 and 3 to 6

[0270] First, the first step is carried out, and then the third step is carried out instead of the second step. In the third step, first, Fig. 22 structure. Fig. 22 The structure is similar to that of Figure 4 Then, the remaining treatments in step 3 are carried out, and then steps 4 to 6 are carried out in sequence. Fig.23 structure.

[0271] <3.1.2> Step 16

[0272] Next, the glass substrate 10 is irradiated with laser light from the second surface S2 toward the first surface S1. Figure 7 As shown, one or more modified portions 11 are formed in the glass substrate 10. The modified portion 11 is formed at a position corresponding to the first through hole. The modified portion 11 extends from the first surface S1 to the second surface S2, for example, in the thickness direction of the glass substrate 10. The laser light intensity is preferably adjusted so that the modified portion 11 extending from the first surface S1 does not reach the second surface S2. The laser irradiation conditions can be the same as those in the second step, for example.

[0273] <3.1.3> Steps 7 to 12

[0274] Furthermore, the composite body including the glass substrate 10 and the first conductor layer 20 is sequentially subjected to the seventh to twelfth steps. Figure 1 The wiring substrate 1 is shown.

[0275] <3.2>Effect

[0276] The third embodiment achieves the same effects as those of the first embodiment.

[0277] <3.3> Modification

[0278] The above-mentioned manufacturing method, the wiring substrate obtained by the manufacturing method, and the package device including the wiring substrate may be modified in the same manner as described in the first embodiment, for example.

[0279] <4> Fourth embodiment

[0280] The fourth embodiment of the present invention is the same as the first embodiment except that the wiring board is manufactured by the following method.

[0281] <4.1> Method for manufacturing wiring board

[0282] Fig.24 This is a cross-sectional view showing a step in the method for manufacturing a wiring substrate according to the fourth embodiment of the present invention. Fig.25 It is a cross-sectional view showing other steps in the method for manufacturing the wiring substrate according to the fourth embodiment of the present invention.

[0283] As described below, the manufacturing method according to the fourth embodiment is similar to the method of the reference embodiment except that the thirteenth step is performed instead of the first step, the second step is omitted, and the seventeenth and fifteenth steps are performed in sequence between the sixth step and the seventh step. Figures 1 to 11 The manufacturing method described is the same.

[0284] <4.1.1> Step 13 and Steps 3 to 6

[0285] First, the 13th step is performed instead of the 1st step, and then the 3rd step is performed instead of the 2nd step. In the 3rd step, first, Fig.24 structure. Fig.24 The structure is not provided with the modified part 11, and the hydrofluoric acid resistant metal layer 21 and the seed layer 23 are sequentially formed on the first surface S1. Fig. 20 Then, the remaining treatments in step 3 are carried out, and then steps 4 to 6 are carried out in sequence. Fig.25 structure.

[0286] <4.1.2> Step 17

[0287] Next, the glass substrate 10 is irradiated with laser light from the second surface S2 toward the first surface S1. Fig.21 As shown, one or more modified portions 11 are formed in the glass substrate 10. The modified portion 11 is formed at a position corresponding to the first through hole. The modified portion 11 extends from the first surface S1 to the second surface S2, for example, in the thickness direction of the glass substrate 10. The laser light intensity is preferably adjusted so that the modified portion 11 extending from the first surface S1 does not reach the second surface S2. The laser irradiation conditions can be the same as those in the second step, for example.

[0288] <4.1.3> Step 15 and Steps 7 to 12

[0289] Next, a fifteenth step is performed to remove the first support 151 and the adhesive 152 from the composite body including the glass substrate 10 , the first conductive layer 20 , and the second support 141 .

[0290] Then, the composite body including the glass substrate 10 and the first conductor layer 20 is sequentially subjected to the seventh to twelfth steps. Figure 1 The wiring substrate 1 is shown.

[0291] <4.2>Effect

[0292] The fourth embodiment achieves the same effects as those of the first and second embodiments.

[0293] <4.3> Modification

[0294] The above-mentioned manufacturing method, the wiring substrate obtained by the manufacturing method, and the package device including the wiring substrate may be modified in the same manner as described in the first embodiment, for example.

[0295] Example

[0296] The following describes experiments conducted in connection with the present invention.

[0297] <Test 1>

[0298] for Figure 2 structure, Fig.19 structure, and Fig.13 For each of the structures, the relationship between the resistance value between the wiring layer included in the first conductor layer 20 and the wiring layer included in the second conductor layer 70 and the length of the through electrode was studied. The thickness of each layer is equal to each other in these structures. The sum T1+T2 of the thickness T1 of the adhesion layer 72 and the thickness T2 of the seed layer 73 is greater than the thickness T3 of the hydrofluoric acid resistant metal layer 21. In addition, for Fig.19 The above relationship was studied when the average depth D of the recessed portion provided in the hydrofluoric acid resistant metal layer 21 was set to 40% of the thickness T3 of the portion of the hydrofluoric acid resistant metal layer 21 where the recessed portion is not provided, and when the average depth D was set to 70% of the thickness T3. The results are shown in Table 1 below.

[0299] [Table 1]

[0300]

[0301] In Table 1, "etching rate" indicates the ratio of the average depth D to the thickness T3. That is, the structure with an etching rate of 100% is Figure 2 The structure with an etching rate of 0% is Fig.13 The structure with an etching rate of 40% or 70% is Fig.19 In addition, the "resistance reduction rate" is the reduction rate of the resistance value relative to the resistance value when the etching rate is 0%.

[0302] As shown in Table 1, regardless of the length of the through-electrode, the resistance reducing effect increases as the etching rate increases. In addition, the shorter the length of the through-electrode, the higher the resistance reducing effect increases as the etching rate increases.

[0303] <Test 2>

[0304] In addition to the built-in Fig.16 In addition to the solenoid coil 110, the capacitor 30 and the solenoid coil 110 constitute an LC filter. Figure 1 The Q value of the capacitor 30 and the solenoid coil 110 and the S parameter S21 of the resonance frequency of the LC filter were studied for a wiring substrate having the same structure as the wiring substrate 1 shown in FIG. Here, the length of the through electrode, that is, the length of the first through hole 12 was set to 100 μm. In addition, except that the etching rate was set to 75%, 50% and 0%, the Q value of the capacitor 30 and the solenoid coil 110 and the S parameter S21 of the resonance frequency of the LC filter were also studied for the wiring substrate same as the above. The results are shown in Table 2 below.

[0305] [Table 2]

[0306]

[0307] In Table 2, the "Q value increase rate" is the increase rate of the Q value relative to the Q value when the etching rate is 0%. In addition, the "S21 value reduction rate" is the reduction rate of the S21 value relative to the S21 value when the etching rate is 0%.

[0308] As shown in Table 2, the Q value of the capacitor 30 and the solenoid coil 110 increases as the etching rate increases, and the higher the etching rate, the higher the Q value improvement effect accompanying the increase in etching rate. In addition, the S21 value of the LC filter decreases as the etching rate increases, and the higher the etching rate, the higher the filter characteristics improvement effect accompanying the increase in etching rate.

[0309] <Test 3>

[0310] Created 50 references Figure 1 and Figure 2 The wiring substrate 1 (etching rate 100%) described above. For these wiring substrates 1, the connection reliability between the wiring layer provided on the glass substrate 10 and the through electrode was studied. Specifically, each wiring substrate 1 was mounted on a thermal shock tester, and a cycle of changing the ambient temperature of the wiring substrate from -40°C to +125°C was repeated 1000 times. Then, the conduction between the above-mentioned wiring layer and the through electrode was confirmed. The conduction between the above-mentioned wiring layer and the through electrode was carried out by measuring the resistance between the wiring layer included in the first conductor layer 20 and the wiring layer included in the second conductor layer 70 using a tester.

[0311] In addition, in addition to using Fig.19 Structural replacement Figure 2In addition to the structure of , 50 wiring substrates similar to the above were manufactured. Here, the above etching rate was set to 70%. For these wiring substrates, the connection reliability between the wiring layer and the through electrode set on the glass substrate 10 was studied by the same method as above.

[0312] In addition, in addition to using Fig.13 Structural replacement Figure 2 In addition to the structure of , 50 wiring substrates similar to the above were manufactured (etching rate 0%). For these wiring substrates, the connection reliability between the wiring layer provided on the glass substrate 10 and the through electrode was studied by the same method as above.

[0313] As a result, after adopting Fig.13 In the wiring substrate with a structure of (etching rate 0%), poor conduction occurred at a frequency of 30%. Fig.19 In a wiring substrate with a structure (etching rate 70%), the frequency of poor conduction is less than 3%. Figure 2 In the wiring substrate with a structure of (etching rate 100%), the frequency of poor conduction is less than 1%.

[0314] <Test 4>

[0315] (Example 1)

[0316] Created 50 references Figure 1 and Figure 2 The wiring substrate 1 (etching rate 100%) is described. Here, the thickness T1 of the adhesion layer 72 is set to 60nm, the thickness T2 of the seed layer 73 is set to 300nm, and the thickness T3 of the hydrofluoric acid-resistant metal layer 21 is set to 50nm. For these wiring substrates 1, the conduction between the wiring layer provided on the glass substrate 10 and the through electrode is confirmed. The conduction between the above-mentioned wiring layer and the through electrode is carried out by measuring the resistance between the wiring layer included in the first conductor layer 20 and the wiring layer included in the second conductor layer 70 using a tester.

[0317] (Example 2)

[0318] Fifty wiring substrates 1 were manufactured similar to those manufactured in Example 1 except that the thickness T3 was changed to 100 nm. For these wiring substrates 1, the conduction between the wiring layer provided on the glass substrate 10 and the through-electrode was checked in the same manner as in Example 1.

[0319] (Example 3)

[0320] Except that the thickness T2 was changed to 100 nm and the thickness T3 was changed to 50 nm, 50 wiring substrates 1 were manufactured which were the same as the wiring substrate manufactured in Example 1. For these wiring substrates 1, the conduction between the wiring layer provided on the glass substrate 10 and the through-electrode was confirmed by the same method as in Example 1.

[0321] (Example 4)

[0322] Except that the thickness T2 was changed to 100 nm and the thickness T3 was changed to 100 nm, 50 wiring substrates 1 were manufactured which were the same as the wiring substrate manufactured in Example 1. For these wiring substrates 1, the conduction between the wiring layer provided on the glass substrate 10 and the through electrode was confirmed by the same method as in Example 1.

[0323] (Comparative Example)

[0324] Except that the thickness T2 was changed to 100 nm and the thickness T3 was changed to 200 nm, 50 wiring substrates were manufactured that were the same as the wiring substrate manufactured in Example 1. For these wiring substrates, the conduction between the wiring layer provided on the glass substrate 10 and the through electrode was confirmed by the same method as in Example 1.

[0325] (result)

[0326] The results are shown in Table 3 below.

[0327] [Table 3]

[0328] Example 1 Example 2 Example 3 Example 4 Comparative Example Thickness of hydrofluoric acid resistant metal layer T3 (nm) 50 100 50 100 200 Thickness of the adhesive layer T1 (nm) 60 60 60 60 60 Thickness of seed layer T2 (nm) 300 300 100 100 100 T3≤T1 Y N Y N N T3≤T1+T2 Y Y Y Y N T1+T3≤T2 Y Y N N N Pass rate (%) 100 100 80 80 20

[0329] In Table 3, "Y" indicates that the relationship shown in the inequality is satisfied, and "N" indicates that the relationship shown in the inequality is not satisfied. In addition, "Qualified Rate" indicates the ratio of the number of wiring substrates with no conduction failure to the total number of wiring substrates (50).

[0330] As shown in Table 3, when the sum of thickness T1 and thickness T2, T1+T2, is equal to or greater than thickness T3, a much higher pass rate can be achieved compared to the case where the sum T1+T2 is less than thickness T3. In addition, when thickness T2 is greater than the sum T1+T3 of thickness T1 and thickness T3, a 100% pass rate can be achieved.

[0331] Explanation of symbols

[0332] 1…wiring substrate, 2…functional device, 3…chip component, 4…conductor for bonding, 5…conductor for bonding, 10…glass substrate, 10ER…etching residue, 11…modified portion, 12…first through hole, 20…first conductor layer, 20A…first conductor path, 21…fluoride-resistant metal layer, 22…adhesion layer, 23…seed layer, 24…first copper layer, 30…capacitor, 31…dielectric layer, 32…upper electrode, 40…interlayer insulating film, 50…conductor layer, 53…seed layer , 54…copper layer, 60…insulating layer, 70…second conductor layer, 70A…second conductor path, 70B…third conductor path, 72…adhesive layer, 73…seed layer, 74…second copper layer, 80…interlayer insulating film, 90…conductor layer, 93…seed layer, 94…copper layer, 100…insulating layer, 110…solenoid coil, 141…second support body, 142…adhesive, 151…first support body, 152…adhesive, S1…first surface, S2…second surface, UC…undercut.

Claims

1. A wiring substrate comprising: A glass substrate having a first surface and a second surface as a back surface thereof, and provided with one or more first through holes extending from the first surface to the second surface respectively; a first conductor layer, comprising a first copper layer opposite to the first surface, and a hydrofluoric acid-resistant metal layer interposed between the first copper layer and the glass substrate, and covering the openings of the one or more first through holes on the first surface side, wherein the surface on the glass substrate side has a recessed portion at the position of the one or more first through holes, and the contour of the opening of each of the recessed portions is larger than and surrounds the opening of the corresponding first through hole on the first surface side; and a second conductor layer, comprising a bonding layer, a seed layer disposed on the bonding layer, and a second copper layer disposed on the seed layer, wherein the bonding layer covers the side walls of the one or more first through holes, the inner surface of the recess, and a region of the second surface surrounding the opening of the one or more first through holes on the second surface side, The sum T1+T2 of the thickness T1 of the adhesion layer and the thickness T2 of the seed layer is equal to or greater than the thickness T3 of the hydrofluoric acid resistant metal layer.

2. The wiring substrate according to claim 1, wherein: In the hydrofluoric acid-resistant metal layer, one or more second through holes are provided at positions of the one or more first through holes, respectively, and the one or more second through holes form the recessed portion on the surface of the first conductor layer on the glass substrate side.

3. The wiring substrate according to claim 1 or 2, wherein: The thickness T1 is equal to or greater than the thickness T3.

4. The wiring substrate according to any one of claims 1 to 3, wherein: The thickness T2 is equal to or greater than a sum T1+T3 of the thickness T1 and the thickness T3.

5. The wiring substrate according to any one of claims 1 to 4, wherein: The thickness T2 is less than 0.5 μm.

6. The wiring substrate according to any one of claims 1 to 5, wherein: The thickness T1 is in the range of 10 nm to 0.5 μm, the thickness T2 is in the range of 100 nm to 0.5 μm, and the thickness T3 is in the range of 10 nm to 0.5 μm.

7. The wiring substrate according to any one of claims 1 to 6 further comprises: a dielectric layer arranged on the first conductor layer, and an upper electrode arranged on the dielectric layer, the portion of the first conductor layer opposite to the upper electrode being a lower electrode, and the upper electrode, the dielectric layer and the lower electrode forming a capacitor.

8. The wiring substrate according to claim 7, wherein: The lower electrode covers at least one of the openings of the one or more first through holes on the first surface side.

9. The wiring substrate according to any one of claims 1 to 6, further comprising: a dielectric layer provided on the first conductor layer, and an upper electrode provided on the dielectric layer, wherein a portion of the first conductor layer facing the upper electrode is a lower electrode, and the upper electrode, the dielectric layer and the lower electrode constitute a capacitor. The one or more first through holes are a plurality of first through holes, a portion of the first conductor layer and a portion of the second conductor layer constitute a solenoid coil, The capacitor and the solenoid coil constitute an LC filter. 10 . The wiring substrate according to claim 1 , which is an interposer.

11. A method for manufacturing a wiring substrate, comprising: preparing a glass substrate having a first surface and a second surface as a back surface thereof; irradiating the glass substrate with laser light to form one or more modified portions in the glass substrate; forming a first conductor layer on the first surface so as to cover the one or more modified portions, the first conductor layer comprising a first copper layer opposite to the first surface and a hydrofluoric acid-resistant metal layer interposed between the first copper layer and the glass substrate; The second surface is etched using an etching solution containing hydrogen fluoride to cause the second surface to recede and to form one or more first through holes at the positions of the one or more modified portions; wet etching a portion of the hydrofluoric acid-resistant metal layer exposed in the one or more first through holes to form a recessed portion on a surface of the first conductor layer on the glass substrate side; forming a close-fitting layer covering the side walls of the one or more first through holes, the inner surface of the recessed portion, and the second surface; forming a seed layer on the sealing layer; as well as forming a second copper layer on the seed layer, The adhesion layer, the seed layer and the hydrofluoric acid resistant metal layer are formed in such a manner that a sum T1+T2 of a thickness T1 of the adhesion layer and a thickness T2 of the seed layer is equal to or greater than a thickness T3 of the hydrofluoric acid resistant metal layer.

12. The method for manufacturing a wiring substrate according to claim 11, further comprising: Before irradiating the glass substrate with the laser, supporting the glass substrate on the first support in a manner that the second surface faces the first support; as well as After forming the first conductor layer and before forming the one or more first through holes, the first support is removed from the glass substrate.

13. The method for manufacturing a wiring substrate according to claim 11 or 12, wherein: The wet etching of the hydrofluoric acid resistant metal layer is performed to form one or more second through holes in the hydrofluoric acid resistant metal layer.

14. The method for manufacturing a wiring substrate according to any one of claims 11 to 13, further comprising: After forming the first conductor layer and before forming the one or more first through holes, the composite body including the glass substrate and the first conductor layer is supported on the second support body so that the first conductor layer faces the second support body.

Images