Method of manufacturing memory device including capacitor

Abstract

A method of manufacturing a memory device including a capacitor is disclosed. In one aspect, a method of manufacturing a memory device including capacitors is described, where each capacitor includes a first electrode and a second electrode separated by an isolation layer. The method includes: providing a first wafer including a sacrificial material and a first electrode disposed in a first hole and in contact with the sacrificial material; hybrid bonding the first wafer with a second wafer including a complementary metal oxide semiconductor (CMOS) device; removing the sacrificial material to expose the first electrode; depositing an isolation layer on the first electrode; and forming a second electrode on the isolation layer.

Description

Technical Field

[0001] The present description relates to the field of semiconductor technology, and more particularly, to a method of manufacturing a memory device including a capacitor. Background Art

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells by stacking memory cells vertically or using memory cells with vertical transistors.

[0003] 3D memory architectures generally include multiple arrays of memory cells and peripheral devices for managing data sent to and from the memory cells. Such memory cells (e.g., DRAM cells) typically include capacitors for storing data bits, such as metal-oxide-silicon (MOS) capacitors, metal-oxide-metal (MOM) capacitors, or polysilicon-oxide-polysilicon (POP) capacitors. The trend in 3D memory is toward higher density memory cells to increase data storage capacity. However, in order to reduce manufacturing costs, the dedicated silicon area of ​​the memory chip remains largely unchanged. Summary of the invention

[0004] This specification describes a method of manufacturing a memory device including a capacitor. According to some embodiments, the method can employ one or more high temperature processes using sacrificial materials to replace high dielectric constant (high-k) materials. After the high temperature process, the sacrificial materials can be removed and the high-k material can then be deposited.

[0005] In a first aspect, a method of manufacturing a memory device including capacitors is described, wherein each capacitor includes a first electrode and a second electrode separated by an isolation layer. The method includes: providing a first wafer, the first wafer including a sacrificial material and a first electrode disposed in a first hole and contacting the sacrificial material; hybrid bonding the first wafer with a second wafer including a complementary metal oxide semiconductor (CMOS) device; removing the sacrificial material to expose the first electrode; depositing the isolation layer on the first electrode; and forming the second electrode on the isolation layer.

[0006] In a second aspect, a method of manufacturing a memory device including capacitors is described, wherein each capacitor includes a first electrode and a second electrode separated by an isolation layer. The method includes: providing a first wafer, the first wafer including a sacrificial material and a first electrode disposed in a first hole and contacting the sacrificial material; thermally treating the first wafer; removing the sacrificial material to expose the first electrode; depositing the isolation layer on the first electrode; and forming the second electrode on the isolation layer.

[0007] In a third aspect, a memory device includes a first wafer and a second wafer, the first wafer including capacitors and the second wafer including CMOS devices, wherein the second wafer is hybrid bonded with the first wafer. Each capacitor includes a first electrode and a second electrode separated by an isolation layer, wherein the isolation layer includes a dielectric material having a dielectric constant of 5 or greater.

[0008] In a fourth aspect, a system includes a memory device and a memory controller electrically connected to the memory device, wherein the memory controller is configured to control the memory device. The memory device includes a memory plane, the memory plane includes a first wafer and a second wafer, the first wafer includes capacitors, the second wafer includes a CMOS device, wherein the second wafer is hybrid bonded with the first wafer. Each capacitor includes a first electrode and a second electrode separated by an isolation layer, wherein the isolation layer includes a dielectric material having a dielectric constant of 5 or greater.

[0009] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a cross-sectional diagram depicting an example of a memory device.

[0011] Figure 1B is a cross-sectional diagram depicting another example of a memory device.

[0012] Figure 2A is a schematic diagram depicting an example of a memory device including peripheral circuitry and an array of memory cells, each memory cell having a vertical transistor.

[0013] Figure 2B is a schematic circuit diagram depicting an example of a memory device including peripheral circuits and an array of dynamic random access memory (DRAM) cells.

[0014] Figure 3A-3D are cross-sectional views depicting different stages of an exemplary method of manufacturing a memory device including a capacitor.

[0015] Figure 4A-4C is a flow chart of an exemplary process for fabricating a memory device having a capacitor.

[0016] Figure 5A and Figure 5B 2 are a top view and a cross-sectional view, respectively, depicting an example of a prepared semiconductor wafer for use in fabricating a memory device.

[0017] Figure 6A-6L are various views depicting different stages of an exemplary method of manufacturing a memory device including a pillar-type capacitor.

[0018] Figure 7A-7E are various views depicting different stages of an exemplary method of manufacturing a memory device including a cup-type capacitor.

[0019] Figure 8 is a block diagram depicting an example of a system including one or more memory devices and a memory controller. DETAILED DESCRIPTION

[0020] Particular embodiments of the subject matter described in this specification can be implemented to realize one or more of the following advantages.

[0021] The present disclosure introduces a method for manufacturing a memory device, which in some embodiments can adapt to one or more high temperature processes while preventing high-k dielectric failure of the capacitor of the memory device. Specifically, during the high temperature process, the present disclosure uses sacrificial materials to replace high-k materials. By introducing high-k materials after the high temperature process has been completed, the dielectric constant of the high-k material will not deteriorate compared to other manufacturing methods, and capacitors with higher quality characteristics (e.g., increased capacitance) can be formed. In some instances, capacitors (e.g., vertical capacitors) can provide improved performance of the entire memory device and / or can promote smaller feature sizes of the memory device. Therefore, higher density components (e.g., DRAM cells) can be combined on a wafer (e.g., a silicon wafer) to increase the storage capacity of the memory device, as well as improve functionality (e.g., reduce delays and memory cell programming errors).

[0022] Reference will now be made in detail to the exemplary embodiments shown in the accompanying drawings in order to understand and implement the present disclosure and to achieve technical effects. It will be appreciated that the following description has been made only by way of example and not by way of limitation of the present disclosure. Various embodiments of the present disclosure and various features that do not conflict with each other in the embodiments may be combined and rearranged in various ways. Without departing from the spirit and scope of the present disclosure, modifications, equivalents or improvements of the present disclosure are understandable to those skilled in the art, and they are intended to be encompassed within the scope of the present disclosure.

[0023] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of a person of ordinary skill in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0024] Generally, a term can be understood, at least in part, from usage in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending, at least in part, on the context, terms such as "a," "an," or "the" can also be understood to convey singular usage or to convey plural usage.

[0025] It should be readily understood that the meanings of “on,” “over,” and “over” in the present disclosure should be interpreted in the broadest manner, so that “on” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “over” not only means “over something” or “on something,” but also can include the meaning of “over something” or “on something” with no intervening features or layers therebetween (i.e., directly on something).

[0026] In addition, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. The term "vertical" refers to a direction perpendicular to the surface of a semiconductor substrate, and the term "horizontal" refers to any direction parallel to the surface of a semiconductor substrate.

[0027] As used herein, the term "substrate" generally refers to a material on which subsequent material layers are added. The substrate itself may include multiple layers of material and / or may be patterned, for example, with an array of first holes. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material (e.g., various dielectric materials, glass, plastic, oxide, or sapphire wafer). The memory device may include multiple substrates.

[0028] As used herein, the term "layer" generally refers to a material portion including an area with a thickness. A layer may extend over the entire underlying layer or overlying structure, or may have a range less than the range of the underlying layer or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes at the top surface and the bottom surface. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above it and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and a contact layer (wherein interconnect lines and / or vertical contacts are formed) and one or more dielectric layers.

[0029] According to some embodiments of the present disclosure, a structure and a manufacturing method for a vertical capacitor with higher density and lower silicon area consumption on a wafer are provided. For example, a vertical capacitor can be used as a storage unit for a vertical transistor of a DRAM memory array. In general, the capacitance is proportional to the area of ​​the capacitor, so a planar capacitor involves a larger silicon area in order to provide sufficient capacitance for the integrated circuit of the memory device. By using a vertical capacitor instead of a planar capacitor in a memory device, sufficient capacitance can be provided, while increasing the overall storage density and reducing manufacturing costs.

[0030] The manufacturing methods described in this specification can be used to form high-quality vertical capacitors in semiconductor devices even when one or more high-temperature processes are involved in the manufacturing. High-temperature processes may include rapid thermal processing (RTP), rapid thermal annealing (RTA), various thermal treatments, hybrid wafer bonding (e.g., die-to-wafer (D2W) or wafer-to-wafer (W2W) hybrid bonding), other types of wafer bonding (e.g., direct bonding, eutectic bonding, glass bonding, thermal compression bonding, etc.), and other high-temperature processes that may be involved in the manufacture of prior art semiconductor devices. When a planar capacitor structure is desired (e.g., in a planar memory device), the manufacturing methods disclosed herein can also be used for planar capacitors.

[0031] The high temperature process may involve temperatures of about 500° C. or higher (e.g., about 600° C. or higher, about 700° C. or higher, about 800° C. or higher, about 900° C. or higher, about 1000° C. or higher) and may be performed at various points in the overall manufacturing process line of a semiconductor device. Generally, one or more components of a semiconductor device may involve a high temperature process that facilitates the formation of the component. For example, in a memory device, a high temperature process such as RTA may be used to form bit lines, as these components typically involve the generation of metal silicides. As another example, hybrid bonding generally involves a high temperature process for producing a direct bond interconnect (DBI), i.e., bonding a dielectric (e.g., silicon oxide (SiO x )) is a permanent bond in combination with an embedded metal (e.g., copper (Cu)). In semiconductor manufacturing, hybrid bonding has become an industry practice for forming metal interconnects between two semiconductor wafers (e.g., two silicon wafers). For memory devices, hybrid bonding can allow one or more peripheral devices (e.g., complementary metal oxide semiconductor (CMOS) devices) to interact with various components of the memory device (e.g., memory cell transistors). Hybrid bonding can contain advanced 3D device stacking, higher storage density, greater bandwidth, improved efficiency, improved speed and performance, higher power, and several other advantages.

[0032] However, the capacitor of the memory device may be sensitive to high temperature processes. Specifically, high dielectric constant (high-k) materials that are typically used as isolation layers between electrodes of a capacitor may degrade in high temperature processes. A high-k dielectric material generally refers to a dielectric material having a dielectric constant greater than the dielectric constant of silicon oxide (SiO2), for example, a dielectric constant of about 3.7 or greater (e.g., about 4 or greater, about 4.5 or greater, about 5 or greater, about 5.5 or greater, about 6 or greater, about 6.5 or greater, about 7 or greater). For example, such a high-k material may include aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), or a combination thereof. During a high temperature process (e.g., involving a temperature of about 500°C or higher), the high-k material is susceptible to failure due to the high temperature changing its crystal structure and / or crystal phase. For example, a high temperature process may cause crystal growth in the high-k material, increasing the percentage of large crystals in the high-k material. In such cases, the dielectric constant of the high-k material is generally reduced, and the high-k material provides reduced capacitance. In some cases, after one or more high temperature processes, the high-k material may have a dielectric constant of about 6 or less (e.g., about 5.5 or less, about 5 or less, about 4.5 or less, about 4 or less, about 3.7 or less, about 3.5 or less).

[0033] To address one or more of these aforementioned problems, the present disclosure introduces a memory device manufacturing method that, in some embodiments, can accommodate one or more high temperature processes while preventing high-k dielectric failure of a capacitor of the memory device. Specifically, during the high temperature process, the present disclosure employs sacrificial materials to replace high-k materials. By introducing the high-k material after the high temperature process has been completed, the dielectric constant of the high-k material is not degraded, and a capacitor with higher quality characteristics (e.g., increased capacitance) can be formed.

[0034] Figure 1A A schematic diagram of a cross section of an exemplary memory device 100 is shown. Memory device 100 represents an example of a bonded die that can be formed using the manufacturing methods disclosed herein. In some embodiments, at least some of the memory cell arrays and peripheral circuits in memory device 100 are formed in parallel on different wafers and then combined to form a bonded die (this process is referred to herein as a "parallel process"). It should be noted that in Figure 1A An x-axis and a y-axis are added to further illustrate the spatial relationship of components of the semiconductor device.

[0035] The memory device 100 may include a first wafer 102, which includes an array of memory cells (also referred to herein as a "memory cell array"). In some embodiments, the memory cell array includes an array of DRAM cells. For ease of description, a DRAM cell array may be used as an example to describe a memory cell array in the present disclosure. In some embodiments, each DRAM cell includes a capacitor for storing a data bit and one or more transistors (also referred to as a transfer transistor) that control (e.g., switch and select) access to it. In some embodiments, each DRAM memory cell is a transistor, a capacitor (1T1C) cell. Because transistors often leak small amounts of charge, capacitors can be discharged slowly, causing the information stored in them to be exhausted. In this way, the DRAM cells can be refreshed, for example, by peripheral circuits to maintain data.

[0036] like Figure 1AAs shown, the first wafer 102 may include at least some of the peripheral circuits of the memory device 100. The second wafer 104 may include the remaining peripheral circuits of the memory device 100. That is, the peripheral circuits of the memory device 100 may be separated into at least two wafers 102 and 104, and some peripheral circuits and the memory cell array are integrated into the first wafer 102. The peripheral circuits (also referred to as control and sensing circuits) may include any appropriate digital, analog and / or mixed signal circuits for facilitating the operation of the memory cell array. For example, the peripheral circuits may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a data input / output buffer, a charge pump, a voltage source or a voltage generator, a current reference or a voltage reference, any portion (e.g., a subcircuit) of the functional circuits mentioned above, or any active or passive component (e.g., a transistor, a diode, a resistor or a capacitor) of the circuit. The peripheral circuits in the first wafer 102 and the second wafer 104 can use CMOS technology. For example, they can be implemented using a logic process of any appropriate technology node (for example, 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0037] The first wafer 102 and the second wafer 104 are stacked in different planes. Therefore, compared with a memory device in which all peripheral circuits are arranged in the same plane, the memory cell array and the peripheral circuits in the first wafer 102 and the peripheral circuits in the second wafer 104 can be stacked in different planes, thereby reducing the plane size of the memory device 100. Figure 1A As shown, the memory device 100 also includes a bonding interface 106 between the first wafer 102 and the second wafer 104. The bonding interface 106 can be an interface between the two semiconductor wafers formed by any appropriate bonding technology (e.g., hybrid bonding) described in detail below. In some embodiments, the bonding interface 106 is where the bonding layers meet and bond. In practice, the bonding interface 106 can be a layer with a certain thickness, which includes the bottom surface of the bonding layer of the first wafer 102 and the top surface of the bonding layer of the second wafer 104.

[0038] The first wafer 102 and the second wafer 104 may be manufactured separately (and in some embodiments, in parallel) by parallel processes, so that the thermal budget of manufacturing one of the first wafer 102 and the second wafer 104 does not limit the process of manufacturing the other of the first wafer 102 and the second wafer 104. In addition, in contrast to the long-distance (e.g., millimeter or centimeter-level) chip-to-chip data bus on a circuit board such as a printed circuit board (PCB), a large number of interconnects (e.g., bonding contacts) may be formed across the bonding interface 106 to form a direct, short-distance (e.g., micrometer-level) electrical connection between the wafers 102 and 104, thereby eliminating chip interface delays and achieving high-speed I / O throughput with reduced power consumption. Data transfer between the memory cell arrays and different peripheral circuits in the first wafer 102 and the second wafer 104 may be performed by the interconnects (e.g., bonding contacts) across the bonding interface 106. By vertically integrating the first wafer 102 and the second wafer 104, the chip size may be reduced, and the memory cell density may be increased.

[0039] In addition, if Figure 1A As shown, the first wafer 102 of the memory device 100 may also include a pad output interconnect layer 103 for pad output purposes (i.e., using contact pads on which bonding wires can be soldered to interconnect with external devices). In some examples, the pad output interconnect layer 103 may be included in the second wafer 104 that does not include the memory cell array. For example, Figure 1B As shown, the second wafer 104 of the memory device 100' may include a bonding interface 106. That is, the pad output interconnect layer 103 may be disposed on either side of the memory device 100 or 100'.

[0040] Figure 2A A schematic diagram of a memory device 200 (which may be similar in operation and / or structure to the memory device 100) is shown including peripheral circuits 108 and an array of memory cells 208, each memory cell 208 having a vertical transistor 210. The memory device 200 may include a memory cell array 201 and peripheral circuits 108 coupled to the memory cell array 201. The memory cell array 201 may be any suitable memory cell array in which each memory cell 208 includes a vertical transistor 210 and a vertical capacitor 10. The vertical capacitor 10 is coupled to the vertical transistor 210 for storing charge as binary information of the memory cell 208.

[0041] like Figure 2AAs shown, the memory cells 208 in the memory cell array 201 may be arranged in a two-dimensional (2D) array having rows and columns. The memory device 200 may include: word lines 204, which couple the peripheral circuit 108 with the memory cell array 201, for controlling the switching of the vertical transistors 210 in the memory cells 208 located in a row; and bit lines 206, which couple the peripheral circuit 108 with the memory cell array 201, for sending data to the memory cells 208 located in a column and / or receiving data from the memory cells 208 located in a column. That is, each word line 204 is coupled to the memory cells 208 of the corresponding row, and each bit line 206 is coupled to the memory cells 208 of the corresponding column.

[0042] The vertical transistor 210 (e.g., a vertical metal oxide semiconductor field effect transistor (MOSFET)) includes a semiconductor body 124 extending vertically above a substrate (not shown). That is, the semiconductor body 124 may extend above the top surface of the substrate, thereby exposing not only the top surface of the semiconductor body 124 but also one or more side surfaces thereof. Figure 2A As shown, for example, the semiconductor body 124 may have a rectangular parallelepiped shape to expose its four sides. It should be understood that the semiconductor body 124 may have any appropriate 3D shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor body 124 in a plan view (e.g., in an xy plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape), or any other appropriate shape.

[0043] like Figure 2A As shown, the vertical transistor 210 also includes a gate structure 216 that contacts one or more sides of the semiconductor body 124, i.e., is located in one or more planes of the side surface(s) of the active region. In other words, the active region of the vertical transistor 210 (i.e., the semiconductor body 124) may be at least partially surrounded by the gate structure 216. The gate structure 216 may include a gate dielectric 126 located on one or more sides of the semiconductor body 124, e.g., Figure 2AAs shown, the gate structure 216 contacts the four side surfaces of the semiconductor body 124. The gate structure 216 may also include a gate electrode 114 located above the gate dielectric 126 and in contact with the gate dielectric 126. The gate dielectric 126 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric 126 may include silicon oxide, i.e., a gate oxide. The gate electrode 114 may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.) or a silicide. For example, the gate electrode 114 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 114 includes a plurality of conductive layers, such as a W layer above the TiN layer. It should be understood that in some examples, the gate electrode 114 and the word line 204 may be a continuous conductive structure. In other words, the gate electrode 114 may be considered as a portion of the word line 204 that forms the gate structure 216 , or the word line 204 may be considered as an extension of the gate electrode 114 to be coupled to the peripheral circuitry 108 .

[0044] like Figure 2A As shown, the vertical transistor 210 may also include a pair of source and drain (S / D doped regions, also referred to as source electrode and drain electrode) formed at both ends of the semiconductor body 124 in the vertical direction (y direction), respectively. The source and drain may be doped with any appropriate P-type dopant (e.g., boron (B) or gallium (Ga)), or any appropriate N-type dopant (e.g., phosphorus (P) or arsenic (As)). The source and drain may be separated by a gate structure 216 in the vertical direction (y direction). In other words, the gate structure 216 is formed vertically between the source and the drain. Therefore, when the gate voltage applied to the gate electrode 114 is higher than the threshold voltage of the vertical transistor 210, one or more channels (not shown) of the vertical transistor 210 may be vertically formed in the semiconductor body 124 between the source and the drain. That is, each channel of the vertical transistor 210 is also formed in the vertical direction along which the semiconductor body 124 extends.

[0045] In some embodiments, the vertical transistor 210 is a multi-gate transistor. That is, the gate structure 216 can be connected to more than one side of the semiconductor body 124 (e.g., Figure 2A The vertical transistor 210 is connected to the four sides of the transistor 210 to form more than one gate, so that more than one channel can be formed between the source and the drain in operation. Figure 2A Although shown as a multi-gate transistor in FIG. 2 , the vertical transistor 210 may also include a single-gate transistor. That is, the gate structure 216 may contact a single side of the semiconductor body 124, for example, for the purpose of increasing transistor and memory cell density.

[0046] The peripheral circuit 108 may be coupled to the memory cell array 201 via the bit lines 206, the word lines 204, and any other appropriate metal connections. As described above, the peripheral circuit 108 may include any appropriate circuitry for facilitating the operation of the memory cell array 201 by applying a voltage signal and / or a current signal to each memory cell 208 via the word lines 204 and the bit lines 206 and sensing a voltage signal and / or a current signal from each memory cell 208. The peripheral circuit 108 may include various types of peripheral circuits (e.g., CMOS devices) formed using CMOS technology.

[0047] like Figure 2A As shown, the vertical capacitor 10 can be coupled to the source or drain of the vertical transistor 210 and can store binary data (e.g., 0 and 1). In some embodiments, the vertical transistor 210 controls the selection and / or state switching of the corresponding capacitor 10. Figure 2B As shown, in some embodiments, each memory cell 208 includes a transistor 304 (eg, using Figure 2A ) and capacitor 306 (eg, Figure 2A DRAM cell 302 (e.g., an example of capacitor 10 in FIG. 1 ). A gate of transistor 304 (e.g., corresponding to gate electrode 114) may be coupled to word line 204, one of a source and a drain of transistor 304 may be coupled to bit line 206, the other of a source and a drain of transistor 304 may be coupled to a first electrode of capacitor 306, and a second electrode of capacitor 306 may be coupled to ground.

[0048] Figure 3A-3D is a cross-sectional view depicting different stages of a memory device during a manufacturing method involving a high temperature process. Specifically, Figure 3A-3D A memory device 300 (which may be similar in operation and / or structure to memory device 100 and / or memory device 200) is shown formed with vertical capacitors 10, each of which includes an isolation layer (e.g., a high-k dielectric material) located between two electrodes (e.g., a first electrode 13 and a second electrode 14). Generally speaking, a sacrificial material 12 is employed to replace one or more components of capacitor 10 to support the structure of capacitor 10 during the entire manufacturing steps involving high temperature processes. The sacrificial material 12 is then removed after the high temperature processes have been completed, and a high-k material is deposited as an isolation layer between the first electrode 13 and the second electrode 14 of each capacitor 10 (e.g., see Figure 3C ).

[0049] Figure 3AA first stage in forming a memory device 300 is shown, which includes providing a first wafer 102. In this example, the first wafer 102 is formed by bonding a carrier wafer 52 to the top of the array wafer 50. The array wafer 50 and the carrier wafer 52 may be formed using any suitable wafer bonding technique (e.g., direct bonding, adhesive bonding, thermocompression bonding, reactive bonding, etc.), which may include one or more high temperature processes. Generally, the carrier wafer 52 is used to support (e.g., carry) the array wafer 50 during various steps in the overall manufacturing process and does not include any functional components of the memory device 300. In some embodiments, the first wafer 102 and the array wafer 50 are the same wafer, so that the carrier wafer 52 is not involved in the manufacturing process.

[0050] The array wafer 50 provides a memory cell array 201 including a plurality of memory cells. Each memory cell includes a structure of a vertical transistor 210 and a vertical capacitor 10. For example, the vertical transistor 210 can perform selection and / or state switching on a data bit stored in the vertical capacitor 10 of the generated memory device 300. In some embodiments, the generated memory device 300 is a DRAM device that provides memory cells in the form of an array of DRAM cells. Figure 2A As depicted, each memory cell may include a semiconductor body 124 surrounded by a gate structure including a gate dielectric 126 and a gate electrode. Figure 3A-3D 204 is depicted as a continuous portion of word line 204. Figure 3A As shown, each semiconductor body 124 can extend vertically through the word line 204. The vertical transistors 210 can be separated by a dielectric material 130 (or, in some cases, an air gap) to electrically isolate two adjacent vertical transistors 210.

[0051] The structure for the vertical capacitor 10 is provided in the form of an array of first holes 11 penetrating a semiconductor structure 140, the semiconductor structure 140 being located above a transistor array region 150, the transistor array region 150 including vertical transistors 210 and word lines 204. The semiconductor structure 140 may include any suitable semiconductor or insulating material, for example, silicon, gallium arsenide, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y) or a combination thereof. The first hole 11 is filled with a sacrificial material 12. Depending on the implementation, the sacrificial material 12 may include a variety of different materials, such as insulating materials (e.g., SiO2, Si3N4, carbon), semiconductor materials (e.g., silicon, gallium arsenide), or others. Since the sacrificial material 12 is generally an intermediate step, that is, it is removed at a certain point in the manufacturing method, the sacrificial material 12 can be selected based on a convenient material removal process (e.g., a wet etching method, an ashing method, etc.). In some embodiments, the sacrificial material 12 is included in the semiconductor structure 140, and the first hole 11 is filled with a filling material. The semiconductor structure 140 can be patterned and / or include multiple layers of sacrificial material 12. In general, the sacrificial material 12 (for example) supports the capacitor 10 during the entire manufacturing steps involving high temperature processes by filling the first hole 11 and / or being included in the semiconductor structure 140. The first hole 11 has a cylindrical (e.g., column) shape, but various geometric shapes are possible, such as conical, tapered, cuboid, etc. The first electrode 13 is lined in the first hole 11 and contacts the sacrificial material 12. The first electrode 13 may be formed of any suitable conductive material, such as titanium nitride (TiN). In this case, for example, the first electrode 13 interfaces with the semiconductor body 124, enabling the vertical transistor 210 to communicate with the capacitor 10 of the resulting memory device 300 to store a data bit.

[0052] Figure 3B The second stage of forming the memory device 300 is shown, which includes hybrid bonding the first wafer 102 on top of the second wafer 104. The second wafer 104 includes, for example, peripheral circuits 108 (e.g., CMOS devices) that can be manufactured in the above-mentioned parallel process. As mentioned above, hybrid bonding generally involves at least one high temperature process for forming interconnects between the first wafer 102 and the second wafer 104. Figure 3B As seen in FIG. 1 , in some embodiments, the bottom surface of the first wafer 102 (i.e., the bottom surface of the array wafer 50 portion of the first wafer 102) can be thinned prior to hybrid bonding with the second wafer 104. For example, excess material can be removed and / or the bottom surface can be polished by chemical mechanical polishing (CMP) or other suitable methods to provide a clean interface for hybrid bonding.

[0053] like Figure 3BAs seen in FIG. 3 , the memory device 300 is a bonded chip formed by a first wafer 102 and a second wafer 104, which are bonded at a bonding interface 106 located therebetween. The second wafer 104 includes a substrate 101, which may be composed of silicon (e.g., crystalline silicon (c-Si) such as polycrystalline silicon (poly-Si) or single crystal silicon (single crystal Si)), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI). The substrate 101 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x and / or z directions (i.e., lateral directions).

[0054] The second wafer 104 of the memory device 300 may include a peripheral circuit 108 located on the substrate 101. In some embodiments, the peripheral circuit 108 is configured to control and sense the memory device 300. The peripheral circuit 108 may be any suitable digital, analog, and / or mixed signal control and sensing circuit for facilitating the operation of the memory device 300, including but not limited to: a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current reference or a voltage reference, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). The peripheral circuit 108 may include a transistor formed on the substrate 101, wherein all or part of the transistor is formed in the substrate 101 (e.g., below the top surface of the substrate 101) and / or directly on the substrate 101. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the transistor) may also be formed in the substrate 101. The transistors may be high-speed and have advanced logic processes (e.g., technology nodes of 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.). In some embodiments, the peripheral circuit 108 may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs)) or memory circuits (e.g., static random access memories (SRAMs) and dynamic RAMs (DRAMs)).

[0055] The second wafer 104 of the memory device 300 may also include an interconnect layer 110 located near the bonding interface 106 and above the peripheral circuit 108. The interconnect layer 110 may include a plurality of interconnects 111 and a dielectric that electrically isolates the interconnects 111. The interconnects 111 may include a conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of ​​the interconnect layer 110 may be formed using a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof.

[0056] Similarly, if Figure 3B As shown, the first wafer 102 of the memory device 300 may further include an interconnect layer 112 located near the bonding interface 106. The interconnect layer 112 may include a plurality of bit line contacts 113 connected to the bit lines 206 and a dielectric electrically isolating the bit line contacts 113. The bit line contacts 113 and the bit lines 206 may include a conductive material, including but not limited to: W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of ​​the interconnect layer 112 may be formed using a dielectric, including but not limited to: silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The word lines 204 of the first wafer 120 may be coupled to the peripheral circuits 108 in the second wafer 104 through the word line contacts 116 in the interconnect layer 112, the bonding contacts 115 in the bonding interface 106, and the interconnects 111 in the interconnect layer 110. The bonding contacts 115 may be used to hybrid bond the first wafer 102 to the second wafer 104.

[0057] The first wafer 102 may be bonded on top of the second wafer 104 in a face-to-face manner at a bonding interface 106. In this case, the bonding interface 106 is disposed between the interconnect layers 110 and 112 as a result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can achieve both metal-to-metal bonding and dielectric-to-dielectric bonding.

[0058] Figure 3C The third stage of forming the memory device 300 is shown, which includes removing the top surface of the first wafer 102 to expose the first hole 11, that is, removing the carrier wafer 52 portion of the first wafer 102. For example, the carrier wafer 52 can be removed from the first wafer 102 by chemical mechanical processing (CMP) or other suitable methods.

[0059] After one or more high temperature processes, the sacrificial material 12 is removed from the first hole 11 and / or the semiconductor structure 140 to expose the first electrode 13. The high temperature process may be performed at any stage of the manufacturing process before removing the sacrificial material 12. A high-k dielectric material is then deposited on the first electrode 13 to form an isolation layer 15.

[0060] Since the high-k material is not subjected to any high temperature process during the entire manufacturing method, the crystal structure and / or crystal phase of the high-k material does not change. In general, the high-k material will have a higher dielectric constant and a smaller average crystal size than the case where the same material is subjected to any high temperature process in the high temperature process. For example, the high-k material included in the final capacitor structure 10 can have a dielectric constant of about 5 or greater (e.g., about 5.5 or greater, about 6 or greater, about 6.5 or greater, about 7 or greater). In some embodiments, the high-k material can have a dielectric constant of about 20 or greater. In some embodiments, the high-k material can have a dielectric constant of about 25 or greater. For example, the high-k material can have a dielectric constant in the range of about 25 to 40. The high-k material can also meet one or more size conditions based on the absolute and / or relative size of its crystals. Specifically, the smallest crystal of the high-k material corresponds to a minimum size d, and the largest crystal of the high-k material corresponds to a maximum size D. In some embodiments, the number of large crystals in the high-k material has a percentage of less than 20% of the total number of crystals, wherein the large crystals have a dielectric constant between about 25 and 40. In other embodiments, the number of large crystals in the high-k material has a percentage of less than 15% of the total number of crystals, wherein the large crystals have a size between In other embodiments, the average size of all crystals in the high-k material is between d and between.

[0061] Figure 3D The fourth stage of forming the memory device 300 is shown, which may include additional manufacturing steps that may be performed to produce the final memory architecture. The second electrode 14 is formed on the isolation layer 15 to produce the final vertical capacitor 10, that is, the capacitors 10 each have a first electrode 13 and a second electrode 14 separated by the isolation layer 15. The isolation layer 15 insulates the first electrode 13 and the second electrode 14 from each other. The second electrode 14 can be composed of any suitable conductive material, such as TiN and / or silicon germanium (SiGe). In some embodiments, the second electrode 14 can be grounded.

[0062] The conductive layer 30 may be deposited on the second electrode 14 and / or the semiconductor structure 140. Depositing the conductive layer 30 may include forming contacts 31 between the bonding interface 106 to communicate with the peripheral circuit 108 of the second wafer 104. The conductive layer 30 and the contacts 31 may include any suitable conductive material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. Alternatively or additionally, a pad output interconnect layer 103 may be deposited on the conductive layer 30 (or one or more layers deposited on the conductive layer 30) for pad output purposes, i.e., interconnecting with an external device using contact pads 32 on which bonding wires may be soldered.

[0063] Generally speaking, any suitable deposition method (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), metal organic CVD (MOCVD), sputtering, atomic layer deposition (ALD) or a combination thereof) may be used to deposit the first electrode 13, sacrificial material 12, isolation layer 15, second electrode 14, conductive layer 30, pad output interconnect layer 103 and / or other material layers.

[0064] Figure 4A A flow chart of an exemplary process 400 for manufacturing a memory device including capacitors is shown. The process 400 generally involves one or more high temperature processes. Each capacitor includes a first electrode and a second electrode separated by an isolation layer. The isolation layer generally includes a high-k dielectric material, such as Al2O3, HfO2, ZrO2, TiO2, or a combination thereof.

[0065] The process 400 includes providing a first semiconductor wafer. The first wafer includes a sacrificial material and a first electrode disposed in an array of first holes. The first electrode contacts the sacrificial material (410).

[0066] The process 400 includes hybrid bonding a first wafer to a second semiconductor wafer including CMOS devices (eg, peripheral circuits) (420). Generally, hybrid bonding involves one or more high temperature processes.

[0067] The process 400 includes removing the sacrificial material to expose the first electrode (430).

[0068] The process 400 includes depositing an isolation layer on the first electrode (440).

[0069] The process 400 includes forming a second electrode on the isolation layer (450).

[0070] In some embodiments, process 400 includes depositing a conductive layer on the second electrode and forming a pad output structure connected to the conductive layer and the CMOS device (460).

[0071] Figure 4B A flow chart of an exemplary process 410 for providing a first semiconductor wafer is shown.

[0072] Process 410 includes providing an array wafer including a sacrificial material and a first electrode disposed in an array of first holes. The first electrode is in contact with the sacrificial material (412).

[0073] Process 410 includes forming a first semiconductor wafer by bonding the array wafer to a carrier wafer and thinning the array wafer (414). The top surface of the array wafer is bonded to the bottom surface of the carrier wafer, and the bottom surface of the array wafer is thinned and / or polished.

[0074] In some embodiments, process 410 includes thermally processing the first wafer ( 416 ). For example, the thermal processing may be used to form one or more components of a memory device, such as a bit line.

[0075] Figure 4C A flow chart of an exemplary process 420 for hybrid bonding the first semiconductor wafer of process 410 with a second semiconductor wafer including CMOS devices is shown.

[0076] The process 420 includes hybrid bonding the array wafer to the second wafer (422). The thinned bottom surface of the array wafer portion of the first wafer is bonded to the top surface of the second wafer at a bonding interface.

[0077] Process 420 includes removing the carrier wafer from the first wafer to expose the array wafer (424).

[0078] Figure 5A 1 is a top view depicting an example of a processed first wafer 102 for fabricating a memory device having vertical capacitors. Each capacitor of the resulting memory device includes a first electrode and a second electrode separated by an isolation layer. The steps for producing such a capacitor are explained below. Figure 5B is a cross-sectional view of an exemplary first semiconductor wafer 102. The first wafer 102 can be used to fabricate at least two different capacitor structures, referred to herein as "pillar capacitors" and "cup capacitors," which involve one or more high temperature processes. Figure 6A-6L The steps for fabricating a pillar type capacitor for a memory device starting from a first wafer 102 are outlined. Figure 7A-7E The steps for fabricating a cup capacitor for a memory device starting from a first wafer 102 are outlined.

[0079] The first wafer 102 includes a transistor array region 150 including a plurality of vertical transistors 210. The vertical transistors 210 are provided in the form of a semiconductor body 124 and a gate structure including a gate dielectric 126 and a gate electrode 114. The semiconductor bodies 124 are separated by dielectric materials 130 (in some cases, air gaps), which can electrically isolate adjacent vertical transistors 210.

[0080] The first wafer 102 also includes an array of first holes 11 vertically penetrating the semiconductor structure 140 disposed above the transistor array region 150. The first holes 11 correspond to the structure of the generated vertical capacitor. For example, the contact 20 interfaces the first hole 11 with the semiconductor body 124 so that the bit stored in the generated capacitor can be selected and / or switched by the vertical transistor 210. The semiconductor structure 140 includes alternating layers of a first dielectric material 41 and a second dielectric material 42. In this example, the alternating layers include two layers of the first dielectric material 41-1 and 41-2 and three layers of the second dielectric material 42-1, 42-2 and 42-3. In general, any number of layers can be included in the semiconductor structure 140, and if necessary, the layers can use more than two dielectric materials. In this example, the first dielectric material 41 and the second dielectric material 42 are different materials and can include any suitable dielectric material, such as silicon oxide (SiO2) or silicon nitride (Si3N4).

[0081] Fig. 6A is a top view illustrating a first stage in forming a memory device 600 having a pillar-type capacitor (which may be operationally and / or structurally similar to memory device 100 , memory device 200 , and / or memory device 300 ). Figure 6B1 is a cross-sectional view showing the first stage. The first stage includes: forming a first electrode 13 (e.g., TiN) in the first hole 11 and filling the first hole 11 with a filling material 16 (e.g., polysilicon, dielectric material). The filling material 16 is also deposited on the second dielectric material 42-1 of the top layer to fully cover the first electrode 13. In this case, the first electrode 13 is lined in the first hole 11 and is recessed to establish a relatively uniform material layer in the first hole 11, but the first hole 11 can be filled in a different manner. For example, depending on the configuration of the vertical capacitor, the first electrode 13 can be partially lined in the first hole 11 or partially fill the first hole 11. Different first holes 11 can also be filled differently as needed. In addition, in this embodiment, the sacrificial material 12 is included in the semiconductor structure 140, and the filling material 16 is generally a material different from the sacrificial material 12. More specifically, the first dielectric material 41 is a sacrificial material 12, so that multiple layers of sacrificial materials 12-1 and 12-2 are included in the semiconductor structure 140. As described below, after one or more high temperature processes, the sacrificial layers 12 - 1 and 12 - 2 may be patterned and subsequently removed to produce a pillar-type capacitor while avoiding high-k dielectric failure.

[0082] Figure 6C is a cross-sectional view showing a second stage of forming a memory device 600 having a pillar capacitor. The second stage includes: hybrid bonding the first wafer 102 to the second wafer 104 at the bonding interface 106. Hybrid bonding generally involves one or more high temperature processes. For example, additional high temperature processes and thermal treatments may be performed before and / or after hybrid bonding to form various components of the memory device 600, such as the bit line 206. In some embodiments, the second stage may include intermediate steps before and / or after hybrid bonding of the first wafer 102 to the second wafer 104. For example, an array wafer including a semiconductor structure 140 and a transistor array region 150 may be provided. The array wafer may be bonded to a carrier wafer to form the first wafer 102 and support the first wafer 102 during the intermediate steps. The array wafer may be thinned and / or polished to provide a clean interface for hybrid bonding, and the carrier wafer may be removed after hybrid bonding to expose the array wafer.

[0083] like Figure 6CAs seen in FIG. 1 , the second wafer 104 includes peripheral circuits 108 (e.g., CMOS technology) embedded in the substrate 101 and connected via the bonding interface 106 through interconnects 111. The second wafer 104 may also include an interconnect layer 110 located near the bonding interface 106 and above the peripheral circuits 108. After hybrid bonding, the first wafer 102 includes interconnects (e.g., bit line contacts) 113 connected to the interconnects 111 of the second wafer 104 through the bonding interface 106. The first wafer 102 may also include an interconnect layer 112 located near the bonding interface 106.

[0084] Fig.6D is a top view showing a third stage in forming a memory device 600 having a pillar-type capacitor. Fig. 6E is a cross-sectional view showing the third stage. The third stage includes: applying a mask 70 on top of the fill material 16 disposed on the semiconductor structure 140. The mask 70 can be used to etch features through one or more layers of the semiconductor structure 140. Here, the mask 70 includes circular spacer holes 73 aligned between the first holes 11. The spacer holes 73 and the perimeter 72 of the mask 70 can be etched to pattern various features in the semiconductor structure 140. Depending on the specific implementation, other mask shapes and / or sizes can also be used. For example, the square, rectangular, triangular, polygonal, etc. spacer holes and / or perimeters of the mask can be implemented depending on the desired patterning.

[0085] Fig. 6F is a top view showing a fourth stage in forming a memory device 600 having a pillar-type capacitor. Figure 6G is a cross-sectional view showing the fourth stage (as shown in Fig. 6F The section AA' shown in FIG. Figure 6H is another cross-sectional view showing the fourth stage (as shown in Fig. 6F The fourth stage includes etching a second hole 71 using the spacer hole 73 of the mask 70 as a guide. The second hole 71 penetrates the semiconductor structure 140. The semiconductor structure 140 is also etched around the first hole 11 along the perimeter 72 of the mask 70, thereby producing an etched perimeter 74 of the semiconductor structure 140. The second hole 71 and the perimeter 74 can be etched using any suitable technique (e.g., a dry etching method). In this example, for example, after etching, CMP or other suitable methods are also used to remove the excess layer of filling material 16 disposed on the semiconductor structure 140.

[0086] In this embodiment, all layers of the semiconductor structure 140 are etched except for etching the bottom second dielectric material 42-3. However, any number of layers of the semiconductor structure 140 may be etched depending on the desired capacitor configuration. For example, in some embodiments, only the top first dielectric material 42-1 is etched, which changes the structure of the resulting pillar capacitor. After etching, the layers of sacrificial materials 12-1 and 12-2 are removed from the semiconductor structure 140 to expose the first electrode 13. For example, the sacrificial layers 12-1 and 12-2 may be removed using a wet etching method or other suitable material removal process. Any excess material created by the etching is also removed along with the layers of sacrificial materials 12-1 and 12-2, thereby creating a Figure 6G The structure of the semiconductor structure 140 shown in FIG. The sacrificial layers 12-1 and 12-2 may be removed through the second holes 71 etched in any of the layers of the first dielectric material 42-1 and 42-2. Alternatively or additionally, the sacrificial layers 12-1 and 12-2 may be removed laterally around the etched perimeter 74 of the semiconductor structure 140.

[0087] Fig.6I is a top view showing a fifth stage in forming a memory device 600 having a pillar-type capacitor. Figure 6J is a cross-sectional view showing the fifth stage (as shown in Fig.6I The section AA' shown in FIG. Figure 6K is another cross-sectional view showing the fifth stage (as shown in Fig.6I The fifth stage includes depositing an isolation layer 15 (e.g., a high-k dielectric material) on the first electrode 13. Specifically, the isolation layer 15 is deposited on the first electrode 13 in the etched second hole 71. Alternatively or additionally, the isolation layer 15 may be deposited laterally around the first hole 11 by way of the etched perimeter 74 of the semiconductor structure 140. Figure 6J As seen in FIG. 1 , the isolation layer 15 may also be deposited on other exposed surfaces, such as the top of the fill material 16 remaining in the first hole 11 and the layers of the second dielectric material 42-1, 42-2, and 42-3. Generally, all high temperature processes (e.g., involving temperatures of about 500° C. or higher) are completed prior to depositing the isolation layer 15. Thus, the isolation layer 15 is not subjected to temperatures that may cause failure or degradation of the high-k material (e.g., change the crystal structure and / or crystalline phase of the high-k material), and thus maintains a relatively high dielectric constant (e.g., a dielectric constant of about 5 or greater).

[0088] A second electrode 14 is then formed on the isolation layer 15 in a similar manner (e.g., deposited through the etched second hole 71 and / or laterally deposited through the etched perimeter 74). Here, the second electrode 14 is composed of layers of two different conductive materials 14-1 and 14-2, which can include, for example, TiN and SiGe, respectively. The second electrode 14 can also be composed of a single layer of conductive material (e.g., TiN or SiGe). The first electrode 13 is separated from the second electrode 14 by the isolation layer 15, thereby forming a columnar capacitor 10. Due to the vertical geometry of the columnar capacitor 10 and the high dielectric constant isolation layer 15, the columnar capacitor 10 is generally of high quality, for example, having higher capacitance and / or reduced wafer area consumption, compared to planar capacitors and / or capacitors manufactured using other methods.

[0089] like Figure 6J As observed in , the columnar capacitor 10 has a relatively complex 3D structure due to various etching processes, material removal and deposition steps. For example, the columnar capacitor 10 includes an area defined by two layers of second dielectric materials 42-1 and 42-2 up and down (vertically). The area is defined by two first electrodes 13 of adjacent first holes 11 left and right (laterally). The isolation layer 15 is supported on a continuous surface opposite to the two layers of second dielectric materials 42-1 and 42-2 and the two first electrodes 13. The shared second electrode 14 occupies the space defined by the continuous surface, so that the conductive material 14-1 is layered on the isolation layer 15, and the conductive material 14-2 fills the remaining space. The columnar capacitor 10 can be understood as two capacitors corresponding to the two first electrodes 13 that share the second electrode 14 between them.

[0090] Figure 6Lis a cross-sectional view showing an optional sixth stage of forming a memory device 600 having a pillar capacitor. A first conductive layer 30-1 is deposited on the second electrode 14, and one or more dielectric layers 33, which may include, for example, silicon oxide, silicon nitride, etc., are subsequently deposited on the second electrode 14. The first conductive layer 30-1 may interface with the pillar capacitor, and the one or more dielectric layers 33 may provide electrical insulation for the memory device 600. In addition, the one or more dielectric layers 33 may fill the dielectric regions of the semiconductor structure 140 that have been removed via etching during the fourth stage. A second conductive layer 30-2 is deposited on the one or more dielectric layers 33. The second conductive layer 30-2 is connected to the peripheral circuit 108 via the bonding interface 106 through the first contact 31-1. The second conductive layer 30-2 may accommodate, for example, a pad output structure including a contact pad 32. Alternatively or additionally, a pad output interconnect layer may be deposited on the second conductive layer 30-2. For example, the second contact 31 - 2 connects the first conductive layer 30 - 1 and the second conductive layer 30 - 2 , thereby allowing the peripheral circuit 108 to adjust the pillar capacitor when operating the vertical transistor of the memory device 600 .

[0091] Fig. 7A is a top view illustrating a first stage in forming a memory device 700 having a cup-type capacitor (which may be operationally and / or structurally similar to memory device 100 , memory device 200 , memory device 300 , and / or memory device 600 ). Figure 7B is a cross-sectional view showing the first stage. The first stage includes: forming a first electrode 13 (e.g., TiN) in the first hole 11 and filling the first hole 11 with a sacrificial material 12 (e.g., carbon) to (at least partially) cover the first electrode 13. In this example, the sacrificial material 12 generally provides support for the structure of the resulting cup capacitor throughout the manufacturing process, especially during one or more high temperature processes. Similar to Figure 6A-6L In the pillar-type capacitor described in the embodiment, the first electrode 13 is lined in the first hole 11 and is recessed to establish a relatively uniform material layer within the first hole 11, but the first hole 11 may be filled in a different manner. In contrast to the pillar-type capacitor, in this embodiment, the semiconductor structure 140 is not composed of the sacrificial material 12. Here, if desired, the semiconductor structure 140 may be a single material, and the layers of the first dielectric material 41 and the second dielectric material 42 may be the same material.

[0092] Figure 7Cis a cross-sectional view showing a second stage of forming a memory device 700 having a cup capacitor. The second stage includes hybrid bonding the first wafer 102 to the second wafer 104 at the bonding interface 106. Hybrid bonding generally involves one or more high temperature processes. For example, additional high temperature processes and thermal treatments may be performed before and / or after hybrid bonding to form various components of the memory device 700, such as the bit line 206.

[0093] The second wafer 104 includes peripheral circuits 108 (e.g., CMOS technology) embedded in the substrate 101 and connected via the bonding interface 106 through interconnects 111. The second wafer 104 may also include an interconnect layer 110 located at the bonding interface 106 and above the peripheral circuits 108. After hybrid bonding, the first wafer 102 includes interconnects (e.g., bit line contacts) 113 connected to the interconnects of the second wafer 104 at the bonding interface 106. The first wafer 102 may also include an interconnect layer 112 located near the bonding interface 106.

[0094] Fig.7D is a cross-sectional view showing a third stage of forming a memory device 700 having a cup-type capacitor. After one or more high temperature processes, the third stage includes: removing the sacrificial material 12 from the first hole 11 to expose the first electrode 13. For example, the sacrificial material 12 can be removed using an ashing method or other suitable material removal process. The sacrificial material 12 may include carbon, silicon oxide, silicon nitride, and other materials different from the first electrode 13. Then, an isolation layer 15 (e.g., a high-k dielectric material) is deposited into the first hole 11 on the first electrode 13. In this example, the isolation layer 15 is also deposited on the semiconductor structure 140. The isolation layer 15 is not subjected to high temperature processes that may cause failure or degradation of the high-k material (e.g., changing the crystal structure and / or crystal phase of the high-k material), and therefore maintains a relatively high dielectric constant (e.g., a dielectric constant of about 5 or greater).

[0095] The third stage also includes: forming a second electrode 14 (e.g., TiN) on the isolation layer 15. The second electrode 14 fills the first hole 11 and forms a layer on the portion of the isolation layer 15 disposed on the semiconductor structure 140. The first electrode 13 is separated from the second electrode 14 by the isolation layer 15, thereby forming a cup capacitor 10. Due to the vertical geometry of the cup capacitor 10 and the isolation layer 15 with a high dielectric constant, the cup capacitor 10 is generally of high quality, for example, with higher capacitance and / or reduced wafer area consumption compared to planar capacitors and / or capacitors manufactured using other methods. The first conductive layer 30-1 is then deposited on the second electrode 14, for example, so as to interface with the cup capacitor 10.

[0096] Fig. 7Eis a cross-sectional view showing a fourth stage of forming a memory device 700 having a cup capacitor. The fourth stage includes: depositing one or more dielectric layers 33 on the first conductive layer 30-1, for example, to provide electrical insulation for the memory device 700. The second conductive layer 30-2 is deposited on the one or more dielectric layers 33. The second conductive layer 30-2 is connected to the peripheral circuit 108 via the bonding interface 106 through the first contact 31-1. The second conductive layer 30-2 can accommodate a pad output structure. Alternatively or additionally, a pad output interconnect layer can be deposited on the second conductive layer 30-2. For example, the second contact 31-2 connects the first conductive layer 30-1 and the second conductive layer 30-2, thereby allowing the peripheral circuit 108 to adjust the cup capacitor 10 when operating the vertical transistor of the memory device 700.

[0097] Figure 8 A block diagram of an exemplary system 1400 including one or more memory devices is shown. System 1400 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game controller, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 8 As shown, the system 1400 may include a host 1408 and a memory system 1402 having one or more memory devices 1404 and a memory controller 1406. The host 1408 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 1408 may be configured to send data to the memory device 1404 or receive data from the memory device 1404.

[0098] The memory devices 1404 may be any combination of the memory devices disclosed herein, such as NAND flash memory devices, NOR flash memory devices, phase change memory (PCM) devices, resistive memory devices, RAM devices, DRAM devices, RRAM devices, magnetic memory devices, spin transfer torque (STT) memory devices, and other devices. Such memory devices with superior quality capacitors (e.g., increased capacitance) may be manufactured using the methods described in the present disclosure. In some embodiments, each memory device 1404 includes a DRAM device. A memory controller 1406 (also referred to as a controller circuit) is coupled to the memory devices 1404 and a host 1408 and is configured to control the memory devices 1404. For example, the controller circuit may be configured to operate memory cells of the memory devices 1404 via word lines and / or bit lines. The memory controller 1406 may manage data stored in the memory devices 1404 and communicate with the host 1408.

[0099] Implementations of the described subject matter may include one or more features alone or in combination.

[0100] For example, in a first embodiment, a method for manufacturing a memory device including capacitors, wherein each capacitor includes a first electrode and a second electrode separated by an isolation layer, the method including: providing a first wafer, the first wafer including a sacrificial material and a first electrode disposed in a first hole and contacting the sacrificial material; hybrid bonding the first wafer with a second wafer including a complementary metal oxide semiconductor (CMOS) device; removing the sacrificial material to expose the first electrode; depositing an isolation layer on the first electrode; and forming a second electrode on the isolation layer.

[0101] The above and other described embodiments may optionally include one or more of the following features:

[0102] The first feature may be combined with any of the following features, wherein providing a first wafer includes: providing an array wafer including a sacrificial material and a first hole; forming a first wafer including the array wafer and a carrier wafer, wherein forming the first wafer includes: bonding the array wafer to the carrier wafer; and thinning the array wafer, and wherein hybrid bonding the first wafer to the second wafer includes: hybrid bonding the array wafer to the second wafer; and removing the carrier wafer from the first wafer to expose the array wafer.

[0103] The second feature, which can be combined with any of the previous or following features, further includes: depositing a conductive layer on the second electrode; and forming a pad output structure connected to the conductive layer and the CMOS device.

[0104] A third feature, which can be combined with any of the previous or following features, wherein the first wafer includes a semiconductor structure, the semiconductor structure includes alternating layers of sacrificial material and dielectric material, and wherein the sacrificial material and the dielectric material are different dielectric materials, and the first hole penetrates the alternating layers.

[0105] A fourth feature, which can be combined with any of the previous or following features, wherein removing the sacrificial material to expose the first electrode comprises: forming second holes penetrating into the alternating layers between the first holes; and removing the layers of sacrificial material to expose the first electrode.

[0106] A fifth feature, which can be combined with any of the previous or following features, wherein depositing an isolation layer on the first electrode includes: depositing the isolation layer into the second hole and around the first hole, wherein the isolation layer is deposited on the first electrode, on a layer of dielectric material, and on a filling material included in the first hole.

[0107] A sixth feature, which can be combined with any of the previous or following features, wherein: the sacrificial material comprises silicon oxide (SiO2) and the dielectric material comprises silicon nitride (Si3N4); or the sacrificial material comprises Si3N4 and the dielectric material comprises SiO2.

[0108] A seventh feature, which can be combined with any of the previous or following features, wherein providing the first wafer includes: filling the first hole with a filling material to cover the first electrode, wherein the sacrificial material and the filling material are different materials.

[0109] An eighth feature, which can be combined with any of the previous or following features, wherein the first wafer includes a semiconductor structure, the semiconductor structure includes a first hole, and wherein providing the first wafer includes filling the first hole with a sacrificial material to cover the first electrode.

[0110] A ninth feature, which can be combined with any of the previous or following features, wherein depositing the isolation layer on the first electrode comprises: depositing the isolation layer into the first hole on the first electrode.

[0111] A tenth feature, which may be combined with any of the previous or following features, wherein the sacrificial material comprises carbon.

[0112] An eleventh feature, which can be combined with any of the previous or following features, wherein the isolation layer includes at least one of aluminum oxide, hafnium oxide or zirconium oxide.

[0113] A twelfth feature, which may be combined with any of the previous or following features, wherein the first electrode comprises titanium nitride (TiN).

[0114] The thirteenth feature, which can be combined with any of the previous or following features, is characterized in that the second electrode includes TiN and silicon germanium (SiGe).

[0115] For example, in a second embodiment, a method for manufacturing a memory device including capacitors, wherein each capacitor includes a first electrode and a second electrode separated by an isolation layer, the method including: providing a first wafer, the first wafer including a sacrificial material and a first electrode disposed in a first hole and contacting the sacrificial material; heat treating the first wafer; removing the sacrificial material to expose the first electrode; depositing an isolation layer on the first electrode; and forming a second electrode on the isolation layer.

[0116] The above and other described embodiments may optionally include one or more of the following features.

[0117] The first feature may be combined with any of the following features, wherein providing a first wafer includes: providing an array wafer including a sacrificial material and a first hole; forming a first wafer including the array wafer and a carrier wafer, wherein forming the first wafer includes: bonding the array wafer to the carrier wafer; and thinning the array wafer; and hybrid bonding the first wafer to a second wafer including a complementary metal oxide semiconductor (CMOS) device, wherein hybrid bonding the first wafer to the second wafer includes: hybrid bonding the array wafer to the second wafer; and removing the carrier wafer from the first wafer to expose the array wafer.

[0118] The second feature, which can be combined with any of the previous or following features, further includes: depositing a conductive layer on the second electrode; and forming a pad output structure connected to the conductive layer and the CMOS device.

[0119] A third feature, which can be combined with any of the previous or following features, wherein the first wafer includes a semiconductor structure, the semiconductor structure includes alternating layers of sacrificial material and dielectric material, wherein the sacrificial material and the dielectric material are different dielectric materials, and wherein the first hole extends through the alternating layers.

[0120] A fourth feature, which can be combined with any of the previous or following features, wherein removing the sacrificial material to expose the first electrode comprises: forming a second hole between the first holes, the second hole extending through the alternating layers; and removing the layer of sacrificial material to expose the first electrode.

[0121] A fifth feature, which can be combined with any of the previous or following features, wherein depositing an isolation layer on the first electrode includes: depositing the isolation layer into the second hole and around the first hole, wherein the isolation layer is deposited on the first electrode, on a layer of dielectric material, and on a filling material included in the first hole.

[0122] A sixth feature, which can be combined with any of the previous or following features, wherein: the sacrificial material comprises silicon oxide (SiO2) and the dielectric material comprises silicon nitride (Si3N4); or the sacrificial material comprises Si3N4 and the dielectric material comprises SiO2.

[0123] A seventh feature, which can be combined with any of the previous or following features, wherein providing the first wafer includes: filling the first hole with a filling material to cover the first electrode, wherein the sacrificial material and the filling material are different materials.

[0124] An eighth feature, which can be combined with any of the previous or following features, wherein the first wafer includes a semiconductor structure, the semiconductor structure includes a first hole, and wherein providing the first wafer includes filling the first hole with a sacrificial material to cover the first electrode.

[0125] A ninth feature, which can be combined with any of the previous or following features, wherein depositing the isolation layer on the first electrode comprises: depositing the isolation layer on the semiconductor structure and into the first hole on the first electrode.

[0126] A tenth feature, which may be combined with any of the previous or following features, wherein the sacrificial material comprises carbon.

[0127] An eleventh feature, which can be combined with any of the previous or following features, wherein the isolation layer includes at least one of aluminum oxide, hafnium oxide or zirconium oxide.

[0128] A twelfth feature, which may be combined with any of the previous or following features, wherein the first electrode comprises titanium nitride (TiN).

[0129] The thirteenth feature, which can be combined with any of the previous or following features, is characterized in that the second electrode includes TiN and silicon germanium (SiGe).

[0130] A fourteenth feature, which may be combined with any of the previous or following features, is characterized in that the heat treatment is performed at a temperature of 500° C. or higher.

[0131] In a third embodiment, a memory device includes: a first wafer including capacitors, wherein each capacitor includes a first electrode and a second electrode separated by an isolation layer, and wherein the isolation layer includes a dielectric material having a dielectric constant of 5 or greater; and a second wafer including a complementary metal oxide semiconductor (CMOS) device, wherein the second wafer is hybrid bonded to the first wafer.

[0132] The above and other described embodiments may optionally include one or more of the following features.

[0133] The first feature can be combined with any of the following features, wherein the dielectric material includes the smallest crystals having a minimum size and the largest crystals having a maximum size, and wherein the crystals in the dielectric material satisfy one or more size conditions, the one or more size conditions including at least one of the following: the number of large crystals in the dielectric material accounts for less than 20% of the total number of crystals, wherein the large crystals have a size between 2 / 3*(minimum size+maximum size) and the maximum size; the number of large crystals in the dielectric material accounts for less than 15% of the total number of crystals, wherein the large crystals have a size between 3 / 4*(minimum size+maximum size) and the maximum size; or the average size of the crystals in the dielectric material is between the minimum size and 1 / 2*(minimum size+maximum size).

[0134] A second feature, which can be combined with any of the following features, further includes two separated layers of material, wherein the capacitor includes a first capacitor and a second capacitor that share a shared second electrode, and wherein the dielectric material is supported on a continuous surface formed by the first electrode of the first capacitor, the first electrode of the second capacitor, and the two separated layers of material, and wherein the shared second electrode is supported in a space defined by the dielectric material supported on the continuous surface.

[0135] A third feature, which can be combined with any of the following features, wherein the capacitor includes a first hole, and wherein the first hole is lined with the first electrode, lined with the dielectric material, and filled with the second electrode.

[0136] In a fourth embodiment, a system includes: a memory device, comprising: a first wafer including capacitors, wherein each capacitor includes a first electrode and a second electrode separated by an isolation layer, wherein the isolation layer includes a dielectric material having a dielectric constant of 5 or greater; and a second wafer including complementary metal oxide semiconductor (CMOS) devices, wherein the second wafer is hybrid bonded to the first wafer; and a memory controller electrically connected to the memory device, wherein the memory controller is configured to control the memory device.

[0137] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. Accordingly, other embodiments are within the scope of the following claims.

Claims

1. A method of manufacturing a memory device comprising a capacitor, wherein: Each capacitor includes a first electrode and a second electrode separated by an isolation layer, the method comprising: A first wafer is provided, wherein the first wafer comprises: Sacrificial materials; and the first electrode, the first electrode being disposed in the first hole and in contact with the sacrificial material; hybrid bonding the first wafer to a second wafer including complementary metal oxide semiconductor (CMOS) devices; removing the sacrificial material to expose the first electrode; depositing the isolation layer on the first electrode; and The second electrode is formed on the isolation layer.

2. The method according to claim 1, wherein: Providing the first wafer includes: An array wafer is provided, wherein the array wafer comprises: the sacrificial material; and the first hole; Forming the first wafer including the array wafer and the carrier wafer, wherein forming the first wafer includes: bonding the array wafer to the carrier wafer; and Thinning the array wafer; and Wherein, hybrid bonding the first wafer and the second wafer comprises: hybrid bonding the array wafer and the second wafer; and The carrier wafer is removed from the first wafer to expose the array wafer.

3. The method according to any preceding claim, further comprising: depositing a conductive layer on the second electrode; as well as A pad output structure is formed that is connected to the conductive layer and the CMOS device.

4. The method according to claim 1, wherein: The first wafer includes a semiconductor structure including alternating layers of the sacrificial material and a dielectric material, and wherein the sacrificial material and the dielectric material are different dielectric materials, and the first hole extends through the alternating layers.

5. The method according to claim 4, wherein: Removing the sacrificial material to expose the first electrode includes: forming second holes penetrating into the alternating layers between the first holes; and The layer of sacrificial material is removed to expose the first electrode.

6. The method according to claim 5, wherein: Depositing the isolation layer on the first electrode comprises: The isolation layer is deposited into the second hole and around the first hole, wherein the isolation layer is deposited on the first electrode, on the layer of dielectric material, and on a fill material included in the first hole.

7. The method according to any one of claims 4 to 6, wherein: The sacrificial material comprises silicon oxide (SiO2) and the dielectric material comprises silicon nitride (Si3N4); or The sacrificial material includes Si3N4, and the dielectric material includes SiO2.

8. A method according to any preceding claim, wherein: Providing the first wafer includes: The first hole is filled with a filling material to cover the first electrode, wherein the sacrificial material and the filling material are different materials.

9. The method according to claim 1, wherein: The first wafer includes a semiconductor structure including the first hole, and wherein providing the first wafer includes filling the first hole with the sacrificial material to cover the first electrode.

10. The method according to claim 9, wherein: Depositing the isolation layer on the first electrode comprises: The isolation layer is deposited into the first hole on the first electrode.

11. The method according to any one of claims 9 to 10, wherein: The sacrificial material includes carbon.

12. A method according to any preceding claim, wherein: The isolation layer includes at least one of aluminum oxide, hafnium oxide or zirconium oxide.

13. A method according to any preceding claim, wherein: The first electrode includes titanium nitride (TiN).

14. A method according to any preceding claim, wherein: The second electrode includes TiN and silicon germanium (SiGe).

15. A method of manufacturing a memory device comprising a capacitor, wherein: Each capacitor includes a first electrode and a second electrode separated by an isolation layer, the method comprising: A first wafer is provided, wherein the first wafer comprises: Sacrificial materials; and the first electrode, the first electrode being disposed in the first hole and in contact with the sacrificial material; performing a heat treatment on the first wafer; removing the sacrificial material to expose the first electrode; depositing the isolation layer on the first electrode; and The second electrode is formed on the isolation layer.

16. The method according to claim 15, wherein: Providing the first wafer includes: An array wafer is provided, wherein the array wafer comprises: the sacrificial material; and the first hole; Forming the first wafer including the array wafer and the carrier wafer, wherein forming the first wafer includes: bonding the array wafer to the carrier wafer; and thinning the array wafer; and Hybrid bonding the first wafer to a second wafer including a complementary metal oxide semiconductor (CMOS) device, wherein hybrid bonding the first wafer to the second wafer comprises: hybrid bonding the array wafer and the second wafer; and The carrier wafer is removed from the first wafer to expose the array wafer.

17. The method according to claim 16, further comprising: depositing a conductive layer on the second electrode; as well as A pad output structure is formed that is connected to the conductive layer and the CMOS device.

18. The method according to claim 15, wherein: The first wafer includes a semiconductor structure including alternating layers of the sacrificial material and a dielectric material, wherein the sacrificial material and the dielectric material are different dielectric materials, and wherein the first hole extends through the alternating layers.

19. The method according to claim 18, wherein: Removing the sacrificial material to expose the first electrode includes: forming second holes between the first holes, the second holes penetrating the alternating layers; and The layer of sacrificial material is removed to expose the first electrode.

20. The method according to claim 19, wherein: Depositing the isolation layer on the first electrode comprises: The isolation layer is deposited into the second hole and around the first hole, wherein the isolation layer is deposited on the first electrode, on the layer of dielectric material, and on a fill material included in the first hole.

21. The method according to any one of claims 18 to 20, wherein: The sacrificial material comprises silicon oxide (SiO2) and the dielectric material comprises silicon nitride (Si3N4); or The sacrificial material includes Si3N4, and the dielectric material includes SiO2.

22. The method according to any one of claims 15 to 21, wherein: Providing the first wafer includes: The first hole is filled with a filling material to cover the first electrode, wherein the sacrificial material and the filling material are different materials.

23. The method according to claim 15, wherein: The first wafer includes a semiconductor structure including the first hole, and wherein providing the first wafer includes filling the first hole with the sacrificial material to cover the first electrode.

24. The method according to claim 23, wherein: Depositing the isolation layer on the first electrode comprises: The isolation layer is deposited on the semiconductor structure and into the first hole on the first electrode.

25. The method according to any one of claims 23-24, wherein: The sacrificial material includes carbon.

26. The method according to any one of claims 15 to 25, wherein: The isolation layer includes at least one of aluminum oxide, hafnium oxide or zirconium oxide.

27. The method according to any one of claims 15 to 26, wherein: The first electrode includes titanium nitride (TiN).

28. The method according to any one of claims 15 to 27, wherein: The second electrode includes TiN and silicon germanium (SiGe).

29. The method according to any one of claims 15 to 28, wherein: The heat treatment is performed at a temperature of 500° C. or higher.

30. A memory device comprising: a first wafer comprising capacitors, wherein each capacitor comprises a first electrode and a second electrode separated by an isolation layer, and wherein the isolation layer comprises a dielectric material having a dielectric constant of 5 or greater; and A second wafer includes complementary metal oxide semiconductor (CMOS) devices, wherein the second wafer is hybrid bonded to the first wafer.

31. The memory device of claim 30, wherein: The dielectric material comprises a smallest crystal having a smallest size and a largest crystal having a largest size, and wherein the crystals in the dielectric material satisfy one or more size conditions, the one or more size conditions comprising at least one of the following: The number of large crystals in the dielectric material accounts for less than 20% of the total number of crystals, wherein the large crystals have a size between 2 / 3*(the minimum size+the maximum size) and the maximum size; The number of large crystals in the dielectric material as a percentage of the total number of crystals is less than 15%, wherein the large crystals have a size between 3 / 4*(the minimum size+the maximum size) and the maximum size; or The average size of the crystals in the dielectric material is between the minimum size and 1 / 2*(the minimum size+the maximum size).

32. The memory device of any one of claims 30-31, further comprising two separated layers of material, wherein: The capacitor includes a first capacitor and a second capacitor that share a shared second electrode, and wherein the dielectric material is supported on a continuous surface formed by the first electrode of the first capacitor, the first electrode of the second capacitor and the two separated layers of material, and wherein the shared second electrode is supported in a space defined by the dielectric material supported on the continuous surface.

33. The memory device according to any one of claims 30 to 31, wherein: The capacitor comprises a first hole, and wherein the first hole is lined with the first electrode, lined with the dielectric material, and filled with the second electrode.

34. A system comprising: A memory device, the memory device comprising: a first wafer comprising capacitors, wherein each capacitor comprises a first electrode and a second electrode separated by an isolation layer, wherein the isolation layer comprises a dielectric material having a dielectric constant of 5 or greater; and a second wafer including complementary metal oxide semiconductor (CMOS) devices, wherein the second wafer is hybrid bonded to the first wafer; and A memory controller is electrically connected to the memory device, wherein the memory controller is configured to control the memory device.

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