Stacked FET with three-terminal SOT MRAM

Abstract

Embodiments for a three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) device are disclosed. A three-terminal SOT MRAM device includes a first type field effect transistor (FET) that drives an SOT line. Additionally, the first type FET includes a write gate in electrical contact with a write word line (WWL). In addition, the device also includes a second type FET in electrical contact with a magnetic tunnel junction (MTJ). Likewise, the second type FET includes a read gate in electrical contact with a read word line (RWL). Additionally, the first type FET is disposed over the second type FET. In addition, the three-terminal SOT MRAM device provides a density of three contact polycrystalline pitches (CPPs) per two cells.

Description

Background Art

[0001] The present disclosure relates to a stacked field effect transistor (FET), and more particularly, to a stacked FET with a three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM).

[0002] Integrated circuits, such as microprocessors, may have a relatively large number of circuit elements, such as transistors, arranged in a limited chip area. Transistors may be either n-type metal oxide semiconductor field effect transistor (nFET) or p-type metal oxide semiconductor FET (pFET) type devices, where the "N" and "P" designations depend on the type of dopants used in creating the source / drain regions of the device. Complementary metal oxide semiconductor (CMOS) technology refers to integrated circuit products that use both n-type and p-type transistor devices.

[0003] Additionally, the CMOS device may include stacked FETs that may be electrically connected, and / or isolated. Furthermore, the stacked FET CMOS device may be used in many applications from memory to computer processors. The memory may include, for example, a read-only memory (ROM) and a random access memory (RAM). More specifically, the RAM may include an MRAM, such as a three-terminal SOT MRAM.

[0004] Three-terminal SOT MRAM can provide separable read and write paths and allow state switching in sub-1 nanosecond (ns) using different write mechanisms (such as spin-orbit coupling). However, SOT MRAM can use two transistors (e.g., FETs) per cell for read and write operations, which increases density loss relative to other configurations (such as one transistor per resistive RAM (RRAM) magnetic tunnel junction (1T / 1R MTJ), which uses one transistor per cell). In SOT MRAM, a cell uses three transistor gate spacings (also known as contacted poly pitch (CPP)) in the X direction, and two fins (or two nanosheet devices) with merged epitaxial layers (epis) in the Y direction. Alternatively, SOT MRAM can include relatively wide nanosheets, which may not be practically implemented. Summary of the invention

[0005] Embodiments for a three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) device are disclosed. The three-terminal SOT MRAM device includes a first-type field effect transistor (FET) that drives a SOT line. Additionally, the first-type FET includes a write gate that is electrically in contact with a write word line (WWL). In addition, the device also includes a second-type FET that is electrically in contact with a magnetic tunnel junction (MTJ). Moreover, the second-type FET includes a read gate that is electrically in contact with a read word line (RWL). Additionally, the first-type FET is disposed above the second-type FET. In addition, the three-terminal SOT MRAM device provides a density of three contacted poly pitches (CPP) per two cells. Advantageously, these embodiments improve the density of a three-terminal SOT MRAM array.

[0006] Embodiments of a three-terminal SOT MRAM device are disclosed. The three-terminal SOT MRAM device includes an NFET that drives a SOT line. Additionally, the NFET includes a write gate that is in electrical contact with the WWL. Furthermore, the three-terminal SOT MRAM device includes a PFET that is in electrical contact with the MTJ. Additionally, the PFET includes a read gate that is in electrical contact with the RWL. Furthermore, the PFET is disposed above the NFET. Advantageously, these embodiments improve the density of a three-terminal SOT MRAM array.

[0007] Embodiments of a three-terminal SOT MRAM device are disclosed. The three-terminal SOT MRAM device includes a PFET that drives a SOT line. Additionally, the PFET includes a write gate that is electrically in contact with the WWL. Furthermore, the three-terminal SOT MRAM device includes an NFET that is electrically in contact with the MTJ. Additionally, the NFET includes a read gate that is electrically in contact with the RWL. Furthermore, the NFET is disposed above the PFET. Advantageously, these embodiments improve the density of a three-terminal SOT MRAM array.

[0008] An embodiment of a method for manufacturing a three-terminal SOT MRAM device is disclosed. The method includes forming a bottom dummy gate on an isolation layer in contact with a substrate. The method also includes forming a bottom source / drain epitaxy (S / D epitaxy). Additionally, the method includes performing ILD deposition on the dummy gate and the bottom S / D epitaxy. Additionally, the method includes performing chemical mechanical planarization to remove a gate hard mask of the bottom dummy gate and a pad in contact with the gate hard mask. Additionally, the method includes forming a bottom S / D sacrificial contact in contact with the bottom S / D epitaxy. Additionally, the method includes forming a bonding oxide disposed above a bottom layer including the bottom dummy gate. Additionally, the method includes bonding the bonding oxide to a nanosheet channel of a top layer. The top layer includes a sacrificial nanosheet layer in contact with the nanosheet channel. Additionally, the method includes performing active device patterning on the top layer. Additionally, the method includes forming a top dummy gate of the top layer. Additionally, the method includes forming a pad for the top layer. Additionally, the method includes forming a top S / D epitaxy for the top layer. Additionally, the method includes depositing an ILD for the top layer. Additionally, the method includes performing CMP to remove a hard mask for the top layer and a spacer for the top layer. Additionally, the method includes forming a gate opening mask. Additionally, the method includes removing a top dummy gate and a bottom dummy gate. Additionally, the method includes performing a SiGe release. Additionally, the method includes removing a sacrificial nanosheet layer. Additionally, the method includes forming a replacement gate for the top layer and the bottom layer. Additionally, the method includes forming a gate cutout that provides access to the top S / D epitaxy and the bottom S / D epitaxy. Additionally, the method includes forming a middle-of-line (MOL) contact. Additionally, the method includes removing a bottom S / D sacrificial contact. Additionally, the method includes using the gate cutout to form a contact metallization. Additionally, the method includes forming a back-end-of-line (BEOL) connection. Advantageously, these embodiments improve the density of a three-terminal SOT MRAM array.

[0009] An embodiment of a computer program product including program instructions stored on a computer-readable storage medium is disclosed. The program instructions are executable by a processor to cause the processor to perform a method for manufacturing a three-terminal SOT MRAM device. The method includes forming a bottom dummy gate on an isolation layer in contact with a substrate. The method also includes forming a bottom source / drain epitaxy (S / D epitaxy). Additionally, the method includes performing ILD deposition on the dummy gate and the bottom S / D epitaxy. In addition, the method includes performing chemical mechanical planarization to remove a gate hard mask of the bottom dummy gate and a pad in contact with the gate hard mask. Additionally, the method includes forming a bottom S / D sacrificial contact in contact with the bottom S / D epitaxy. In addition, the method includes forming a bonding oxide disposed above a bottom layer including the bottom dummy gate. In addition, the method includes bonding the bonding oxide to a nanosheet channel of a top layer. The top layer includes a sacrificial nanosheet layer in contact with the nanosheet channel. Additionally, the method includes performing active device patterning on the top layer. In addition, the method includes forming a top dummy gate of the top layer. In addition, the method includes forming a pad for the top layer. Additionally, the method includes forming a top S / D epitaxy for the top layer. Additionally, the method includes depositing an ILD for the top layer. Additionally, the method includes performing CMP to remove a hard mask for the top layer and a pad for the top layer. Additionally, the method includes forming a gate opening mask. Additionally, the method includes removing a top dummy gate and a bottom dummy gate. Additionally, the method includes performing a SiGe release. Additionally, the method includes removing a sacrificial nanosheet layer. Additionally, the method includes forming a replacement gate for the top layer and the bottom layer. Additionally, the method includes forming a gate cutout that provides access to the top S / D epitaxy and the bottom S / D epitaxy. Additionally, the method includes forming a middle-of-line (MOL) contact. Additionally, the method includes removing a bottom S / D sacrificial contact. Additionally, the method includes using the gate cutout to form a contact metallization. Additionally, the method includes forming a back-end-of-line (BEOL) connection. Advantageously, these embodiments improve the density of a three-terminal SOT MRAM array. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings included in this application are incorporated into this specification and form a part of this specification. They illustrate embodiments of the present disclosure and are used together with this specification to explain the principles of the present disclosure. The accompanying drawings only illustrate certain embodiments and do not limit the present disclosure.

[0011] Figure 1 is a block diagram of an example stacked field effect transistor (FET) with a three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) manufacturing manager according to some embodiments of the present disclosure.

[0012] Figure 2Ais a side view of a stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure.

[0013] Figure 2B is a top view of a stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure.

[0014] Figure 2C is a schematic diagram of stacked FETs with a three-terminal SOT MRAM according to some embodiments of the present disclosure.

[0015] Figure 3A and Figure 3B is a process flow diagram of a method for fabricating a stacked FET device with a three-terminal SOT MRAM according to some embodiments of the present disclosure.

[0016] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Fig. 4I , Figure 4J , Figure 4K ,and Figure 4L is an example state of manufacture of an example stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure.

[0017] Although the present disclosure can be processed into various modifications and alternative forms, its details have been shown in the accompanying drawings by way of example and will be described in detail. However, it should be understood that its purpose is not to limit the present disclosure to the described embodiments. On the contrary, its purpose will cover all modifications, equivalents, and alternatives that fall within the scope of the present disclosure. DETAILED DESCRIPTION

[0018] As previously described, three-terminal SOT MRAM can provide separable read and write paths and allow state switching in sub-1 nanosecond (ns) using different write mechanisms (such as spin-orbit coupling). However, SOT MRAM can use two transistors (e.g., FETs) per cell for read and write operations, which increases density loss relative to other configurations (e.g., one transistor per resistive RAM (RRAM) magnetic tunnel junction (1T / 1R MTJ), which uses one transistor per cell). In SOT MRAM, a cell uses three transistor gate spacings (also known as CPP (contacted poly pitch)) in the X direction and two fins (or two nanosheet devices) with merged epitaxial layers (epi) in the Y direction. Alternatively, SOT MRAM can include relatively wide nanosheets, which may not be practically implemented.

[0019] Thus, some embodiments of the present disclosure may provide a relatively high density three-terminal SOT MRAM integrated using stacked nanosheet technology, and a method of manufacturing such an embodiment, which may provide a stacked FET SOT MRAM with 3CPP for every two cells (i.e., 1.5CPP per cell). More specifically, such an embodiment may include a three-terminal spin-orbit torque MRAM array having an NFET transistor driving a SOT line, wherein the gate is connected to a write word line. Additionally, such an embodiment may include a PFET transistor connected to an MTJ, wherein the gate is connected to a read word line. In addition, at least one type of FET (i.e., n-type) is stacked on top of a different type of FET (i.e., p-type). The method of manufacturing such an embodiment may be performed using stacked nanosheet technology through a wafer through isolation oxide bonding and contacting the bottom FET.

[0020] In this way, some embodiments of the present disclosure can provide memory devices that represent improvements over existing memory devices. Specifically, such embodiments can double the surface density achieved by current SOT schemes. Additionally, such embodiments can be compatible with technologies including, but not limited to, nanosheets, FinFETs, and monolithic transistor integration. In addition, in such embodiments, strong pFETs (e.g., pFETs with enhanced current drive) can be used for read operations using directional engineering of top or high mobility channel materials (e.g., silicon germanium and / or germanium [SiGe / Ge]). Additionally, in such embodiments, the PFET current can be tuned by increasing the number of pFET slices.

[0021] Figure 1 is a block diagram of an example stacked field effect transistor (FET) with a three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) manufacturing manager 150 according to some embodiments of the present disclosure.

[0022] In various embodiments, the example stacked FET with three-terminal SOT MRAM manufacturing manager 150 may perform the method described in FIG. 3 and / or cause one or more machines to design, manufacture, and / or utilize the method described in FIG. Figure 2A , Figure 2B , Figures 4A-4L, 5A, and 5B. In some embodiments, the example stacked FET with three-terminal SOT MRAM manufacturing manager 150 provides instructions for the aforementioned methods and / or functions to a client machine, so that the client machine performs the method, or a portion of the method, based on the instructions provided by the example stacked FET with three-terminal SOT MRAM manufacturing manager 150. In some embodiments, the example stacked FET with three-terminal SOT MRAM manufacturing manager 150 includes software executed on hardware incorporated into multiple devices.

[0023] Various aspects of the present disclosure are described by narrative text, flow charts, block diagrams of computer systems, and / or block diagrams of machine logic included in computer program product (CPP) embodiments. With respect to any flow chart, depending on the technology involved, the operations may be performed in an order different from the order shown in a given flow chart. For example, again depending on the technology involved, two operations shown in consecutive flow chart blocks may be performed in a reverse order, as a single integrated step, simultaneously, or in a manner that at least partially overlaps in time.

[0024] Computer program product embodiments ("CPP embodiments" or "CPP") are terms used in this disclosure to describe any collection of one or more storage media (also referred to as "media") that are collectively included in a collection of one or more storage devices that collectively include machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A "storage device" is any tangible device that can hold and store instructions for use by a computer processor. Without limitation, a computer-readable storage medium may be an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include: magnetic disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), static random access memories (SRAM), compact disk read-only memories (CD-ROM), digital versatile disks (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punch cards or pits / land formed in a major surface of a disk), or any suitable combination of the foregoing. Computer-readable storage media (as the term is used in this disclosure) should not be construed as storage in the form of transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, light pulses transmitted through fiber optic cables, electrical signals transmitted through wires, and / or other transmission media. As those skilled in the art will appreciate, data is typically moved at some occasional point in time during normal operation of the storage device, such as during access, defragmentation, or garbage collection, but this does not make the storage device transient because the data is not transient when it is stored.

[0025] The computing environment 100 includes an example of an environment for executing at least some of the computer codes involved in executing the methods of the present invention, such as a stacked FET three-terminal SOT MRAM manufacturing manager 150. In addition, the computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end-user device (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, the computer 101 includes a processor set 110 (including a processing circuit system 120 and a cache 121), a communication structure 111, a volatile memory 112, a persistent storage device 113 (including an operating system 122 and a box 150, as identified above), a peripheral device set 114 (including a user interface (UI) device set 123, a storage device 124, and an Internet of Things (IoT) sensor set 125), and a network module 115. The remote server 104 includes a remote database 130. The public cloud 105 includes a gateway 140 , a cloud orchestration module 141 , a host physical machine set 142 , a virtual machine set 143 , and a container set 144 .

[0026] Computer 101 may take the form of a desktop computer, laptop computer, tablet computer, smart phone, smart watch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device now known or to be developed in the future that is capable of running programs, accessing a network, or querying a database such as remote database 130. As is well known in the art of computer technology, and depending on the technology, the performance of computer-implemented methods may be distributed among multiple computers and / or among multiple locations. On the other hand, in this presentation of computing environment 100, the detailed discussion focuses on a single computer, particularly computer 101, to keep the presentation as simple as possible. Even though Figure 1 1 is not shown as being in the cloud, but the computer 101 can be located in the cloud. On the other hand, the computer 101 need not be in the cloud, except to any extent that can be positively indicated.

[0027] Processor set 110 includes one or more computer processors of any type now known or to be developed in the future. Processing circuit system 120 can be distributed over multiple packages, such as multiple coordinated integrated circuit chips. Processing circuit system 120 can implement multiple processor threads and / or multiple processor cores. Cache 121 is a memory located in (multiple) processor chip packages, and is generally used for data or code that should be quickly accessed by threads or cores running on processor set 110. Cache memory is generally organized into multiple levels according to relative proximity to the processing circuit system. Alternatively, some or all of the caches of the processor set may be located "off chip". In some computing environments, processor set 110 may be designed to work with qubits and perform quantum computing.

[0028] Computer readable program instructions are typically loaded onto the computer 101 to cause the processor set 110 of the computer 101 to perform a series of operating steps to implement the computer-implemented method, so that the executed instructions will instantiate the method specified in the flowchart and / or the narrative description of the computer-implemented method included in this document (collectively referred to as the "inventive method"). These computer readable program instructions are stored in various types of computer readable storage media, such as cache 121 and other storage media discussed below. The program instructions and associated data are accessed by the processor set 110 to control and direct the execution of the inventive method. In the computing environment 100, at least some of the instructions for executing the inventive method can be stored in the persistent storage device 113 in the box 150.

[0029] The communication fabric 111 is the signal conduction paths that allow the various components of the computer 101 to communicate with each other. Typically, the fabric is made up of switches and conductive paths, such as those that make up a bus, a bridge, physical input / output ports, etc. Other types of signal communication paths may be used, such as fiber optic communication paths and / or wireless communication paths.

[0030] The volatile memory 112 is any type of volatile memory now known or to be developed in the future. Examples include dynamic random access memory (RAM) or static RAM. Typically, the volatile memory 112 is characterized by random access, but this is not required unless affirmatively indicated. In the computer 101, the volatile memory 112 is located in a single package and is internal to the computer 101, but, alternatively or additionally, the volatile memory can be distributed in multiple packages and / or located externally relative to the computer 101.

[0031] Persistent storage 113 is any form of non-volatile storage for computers known now or to be developed in the future. The non-volatility of the storage means that the stored data is maintained regardless of whether power is supplied to the computer 101 and / or directly to the persistent storage 113. Persistent storage 113 may be a read-only memory (ROM), but typically at least a portion of the persistent storage allows writing of data, deletion of data, and rewriting of data. Some common forms of persistent storage include disks and solid-state storage devices. Operating system 122 may take several forms, such as various known proprietary operating systems or operating systems of the open source portable operating system interface type using a kernel. The code included in box 150 typically includes at least some of the code in the computer code involved in executing the method of the present invention.

[0032] The peripheral device set 114 includes a collection of peripheral devices of the computer 101. The data communication connection between the peripheral devices and other components of the computer 101 can be implemented in various ways, such as a Bluetooth connection, a near field communication (NFC) connection, a connection made by a cable (such as a universal serial bus (USB) type cable), a plug-in type connection (for example, a secure digital (SD) card), a connection made through a local area communication network, and even a connection made through a wide area network (such as the Internet). In various embodiments, the UI device set 123 may include components such as display screens, speakers, microphones, wearable devices (such as goggles and smart watches), keyboards, mice, printers, touchpads, game controllers, and tactile devices. The storage device 124 is an external storage device, such as an external hard drive, or a pluggable storage device, such as an SD card. The storage device 124 can be persistent and / or volatile. In some embodiments, the storage device 124 can take the form of a quantum computing storage device for storing data in the form of quantum bits. In embodiments where the computer 101 needs to have a large amount of storage (e.g., where the computer 101 locally stores and manages a large database), the storage may be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 125 is made up of sensors that can be used in IoT applications. For example, one sensor may be a thermometer, and another sensor may be a motion detector.

[0033] The network module 115 is a collection of computer software, hardware, and firmware that allows the computer 101 to communicate with other computers via the WAN 102. The network module 115 may include hardware such as a modem or a Wi-Fi signal transceiver, software for packetizing and / or depacketizing data transmitted over a communication network, and / or web browser software for transmitting data over the Internet. In some embodiments, the network control function and the network forwarding function of the network module 115 are executed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software defined networks (SDN)), the control function and the forwarding function of the network module 115 are executed on physically separated devices so that the control function manages several different network hardware devices. Computer-readable program instructions for executing the method of the present invention can be downloaded to the computer 101 from an external computer or an external storage device typically through a network adapter card or a network interface included in the network module 115.

[0034] WAN 102 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances by any technology now known or to be developed in the future for transmitting computer data. In some embodiments, WAN 102 may be replaced and / or supplemented by a local area network (LAN) designed to transmit data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include computer hardware, such as copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and edge servers.

[0035] End-user device (EUD) 103 is any computer system used and controlled by an end-user (e.g., a customer of an enterprise operating computer 101), and may take any form discussed above in conjunction with computer 101. EUD 103 typically receives helpful and useful data from the operation of computer 101. For example, in the hypothetical case where computer 101 is designed to provide recommendations to an end-user, the recommendations would typically be transmitted from network module 115 of computer 101 to EUD 103 via WAN 102. In this manner, EUD 103 may display or otherwise present the recommendations to the end-user. In some embodiments, EUD 103 may be a client device, such as a thin client, a heavy client, a mainframe computer, a desktop computer, etc.

[0036] Remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. Remote server 104 may be controlled and used by the same entity that operates computer 101. Remote server 104 represents a machine(s) that collects and stores helpful and useful data for use by other computers, such as computer 101. For example, in the hypothetical case where computer 101 is designed and programmed to provide recommendations based on historical data, the historical data may be provided to computer 101 from remote database 130 of remote server 104.

[0037] The public cloud 105 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and / or other computer capabilities, particularly data storage (cloud storage) and computing capabilities, without direct active management by users. Cloud computing typically leverages the sharing of resources to achieve consistency and economy of scale. The direct and active management of the computing resources of the public cloud 105 is performed by computer hardware and / or software of the cloud orchestration module 141. The computing resources provided by the public cloud 105 are typically implemented by virtual computing environments running on various computers that constitute the host physical machine set 142, which is the universe of physical computers in the public cloud 105 and / or the universe of physical computers available for the public cloud 105. Virtual computing environments (VCEs) typically take the form of virtual machines from a virtual machine set 143 and / or containers from a container set 144. It should be understood that these VCEs can be stored as images and can be transferred between various physical machine hosts as images or after instantiation of the VCEs. Cloud orchestration module 141 manages the transfer and storage of images, deploys new instantiations of VCEs, and manages active instantiations of VCE deployments. Gateway 140 is a collection of computer software, hardware, and firmware that allows public cloud 105 to communicate over WAN 102 .

[0038] Some further explanation of the virtualized computing environment (VCE) will now be provided. A VCE can be stored as an "image". A new active instance of the VCE can be instantiated from the image. Two common types of VCEs are virtual machines and containers. A container is a VCE that uses virtualization at the operating system level. This refers to an operating system feature in which the kernel allows the existence of multiple isolated user space instances (referred to as containers). From the perspective of the programs running therein, these isolated user space instances typically appear as actual computers. Computer programs running on ordinary operating systems can utilize all the resources of the computer, such as connected devices, files and folders, network sharing, CPU capabilities, and quantifiable hardware capabilities. However, programs running in a container can only use the contents of the container and the devices assigned to the container, which is a feature known as containerization.

[0039] Private cloud 106 is similar to public cloud 105, except that computing resources are only available for use by a single enterprise. Although private cloud 106 is depicted as communicating with WAN 102, in other embodiments, the private cloud can be completely disconnected from the Internet and can only be accessed through a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types), which are typically implemented by different vendors, respectively. Each of the multiple clouds remains as a separate and discrete entity, but the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable coordination, management, and / or data / application portability between the multiple constituent clouds. In this embodiment, public cloud 105 and private cloud 106 are both part of a larger hybrid cloud.

[0040] Figure 2A 2 is a side view of a stacked FET 200 with a three-terminal SOT MRAM according to some embodiments of the present disclosure. The stacked FET 200 with a three-terminal SOT MRAM includes a substrate 202, an isolation layer 204, a source / drain epitaxy (S / D epitaxy) 205, a nanosheet channel 210, a spacer (Sp) 216, an interlayer dielectric (ILD) 218, a high-K metal gate (HK / MG) 222, a metal layer (M1) 228, a bit line (BL) 230, a SOT channel 232, and a magnetic tunnel junction (MTJ) 234. The SOT channel 232 can be a heavy metal with a high spin Hall effect (SHE). The spin Hall effect is the conversion of a charge current to a spin-polarized current due to a spin-orbit interaction. The SOT channel 232 can be a heavy metal.

[0041] Substrate 202 may represent a silicon (Si) layer. In addition, isolation layer 204 may be composed of doped Si, epitaxial doped Si, buried oxide (BOX) (such as silicon dioxide (SiO2)), etc. In addition, S / D epitaxy 205 may represent a single crystal lattice structure across the interface. Nanosheet channel 210 may include nanosheets, which may be a semiconductor that is conductive ("on" state) in a transistor, or a semiconductor that is highly resistive ("off" state) in a transistor. The conductivity may be controlled by HK / MG 222. Spacer 216 may be a deposited material layer and etched back to provide a spacing between HK / MG 222 and contact (CA). Additionally, ILD 218 may be a dielectric material with a relatively low k constant (e.g., k=3.9 or less). HK / MG222 may provide a conductive gate electrode for a transistor. The material used for HK / MG may differ based on the type of device in the construction (e.g., N-type or P-type). Metal layer 222 may provide power or ground for MRAM 200. Bit line 230 may be a collection of memory cells used to generate a memory address in conjunction with a read or write WL.

[0042] According to some embodiments of the present disclosure, the three-terminal SOT MRAM 200 may represent a structure having a three-terminal spin-orbit torque MRAM array, wherein an NFET transistor drives a SOT line (SL) having a gate connected to a write word line (WW). Additionally, a PFET transistor connected to a magnetic tunnel junction (MTJ) having a gate connected to a read word line and at least one type of FET (i.e., N-type) is stacked on top of another type of FET (i.e., P-type). This stacked NFET and PFET configuration may provide a higher memory density than a conventional three-terminal SOT MRAM.

[0043] Figure 2B is a top view of a stacked FET with a three-terminal SOT MRAM 200 according to some embodiments of the present disclosure. The three-terminal SOT MRAM 200 includes a read word line (RWL) and a write word line (WWL) in the horizontal direction, and a SOT line (SL) and a bit line (BL) in the vertical direction. By providing current along a specific RWL or WWL and BL, the three-terminal SOT MRAM 200 can identify a specific HK / MG being written to or read from.

[0044] Figure 2C is a schematic diagram of a stacked FET with a three-terminal SOT MRAM 200 according to some embodiments of the present disclosure. The three-terminal SOT MRAM 200 includes RWL and WWL in the horizontal direction, and SL and BL in the vertical direction. In addition, the three-terminal SOT MRAM 200 includes a SOT channel made of a heavy metal (HM), and a magnetic tunnel junction (MTJ). The MTJ can be a magnetic storage device in which two magnetic layers are separated by an insulating barrier that allows a current whose amplitude depends on the orientation of the two magnetic layers to tunnel through the barrier when it is subjected to a small electrical bias.

[0045] According to some embodiments of the present disclosure, the three-terminal SOT MRAM 200 can read data from the MTJ and write data to the MTJ through the SOT channel by providing current to the S / D epitaxy 205. The specific S / D epitaxy 205 can be determined by the WL and BL carrying current, which flows to the S / D epitaxy 205 through the contact (CA). More specifically, the current flowing through the read WL can cause a read operation. Similarly, the current flowing through the write WL can cause a write operation. In this way, the three-terminal SOT MRAM 200 can store and retrieve data.

[0046] More specifically, the three-terminal SOT MRAM 200 can set the values ​​of WWL, RWL, BL, and SL by providing current (e.g., value = 1) or not providing current (e.g., value = 0), thereby performing read and write operations. Therefore, for a write operation, the three-terminal SOT MRAM 200 can set the value of WWL = RWL = 1. In addition, the three-terminal SOT MRAM 200 can set the value of BL / SL = Vw / GND or GND / Vw depending on the stored value. Conversely, for a read operation, the three-terminal SOT MRAM 200 can set the value of WWL = RWL = 0, and the value of BL / SL = Vr / VDD. Here, Vw and Vr refer to the write voltage and read voltage depending on the SOT and MTJ properties, respectively.

[0047] Figure 3 (covering Figure 3A and Figure 3B ) is a process flow diagram of a method for manufacturing a stacked FET device with a three-terminal SOT MRAM according to some embodiments of the present disclosure. In some embodiments, an example stacked FET with a three-terminal SOT MRAM manufacturing manager (such as for Figure 1 The described example stacked FET with a three-terminal SOT MRAM manufacturing manager 150) can perform method 300. In the method, the three-terminal SOT MRAM manufacturing manager 150 can use stacked nanosheet technology to manufacture the above-mentioned three-terminal spin-orbit torque MRAM structure by wafer bonding and contacting the bottom FET through an isolation oxide. By manufacturing the three-terminal SOT MRAM 200 in this manner, some embodiments of the present disclosure can improve the area density of current SOT MRAM devices. In addition, such embodiments can use stronger stacked FinFETs (e.g., fin height, channel orientation, or channel SiGe) or stacked nanosheets with an increased number of vertical stacks to adjust the pFET current without area loss. In some embodiments of the present disclosure, the three-terminal SOT MRAM 200 can provide a stacked FET SOT MRAM with 3CPP for two cells (i.e., 1.5CPP per cell). In contrast, the current three-terminal SOT MRAM can only provide 3CPP per cell. For clarity, refer to FIG. 4A to FIG. 4L Method 300 is described.

[0048] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Fig. 4I , Figure 4J , Figure 4K ,and Figure 4L 4A-4L include a top view 400-T and multiple side views (e.g., X, Y1, Y2, Y3) of a (multiple) manufacturing unit. Thus, the top view represents an active region 403 and three pillars 401 of a transistor. The active region 403 includes a channel under the gate, a channel under the spacer region, and a source / drain region. The pillar 401 can represent the location of the gate of the three-terminal SOT MRAM 200.

[0049] In addition, the side view is represented as a cross section of the unit(s) from the view of the corresponding cutting line in the top view 400-T. Figure 4A , view X shows a cross section of the unit(s) along cut line X. Similarly, views Y1, Y2, and Y3 show cross-sectional views of the unit(s) along cut lines Y1, Y2, and Y3. In this manner, example manufacturing state 4A may represent the unit(s) after operation 302 of method 300. Similarly, example manufacturing states 4B through 4C may represent the unit(s) after operation 302 of method 300. Figure 4L Views X, Y1, Y2, and Y3 of may represent the unit(s) after operations 304 to 320, respectively.

[0050] Return to reference Figure 3A, at operation 302, the stacked FET with the three-terminal SOT MRAM manufacturing manager 150 can direct the manufacturing tool to form a dummy gate and S / D epitaxy. Forming the dummy gate can involve depositing a sacrificial layer that serves as a placeholder for the gate. More specifically, the stacked FET with the three-terminal SOT MRAM manufacturing manager 150 can direct the manufacturing tool to form a patterned nanosheet stack on the isolation layer 404. The patterned nanosheet stack includes a sacrificial nanosheet layer 412, which can be composed of, for example, SiGe. Additionally, the channel nanosheet layer 410 can be composed of, for example, Si. In addition, the stacked FET with the three-terminal SOT MRAM manufacturing manager 150 can direct the manufacturing tool to deposit a dummy gate 408 and a gate hard mask layer 406 on the patterned nanosheet stack, and perform dummy gate patterning. Additionally, the stacked FET with the three-terminal SOT MRAM manufacturing manager 150 can direct the manufacturing tool to form a spacer 414 at the sidewalls of the dummy gate 408 and the gate hard mask 406. In addition, the stacked FET with the three-terminal SOT MRAM manufacturing manager 150 can direct the manufacturing tool to etch the nanosheet stack that is not protected by the gate hard mask 406 and the spacer 414. Additionally, the stacked FET with the three-terminal SOT MRAM manufacturing manager 150 can direct the manufacturing tool to perform SiGe indentation and form internal spacers. In addition, the stacked FET with the three-terminal SOT MRAM manufacturing manager 150 can direct the manufacturing tool to expand the S / D epitaxy 405 on the exposed channel nanosheet layer 410.

[0051] Figure 4A is an example manufacturing state 400A of a stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. The example manufacturing state 400A may represent a state of a cell with a stacked FET with a three-terminal SOT MRAM after operation 302 .

[0052] View X includes substrate 402, isolation layer 404, sacrificial nanosheet layer 412, hard mask cap 406, and source-drain epitaxy (S / D epitaxy) 405. More specifically, substrate 402 is a Si substrate. Furthermore, isolation layer 404 may represent an isolation layer and may be composed of silicon dioxide (SiO2). Additionally, sacrificial nanosheet layer 412 may be a SiGe layer that serves as a placeholder for a gate to be fabricated. Thus, sacrificial nanosheet layer 412 surrounds channel nanosheet layer 410 of cell 402-L, similar to a gate. To protect sacrificial nanosheet layer 412, hard mask cap 406 may provide coverage.

[0053] Views Y1 and Y2 include substrate 402, isolation layer 404, and S / D epitaxy 405. According to some embodiments of the present disclosure, S / D epitaxy 405 may be n-type epitaxy or p-type epitaxy. View Y3 includes substrate 402, isolation layer 404, channel nanosheet layer 410, sacrificial nanosheet layer 412, hard mask cap 406, and dummy gate 408. In this way, example manufacturing state 400A may represent the result of operation 302.

[0054] Referring back to FIG3 , at operation 304 , the three-terminal SOT MRAM manufacturing manager 150 may perform interlayer dielectric (ILD) deposition and chemical mechanical planarization. Performing ILD deposition may involve depositing ILD material (e.g., ILD 418). Additionally, performing CMP may involve removing the hard mask cap 406 and surrounding spacers 414 using chemical and mechanical processes.

[0055] At operation 306 , the three-terminal SOT MRAM fabrication manager 150 may form a bottom S / D sacrificial contact. Forming the bottom S / D sacrificial contact may involve depositing a sacrificial material in the ILD 418 .

[0056] Figure 4B is a block diagram of an example state of fabrication 400B of stacked FETs with a three-terminal SOT MRAM according to some embodiments of the present disclosure. The example state of fabrication 400B may represent a three-terminal SOT MRAM after operations 304 and 306.

[0057] View X includes substrate 402, isolation layer 404, S / D epitaxy 405, dummy gate 408, channel nanosheet layer 410, sacrificial nanosheet layer 412, spacer 414, and ILD 418. ILD 418 may be a dielectric material with a relatively low k constant (e.g., k=3.9 or less) that electrically isolates relatively close interconnects (e.g., channel nanosheet layer 410) arranged in several stages. Low-k dielectric materials may mitigate capacitive coupling between adjacent channel nanosheet layers 410. Compared to example manufacturing state 400A, view X shows the result of operation 304, i.e., removing hard mask cap 406 from example manufacturing state 400A by a CMP process, and depositing ILD 418 on S / D epitaxy 205.

[0058] The Y1 view includes the substrate 402, the isolation layer 404, the S / D epi 405, the ILD 418, and the bottom S / D sacrificial contact 420. The bottom S / D sacrificial contact 420 can be a placeholder for a contact to the S / D epi 205. The Y2 view includes the substrate 402, the isolation layer 404, the S / D epi, and the ILD 418. Compared to the example manufacturing state 400A, the views Y1, Y2 show the result of operation 304, i.e., the ILD 418 is deposited on the S / D epi 205.

[0059] View Y3 includes substrate 402, isolation layer 404, dummy gate 408, channel nanosheet layer 410, and sacrificial nanosheet layer 412. View Y3 shows the result of operation 304 compared to example fabrication state 400A, namely, hard mask cap 406 is removed from example fabrication state 400A by a CMP process.

[0060] Referring back to FIG3 , at operation 308 , the three-terminal SOT MRAM manufacturing manager 150 may form a bonding oxide and bond to the channel. Forming a bonding oxide may involve generating an isolation layer for the three-terminal SOT MRAM that isolates the bottom layer from the top layer to be fabricated. Additionally, bonding to the channel may involve depositing an additional sacrificial nanosheet layer 412 and a channel nanosheet layer 410.

[0061] Figure 4C 3 is a block diagram of an example state of manufacture 400C of stacked FETs with a three-terminal SOT MRAM according to some embodiments of the present disclosure. The example state of manufacture 400C may represent the three-terminal SOT MRAM after operation 308. Compared to the example state of manufacture 400B, the example state of manufacture 400C includes additional elements of a sacrificial nanosheet layer 412 and a channel nanosheet layer 410. More specifically, views X, Y1, Y2, and Y3 include a sacrificial nanosheet layer 412 and a channel nanosheet layer 410 on the bottom layer of the three-terminal SOT MRAM.

[0062] Return to reference Figure 3A At operation 310, the stacked FET with three-terminal SOT MRAM manufacturing manager 150 may direct the manufacturing tools to perform top active area patterning, dummy gate formation, spacer and s / d epitaxial formation, ILD deposition, and CMP. Operation 310 may be similar to operations 302 and 304. However, operation 310 may be performed with respect to the top layer of the stacked FET with three-terminal SOT MRAM.

[0063] Figure 4D 3 is a block diagram of an example manufacturing state 400D of an example stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. The example manufacturing state 400D may represent a three-terminal SOT MRAM after operation 310. As previously described, operation 310 is similar to operations 302 and 304 described above. Thus, views X, Y1, Y2, and Y3 include information related to Figure 4A The bottom layer described is similar to the top layer.

[0064] Compared to example fabrication state 400C, views X, Y1, Y2, Y3 of example fabrication state 400D show the result of operation 310, namely a top layer similar to the bottom layer below bonding oxide 416. However, view Y1 does not include sacrificial bottom S / D epitaxial contact 420 in the top layer.

[0065] 3, at operation 312, the stacked FET with three-terminal SOT MRAM fabrication manager 150 may direct the fabrication tool to perform gate opening masking. Performing gate opening masking may involve etching openings 421 into the top and bottom dummy gates 408 of the three-terminal SOT MRAM.

[0066] Figure 4E is a block diagram of an example state of manufacture 400E with example stacked FETs of a three-terminal SOT MRAM according to some embodiments of the present disclosure. The example state of manufacture 400E may represent the three-terminal SOT MRAM after operation 312.

[0067] Compared to example manufacturing state 400D, example manufacturing state 400E is similar with respect to views X, Y1, and Y2. However, view Y3 includes opening 421. In this manner, example manufacturing state 400E represents the result of operation 312.

[0068] Referring back to FIG3 , at operation 314, the stacked FET with three-terminal SOT MRAM manufacturing manager 150 can direct the manufacturing tool to perform dummy gate removal and SiGe release, as well as removal of the sacrificial gate extension. Removing the dummy gate can involve an etching process to remove the dummy gate 408. In addition, SiGe release can involve a chemical process to remove the sacrificial nanosheet layer 412 selective to the channel nanosheet layer 410.

[0069] Figure 4F is a block diagram of an example state of fabrication 400F with example stacked FETs of a three-terminal SOT MRAM according to some embodiments of the present disclosure. The example state of fabrication 400F may represent the three-terminal SOT MRAM after operation 314.

[0070] As shown, compared to the example manufacturing state 400E, the example manufacturing state 400E no longer includes the elements removed by operation 314. Specifically, view X no longer includes the dummy gate 408 and the sacrificial nanosheet layer 412. Similarly, view Y3 no longer includes the dummy gate 408 and the sacrificial nanosheet layer 412. However, the Y1 and Y2 views are unchanged compared to the example manufacturing state 400E. In these ways, the example manufacturing state 400F represents the result of operation 314.

[0071] 3 , at operation 316 , the stacked FET with three-terminal SOT MRAM manufacturing manager 150 can direct the manufacturing tool to form a replacement gate. Forming the replacement gate can involve using opening 421 to deposit a high-k metal gate material in the space created by removing dummy gate 408 and sacrificial nanosheet layer 412 .

[0072] Figure 4G is a block diagram of an example state of manufacture 400G with example stacked FETs of a three-terminal SOT MRAM according to some embodiments of the present disclosure. The example state of manufacture 400G may represent the three-terminal SOT MRAM after operation 316 .

[0073] Compared to example manufacturing state 400F, example manufacturing state 400G shows the space emptied by operation 314 being filled with high-k metal gate material 422. Specifically, views X and Y3 include deposited high-k metal gate material 422. In contrast, views Y1 and Y2 are unchanged from example manufacturing state 400F. In these ways, example manufacturing state 400G represents the result of operation 316.

[0074] 3 , at operation 318 , the stacked FET with three-terminal SOT MRAM manufacturing manager 150 may direct the manufacturing tool to form a gate cut. Forming the gate cut may involve removing the high-k gate material 422 .

[0075] Figure 4H is a block diagram of an example state of fabrication 400H with example stacked FETs of a three-terminal SOT MRAM according to some embodiments of the present disclosure. The example state of fabrication 400H may represent the three-terminal SOT MRAM after operation 318.

[0076] Compared to the example manufacturing state 400G, views X, Y1, and Y2 are unchanged. However, view Y3 shows the gate cut 424 formed by removing the high-k metal gate material 422. In this manner, the example manufacturing state 400H represents the result of operation 318.

[0077] Return to reference Figure 3A , operation 318 shows the flow to placeholder A. Placeholder A does not represent an operation of the method, but is used to convert Figure 3A The operations described in are connected with other operations of method 300, which will be referred to as Figure 3B Let's describe it in more detail.

[0078] Figure 3B is a process flow diagram of operations 320 to 326 of method 300 according to some embodiments of the present disclosure. For clarity, reference is made to Figures 4I to 4L to describe these operations.

[0079] Figure 3B The process flow diagram of FIG. 300 shows the flow from placeholder A to operation 320. As mentioned above, placeholder A does not represent the operation of method 300, but is used to connect Figure 3A Operations 302-318 described in and operations 320-326 described below.

[0080] At operation 320 , the stacked FET with three-terminal SOT MRAM manufacturing manager 150 may direct the manufacturing tool to form a middle-of-line (MOL) contact. Forming the middle-of-line contact may involve removing the ILD 418 to provide access to the S / D epi 405 and the bottom S / D sacrificial contact 420 .

[0081] Fig. 4I is a block diagram of an example state of fabrication 400I of stacked FETs with a three-terminal SOT MRAM according to some embodiments of the present disclosure. The example state of fabrication 400I may result from operation 320.

[0082] Compared to the example manufacturing state 400H, the example manufacturing state 400I shows the contact opening 423 created by removing the ILD 418 in operation 320. In particular, views X, Y1, Y2, and Y3 include openings 423 that provide access to the S / D epi 405 and the bottom S / D sacrificial contact 420. In this way, the example manufacturing state 400I represents the result of operation 320.

[0083] Return to reference Figure 3B At operation 322 , the stacked FET with three-terminal SOT MRAM manufacturing manager 150 may direct the manufacturing tool to remove the sacrificial contacts. Removing the sacrificial contacts may involve an etching process that removes the bottom S / D sacrificial contacts 420 .

[0084] Figure 4J 400J is a block diagram of an example manufacturing state 400J of a stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. The example manufacturing state 400J may be produced by operation 322. Compared to the example manufacturing state 400I, views X, Y2, and Y3 are not changed. However, view Y1 shows an opening instead of the bottom S / D sacrificial contact 420. In this way, the example manufacturing state 400J represents the result of operation 322.

[0085] Return to reference Figure 3B At operation 324 , the stacked FET with three-terminal SOT MRAM manufacturing manager 150 may direct the manufacturing tool to form contact metallization. Forming the contact metallization may involve depositing a metal material to create a conductive contact with the S / D epitaxy 205 .

[0086] Figure 4K4 is a block diagram of an example manufacturing state 400K of a stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. The example manufacturing state 400K may result from operation 324. As shown in top view 400-T, the three-terminal SOT MRAM includes contacts 426 along cut lines Y1, Y3, and Y2. Additionally, the contacts 426 along cut line Y2 are represented as bit line (BL) contacts.

[0087] Furthermore, views X, Y1, and Y2 show contacts 426, 426-BL in contact with the S / D epi 405 in the top and bottom layers. Additionally, view Y3 shows contact 426-BL in contact with the S / D epi 405 in the top layer. In this manner, example fabrication state 400K represents the result of operation 324.

[0088] Return to reference Figure 3B At operation 326, the stacked FET with three-terminal SOT MRAM manufacturing manager 150 can direct the manufacturing tool to form back-end-of-line (BEOL) connections. Forming the BEOL connections can involve depositing ILD 418 and connections from word lines (e.g., WWL, RWL), bit lines (BL), and SOT lines (SL) to contacts 426 of the S / D epi 405.

[0089] Figure 4L is a block diagram of an example state of manufacture 400L of stacked FETs with a three-terminal SOT MRAM according to some embodiments of the present disclosure. The example state of manufacture 400L may result from operation 326. As shown in top view 400-T, the three-terminal SOT MRAM includes WWL, RWL, BL, and SL.

[0090] Additionally, the example manufacturing state 400L shows BEOL connections compared to the example manufacturing state 400K. Specifically, views X, Y1, Y2, and Y3 show deposited ILD 418, metal line M1 428, bit line 430, SOT line 432, WWL 434, RWL 436, MTJ 438, and heavy metal layer 440. The heavy metal layer 440 can have a relatively high SHE. In these ways, the example manufacturing state 400L represents the result of operation 326.

[0091] A non-limiting list of examples is provided below to illustrate some aspects of the present disclosure.

[0092] Example 1 is a three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) device. The device includes a first-type field effect transistor (FET) driving a SOT line, wherein the first-type FET includes a write gate electrically contacting a write word line (WWL); and a second-type FET electrically contacting a magnetic tunnel junction (MTJ), wherein the second-type FET includes a read gate electrically contacting a read word line (RWL), wherein the first-type FET is disposed above the second-type FET, and wherein the three-terminal SOT MRAM device provides a density of three contact poly pitches (CPPs) per two cells.

[0093] Example 2 includes the apparatus of Example 1, including or excluding the optional features. In this example, the first type FET includes an n-type FET (NFET). Optionally, the second type FET includes a p-type FET (PFET).

[0094] Example 3 includes the apparatus of any of Examples 1 to 2, including or excluding the optional features. In this example, the first type FET includes a PFET. Optionally, the second type FET includes a NFET.

[0095] Example 4 includes the device of any one of Examples 1 to 3, including or excluding the optional features. In this example, the device includes a substrate; and an isolation layer disposed between the second-type FET and the substrate. Optionally, the isolation layer includes a material selected from the group consisting of: doped silicon (Si); epitaxially doped Si; and buried oxide.

[0096] Example 5 includes the apparatus of any of Examples 1 to 4, including or excluding the optional features. In this example, the apparatus includes a SOT line including a heavy metal; and an MTJ.

[0097] Example 6 is a three-terminal SOT MRAM device. The device includes an NFET driving a SOT line, wherein the NFET includes a write gate electrically contacting the WWL; and a PFET electrically contacting the MTJ, wherein the PFET includes a read gate electrically contacting the RWL, and wherein the PFET is disposed above the NFET.

[0098] Example 7 includes the device of Example 6, including or excluding the optional features. In this example, the three-terminal SOT MRAM device provides a density of 1.5 CPP per cell.

[0099] Example 8 includes the device of any of Examples 6 to 7, including or excluding the optional features. In this example, the device includes a substrate; and an isolation layer disposed between the second-type FET and the substrate. Optionally, the isolation layer includes a material selected from the group consisting of: doped silicon (Si); epitaxially doped Si; and buried oxide

[0100] Example 9 is a three-terminal SOT MRAM device. The device includes a PFET driving a SOT line, wherein the PFET includes a write gate electrically contacting the WWL; and an NFET electrically contacting the MTJ, wherein the NFET includes a read gate electrically contacting the RWL, and wherein the NFET is disposed above the PFET. Optionally, the three-terminal SOT MRAM device provides a density of 1.5 CPP per cell. Optionally, the device includes a substrate; and an isolation layer disposed between the second-type FET and the substrate. Optionally, the isolation layer includes a material selected from the group consisting of: doped silicon (Si); epitaxially doped Si; and buried oxide

[0101] Example 10 is a method for manufacturing a three-terminal SOT MRAM device. The method includes forming a bottom dummy gate on an isolation layer in contact with a substrate; forming a bottom source / drain epitaxy (S / D epitaxy); performing interlayer dielectric (ILD) deposition on the dummy gate and the bottom S / D epitaxy; performing chemical mechanical planarization to remove: a gate hard mask of the bottom dummy gate; and a plurality of pads in contact with the gate hard mask; forming a bottom S / D sacrificial contact in contact with the bottom S / D epitaxy; forming a bonding oxide disposed above a bottom layer including the bottom dummy gate; bonding the bonding oxide to a plurality of nanosheet channels of a top layer, wherein the top layer includes a plurality of sacrificial nanosheet layers in contact with the plurality of nanosheet channels; performing active device patterning on the top layer ; forming a top dummy gate for the top layer; forming a plurality of pads for the top layer; forming a top S / D epi for the top layer; depositing an ILD for the top layer; performing CMP to remove: a hard mask for the top layer; and a plurality of pads for the top layer; forming a gate opening mask; removing the top dummy gate and the bottom dummy gate; performing SiGe release; removing a plurality of sacrificial nanosheet layers; forming replacement gates for the top layer and the bottom layer; forming a plurality of gate cuts providing access to the top S / D epi and the bottom S / D epi; forming a plurality of mid-line (MOL) contacts; removing the bottom S / D sacrificial contacts; forming contact metallization using a plurality of gate cuts; and forming a plurality of back-end-of-line (BEOL) connections. Optionally, the three-terminal SOT MRAM device provides a density of three contacted poly pitches (CPPs) per two cells

[0102] Example 11 includes the method of any of Examples 10 to 10, including or excluding the optional features. In this example, forming replacement gates for the top and bottom layers includes: forming a bottom replacement gate for the removed bottom dummy gate; and forming a top replacement gate for the removed top dummy gate. Optionally, the bottom S / D epitaxy includes an n-type field effect transistor (NFET), and wherein the top S / D epitaxy includes a p-type field effect transistor (PFET). Optionally, the bottom S / D epitaxy includes a PFET, and wherein the top S / D epitaxy includes an NFET.

[0103] Example 12 is a computer program product comprising program instructions stored on a computer-readable storage medium. The computer-readable medium comprises instructions that direct a processor to form a bottom dummy gate on an isolation layer in contact with a substrate; form a bottom source / drain epitaxy (S / D epitaxy); perform interlayer dielectric (ILD) deposition on the dummy gate and the bottom S / D epitaxy; perform chemical mechanical planarization to remove: a gate hard mask of the bottom dummy gate; and a plurality of pads in contact with the gate hard mask; form a bottom S / D sacrificial contact in contact with the bottom S / D epitaxy; form a bonding oxide disposed above a bottom layer including the bottom dummy gate; bond the bonding oxide to a plurality of nanosheet channels on a top layer, wherein the top layer comprises a plurality of sacrificial nanosheet layers in contact with the plurality of nanosheet channels; perform a chemical mechanical planarization on the top layer. Source device patterning; forming a top dummy gate for the top layer; forming a plurality of pads for the top layer; forming a top S / D epi for the top layer; depositing ILD for the top layer; performing CMP to remove: a hard mask for the top layer; and a plurality of pads for the top layer; forming a gate opening mask; removing the top dummy gate and the bottom dummy gate; performing SiGe release; removing a plurality of sacrificial nanosheet layers; forming replacement gates for the top layer and the bottom layer; forming a plurality of gate cuts providing access to the top S / D epi and the bottom S / D epi; forming a plurality of mid-line process (MOL) contacts; removing the bottom S / D sacrificial contacts; forming contact metallization using a plurality of gate cuts; and forming a plurality of back-end process (BEOL) connections. Optionally, the three-terminal SOT MRAM device provides a density of three contacted poly pitches (CPP) per two cells.

[0104] Example 13 includes the computer readable medium of any one of Examples 12 to 12, including or excluding the optional features. In this example, forming replacement gates for the top and bottom layers includes: forming a bottom replacement gate for the removed bottom dummy gate; and forming a top replacement gate for the removed top dummy gate. Optionally, the bottom S / D epitaxy includes an n-type field effect transistor (NFET), and wherein the top S / D epitaxy includes a p-type field effect transistor (PFET). Optionally, the bottom S / D epitaxy includes a PFET, and wherein the top S / D epitaxy includes an NFET.

Claims

1. A three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) device, comprising: a first type field effect transistor (FET) driving the SOT line, wherein the first type FET includes a write gate in electrical contact with a write word line (WWL); as well as A second-type FET electrically contacted with a magnetic tunnel junction (MTJ), wherein the second-type FET includes a read gate electrically contacted with a read word line (RWL), wherein the first-type FET is disposed above the second-type FET, and wherein the three-terminal SOTMRAM device provides a density of three contacted poly pitches (CPPs) per two cells. 2 . The three-terminal SOT MRAM device of claim 1 , wherein the first-type FET comprises an n-type FET (NFET). 3 . The three-terminal SOT MRAM device of claim 2 , wherein the second-type FET comprises a p-type FET (PFET). 4 . The three-terminal SOT MRAM device of claim 1 , wherein the first-type FET comprises a PFET. 5 . The three-terminal SOT MRAM device of claim 4 , wherein the second-type FET comprises an NFET.

6. The three-terminal SOT MRAM device of claim 1 , further comprising: substrate; as well as An isolation layer is provided between the second-type FET and the substrate.

7. The three-terminal SOT MRAM device of claim 6, wherein the isolation layer comprises a material selected from the group consisting of: Doped silicon (Si); Epitaxially doped Si; and buried oxide.

8. The three-terminal SOT MRAM device of claim 1 , further comprising: The SOT line, the SOT line comprising a heavy metal; and The MTJ.

9. A three-terminal SOT MRAM device, comprising: an NFET driving the SOT line, wherein the NFET includes a write gate in electrical contact with the WWL; as well as A PFET in electrical contact with the MTJ, wherein the PFET includes a read gate in electrical contact with the RWL, and wherein the PFET is disposed above the NFET. 10 . The three-terminal SOT MRAM device of claim 9 , wherein the three-terminal SOT MRAM device provides a density of 1.5 CPP per cell.

11. The three-terminal SOT MRAM device of claim 9, further comprising: substrate; as well as An isolation layer is disposed between the NFET and the substrate.

12. The three-terminal SOT MRAM device of claim 11 , wherein the isolation layer comprises a material selected from the group consisting of: Doped silicon (Si); Epitaxially doped Si; and buried oxide.

13. A three-terminal SOT MRAM device, comprising: a PFET driving the SOT line, wherein the PFET includes a write gate in electrical contact with the WWL; as well as An NFET in electrical contact with the MTJ, wherein the NFET includes a read gate in electrical contact with the RWL, and wherein the NFET is disposed above the PFET, wherein the three-terminal SOT MRAM device provides a density of 1.5 CPP per cell.

14. The three-terminal SOT MRAM device of claim 13, further comprising: substrate; as well as An isolation layer is disposed between the PFET and the substrate.

15. The three-terminal SOT MRAM device of claim 14, wherein the isolation layer comprises a material selected from the group consisting of: Doped silicon (Si); Epitaxially doped Si; and buried oxide.

16. A method for manufacturing a three-terminal SOT MRAM device, the method comprising: forming a bottom dummy gate on the isolation layer in contact with the substrate; forming bottom source / drain epitaxy (S / D epitaxy); performing an interlayer dielectric (ILD) deposition on the dummy gate and the bottom S / D epitaxy; Chemical mechanical planarization is performed to remove: a gate hard mask of the bottom dummy gate; as well as a plurality of pads in contact with the gate hard mask; forming a bottom S / D sacrificial contact to the bottom S / D epitaxial contact; forming a bonding oxide disposed over a bottom layer including the bottom dummy gate; bonding the bonding oxide to a plurality of nanosheet channels of a top layer, wherein the top layer comprises a plurality of sacrificial nanosheet layers in contact with the plurality of nanosheet channels; performing active device patterning on the top layer; forming a top dummy gate of the top layer; forming a plurality of shims for the top layer; forming a top S / D epitaxy for the top layer; depositing an ILD on the top layer; Perform CMP to remove: a hard mask of the top layer; as well as said plurality of spacers for said top layer; forming a gate opening mask; removing the top dummy gate and the bottom dummy gate; Perform SiGe release; removing the plurality of sacrificial nanosheet layers; forming replacement gates for the top layer and the bottom layer; forming a plurality of gate cuts providing access to the top S / D epitaxy and the bottom S / D epitaxy; forming multiple middle-of-line (MOL) contacts; removing the bottom S / D sacrificial contact; forming contact metallization using the plurality of gate cuts; as well as Multiple back-end-of-line (BEOL) connections are formed.

17. The method of claim 16, wherein the three-terminal SOT MRAM device provides a density of three contacted poly pitches (CPPs) per two cells.

18. The method of claim 17, wherein forming the replacement gates for the top and bottom layers comprises: forming a bottom replacement gate for the removed bottom dummy gate; as well as A top replacement gate is formed for the removed top dummy gate.

19. The method of claim 18, wherein the bottom S / D epitaxial layer comprises an n-type field effect transistor (NFET), and wherein the top S / D epitaxial layer comprises a p-type field effect transistor (PFET).

20. The method of claim 18, wherein the bottom S / D epitaxy comprises a PFET, and wherein the top S / D epitaxy comprises a NFET.

21. A computer program product comprising program instructions stored on a computer readable storage medium, the program instructions being executable by a processor to cause the processor to perform a method on a wafer, the method comprising: forming a bottom dummy gate on the isolation layer in contact with the substrate; forming bottom source / drain epitaxy (S / D epitaxy); performing an interlayer dielectric (ILD) deposition on the dummy gate and the bottom S / D epitaxy; Chemical mechanical planarization is performed to remove: a gate hard mask of the bottom dummy gate; as well as a plurality of pads in contact with the gate hard mask; forming a bottom S / D sacrificial contact to the bottom S / D epitaxial contact; forming a bonding oxide disposed over a bottom layer including the bottom dummy gate; bonding the bonding oxide to a plurality of nanosheet channels of a top layer, wherein the top layer comprises a plurality of sacrificial nanosheet layers in contact with the plurality of nanosheet channels; performing active device patterning on the top layer; forming a top dummy gate of the top layer; forming a plurality of shims for the top layer; forming a top S / D epitaxy for the top layer; depositing an ILD on the top layer; Perform CMP to remove: a hard mask of the top layer; as well as said plurality of spacers for said top layer; forming a gate opening mask; removing the top dummy gate and the bottom dummy gate; Perform SiGe release; removing the plurality of sacrificial nanosheet layers; forming replacement gates for the top layer and the bottom layer; forming a plurality of gate cuts providing access to the top S / D epitaxy and the bottom S / D epitaxy; forming multiple middle-of-line (MOL) contacts; removing the bottom S / D sacrificial contact; forming contact metallization using the plurality of gate cuts; as well as Multiple back-end-of-line (BEOL) connections are formed.

22. The computer program product of claim 21, wherein the three-terminal SOT MRAM device provides a density of three contacted poly pitches (CPPs) per two cells.

23. The computer program product of claim 22, wherein forming the replacement gates for the top and bottom layers comprises: forming a bottom replacement gate for the removed bottom dummy gate; as well as A top replacement gate is formed for the removed top dummy gate.

24. The computer program product of claim 23, wherein the bottom S / D epitaxy comprises an n-type field effect transistor (NFET), and wherein the top S / D epitaxy comprises a p-type field effect transistor (PFET).

25. The computer program product of claim 23, wherein the bottom S / D epitaxy comprises a PFET, and wherein the top S / D epitaxy comprises a NFET.

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