Semiconductor device and manufacturing method

Abstract

In one embodiment, the semiconductor device (1) comprises a semiconductor body (2), a gate electrode (33) and a first electrode (31), in which-the semiconductor body (2) comprises a first region (21), which is a source region or an emitter region, and the semiconductor body comprises a well region (22) positioned immediately adjacent to the first region (21), the first region (21) having a first conductivity type, the gate electrode (33) having a second conductivity type, and the first electrode (31) having a second conductivity type. The first region (21) has a first conductivity type, and the well region (22) has a second, different conductivity type,-the well region (22) is separated from the gate electrode (33) by the gate insulating layer (4),-the first region (21) is in electrical contact by means of the first electrode (31),-in the first region (21), at least one current limiting region (5) is present, and-the at least one current limiting region (5) is a sub-region of the first region (21) having a reduced electrical conductivity.

Description

Technical Field

[0001] A semiconductor device is provided. Also provided is a method for manufacturing such a semiconductor device. Background Art

[0002] Documents US 2017 / 0243970 A1, US 2017 / 0229535 A1 and US 2015 / 0108564 A1 mention semiconductor devices.

[0003] The problem to be solved is to provide a semiconductor device having an improved trade-off between conduction losses and short circuit withstand time SC WT. Summary of the invention

[0004] This object is achieved in particular by a semiconductor device and a method as defined in the independent patent claims. Exemplary further developments form the subject matter of the dependent claims.

[0005] For example, the semiconductor device described herein comprises one or more current limiting regions as sub-regions of the source region or the emitter region, which are irradiated so that there are more lattice defects in these sub-regions than in the remaining region of the source region or the emitter region, and thus, the at least one current limiting region has a reduced conductivity compared to the remaining region of the source region or the emitter region. By means of the at least one current limiting region, the source resistance value R S Increased. S This increase in does not significantly hamper device performance under normal operation, but improves the short-circuit behavior.

[0006] According to at least one embodiment, the semiconductor device includes a semiconductor body, a gate electrode and a first electrode. For example, the semiconductor body is a wide bandgap semiconductor material, such as SiC, Ga2O3 or GaN. However, the semiconductor body can alternatively be silicon (abbreviated as Si). These electrodes can be made of at least one metal, or can also be made of a highly doped and / or ohmic conductive semiconductor material (e.g., polycrystalline Si).

[0007] According to at least one embodiment, the semiconductor body includes a first region. For example, the first region is a source region or an emitter region.

[0008] According to at least one embodiment, the semiconductor body includes a well region. The well region is positioned adjacent to the first region. That is, the first region may contact the well region and may therefore be in direct physical contact with it. The channel region is a portion of the well region and may have the same doping concentration. During operation, electrons flow from the source region to the drift region along the gate insulating layer in the channel region. In operation of the semiconductor device, the channel region may be a portion of the well region adjacent to the gate insulating layer.

[0009] According to at least one embodiment, the first region has a first conductivity type, and the well region has a different second conductivity type. For example, the first conductivity type is n-conductivity and the second conductivity type is p-conductivity, or vice versa. Hereinafter, the first conductivity type is referred to as n-conductivity; therefore, if the first conductivity type is changed to p-conductivity, the doping relationship described below must be reversed.

[0010] According to at least one embodiment, the well region is adjacent to the gate electrode and is separated from the gate electrode by a gate insulating layer. The gate insulating layer may be directly between the gate electrode and the well region.

[0011] According to at least one embodiment, the first region is electrically contacted by means of a first electrode, which is, for example, a source electrode or an emitter electrode. Thus, the first electrode can contact the semiconductor body at least at the first region. For example, the well is also electrically contacted by means of the first electrode, or is otherwise electrically contacted by a separate electrode.

[0012] According to at least one embodiment, in the first region, there is one current limiting region, or there are multiple current limiting regions. The at least one current limiting region is a sub-region of the first region with reduced electrical conductivity. For example, the first region and the at least one current limiting region have the same base material, such as SiC. However, in the at least one current limiting region, there are more lattice defects than in other regions of the first region, so that the electrical conductivity in the at least one current limiting region is intentionally lower than the electrical conductivity in other regions of the first region.

[0013] In at least one embodiment, a semiconductor device includes a semiconductor body, a gate electrode, and a first electrode, wherein:

[0014] the semiconductor body comprises a first region and a well region located next to the first region, the first region having a first conductivity type and the well region having a second, different conductivity type,

[0015] - the well region is adjacent to the gate electrode and is separated from the gate electrode by a gate insulating layer,

[0016] the first region is electrically contacted by means of a first electrode,

[0017] - in the first region, there is at least one current limiting region, and

[0018] The at least one current limiting region is a sub-region of the first region having reduced electrical conductivity.

[0019] Thus, the present application describes, for example, a metal insulator semiconductor field effect transistor MISFET, a metal oxide semiconductor field effect transistor MOSFET or a junction gate field effect transistor JFET based on silicon carbide SiC material, wherein at least one subregion of the source region or the emitter region is damaged by irradiation to reduce its conductivity, thereby improving the trade-off between conduction losses and short-circuit withstand time.

[0020] SiC MOSFETs are currently available from several suppliers. In case they are offered in either planar or trench cell designs, SiC MOSFETs offer competitive static losses, fast dynamic performance and adequate reliability. Regarding fault handling capability, SiC MOSFETs have not yet reached the typical industry standard values ​​of about 10μs demonstrated by their Si counterparts. This is usually associated with a strong trade-off between conduction losses and short circuit withstand time SCWT. The resistance R of the device in the on-state is given by the SCWT. DS,on One approach to achieve the best trade-off between the two is to use a slightly increased source resistor value, R S .

[0021] Thus, for example, a SiC MOSFET is described herein, in which a portion of the source region is subjected to an irradiation process. If an appropriate mask (eg, a SiO2 mask or an Al mask) is used, then n + Irradiation of electrons, protons or neutrons in the source leads to the formation of defects which reduce the mobility and thus increase the source resistance R S For example, in the at least one current confinement region, the resistivity may be changed to 10 -2 Up to 10 7 Ωcm range.

[0022] Therefore, for at least one of the proposed current limiting regions, the current flows in a more resistive and / or more restricted path. This effect results in a source resistance R S Increase the value of R S The value will become the saturation current I during a short circuit (SC) SAT The depth d of the irradiated area and its length L can be appropriately designed to achieve the desired effect on the SC current while minimizing its effect during conduction under nominal conditions (i.e., on the total resistance between the source and the drain in the on-state, also referred to as R DS,on )'s influence) remains negligible.

[0023] According to at least one embodiment, the semiconductor device is a power device. This means, for example, that the semiconductor device is configured to have a maximum current of at least 10 A or at least 50 A through the well region. As an option, the maximum current is at most 500 A or at most 1.5 kA. Alternatively or additionally, the semiconductor device is configured to achieve a maximum voltage of at least 0.6 kV or at least 1.2 kV between the source and the drain or between the emitter and the collector. As an option, the maximum voltage may be at most 6.5 kV.

[0024] According to at least one embodiment, the gate electrode and the first electrode overlap the first region as seen in a top view of the semiconductor body. Here and hereinafter, 'top view' may refer to a view perpendicular to the top side of the semiconductor body, on which the first electrode is applied and at which the first region is located.

[0025] According to at least one embodiment, the at least one current confinement region is far away from the gate electrode and / or the first electrode when viewed in a top view of the semiconductor body. For example, the at least one current confinement region is far away from the gate electrode and the first electrode when viewed in a top view.

[0026] According to at least one embodiment, the at least one current limiting region is located in the assigned first region in a mirror-symmetrical manner, for example within manufacturing tolerances. That is, the first region together with the at least one current limiting region, seen in a top view of the semiconductor body, has, for example, a mirror-symmetrical axis with respect to the shape of the first region and the at least one current limiting region. The mirror-symmetrical axis, seen in the top view, may extend parallel to the gate electrode and / or the first electrode, and / or may be located between the gate electrode and the first electrode. In other aspects, a non-mirror-symmetrical arrangement of the at least one current limiting region in the assigned first region, seen in the top view, is also possible.

[0027] According to at least one embodiment, the first region extends completely between the at least one current confinement region and the first electrode and between the at least one current confinement region and the gate electrode, as seen in a top view of the semiconductor body. In other words, there is a portion of the first region between the at least one current confinement region and the respective electrode, for example at the top side of the semiconductor body and as seen in a top view of the semiconductor body.

[0028] As an alternative, the at least one current confinement region may be partially covered by the gate electrode, or the at least one current confinement region may contact the gate electrode, as seen in a view of the semiconductor body.

[0029] According to at least one embodiment, the at least one current confinement region is located between the first electrode and the gate electrode. For example, the entirety of the at least one current confinement region is placed between the electrodes.

[0030] According to at least one embodiment, the first region, seen in a cross section of the semiconductor body, extends all around the at least one current confinement region in a direction towards the well region. This may mean that the first region is embedded in the well region and / or that the at least one current confinement region is embedded in the first region. For example, seen in a cross section, in this case there is a portion of the first region that completely surrounds the at least one current confinement region, such that there is no straight line connection line from the at least one current confinement region to the well region within the semiconductor body that does not cross the first region.

[0031] The term 'cross section of the semiconductor body' may refer, for example, to a cross section through the first region, through the current confinement region or through at least one of the current confinement regions, and through the gate electrode in a direction perpendicular to the top side of the semiconductor body and / or perpendicular to a main extension direction of the gate electrode.

[0032] According to at least one embodiment, the at least one current confinement region is completely embedded in the first region, as seen in a cross section of the semiconductor body. For example, the first region completely surrounds the at least one current confinement region, as seen in a cross section of the semiconductor body.

[0033] According to at least one embodiment, the at least one current confinement region extends completely through the first region, e.g. as seen in a cross section of the semiconductor body. Thus, the at least one current confinement region may be as deep as the first region or deeper than the first region. In other words, the at least one current confinement region penetrates the first region in a direction perpendicular to the top side of the semiconductor body. The at least one current confinement region may start directly at the top side or may start in the first region away from the top side in another way.

[0034] According to at least one embodiment, the volume of the at least one current limiting region is at least 5% or at least 10% or at least 20% or at least 40% or at least 60% of the total volume of the associated first region. Alternatively or additionally, the percentage is at most 95% or at most 85% or at most 75%. For example, the percentage is between 40% and 85%, inclusive.

[0035] For example, due to the at least one current limiting region, the resistance through the first region between the first electrode and the channel region is increased by at least 1.1 times or at least 1.5 times or at least 2 times or at least 5 times. Alternatively or additionally, the multiple is at most 100 or at most 25 or at most 15 or at most 10 or at most 5. For example, the multiple is between 2 and 10, inclusive. The resistance through the first region may refer to the normal operating current for which the semiconductor device is designed in the on state. These multiples refer to a comparison with a device that does not have at least one current limiting region in the first region, but otherwise has the same construction within manufacturing tolerances.

[0036] According to at least one embodiment, the conductivity of the at least one current confinement region is at least 0.1% or at least 1% or at least 5% of the conductivity of the rest of the first region. Alternatively or additionally, said values ​​are at most 95% or at most 80% or at most 20% or at most 10%.

[0037] According to at least one embodiment, the lattice in the at least one current confinement region has at least two times, or at least five times, or at least ten times more defects than the rest of the first region. Alternatively or additionally, the multiple is at most ten. 3 or at most 100 or at most 10. Thus, in the at least one current confinement region there is a higher defect density than in the remainder of the first region, which is achieved by irradiating the at least one current confinement region.

[0038] For example, by means of the at least one current restriction region, the effective cross section for the current flow in the first region from the first electrode to the well region immediately adjacent to the gate insulating layer (i.e., to the channel region) is reduced by at least 1.5 times or at least 2 times or at least 5 times due to the at least one current restriction region. Alternatively or additionally, the multiple is at most 100 or at most 15 or at most 10 or at most 5 or at most 2. For example, the multiple is between 2 and 10, inclusive.

[0039] Effective cross section A for current flow eff may be the minimum value of the local resistance r integrated over the area A of the cross section through the first region perpendicular to the main current direction,

[0040] A eff =min∫rdA.

[0041] According to at least one embodiment, the at least one current limiting region terminates in alignment with the first region. Thus, across the first region and the at least one current limiting region, the top side may be planar, and both the at least one current limiting region and the remaining region of the first region terminate in the top side. In other words, the first region and the current limiting region form a flat surface and terminate in alignment with each other.

[0042] According to at least one embodiment, the semiconductor body further includes a drift region. The drift region has the first conductivity type and has a lower maximum doping concentration than the first region and the well region, for example.

[0043] According to at least one embodiment, the semiconductor body further includes a second region. For example, the second region is a drain region or a collector region. In the case of a drain region, the second region also has the first conductivity type, but for example has a higher maximum doping concentration than in the drift region. In the case of a collector region, the second region has the second conductivity type.

[0044] According to at least one embodiment, the drift region is located between the well region and the second region. Therefore, the first region is separated from the second region by the well region.

[0045] According to at least one embodiment, the semiconductor device further includes a second electrode, which is, for example, a collector electrode or a drain electrode. The second electrode may be located on a side of the second region away from the drift region and / or away from the first region.

[0046] According to at least one embodiment, the gate electrode and the first electrode each extend along a straight line as seen in a top view of the semiconductor body. If there are multiple first electrodes and / or gate electrodes, there may be multiple straight lines along which these first electrodes and / or gate electrodes extend.

[0047] In accordance with at least one embodiment, the first region extends parallel to the gate electrode and / or the first electrode.Thus, the semiconductor device may have a strip design including a plurality of rectilinearly extending strips of the gate electrode and / or the first electrode.

[0048] According to at least one embodiment, the gate electrode and / or the first electrode each include a plurality of sub-segments as seen in a top view of the semiconductor body. For example, these sub-segments correspond to unit cells. The unit cells may be arranged, for example, in a regular two-dimensional grid. The semiconductor body may extend continuously throughout all unit cells and include a plurality of first regions arranged accordingly. Thus, the semiconductor device may have a cellular design including a plurality of cells, each having a first electrode, a corresponding gate electrode, and a corresponding first region with the at least one current limiting region.

[0049] According to at least one embodiment, the semiconductor device has a planar design. That is, the gate insulation layer and the gate electrode are applied on a planar section of the top side of the semiconductor body. The first region and the at least one current confinement region may be located at the top side.

[0050] According to at least one embodiment, the semiconductor device has a trench design. Therefore, the gate insulating layer and the gate electrode are partially or completely arranged in a trench in the semiconductor body. For example, starting from the top side of the semiconductor body, the depth of the trench exceeds the depth of the well region. In this case, the first region and the at least one current limiting region can also be located at the top side.

[0051] According to at least one embodiment, there is exactly one current limiting region in the first region. In case of a plurality of first regions, there may be a one-to-one assignment between the first regions and the current limiting regions.

[0052] In other aspects, there are multiple current limiting regions in the first region. In the case of multiple first regions, there may be multiple current limiting regions per first region. When viewed in a top view of the semiconductor body, the current limiting regions of each or exactly one of the first regions are far away from each other.

[0053] The or each of the current limiting regions can be completely surrounded by the respectively assigned first region, as seen in a plan view of the semiconductor body.

[0054] According to at least one embodiment, the current limiting region is arranged along a strip or along a plurality of strips. Additionally, as an option, the current limiting region is arranged along a row or along a plurality of rows, as seen in a top view, wherein the strips and rows may be oriented perpendicular to each other. In the case of a plurality of first regions, this may apply to each of the first regions, wherein each of the first regions is assigned to a plurality of current limiting regions.

[0055] According to at least one embodiment, the current limiting region is shaped as at least one of the following when viewed in a top view of the semiconductor body: a triangle, a square, a rectangle, a hexagon, a circle. When viewed in a top view, all current limiting regions may have the same shape and / or area content. In other aspects, also for each first region, current limiting regions of different shapes and / or sizes may be combined with each other.

[0056] Additionally provided is a method for manufacturing a semiconductor device. By means of the method, a semiconductor device as indicated in conjunction with at least one of the embodiments stated above is produced. Therefore, features of the semiconductor device are also disclosed for the method, and vice versa.

[0057] In at least one embodiment, the manufacturing method is for producing a semiconductor device, the method comprising, for example, the following in the order recited:

[0058] - providing a semiconductor body,

[0059] - forming a first region and a well region in the semiconductor body,

[0060] - applying a mask layer on the semiconductor body,

[0061] - irradiating at least one portion of the first region defined by the mask layer with at least one of x-rays, electrons, protons, neutrons or ions so that the at least one current confinement region is generated in the at least one irradiated portion, and

[0062] - applying a gate insulating layer as well as a gate electrode and a first electrode to the semiconductor body.

[0063] The dose used to irradiate the at least one portion can be used as a design parameter to tune the resistance of the at least one current confinement region and thus the resistance of the first region and achieve the desired effect. For example, in the case of electron irradiation, the dose can range from 10 10 cm -2 with 10 17 cm -2 For proton irradiation, for example, the dose may be between 10 8 cm -2 with 10 14 cm -2 between.

[0064] The shape of the at least one current confinement region, seen in a top view from the top side, is defined by the mask layer, while the depth of the at least one current confinement region depends on the mask layer thickness and the energy used for the irradiation, for example a minimum of 116 keV for electrons or a minimum of 200 keV for protons and neutrons. It is possible that only one type of irradiation is present, for example only electron irradiation, or that different types of irradiation may be combined with each other.

[0065] According to at least one embodiment, the method further comprises: forming at least one plug region into the semiconductor body. The at least one plug region has the second conductivity type and has a maximum doping concentration higher than a maximum doping concentration of the well region. The at least one plug region is used to electrically contact the well region, for example by means of the first electrode.

[0066] In accordance with at least one embodiment, the first region extends deeper into the semiconductor body than the at least one plug region.

[0067] According to at least one embodiment, producing the first region comprises two different doping steps, so that the doping profile of the first region, seen in cross section, has a stepped pattern. ie, the first region may widen towards the top side.

[0068] The semiconductor devices and methods described herein are explained in more detail below by exemplary embodiments with reference to the accompanying drawings. The same elements in the various figures are indicated by the same reference numerals. However, the relationship between the elements is not shown to scale, but the individual elements may be shown as exaggeratedly large to assist understanding. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] In the attached picture:

[0070] Figure 1 is a schematic perspective cross-sectional view of an exemplary embodiment of a semiconductor device described herein,

[0071] Figures 2 to 4 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein,

[0072] Figure 5 and Figure 6 is a schematic perspective cross-sectional view of an exemplary embodiment of a semiconductor device described herein,

[0073] Figures 7 to 9 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein,

[0074] Fig.10 and Fig.11 is a schematic diagram of simulated electrical characteristics of exemplary embodiments of semiconductor devices described herein compared to corresponding semiconductor devices without the at least one current confinement region,

[0075] Fig.12 is a schematic block diagram of an exemplary embodiment of a method for manufacturing a semiconductor device described herein,

[0076] Fig.13 are schematic cross-sectional views of method steps of an exemplary embodiment of the method described herein, and

[0077] Fig.14 and Fig.15 is a schematic top view of an exemplary embodiment of a semiconductor device described herein. DETAILED DESCRIPTION

[0078] Figure 1 An exemplary embodiment of a semiconductor device 1 is illustrated. The semiconductor device 1 comprises a semiconductor body 2, for example SiC. In the semiconductor body 2, there are a first region 21, a well region 22 and a drift region 23. Further, there is a plug region 25 for electrically contacting the well region 22.

[0079] Further, the semiconductor device 1 comprises a gate electrode 33, which is separated from the semiconductor body 2 by means of a gate insulating layer 4. Further, there is a first electrode 31 that electrically contacts the first region 21 and the plug region 25. The gate insulating layer 4 and the first electrode 31 are located at the top side 20 of the semiconductor body 2. The top side 20 has a planar form. The gate electrode 33 and the first electrode 31 can each be arranged along a straight line (along a line perpendicular to the Figure 1 The gate insulating layer 4 may be a metal oxide, a semiconductor oxide, a metal nitride and / or a semiconductor nitride. For example, the gate insulating layer 4 includes one or more of the following materials: SiO2, Si3N4, Al2O3, Y2O3, ZrO2, HfO2, La2O3, Ta2O5, TiO2.

[0080] For example, the first region 21 and the drift region 23 are n-type doped, and the well region 22 and the plug region 25 are p-type doped. If the semiconductor device 1 is an insulated gate bipolar transistor IGBT or a reverse conducting insulated gate bipolar transistor RC-IGBT, the first region 21 is an emitter region and the first electrode 31 is an emitter electrode. If the semiconductor device 1 is a junction gate field effect transistor JFET, a metal insulator semiconductor field effect transistor MISFET, or a metal oxide semiconductor field effect transistor MOSFET, the first region 21 is a source region and the first electrode 31 is a source electrode.

[0081] In the first region 21, there is a current confinement region 5. The current confinement region 5 is the same material as the rest of the first region, for example, SiC. However, since the portion of the first region 21 constituting the current confinement region 5 is irradiated, the conductivity in the current confinement region 5 is reduced compared to the rest of the first region 21.

[0082] therefore, Figure 1The basic concept of the proposed semiconductor device 1 is depicted. After source activation a region is irradiated, namely the at least one current confinement region 5. The width of this region is defined by the mask design, while the depth of this region 5 depends on the mask thickness and the energy used for irradiation. During irradiation, for example, several point defects are formed. These defects can form electrically active energy levels in the band gap, such as EH1, Z1 / 2, EH3, EH4, EH5, and EH6 / 7, as compared to G. Alfieri et al., “Annealing behavior of deep level defects in electron-irradiated n-type 4H silicon carbide between room temperature and 2000°C,” Journal of Applied Physics 98, 043518 (2005), doi:10.1063 / 1.2009816; and Alfieri et al., “Isothermal annealing study of EH1 and EH3 levels in n-type 4H-SiC,” Journal of Condensed Matter Physics 32, 4657'3 (2020), doi:10.1088 / 1361-648X / abaeaf. These energy levels trap charge carriers and reduce mobility. Lower mobility increases the source resistance R S The value of .

[0083] The current confinement region 5 extends along a straight line parallel to the gate electrode 33 and the first electrode 31. Like the first region 21, the current confinement region 5 is located directly at the top side 20. Starting from the top side 20, the first region 21 penetrates deeper into the semiconductor body 2 than the current confinement region 5 penetrates into the semiconductor body 2. Seen in cross section, towards the well region 22 in which the first region 21 is embedded, there is a first region 21 that completely surrounds the current confinement region 5.

[0084] For example, as seen in a top view and as seen in a cross section, the at least one current limiting region 5 is arranged mirror-symmetrically in the first region 21. For example, as seen in a top view of the top side 20, the current limiting region 5 is arranged symmetrically in the first region 21 and between the electrodes 31, 33. Therefore, there may be a mirror symmetry line M about the current limiting region 5 and the first region 21.

[0085] The at least one current confinement region 5 may have different shapes and depths and may be arranged along a direction perpendicular to the Figure 1 The cross-section direction can be uniform or non-uniform, see also below Figures 2 to 9 .

[0086] For the proposed at least one current limiting region 5, the current flows in a more resistive and / or more restricted path. This effect results in an increase in the value of the source resistance RS or, respectively, the emitter resistance. Increasing the value of RS will translate into a reduction in the saturation current ISAT during a short circuit condition. The depth d of the current limiting region 5 and its depth parallel to the top side 20 and along the Figure 1The length L of the cross-section is adjusted to achieve the desired effect on the short-circuit current while keeping its influence (eg on the total RDS,on) during conduction under nominal conditions negligible.

[0087] For example, the effective channel-to-contact path length Leff of the carriers is the minimum value of the local resistance r along all possible routes S with an incremental element s within the first region 21 (including the at least one current confinement region 5), L eff =min∫ S rds.

[0088] Figure 1 The semiconductor device 1 is of planar design. In contrast, Figure 2 The semiconductor device 1 is of trench design. Therefore, the gate electrode 33 and the gate insulation layer 4 are at least partially located in the trench entering the semiconductor body 2. Figure 1 In contrast to the situation in FIG. 2 , the top side 20 is not planar because it is penetrated by the trench. For example, starting from the top side 20 , the gate electrode 33 extends deeper into the semiconductor body 2 than the well region 22 .

[0089] Further, in Figure 2 What is shown in FIG. 1 is that there are a plurality of first regions 21 and therefore there are current confinement regions 5 that are arranged, for example, symmetrically with respect to the gate electrode 33. Figure 2 The plurality of cells illustrated in FIG. 2 are adjacent to each other in a direction parallel to the top side 20 so that there may be a plurality of strips of the gate region 33 and the first electrode 31 perpendicular to the top side 20. Figure 2 The projection planes extend and extend parallel to each other.

[0090] Figure 2 This symmetrical arrangement (see also Fig.14 ) and / or Figure 2 The groove design can also be similarly applied to all other embodiments.

[0091] Figure 2 The current limiting region 5 (one current limiting region for each first region 21) has the same Figure 1 The same design as in the example above, i.e. with a cubic shaped slot. Figure 2 , the groove has sharp edges and corners; according to Figure 1 , the grooves have rounded edges and corners. In all embodiments, both designs are possible, depending on the manufacturing process of the at least one current confinement region 5 .

[0092] In addition, Figure 2It is shown that there is a second electrode 32 and that the semiconductor body 2 includes a second region 24. For example, the second region 24 is a substrate on which the other regions 23, 22, 21, 25 are formed by means of growth and / or doping (e.g., ion implantation). In the case of an IGBT or RC-IGBT, the second electrode 32 is a collector electrode and the second region is a collector region having the same doping type as the well region. In the case of a MOSFET or MISFET, the second electrode 32 is a drain electrode and the second region is a drain region having the same doping type as the first region. The same applies to all other embodiments of the semiconductor device 1.

[0093] Further, according to Figure 2 , starting from the top side 20 , the plug region 25 extends deeper into the semiconductor body 2 than the first region 21 . For other aspects, see Figure 1 , the plug region 25 can have the same depth as the first region 21, or can also be shallower or deeper than the first region 21. Both possibilities are applicable to all embodiments.

[0094] and Figure 1 Same as in Figure 2 In the embodiment, the at least one current confinement region 5 of each first region 21 is away from the first electrode 31 , the gate electrode 33 and the gate insulating layer 4 .

[0095] For example, the maximum doping concentration of the first region 21, the second region 24, and the at least one plug region 25 is at least 1×10 18 cm -3 or at least 5x 10 18 cm- 3 or at least 1x 10 19 cm -3 and / or up to 5x 10 20 cm -3 or up to 2x10 20 cm -3 or up to 1x 10 20 cm -3 Furthermore, the maximum doping concentration of the well region 22 and thus the maximum doping concentration of the channel region immediately adjacent to the gate insulating layer 4 may be at least 5×10 16 cm -3 or at least 1x 10 17 cm -3 and / or up to 5x 10 19 cm -3 or up to 5x10 18 cm -3 Depending on the voltage level of the semiconductor device 1, the maximum doping concentration of the drift region 23 may be at least 1×1011 cm -3 or at least 1x 10 12 cm -3 or at least 1x 10 13 cm -3 and / or up to 1x10 17 cm -3 or up to 5x 10 16 cm -3 or up to 1x10 16 cm -3 For example, the thickness of the gate insulating layer 4 is between 10 nm and 250 nm or between 80 nm and 150 nm. These parameters may also apply individually or collectively to all other embodiments.

[0096] In other aspects, Figure 1 The same applies to Figure 2 , and vice versa.

[0097] exist Figure 3 and Figure 4 In, like Figure 1 As in the embodiment of the present invention, there is one current limiting region 5 per first region 21 . The current limiting regions 5 can be arranged in a mirror-symmetrical manner in the first region 25 , with the mirror-symmetrical axis extending perpendicularly to the top side 20 .

[0098] and Figure 1 The opposite is true according to Figure 3 and Figure 4 , the current confinement region 5 extends beyond the gate insulating layer 4 and the gate electrode 33. Such an arrangement is also possible in all other embodiments. Figure 3 and Figure 4 In contrast to the situation shown in , the current confinement region 5 may be located asymmetrically in the first region 21, so that the current confinement region 5 ends away from the gate insulating layer 4 and thus may not extend beyond the gate electrode 33. This is also possible in all other embodiments.

[0099] according to Figure 3 , the current confinement region 5 is formed as a shallow groove in the first region 21, which is also formed as a groove. The depth d of the current confinement region 5 reaches, for example, between 10% and 90% or between 40% and 80% of the depth D of the first region 21. The first region 21 and the plug region 25 may have the same depth, for example within manufacturing tolerances. For example, the depth D of the first region 21 is at least 0.1 μm and / or at most 2 μm.

[0100] according to Figure 4, the current confinement region 5 is formed as a deep groove in the first region 21, which is formed as two grooves (one above the other), wherein the groove next to the top side 20 has a Figure 4 In this case, too, the depth d of the current confinement region 5 can reach between 10% and 90% or between 40% and 80% of the depth D of the entire first region 21. Due to the design with two stacked grooves, the first region 21 can extend deeper into the semiconductor body 2 than the plug region 25. It is possible that the plug region 25 has the same depth as the groove of the first region 21 adjacent to the top side 20, for example within manufacturing tolerances. For example, the depth D of the first region 21 is at least 2 μm and / or at most 4 μm.

[0101] For example, the trenches next to the top side 20 are first formed by corresponding doping, and then the doping for the trenches further away from the top side 20 is provided, for example, by using different energies in the ion implantation steps. Thus, as seen in the cross section, Figure 4 The groove has a stepped design. Figure 4 In the configuration of Figure 3 Deep grooves of rectangular shape (as depicted in ) are also possible.

[0102] A shallow or deep first region 21 (eg Figure 3 and Figure 4 The two designs shown in (shown in ) are also possible in all other exemplary embodiments.

[0103] For example, the length L of the current confinement region 5 is between 10% and 90% or between 40% and 80% or between 50% and 70% of the width B of the first region 21. This is also possible in all other embodiments.

[0104] In other respects, Figure 1 and Figure 2 The same content also applies to Figure 3 and Figure 4 , and vice versa.

[0105] according to Figures 5 to 7 , there are multiple current limiting regions 5 per first region 21. With regard to the parameters d, D, B, L as stated above for the case of a single current limiting region 5 per first region 21, the same applies to the case of multiple current limiting regions 5 per first region 21, wherein L corresponds to the total width of all corresponding current limiting regions 5 (compare, for example Figure 6 ). With the help of the multiple current limiting regions 5, there are more design parameters to achieve the optimized first region.

[0106] In the case of a current confinement region 5 in a direction perpendicular to the gate electrode 33 and / or the first electrode 31 (see Figure 5 ), the total width L is as follows Figure 4 The widths W of the individual island-shaped current confinement regions 5 shown in the figure are the same.

[0107] However, according to Figure 5 , there is one strip of current restriction region 5 extending parallel to electrodes 31, 33. Seen in top view, the current restriction regions 5 have a rectangular or square shape (optionally with rounded corners), each having a width W and a length range V. For example, V is between 0.5L and 100L or between 0.5L and 10L or between 0.7L and 5L.

[0108] For example, the distance Zs between adjacent current restriction areas 5 along the strip is between 10% and 75% or between 10% and 40% of the width W and / or length V. The individual current restriction areas 5 in the strip may be arranged in an equidistant manner, or in addition Figure 5 In addition to the case shown in , they are arranged with varying distances from each other. These aspects can also be applied individually or collectively to all other embodiments.

[0109] Except for the case shown, the current confinement region 5 need not have a square shape as seen in a plan view, but may also have a rectangular, hexagonal, regular or irregular polygonal or circular shape as seen in a plan view. The same applies to all other embodiments.

[0110] according to Figures 5 to 7 , all the current limiting regions 5 of each first region 21 have the same shape. This is not absolutely necessary. That is, the current limiting regions 5 of different shapes can be combined in one first region 21.

[0111] There may be N strips of current confinement region 5 between electrodes 31, 33, where N is a natural number greater than or equal to two. For example, N is at most ten or at most four. Figure 6 In the example of , N is two. For example, it is applicable that 0.1B / N≤W≤0.99B / N or 0.4B / N≤W≤0.95B / N or 0.7B / N≤W≤0.90B / N. Alternatively or additionally, for example, the distance Zt between adjacent current restriction regions 5 in the traverse direction perpendicular to the strip is between 10% and 75% or between 10% and 40% of the length range V. Alternatively or additionally, for example, it is applicable that 0.1B / N≤V≤100B / N or 0.4B / N≤V≤10B / N or 0.7B / N≤V≤5B / N. The current restriction regions 5 can be arranged in an equidistant manner parallel to and perpendicular to the electrodes 31, 33.

[0112] like Figure 6 As shown in FIG, all N stripes have the same number of current confinement areas 5, so that in each case there are K current confinement areas 5 next to each other in a direction parallel to the stripes. Thus, a regular array of N x K current confinement areas 5 is formed, and all current confinement areas 5 have the same shape.

[0113] However, this is not necessary. That is, current restriction regions 5 of different shapes and sizes may be combined with each other, and there may be a different number K of current restriction regions 5 per strip and / or a different number N of current restriction regions 5 in a direction parallel to the width L. For example, by way of example, there are current restriction regions 5 with different widths W, so that there may be rows parallel to the direction along the width L, which have a single wide current restriction region 5 and alternate with rows having a plurality of narrower current restriction regions 5.

[0114] exist Figure 7 As shown in FIG. 1 , N is three. As an option, the strip farthest from the first electrode 31 extends beyond the gate insulating layer 4. However, except Figure 7 Apart from the case shown in , all stripes may be located away from the gate electrode 33 , for example as seen in a top view of the top side 20 .

[0115] Figure 7 Each of the strips may be composed of a plurality of current limiting regions 5 (e.g. Figure 5 and Figure 6 ), or there may be only one current confinement region 5 per strip (as in Figures 1 to 4 The same applies to all other embodiments.

[0116] Figures 5 to 7 The current limiting region 5 has a shallow design (compare with the above Figure 3 ). It is also possible that all or some of the current limiting regions 5 of each first region 21 have a deep design, such as in Figure 4 depicted in the context of.

[0117] In other respects, Figures 1 to 4 The same content also applies to Figures 5 to 7 , and vice versa.

[0118] exist Figure 8In the semiconductor device 1, the current confinement region 5 completely extends from the top side 20 through the first region 21 to the well region 22. Therefore, all currents from the first electrode 31 to the channel region of the well region 22 adjacent to the gate insulating layer 4 must flow through the current confinement region 5 having lower conductivity, thereby ignoring possible tiny currents in the portion of the current confinement region 5 on the side of the current confinement portion 5 away from the top side 20 that passes through the well region 22 around the current confinement region 5.

[0119] With the help of Figure 8 The resistance of the first region 21 can be adjusted particularly accurately by virtue of the length parallel to the projection plane of the first region 21 and the conductivity of the current confinement region 5 .

[0120] In other aspects, Figures 1 to 7 The same content also applies to Figure 8 , and vice versa.

[0121] exist Fig. 9 In the semiconductor device 1 of FIG. 1 , the current confinement region 5 is completely embedded in the remaining portion of the first region 21. That is, the first region 21 completely surrounds the current confinement region 5. Therefore, it is possible that the current confinement region 5 extends beyond the gate electrode 33. Except for the case shown, the current confinement region 5 may not extend below the gate electrode 33.

[0122] For example, the layer thickness of the first region 21 completely surrounding the current confinement region 5 has a thickness of at least 5% or at least 10% and / or at most 30% or at most 45% of the total thickness of the first region 21 together with the embedded current confinement region 5 .

[0123] Fig. 9 In the case where each first region 21 has a plurality of current limiting regions 5 (compare with, for example Figures 5 to 7 ) is possible, or in the deep current confinement region 5 (compare e.g. Figure 4 ) is also possible.

[0124] In other aspects, Figures 1 to 8 The same content also applies to Fig. 9 , and vice versa.

[0125] Fig.10 and Fig.11 Shown for Figure 8 These semiconductor devices 1 have a gate-source voltage V GS = Isothermal output J simulated at 15V and 300K D V DS , and the drain-source voltage V DS =600V and at V GS,Swing= Electrothermal short-circuit waveform at –5V / +15V (compared to the corresponding reference MOSFET design 9 without any current limiting region). Figure 8 In the semiconductor device 1 , the quotient d / D of the depth d of the current confinement region 5 and the depth D of the first region 21 is 1. The quotient L / B of the length L of the current confinement region 5 and the width B of the first region 21 is 0.5.

[0126] It can be noted that the maximum saturation current I achieved during short circuit is SAT,peak The decrease is greater than the resistance R in the on state DS,on Since the energy experienced by the device during the short circuit is equal to I SAT is directly related to the maximum value of , so the semiconductor device 1 described in this article improves the short-circuit withstand time without significantly affecting the conduction losses.

[0127] exist Fig.12 , a method for producing a semiconductor device 1 is illustrated. In method step S1, a semiconductor body 2 is provided. For example, the semiconductor body 2 provides a drift region 23. Then, in method step S2, a first region 21 and a well region 22 as well as a plug region 25 are formed in the semiconductor body 2.

[0128] Next, in step S3, at least one mask layer is provided on the top side 20 of the semiconductor body 2. Further, see step S4, at least one portion of the first region 21 defined by the mask layer is irradiated with at least one of x-rays, electrons, protons, neutrons or ions, so that the at least one current confinement region 5 is generated in the at least one irradiated portion. Then, in step S5, the gate insulation layer 4, the gate electrode 33 and the first electrode 31 are applied to the semiconductor body 2, and optionally, the second electrode 32 is also applied.

[0129] In a further step, not shown, the mask layer may be partially or completely removed and the semiconductor device 1 may be completed.

[0130] Method steps S1 to S5 may not necessarily be performed in the order stated.

[0131] exist Fig.13 In the example, method step S5 is illustrated in more detail. Fig.13 It can be seen that in this step S5, the electrodes have not yet been applied. It is also possible to apply the gate insulation layer 4 just after the irradiation step, which is Fig.13 In the figure, the gate insulating layer 4 is represented by a dotted line to symbolize this.

[0132] Therefore, according to Fig.13A mask layer 6, which is, for example, silicon dioxide, is applied on the top side 20 and is structured to represent the at least one current confinement region 5. In the region of the at least one current confinement region 5, radiation R can pass through the mask layer 6 to the first region 21. In other parts of the semiconductor body 2, it is possible that radiation R cannot reach the semiconductor body 2.

[0133] and Fig.13 In contrast to the situation shown in FIG. 5 , it is also possible to leave the top side 20 completely free of the mask layer 6 in the region of the at least one current confinement region 5 .

[0134] For example, the radiation R consists of electrons, protons or neutrons having an energy higher than about 0.1 MeV. With such radiation, the crystal lattice of the material of the first region 21 is damaged, so that an increased number of point defects occurs. In addition to suffering an increased defect density, it is alternatively or additionally possible to neutralize the doping of the first region 21, for example by counter-doping, so that the radiation R can also consist of ions.

[0135] exist Fig.14 , an example of a semiconductor device 1 is illustrated in a top view. It can be seen that the strip of the gate electrode 33 is located, for example, in a symmetrical manner between two strips of each half of the first electrode 31 and thus between two strips of the first region 21 with the current confinement region 5. Fig.14 The structure in corresponds to a unit cell, which can be multiplied so that multiple unit cells can be arranged next to each other.

[0136] This strip design can also be applied similarly to Figure 1 as well as Figures 3 to 9 Embodiment of Figure 2 , such a symmetrical design has been shown.

[0137] In other aspects, Figures 1 to 13 The same content also applies to Fig.14 , and vice versa.

[0138] Further, see Fig.15 , the semiconductor device 1 can also have a honeycomb design, as seen in a top view, so that rectangular or square unit cells can appear. For example, there is a first electrode 31 in the center of the unit cell, which is surrounded in a frame-like manner by a gate electrode 33. Such unit cells can be arranged two-dimensionally, so that the semiconductor device 1 can include a large number of such unit cells.

[0139] In other respects, Fig.14 The same applies to Fig.15 , and vice versa.

[0140] Unless otherwise indicated, the components shown in the figures follow one on top of the other in the order specified. Components that are not in contact in the figures are spaced apart from each other. If the lines are drawn parallel to each other, the corresponding surfaces may be oriented parallel to each other. Likewise, unless otherwise indicated, the positions of the drawn components relative to each other are correctly reproduced in the figures.

[0141] The invention described herein is not limited by the description based on the exemplary embodiments. On the contrary, the invention covers any novel feature and any combination of features, which in particular includes any combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or the exemplary embodiments.

[0142] Reference numerals list

[0143] 1 Semiconductor devices

[0144] 2 Semiconductor body

[0145] 20 Top side of semiconductor body

[0146] 21 first region (source region or emitter region)

[0147] 22 Well Region

[0148] 23 Drift Zone

[0149] 24 Second region (drain region or collector region)

[0150] 25 plug area

[0151] 31 first electrode (source electrode or emitter electrode)

[0152] 32 second electrode (drain electrode or collector electrode)

[0153] 33. Gate electrode

[0154] 4 Gate insulation layer

[0155] 5 Current Limiting Region

[0156] 6 Mask layer

[0157] 9 Comparative Examples of Semiconductor Devices

[0158] B The width of the first region

[0159] d Depth of current limiting region

[0160] D Depth of the first zone

[0161] E1 First Example of Semiconductor Device

[0162] E2 First Example of Semiconductor Device

[0163] E3 First Example of Semiconductor Device

[0164] L Length of the current limiting region

[0165] M Mirror symmetry line

[0166] R Radiation

[0167] S..Method steps

[0168] T is the time in μs

[0169] J D The current density in the drain region (in A / cm 2 Units)

[0170] V DS The voltage between the drain electrode and the source electrode (in V)

[0171] The length range of the V current limiting region

[0172] WThe width of the island current limiting area

[0173] Z s The distance between the current confinement areas along the strip

[0174] Z t The distance between the current limiting areas along the traverse direction

Claims

1. A semiconductor device (1), comprising a semiconductor body (2), a gate electrode (33) and a first electrode (31), wherein: the semiconductor body (2) comprises a first region (21), the first region being a source region or an emitter region, and the semiconductor body comprises a well region (22), the well region being located adjacent to the first region (21), the first region (21) having a first conductivity type, and the well region (22) having a second, different conductivity type, - the well region (22) is adjacent to the gate electrode (33) and is separated from the gate electrode (33) by a gate insulating layer (4), - the first region (21) is electrically contacted by means of the first electrode (31), the first electrode being a source electrode or an emitter electrode, - in said first region (21), there is at least one current limiting region (5), and The at least one current limiting region (5) is a sub-region of the first region (21) having reduced electrical conductivity.

2. The semiconductor device (1) according to the preceding claim, in, As seen in a top view of the semiconductor body (2), the gate electrode (33) and the first electrode (31) overlap with the first region (21), and the at least one current limiting region (5) is away from the gate electrode (33) and the first electrode (31).

3. The semiconductor device (1) according to any one of the preceding claims, in, As seen in a top view of the semiconductor body (2), the first region (21) extends completely between the at least one current limiting region (5) and the first electrode (31) and between the at least one current limiting region (5) and the gate electrode (33), the at least one current limiting region (5) being located between the first electrode (31) and the gate electrode (33).

4. The semiconductor device (1) according to any one of the preceding claims, in, As seen in a cross section of the semiconductor body (2) through the first region (21) and through the gate electrode (33), the first region (21) extends completely around the at least one current limiting region (5) in a direction toward the well region (22), so that the first region (21) is embedded in the well region (22) and the at least one current limiting region (5) is embedded in the first region (21).

5. The semiconductor device (1) according to the preceding claim, in, The at least one current confinement region (5) is completely embedded in the first region (21), so that the first region (21) completely surrounds the at least one current confinement region (5) when viewed in a cross section of the semiconductor body (2).

6. The semiconductor device (1) according to any one of claims 1 to 3, in, The at least one current limiting region (5) extends completely through the first region (21), so that the at least one current limiting region (5) is as deep as or deeper than the first region (21).

7. The semiconductor device (1) according to any one of the preceding claims, in, The volume of the at least one current confinement region (5) is at least 10% and at most 95% of the total volume of the first region (21).

8. The semiconductor device (1) according to any one of the preceding claims, in, The electrical conductivity of the at least one current confinement region (5) is between 5% and 90% of the electrical conductivity of the remaining region of the first region (21), The crystal lattice in the at least one current confinement region (5) has at least twice as many defects as the rest of the first region (21).

9. The semiconductor device (1) according to any one of the preceding claims, in, The semiconductor body (2) further comprises a drift region (23), the drift region having the first conductivity type, and the semiconductor body further comprises a second region (24), the second region being a drain region or a collector region, The drift region is located between the well region (22) and the second region (24). The semiconductor device (1) further comprises a second electrode (32), the second electrode is a collector electrode or a drain electrode, the second electrode (32) is located on a side of the second region (24) away from the drift region (23), and, Wherein, the semiconductor body (2) is SiC.

10. The semiconductor device (1) according to any one of the preceding claims, in, In a top view of the semiconductor body (2), the gate electrode (33) and the first electrode (31) each extend along a straight line, and the first region (21) extends parallel to the gate electrode (33) and the first electrode (31); or In which, as seen in a top view of the semiconductor body (2), the gate electrode (33) and the first electrode (31) each include a plurality of sub-segments arranged along at least one arrangement line, and the first region (21) extends between adjacent sub-segments of the gate electrode (33) and the first electrode (31).

11. The semiconductor device (1) according to any one of the preceding claims, The semiconductor component has a planar design such that the gate insulation layer (41) and the gate electrode (33) are applied on a planar section of a top side (20) of the semiconductor body (2), the first region (21) being located at the top side (20).

12. The semiconductor device (1) according to any one of claims 1 to 10, The semiconductor device has a trench design, so that the gate insulating layer (41) and the gate electrode (33) are at least partially arranged in a trench in the semiconductor body (2), starting from the top side (20) of the semiconductor body (2), the depth of the trench exceeds the depth of the well region (22), and the first region (21) is located at the top side (20).

13. The semiconductor device (1) according to any one of the preceding claims, in, In the first region (21) there is exactly one current limiting region (5).

14. The semiconductor device (1) according to any one of claims 1 to 10, in, There are a plurality of current limiting regions (5) in the first region (21), and the current limiting regions (5) are spaced apart from each other when viewed in a plan view of the semiconductor body (2).

15. A method for manufacturing a semiconductor device (1) according to any one of the preceding claims, the method comprising: - providing the semiconductor body (2), - forming the first region (21) and the well region (22) in the semiconductor body (2), - applying a mask layer (6) on the semiconductor body (2), - irradiating at least one portion of the first region (21) defined by the mask layer (6) with at least one of x-rays, electrons, protons, neutrons or ions, so that the at least one current confinement region (5) is generated in the at least one irradiated portion, and - applying the gate insulating layer (41) as well as the gate electrode (33) and the first electrode (31) to the semiconductor body (2).

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