Semiconductor integrated circuit device

Abstract

A semiconductor integrated circuit device (1) is provided with: a plurality of standard cell rows (10) having a plurality of standard cells (11) arranged in the X direction, and a plurality of power supply wires (L1) extending in the X direction and supplying power to the plurality of standard cells (11); a plurality of strip-shaped power supply wires (30) extending in the Y direction; a plurality of sub-belt-shaped power supply wires (40) extending in the Y direction and each connected to each of the plurality of power supply wires (L1); and a plurality of switching units (SW) provided at intersections between the plurality of strip-shaped power supply wirings (30) and the plurality of power supply wirings (L1). The plurality of standard cell rows (10) have a standard cell row (10b) in which no switching cell (SW) is disposed at a position corresponding to one or more standard cell columns other than the standard cell columns (21, 22) at both ends among the plurality of standard cell columns (20).

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit device. Background Art

[0002] In order to realize low power consumption of semiconductor integrated circuit devices, a technology has been studied in which a switch for switching power supply and cutoff is arranged in each standard cell column to cut off the power supply to the standard cell column that does not need power supply. Power is supplied to each standard cell from the strip power wiring through the switch and the standard cell power wiring.

[0003] However, if switches are arranged in each standard cell power supply line, there is a problem that the area of ​​the circuit block including each standard cell column increases. Therefore, Patent Document 1 discloses a semiconductor integrated circuit device that can reduce the number of arranged switches.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: International Publication No. 2017 / 208887 Summary of the invention

[0007] Problems to be solved by the invention

[0008] In addition, since various wirings are provided in semiconductor integrated circuit devices, it is desired to improve wiring properties. However, Patent Document 1 does not disclose improving wiring properties.

[0009] Therefore, the present disclosure provides a semiconductor integrated circuit device capable of achieving low power consumption and improved wiring properties.

[0010] Means used to solve problems

[0011] A semiconductor integrated circuit device according to a technical solution of the present disclosure comprises: a plurality of standard cell rows, each of which has a plurality of standard cells arranged in a first direction, and a plurality of power supply wirings extending in the first direction and supplying power to the plurality of standard cells; a plurality of strip-shaped power supply wirings extending in a second direction orthogonal to the first direction on an upper layer of the plurality of power supply wirings; a plurality of sub-strip-shaped power supply wirings extending in the second direction on an upper layer of the plurality of power supply wirings and each connected to each of the plurality of power supply wirings; and a plurality of first switch units provided at intersections of the plurality of strip-shaped power supply wirings and the plurality of power supply wirings and configured to switch whether to electrically connect the strip-shaped power supply wirings to the power supply wirings according to a control signal; the plurality of standard cell rows are arranged in the second direction to form a plurality of standard cell columns; the plurality of standard cell rows include a first standard cell row, wherein the plurality of first switch units are not provided at positions in the first standard cell row corresponding to at least one standard cell column other than the standard cell columns at both ends of the plurality of standard cell columns.

[0012] Effects of the Invention

[0013] According to one aspect of the present disclosure, a semiconductor integrated circuit device can be realized which can achieve low power consumption and improved wiring properties. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a plan view showing the structure of a semiconductor integrated circuit device according to an embodiment.

[0015] Figure 2 It means in Figure 1 A cross-sectional view of the semiconductor integrated circuit device taken along line II-II is shown.

[0016] Figure 3 This is a first plan view for explaining the arrangement of switch cells in the semiconductor integrated circuit device according to the embodiment.

[0017] Figure 4 This is a second plan view for explaining the arrangement of switch cells in the semiconductor integrated circuit device according to the embodiment.

[0018] Figure 5 It is a plan view showing the structure of a semiconductor integrated circuit device according to Modification 1 of the embodiment.

[0019] Figure 6 It is a plan view showing the structure of a semiconductor integrated circuit device according to a second variation of the embodiment.

[0020] Figure 7 It is a plan view showing the structure of a semiconductor integrated circuit device according to a third variation of the embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments and the like will be described in detail with reference to the drawings.

[0022] In addition, the embodiments described below all represent general or specific examples. The numerical values, constituent elements, configuration positions and connection forms of the constituent elements shown in the following embodiments are examples and are not intended to limit the present disclosure. In addition, the constituent elements in the following embodiments that are not described in the independent claims are described as arbitrary constituent elements.

[0023] In addition, each figure is a schematic diagram and does not necessarily illustrate strictly. Therefore, for example, the scales in each figure are not necessarily the same. In addition, in each figure, the same reference numerals are given to substantially the same structure, and repeated descriptions are omitted or simplified.

[0024] In addition, in this specification, terms such as orthogonal that indicate the relationship between elements, terms such as jagged that indicate the shape of elements, and numerical values ​​and numerical ranges do not express only strict meanings, but mean essentially the same range, for example, also including differences of about a few percentage points (or about 10%).

[0025] In the present specification, ordinal numbers such as “first” and “second” do not refer to the number or order of components unless otherwise specified, but are used to distinguish between components of the same kind to avoid confusion.

[0026] (Implementation Method)

[0027] [1. Structure of semiconductor integrated circuit device]

[0028] Below, refer to Figure 1 to Figure 4 A semiconductor integrated circuit device according to this embodiment will be described. Figure 1 FIG. 1 is a plan view showing the structure of a semiconductor integrated circuit device 1 according to the present embodiment. Figure 1 In the figure, the layout pattern in the circuit block for power cutoff is simplified and illustrated. In addition, in each figure, for convenience, hatching is added to illustrate the switch unit SW, etc., but it is not intended to show the cross section of the switch unit SW, etc. Figure 1 In FIG. 1 , a region where the standard cell 11 is arranged is illustrated with a reference numeral representing the standard cell 11 .

[0029] like Figure 1 As shown, the semiconductor integrated circuit device 1 includes a plurality of standard cell rows 10, a plurality of strip-shaped power supply wirings 30, a plurality of sub-strip-shaped power supply wirings 40, and a plurality of switch cells SW. Each component of the semiconductor integrated circuit device 1 is disposed on, for example, a substrate (not shown).

[0030] The plurality of standard cell rows 10 are respectively configured to include a plurality of standard cells 11 arranged in the X direction (first direction), and a plurality of power supply wirings L1 and a plurality of ground power supply wirings L2 extending in the X direction (i.e., the arrangement direction of the standard cells 11). In addition, the plurality of standard cell rows 10 are arranged in the Y direction orthogonal to the X direction to form a plurality of standard cell columns 20.

[0031] The standard cell 11 is a basic circuit element having functions such as an inverter and a logic circuit. By combining and arranging the standard cells 11, a semiconductor integrated circuit device that realizes a predetermined function can be manufactured. The standard cell 11, for example, has an N-type region that forms a P-type MOS (Metal Oxide Semiconductor) transistor (PMOS) and a P-type region that forms an N-type MOS transistor (NMOS). In addition, the standard cell 11 may also have an N-type region and a P-type region arranged in the Y direction. In addition, the internal structure of the standard cell 11 is omitted from the figure.

[0032] The power supply wiring L1 and the ground power supply wiring L2 are mutually arranged between the standard cell rows 10. The power supply wiring L1 is connected to each of the plurality of standard cells 11 arranged in the standard cell row 10, and is a wiring for supplying power (power supply potential (VDD)) to each of the plurality of standard cells 11. In addition, the ground power supply wiring L2 is connected to each of the plurality of standard cells 11 arranged in the standard cell row 10, and is a wiring for supplying a ground potential (VSS) to each of the plurality of standard cells 11.

[0033] In this embodiment, the plurality of standard cell rows 10 include standard cell rows 10a1 and 10a2 (second standard cell rows) in which switch cells SW are arranged and a standard cell row 10b (second standard cell row) in which no switch cells SW are arranged. Figure 1 The “row without SW” in the standard cell row 10b is the first standard cell row. In addition, at least one standard cell row 10b only needs to be arranged.

[0034] In addition, one standard cell row 10 is formed by a range in which two standard cells 11 are arranged in the vertical direction (Y direction) and arranged in the horizontal direction (X direction). For example, the standard cell row 10b is formed by the range of the dotted line frame.

[0035] The strip-shaped power supply wiring 30 is provided so as to extend in the Y direction. The strip-shaped power supply wiring 30 can be provided, for example, on the upper layer of the standard cell row 20 and the power supply wiring L1. In addition, the strip-shaped power supply wiring 30 is connected to the power supply wiring L1 through a via structure (see Figure 2) and connected to the input terminal (not shown) of the switch unit SW arranged therebelow. In addition, the strip-shaped power supply wiring 30 is provided so as to overlap (be electrically connected to) each switch unit SW arranged in the standard cell array 20 in a plan view.

[0036] The sub-strip-shaped power wiring 40 is provided so as to extend in the Y direction. The sub-strip-shaped power wiring 40 can be provided, for example, on the upper layer of the standard cell column 20 and the power wiring L1. The sub-strip-shaped power wiring 40 is connected to the power wiring L1 passing thereunder via a via structure (not shown). In addition, in a plan view, the sub-strip-shaped power wiring 40 is provided at a position that does not overlap with the switch cell SW. For example, the sub-strip-shaped power wiring 40 and the strip-shaped power wiring 30 are alternately arranged along the X direction.

[0037] The sub-strip-shaped power supply wiring 40 is connected to the power supply wiring L1 provided in the standard cell rows 10a1, 10a2, and 10b, respectively. That is, the sub-strip-shaped power supply wiring 40 connects the power supply wiring L1 of the standard cell row where the switch cell SW is arranged with the power supply wiring L1 of the standard cell row where the switch cell SW is not arranged. For example, each of the plurality of sub-strip-shaped power supply wirings 40 is connected to each of the plurality of power supply wirings L1.

[0038] The sub-strip-shaped power supply wiring 40 and the strip-shaped power supply wiring 30 are not electrically connected.

[0039] The switch unit SW controls whether to cut off the power supply to the standard cell 11. The switch unit SW is provided at the intersection of the strip-shaped power wiring 30 and the power wiring L1 in a plan view, and is configured to be able to switch whether to electrically connect the strip-shaped power wiring 30 to the power wiring L1 according to a control signal. That is, the switch unit SW switches between the conduction and non-conduction of the strip-shaped power wiring 30 and the power wiring L1. For example, the switch unit SW is provided between one of the plurality of strip-shaped power wirings 30 and a wiring group consisting of N (N is an integer greater than or equal to 1) of the plurality of power wirings L1, and is configured to be able to switch whether to electrically connect the strip-shaped power wiring 30 to the power wiring L1 belonging to the wiring group according to a control signal. The control signal is input, for example, from a control device that controls the power cutoff.

[0040] The switch unit SW has an input terminal connected to the strip power wiring 30 and a terminal receiving a control signal for switching between conduction and non-conduction. The switch unit SW is a semiconductor switch whose source is connected to the input terminal (i.e., the strip power wiring 30), whose drain is connected to the power wiring L1, and whose gate is connected to a terminal receiving a control signal. The conduction and non-conduction between the strip power wiring 30 and the power wiring L1 are switched according to the High / Low of the control signal.

[0041] In addition, the switch unit SW is not arranged at all the intersections of the plurality of strip-shaped power supply wires 30 and the plurality of power supply wires L1. The switch unit SW is an example of a first switch unit.

[0042] In the semiconductor integrated circuit device 1 as described above, power is supplied to the standard cell row 10b via any of the plurality of sub-strip-shaped power supply wirings 40. For example, when power is supplied to the standard cell 11 of the standard cell row 10b, the switch unit SW of the standard cell row (for example, the standard cell row 10a1 or 10a2) located close to (for example, adjacent to) the standard cell row 10b is turned on, and power is supplied to the power supply wiring L1 of the standard cell row.

[0043] Since the power supply wiring L1 is connected to the sub-strip-shaped power supply wiring 40 via a via structure, power is also supplied to the sub-strip-shaped power supply wiring 40. That is, power is supplied along the sub-strip-shaped power supply wiring 40. Since the sub-strip-shaped power supply wiring 40 is also connected to the power supply wiring L1 of the standard cell row 10b via a via structure, power is supplied from the power supply wiring L1 of the standard cell row in which the switch cell SW is arranged to the power supply wiring L1 of the standard cell row 10b via the sub-strip-shaped power supply wiring 40.

[0044] In this way, power is supplied to the standard cell 11 in the standard cell row 10b where the switch cell SW is not provided via the strip-shaped power supply wiring 30, the switch cell SW, the power supply wiring L1 of the standard cell row where the switch cell SW is provided, and the sub-strip-shaped power supply wiring 40. In addition, in the present embodiment, power is supplied to the standard cell row 10b only via the sub-strip-shaped power supply wiring 40.

[0045] Next, refer to Figure 2 The cross-sectional structure (laminate structure) of the semiconductor integrated circuit device 1 will be described. Figure 2 It means in Figure 1 The semiconductor integrated circuit device 1 is shown in a cross-sectional view taken along line II-II. Figure 2 The cross-sectional structure of the portion where the switch unit SW is arranged is shown.

[0046] like Figure 2 As shown, the semiconductor integrated circuit device 1 has a switch unit SW and more than 5 wiring layers on a substrate. For example, the 1st to 5th wiring layers (metal 1 to metal 5) are formed in a stacked manner from the substrate side. The 1st to 5th wiring layers are respectively connected through vias (via 1 to via 4). The 1st wiring layer is a wiring layer for power supply. For example, the power supply wiring L1 and the ground power supply wiring L2 are formed in the 1st wiring layer (metal 1). The wiring of the 1st wiring layer (for example, the power supply wiring L1) is also connected to the switch unit SW.

[0047] In addition, the second and fourth wiring layers (metal 2 and metal 4) are wiring layers for signal wiring provided in the X direction. The preferred wiring direction of the second and fourth wiring layers is the X direction. In addition, the third and fifth wiring layers (metal 3 and metal 5) are wiring layers for wiring provided in the Y direction. The preferred wiring direction of the third and fifth wiring layers is the Y direction. The strip-shaped power wiring 30 and the sub-strip-shaped power wiring 40 are formed in either the third or fifth wiring layer. For example, the sub-strip-shaped power wiring 40 may be provided as a lower layer than the strip-shaped power wiring 30.

[0048] In addition, regarding the cross-sectional structure of the position where the switch unit SW is not provided on the strip-shaped power supply wiring 30, for example, although the wiring layer (for example, metal 3 or metal 5) for the strip-shaped power supply wiring 30 is formed, other wiring layers are not formed. That is, by reducing the number of switch units SW provided, it is no longer necessary to form Figure 2 Since only a portion of the first to fifth wiring layers (eg, wiring layers 2 to 4) is shown, other wiring can be passed through the portion in a straight line. That is, according to the semiconductor integrated circuit device 1, wiring properties are improved.

[0049] Next, refer to Figure 3 and Figure 4 The configuration position of the switch unit SW is described. Figure 3 An example in which the switch units SW are repeatedly arranged in the X direction will be described. Figure 3 1 is a first plan view for explaining the arrangement of the switch unit SW in the semiconductor integrated circuit device 1 of the present embodiment. Figure 3 is a diagram for explaining that the configuration positions of the switch units SW are repeated in the same pattern in the X direction. Figure 1 A portion of the structure is removed for illustration. Figure 3 For convenience, the number of standard cell rows 10 and standard cell columns 20 is shown in FIG. Figure 1 Different situations.

[0050] like Figure 3As shown, in the standard cell row 10b, the switch unit SW is not configured in the standard cell row. The standard cell row 10b does not have a switch unit SW configured at each of the positions corresponding to one or more standard cell columns 20 other than the standard cell columns 21 and 22 at the ends of the standard cell row 10b, and the positions corresponding to the standard cell columns 21 and 22 at the ends. The standard cell row 10b is a standard cell row having a plurality of standard cells 11 (power supply objects) but not having a switch unit SW (power supply source). In addition, for example, the standard cell row 10b is configured in a manner sandwiched by the standard cell rows 10a1 and 10a2, but is not limited thereto. In addition, for example, the standard cell row 10b may be configured continuously in the Y direction or may be configured discontinuously.

[0051] In addition, it is not necessary to configure the switch unit SW at the positions corresponding to the standard cell columns 21 and 22 at both ends. Figure 6 and Figure 7 This will be described later.

[0052] In this embodiment, the standard cell rows 10b are arranged every three rows. In this way, the standard cell rows 10b may be arranged at equal intervals every a predetermined number of rows. In addition, the standard cell rows 10b are not limited to being arranged at equal intervals, but may be arranged randomly.

[0053] In addition, in the present embodiment, the plurality of strip power wirings 30 include strip power wirings 31 (first strip power wiring) and strip power wirings 32 (second strip power wiring) that are adjacent to each other and have different positions of switch cells SW in the Y direction. For example, in a plan view, the switch cells SW on the strip power wirings 31 and 32 are arranged in a zigzag shape. In this way, the positions of switch cells SW in the Y direction may be different in adjacent strip power wirings 30. For example, in the present embodiment, in one standard cell row 10, no switch cells SW are arranged for both adjacent strip power wirings 30.

[0054] Furthermore, in the present embodiment, the arrangement positions of the plurality of switch units SW in the X direction are arranged every two strip-shaped power supply wirings 30 ( Figure 3 That is, the configuration positions of the switch units SW repeat the same configuration pattern for every two strip-shaped power supply wirings 30. Figure 3 In the example of FIG. 1 , strip-shaped power supply wirings 31 and 32 are alternately arranged.

[0055] Moreover, it is not limited to being the same for every two strips, but may be the same for every three strips, etc. For example, the arrangement positions of the plurality of switch units SW in the X direction may be the same for every M (M is a natural number greater than or equal to 2) strip power supply wires 30 among the plurality of strip power supply wires 30 .

[0056] In addition, at least one standard cell row 10b is included in the repeating unit R1. Figure 3 In the example of FIG. 1 , in the repetitive unit R1, there is a standard cell row 10 in which no corresponding switch cell SW is arranged. By repeatedly arranging the standard cell row 10 in which no switch cell SW is arranged in the repetitive unit in the X direction, a standard cell row 10b is formed.

[0057] Next, refer to Figure 4 An example in which the arrangement of the switch units SW is repeated in the Y direction will be described. Figure 4 It is a second plan view for explaining the arrangement of the switch unit SW in the semiconductor integrated circuit device 1 according to the present embodiment. Figure 4 The structure of the semiconductor integrated circuit device 1 shown is similar to Figure 3 same.

[0058] like Figure 4 As shown, in the present embodiment, the plurality of standard cell rows 10 include a standard cell row 10a2 (the fifth standard cell row) and a standard cell row 10a1 (the fourth standard cell row) which are adjacent to each other and are respectively provided with at least one switch cell SW among the plurality of switch cells SW. The configuration positions of the at least one switch cell SW respectively provided in the standard cell rows 10a1 and 10a2 in the X direction are different from each other. For example, in a plan view, the switch cells SW provided in the standard cell rows 10a1 and 10a2 are arranged in a zigzag shape. In this way, the configuration positions of the switch cells SW in the X direction may also be different from each other in adjacent standard cell rows 10.

[0059] Furthermore, in the present embodiment, the arrangement positions of the plurality of switch cells SW in the Y direction are arranged every three standard cell rows 10 ( Figure 4 That is, the arrangement positions of the switch cells SW repeat the same arrangement pattern every three standard cell rows 10.

[0060] In addition, it is not limited to being the same for every three rows, and it may be the same for every two rows, every four rows, etc. For example, the arrangement positions of the plurality of switch cells SW in the X direction may be the same for every N (N is a natural number greater than or equal to 2) standard cell rows 10 among the plurality of standard cell rows 10. In addition, the N standard cell rows 10 (i.e., the repeating unit R2) include the standard cell row 10b. That is, the standard cell row 10b is arranged for every predetermined number of rows.

[0061] In addition, in this embodiment, using Figure 3 and Figure 4 An example in which the arrangement position of the switch unit SW is repeated in both the X direction and the Y direction has been described, but the arrangement position of the switch unit SW may be repeated in at least one of the X direction and the Y direction.

[0062] [2. Effects, etc.]

[0063] As described above, the semiconductor integrated circuit device 1 of the present embodiment comprises: a plurality of standard cell rows 10, each of which has a plurality of standard cells 11 arranged in an X direction (a first direction), and a plurality of power supply wirings L1 extending in the X direction and supplying power to the plurality of standard cells 11; a plurality of strip-shaped power supply wirings 30 extending in the Y direction (a second direction) orthogonal to the X direction on the upper layer of the plurality of power supply wirings L1; a plurality of sub-strip-shaped power supply wirings 40 extending in the Y direction on the upper layer of the plurality of power supply wirings L1 and each connected to each of the plurality of power supply wirings L1; and a plurality of switch units SW (a first switch unit) provided at intersections of the plurality of strip-shaped power supply wirings 30 and the plurality of power supply wirings L1 and configured to be able to switch whether or not to electrically connect the strip-shaped power supply wirings 30 to the power supply wirings L1 according to a control signal. Furthermore, the plurality of standard cell rows 10 are arranged in the Y direction to form a plurality of standard cell columns 20; the plurality of standard cell rows 10 include a standard cell row 10b (the first standard cell row), and the plurality of switch cells SW are not configured at positions in the standard cell row 10b corresponding to one or more standard cell columns 23 in the plurality of standard cell columns 20 except the standard cell columns 21 and 22 at both ends.

[0064] Thus, the semiconductor integrated circuit device 1 includes the switch unit SW that can switch the connection between the strip-shaped power supply wiring 30 and the power supply wiring L1, that is, it has a structure that cuts off the supply of power, so that low power consumption can be achieved. In addition, in the standard cell row 10b where the switch unit SW is not configured, since a via structure for connecting the strip-shaped power supply wiring 30 to the power supply wiring L1 is not required, it is easy to form other wiring. Thus, the semiconductor integrated circuit device 1 can achieve low power consumption and improve wiring performance.

[0065] Furthermore, in the standard cell row 10 b , the plurality of switch cells SW are not arranged at positions corresponding to the standard cell columns 21 and 22 at both ends of the standard cell row 10 b .

[0066] This can further reduce the number of switch units SW, that is, the number of via structures can be reduced, so that the wiring property can be further improved.

[0067] In addition, power is supplied to the standard cell row 10b via one of the plurality of sub-strip-shaped power supply wirings 40. For example, the plurality of standard cell rows 10 include a standard cell row 10a1 or 10a2 (a second standard cell row), and one or more switch cells SW of the plurality of switch cells SW are arranged at positions in the standard cell row 10a1 or 10a2 corresponding to one or more other standard cell columns 23 of the plurality of standard cell columns 20. The plurality of sub-strip-shaped power supply wirings 40 are connected to the power supply wiring L1 arranged in each of the standard cell row 10b and the standard cell row 10a1 or 10a2.

[0068] Thus, power can be supplied to the standard cell row 10 without switch cells SW via the sub-strip-shaped power supply wiring 40. That is, the standard cell 11 in the standard cell row 10 without switch cells SW can be operated, and power consumption can be reduced and wiring properties can be improved.

[0069] In addition, the plurality of strip power wirings 30 include adjacent strip power wirings 31 (first strip power wirings) and strip power wirings 32 (second strip power wirings), and the arrangement positions of the plurality of switch units SW in the Y direction may be different from each other in the strip power wirings 31 and 32. For example, the arrangement positions of the plurality of switch units SW in the X direction may be the same for every M strip power wirings 30 among the plurality of strip power wirings 30, where M is a natural number greater than or equal to 2.

[0070] In addition, the plurality of standard cell rows 10 include a standard cell row 10a1 (the fourth standard cell row) and a standard cell row 10a2 (the fifth standard cell row) adjacent to each other and each of which is provided with at least one switch cell SW among the plurality of switch cells SW. Furthermore, the configuration positions of at least one switch cell SW in each of the standard cell rows 10a1 and 10a2 in the X direction may be different from each other. For example, the configuration positions of the plurality of switch cells SW in the Y direction may be the same for every N standard cell rows including the standard cell row 10b among the plurality of standard cell rows 10, where N is a natural number greater than or equal to 2.

[0071] In this way, since the arrangement of the switch unit SW can be arbitrarily set, the degree of freedom of arrangement of the switch unit SW increases.

[0072] (Variation 1 of the embodiment)

[0073] Below, refer to Figure 5 A semiconductor integrated circuit device according to this modification example will be described. Figure 51 is a plan view showing the structure of the semiconductor integrated circuit device 1a of this modification. In addition, the following description will focus on the differences from the embodiment, and the description of the same or similar contents as the embodiment will be omitted or simplified. The semiconductor integrated circuit device 1a of this modification is different from the semiconductor integrated circuit device 1 of the embodiment in that the configuration positions of the switch cells are repeated in different patterns in the Y direction. In addition, the following description will take three standard cell rows 10 as one repeating unit, and explain an example in which the configuration of the standard cell rows 10 in the Y direction is different in adjacent repeating units.

[0074] like Figure 5 As shown, the semiconductor integrated circuit device 1a has a structure in which three standard cell rows 10 are used as one repeating unit (repeating units R11, R12, and R13), and the repeating units R11, R12, and R13 are arranged in the Y direction.

[0075] The repeating units R11, R12, and R13 are each formed of a plurality of standard cell rows 10. For example, the numbers of standard cell rows 10 included in each of the repeating units R11, R12, and R13 are equal, but may be different.

[0076] exist Figure 5 In the example, the repeating units R11, R12 and R13 are formed by including one standard cell row 10a1, 10a2 and 10b respectively, and the standard cell rows 10a1, 10a2 and 10b are arranged differently in the Y direction. The repeating units R11, R12 and R13 each include at least one standard cell row 10b.

[0077] In addition, the arrangement of the repeating units R11, R12 and R13 is not particularly limited, and for example, the arrangement may be set in a manner that the same repeating units are arranged discontinuously in the Y direction. For example, the arrangement of the repeating units R11, R12 and R13 may be randomly set in a manner that the same repeating units are arranged discontinuously in the Y direction. In addition, in the above, the example in which the number of standard cell rows 10 included in each of the repeating units R11, R12 and R13 and the configuration positions of the switch cells SW in the standard cell rows 10 are the same is described, but they may also be different. In addition, the standard cell rows 10 included in at least one of the repeating units R11, R12 and R13 may also be configured with the switch cells SW at the positions corresponding to the standard cell columns 21 and 22 at both ends.

[0078] (Variation 2 of the embodiment)

[0079] Below, refer to Figure 6 A semiconductor integrated circuit device according to this modification example will be described. Figure 6: is a plan view showing the structure of the semiconductor integrated circuit device 1b of this variant. In addition, the following description will focus on the differences from the embodiment, and the description of the same or similar contents as the embodiment will be omitted or simplified. The semiconductor integrated circuit device 1b of this variant is different from the semiconductor integrated circuit device 1 of the embodiment in that the switch unit SW1 is configured in all of the standard cell columns 21 and 22 at both ends. In addition, the hatching shape of the switch unit SW1 configured in the standard cell columns 21 and 22 at both ends is changed compared to the switch unit SW configured in the embodiment, etc. Figure 6 Hereinafter, the description of “a row where SW is not arranged” is omitted.

[0080] like Figure 6 As shown, the semiconductor integrated circuit device 1b has Figure 3 and Figure 4 In addition to the semiconductor integrated circuit device 1 shown, the standard cell columns 21 and 22 are provided with switch cells SW1 and strip-shaped power supply wiring 33. Regardless of whether switch cells SW are arranged at positions corresponding to other standard cell columns 23 other than the standard cell columns 21 and 22, the switch cells SW1 are arranged in the standard cell columns 21 and 22.

[0081] Thus, in the standard cell row 10b1 (first standard cell row), 10a3 and 10a4 (second standard cell row), switch cells SW1 are further arranged at positions corresponding to the standard cell columns 21 and 22 at both ends of the plurality of standard cell columns 20 in the standard cell rows 10b1, 10a3 and 10a4. It can be said that the switch cell SW1 is arranged at positions corresponding to the standard cell columns 21 and 22 at both ends of the standard cell row 10b1. In addition, the switch cell SW1 has the same structure as the switch cell SW. In addition, the switch cell SW1 is an example of the second switch cell.

[0082] In addition, the switch unit SW1 is not limited to being arranged on both sides of the standard cell columns 21 and 22, but may be arranged only on one side. In addition, the switch unit SW1 is not limited to being arranged on each standard cell column 20, but may be arranged only on the standard cell row 10b1. For example, the switch unit SW1 may be arranged at a position corresponding to the standard cell columns 21 and 22 at least one of the two ends of the plurality of standard cell columns 20 in the standard cell row 10b1. In addition, the switch unit SW1 may be arranged for every predetermined number of rows in the standard cell columns 21 and 22. The semiconductor integrated circuit device 1b only needs to have at least one switch unit SW1 at a certain position in the standard cell columns 21 and 22.

[0083] The strip power supply wiring 33 is provided in the standard cell columns 21 and 22 so as to extend in the Y direction. The strip power supply wiring 33 may be provided, for example, in the upper layer of the standard cell columns 21 and 22 and the power supply wiring L1. Figure 2 ) and connected to the input terminal (not shown) of the switch unit SW1 arranged therebelow. In addition, the strip-shaped power supply wiring 33 is provided so as to overlap (electrically connect) the switch units SW1 arranged in the standard cell rows 21 and 22, respectively, in a plan view.

[0084] As described above, the semiconductor integrated circuit device 1b of the present embodiment further includes a switch unit SW1 (a second switch unit) arranged at a position corresponding to at least one of the standard cell columns 21 and 22 at both ends in the standard cell row 10b1 (the first standard cell row). For example, the switch unit SW1 may be arranged at positions corresponding to the standard cell columns 21 and 22 at both ends in the standard cell row 10b1.

[0085] Thus, since the switch cell SW1 can be arranged at the position corresponding to the standard cell columns 21 and 22 where the power supply is weakened, the weakening of the power supply can be suppressed in the semiconductor integrated circuit device 1 b.

[0086] (Variation 3 of the embodiment)

[0087] Below, refer to Figure 7 A semiconductor integrated circuit device according to this modification example will be described. Figure 7 1 is a plan view showing the structure of a semiconductor integrated circuit device 1c of this variant. In addition, the following description will focus on the differences from the embodiment, and the description of the same or similar contents as the embodiment will be omitted or simplified. The semiconductor integrated circuit device 1c of this variant is different from the semiconductor integrated circuit device 1 of the embodiment in that it also has standard cell rows in which switch cells are arranged at positions corresponding to standard cell columns other than the standard cell columns at both ends. In addition, the hatching form of the switch cell SW2 added to the switch cell SW of the semiconductor integrated circuit device 1 of the embodiment is changed with respect to the switch cells SW and SW3. The switch cell SW3 corresponds to the switch cell SW1 in the variant 2 of the embodiment.

[0088] like Figure 7 As shown, the standard cell row 10 of the semiconductor integrated circuit device 1c has standard cell rows 10c1, 10c2 and 10c3 (the third standard cell row), and a switch unit SW2 is configured at a position in each of the standard cell rows 10c1, 10c2 and 10c3 corresponding to one or more standard cell columns 23 among the multiple standard cell columns 20 except the standard cell columns 21 and 22 at the two ends.

[0089] In each of the standard cell rows 10c1, 10c2, and 10c3, one or more switch cells SW2 are arranged. The standard cell rows 10c1, 10c2, and 10c3 do not have switch cells SW arranged at positions corresponding to the standard cell columns 21 and 22 at both ends of the plurality of standard cell columns 20, and have switch cells SW2 arranged at positions corresponding to one or more other standard cell columns 23 and different from those of the standard cell rows 10a1 and 10a2.

[0090] The standard cell rows 10 c 1 and 10 c 2 have one switch cell SW 2 at a position corresponding to one or more other standard cell columns 23 .

[0091] The standard cell row 10 c 3 has two switch cells SW2 at positions corresponding to one or more other standard cell columns 23 .

[0092] The switch unit SW2 may be arranged at a random position in the standard cell rows 10c1, 10c2, and 10c3, for example. In addition, the switch unit SW2 may be arranged in a row with the switch unit SW in the Y direction, for example. The number of the switch units SW2 arranged in the standard cell rows 10c1, 10c2, and 10c3 may be less than the number of the switch units SW arranged in the standard cell row 10a3 or 10a4. The switch unit SW2 is an example of one or more other switch units among the plurality of switch units SW.

[0093] In addition, the semiconductor integrated circuit device 1c only needs to include at least one of the standard cell rows 10c1, 10c2, and 10c3. For example, the standard cell row 10c may be configured such that the switch unit SW3 is not configured at positions corresponding to the standard cell columns 21 and 22 at both ends of the plurality of standard cell columns 20 in the standard cell row 10c, and one or more switch units SW2 are configured at positions (e.g., random positions) corresponding to one or more other standard cell columns 23 and different from the standard cell rows 10a1 and 10a2.

[0094] Furthermore, the semiconductor integrated circuit device 1c may include standard cell rows 10a5, 10a6, and 10b2 and strip-shaped power supply wiring 33. Each of the standard cell rows 10a5, 10a6, and 10b2 does not include the switch unit SW2.

[0095] In the standard cell row 10 a 5 , SW 3 is arranged at a position corresponding to the standard cell column 21 in the standard cell row 10 a 1 .

[0096] In the standard cell row 10 a 6 , SW 3 is arranged at a position corresponding to the standard cell column 21 in the standard cell row 10 a 2 .

[0097] In the standard cell row 10 b 2 , SW 3 is arranged at a position corresponding to the standard cell column 21 in the standard cell row 10 b 1 .

[0098] In addition, the switch units SW2 and SW3 control whether to cut off the power supply to the standard cell 11. The switch units SW2 and SW3 are provided at the intersection of the strip-shaped power wiring 30 and the power wiring L1 in a plan view, and are configured to be able to switch whether to electrically connect the strip-shaped power wiring 30 to the power wiring L1 according to a control signal. That is, the switch units SW2 and SW3 switch between conduction and non-conduction between the strip-shaped power wiring 30 and the power wiring L1. In addition, the switch units SW2 and SW3 have the same structure as the switch unit SW. In addition, the switch unit SW3 may also be arranged in at least one of the standard cell rows 10c1, 10c2 and 10c3, for example.

[0099] The strip-shaped power supply wiring 33 is provided in the standard cell row 21 so as to extend in the Y direction. For example, the strip-shaped power supply wiring 33 is provided only in the standard cell row 21 where the switch cell SW3 is arranged, among the standard cell rows 21 and 22 at both ends.

[0100] As described above, the plurality of standard cell rows 10 included in the semiconductor integrated circuit device 1c of the present embodiment further include a standard cell row 10c1, 10c2 or 10c3 (the third standard cell row), and the switch cell SW3 is not configured at a position in the standard cell row 10c1, 10c2 or 10c3 corresponding to the standard cell columns 21 and 22 at both ends of the plurality of standard cell columns 20, and one or more other switch cells SW2 among the plurality of switch cells SW are configured at a position corresponding to one or more other standard cell columns 23 and different from the standard cell row 10a1 or 10a2 (the second standard cell row).

[0101] Thus, the degree of freedom in configuring the switch unit SW2 increases.

[0102] (Other embodiments)

[0103] The semiconductor integrated circuit device of one or more technical solutions is described above based on the implementation mode, etc., but the present disclosure is not limited to the implementation mode, etc. As long as it does not deviate from the main purpose of the present disclosure, various forms after the present embodiment is applied to the present embodiment and the forms constructed by combining the constituent elements of different implementation modes may also be included in the present disclosure.

[0104] For example, in the above-mentioned embodiments, the configuration positions of the plurality of switch units in the second direction are different from each other in adjacent strip-shaped power wirings (e.g., the first and second strip-shaped power wirings), but the present invention is not limited thereto. For example, the configuration positions of the plurality of switch units in the first direction are different from each other in adjacent standard cell rows (e.g., the fourth and fifth standard cell rows ....

[0105] In addition, the power supply cutoff method of the switch unit in the above-mentioned embodiment and the like may be a method of cutting off the power supply potential (VDD) or a method of cutting off the ground potential (VSS).

[0106] Industrial Applicability

[0107] The present disclosure is useful for semiconductor integrated circuit devices using a power supply cutoff technique.

[0108] Description of Reference Numerals

[0109] 1, 1a, 1b, 1c semiconductor integrated circuit device

[0110] 10, 10a5, 10a6 standard cell rows

[0111] 10a1 standard cell row (2nd standard cell row, 4th standard cell row)

[0112] 10a2 standard cell row (2nd standard cell row, 5th standard cell row)

[0113] 10a3, 10a4 standard cell row (2nd standard cell row)

[0114] 10b, 10b1, 10b2 standard cell row (1st standard cell row)

[0115] 10c1, 10c2, 10c3 standard cell row (3rd standard cell row)

[0116] 11 standard units

[0117] 20, 21, 22, 23 standard unit columns

[0118] 30 ribbon power wiring

[0119] 31 Strip power wiring (1st strip power wiring)

[0120] 32 Strip power wiring (2nd strip power wiring)

[0121] 33 ribbon power wiring

[0122] 40 pairs of power strip wiring

[0123] L1 power wiring

[0124] L2 ground power wiring

[0125] R1, R2, R11, R12, R13 repeating units

[0126] SW switch unit (1st switch unit)

[0127] SW1, SW3 switch unit (second switch unit)

[0128] SW2 switch unit

Claims

1. A semiconductor integrated circuit device, characterized in that: have: A plurality of standard cell rows each having a plurality of standard cells arranged in a first direction and a plurality of power supply wirings extending in the first direction and supplying power to the plurality of standard cells; A plurality of strip-shaped power supply wirings extending in a second direction orthogonal to the first direction on an upper layer of the plurality of power supply wirings; a plurality of sub-strip-shaped power supply wirings extending in the second direction on an upper layer of the plurality of power supply wirings and connected to respective ones of the plurality of power supply wirings; as well as a plurality of first switch units, provided at intersections of the plurality of strip-shaped power wirings and the plurality of power wirings, and configured to switch whether to electrically connect the strip-shaped power wirings to the power wirings according to a control signal; The plurality of standard cell rows are arranged in the second direction to form a plurality of standard cell columns; The plurality of standard cell rows include a first standard cell row, and the plurality of first switch cells are not arranged at positions in the first standard cell row corresponding to at least one standard cell column other than the standard cell columns at both ends of the plurality of standard cell columns.

2. The semiconductor integrated circuit device according to claim 1, wherein: Furthermore, in the first standard cell row, the plurality of first switch cells are not arranged at positions corresponding to the standard cell columns at both ends in the first standard cell row.

3. The semiconductor integrated circuit device according to claim 1, wherein: The invention further includes a second switch unit disposed at a position in the first standard cell row corresponding to at least one of the standard cell columns at both ends.

4. The semiconductor integrated circuit device according to claim 3, wherein: The second switch cells are arranged at positions corresponding to the standard cell columns at both ends in the first standard cell row.

5. The semiconductor integrated circuit device according to any one of claims 1 to 4, wherein: Power is supplied to the first standard cell row via any one of the plurality of sub-strip-shaped power supply wirings.

6. The semiconductor integrated circuit device according to any one of claims 1 to 5, wherein: The plurality of standard cell rows include a second standard cell row, and one or more first switch cells among the plurality of first switch cells are arranged at positions in the second standard cell row corresponding to the other one or more standard cell columns among the plurality of standard cell columns; The plurality of sub-strip-shaped power supply wirings are respectively connected to power supply wirings arranged in the first standard cell row and the second standard cell row.

7. The semiconductor integrated circuit device according to any one of claims 1 to 6, wherein: The plurality of strip-shaped power supply wirings include a first strip-shaped power supply wiring and a second strip-shaped power supply wiring adjacent to each other; The arrangement positions of the plurality of first switch units in the second direction are different between the first strip-shaped power wiring and the second strip-shaped power wiring.

8. The semiconductor integrated circuit device according to any one of claims 1 to 7, wherein: The arrangement positions of the plurality of first switch units in the first direction are the same for every M strip-shaped power supply wirings among the plurality of strip-shaped power supply wirings, where M is a natural number greater than or equal to 2.

9. The semiconductor integrated circuit device according to claim 6, wherein: The above-mentioned multiple standard cell rows also have a third standard cell row, in which the above-mentioned third standard cell row has no switch unit configured at the positions corresponding to the above-mentioned standard cell columns at the two ends of the above-mentioned multiple standard cell columns, and at a position corresponding to the above-mentioned other one or more standard cell columns and different from the above-mentioned second standard cell row, one or more other first switch units among the above-mentioned multiple first switch units are configured.

10. The semiconductor integrated circuit device according to any one of claims 1 to 9, wherein: The plurality of standard cell rows include a fourth standard cell row and a fifth standard cell row which are adjacent to each other and are respectively provided with at least one first switch cell among the plurality of first switch cells; The one or more first switch cells in each of the fourth standard cell row and the fifth standard cell row are arranged at different positions in the first direction.

11. The semiconductor integrated circuit device according to any one of claims 1 to 10, wherein: Arrangement positions of the plurality of first switch cells in the second direction are the same for every N standard cell rows including the first standard cell row among the plurality of standard cell rows, where N is a natural number greater than or equal to 2.

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