Processing equipment and processing method of semiconductor structure

Abstract

The invention discloses processing equipment and a processing method of a semiconductor structure. The treatment apparatus comprises: a reaction chamber; a base; a gas spray head; the plurality of gas supply devices are respectively communicated with the gas inlet channels of the gas spray heads through pipelines, and supply gas to the reaction cavity through the gas spray heads; wherein at least one gas supply device is a remote plasma source; and the buffer tank is arranged between the remote plasma source and the gas spraying head and is used for conveying the processing gas from the remote plasma source into the reaction cavity at a certain process pressure. According to the invention, the buffer tank is arranged, the processing gas is firstly subjected to pressure building processing, after the preset pressure is reached, the gas is instantaneously released to the reaction cavity of the processing equipment, and the processing gas with a certain pressure can deeply enter the semiconductor structure, so that the top area of the semiconductor structure can be etched and thinned; and the bottom region of the semiconductor structure can be etched and thinned, so that the step coverage rate reaches 100%.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a processing device and a processing method for a semiconductor structure. Background Art

[0002] The 3D NAND structure includes a substrate and a base layer disposed on the substrate. The base layer includes multiple stacked dielectric layers, and the dielectric layers need to be electrically connected through conductive metal. Therefore, conductive metal needs to be filled between two adjacent dielectric layers and in the through hole.

[0003] At present, the industry usually uses ALD (atomic deposition process) to fill 3D NAND structures. During this process, the chamber needs to be fully purged and the dead zone of the equipment gas pipeline is required to be reduced as much as possible to reduce CVD reactions. When the tungsten thickness deposited in the top area of ​​the 3D NAND structure is thicker than that in the bottom area or the overall tungsten layer has poor conformality, it may cause uneven etching in the subsequent wet etching process. The subsequent wet etching process requires the through-hole structure of the 3D NAND structure to be uniform and conformal.

[0004] The conventional processing method is to introduce an etching gas at normal pressure and then etch the top area of ​​the 3D NAND structure after plasma excitation to reduce its thickness. However, this process still cannot solve the conformal problem of the 3D NAND structure. Summary of the invention

[0005] The object of the present invention is to provide a method and equipment for processing a semiconductor structure, so that the step coverage of the processed semiconductor structure reaches 100%, and the conformality of the structure is maintained, which is beneficial to wet etching in the subsequent process.

[0006] In order to achieve the above object, the present invention provides a semiconductor structure processing device, comprising:

[0007] Reaction chamber;

[0008] A base, which is arranged at the bottom of the reaction chamber and is used to carry the substrate;

[0009] A gas shower head, which is arranged at the top of the reaction chamber and is arranged opposite to the base;

[0010] A gas supply device, connected to the gas inlet channel of the gas shower head through a pipeline, and supplies gas to the reaction chamber through the gas shower head; wherein the gas supply device includes a remote plasma source;

[0011] A buffer tank is disposed between the remote plasma source and the gas shower head and is used to deliver the processing gas from the remote plasma source to the reaction chamber at a certain process pressure, wherein the processing gas contains halogen active free radicals.

[0012] Optionally, the processing equipment further comprises: a flow metering element, which is arranged on the communication pipeline between the remote plasma source and the buffer tank and is used to measure the amount of the processing gas flowing into the buffer tank.

[0013] Optionally, the processing equipment further comprises: a gas valve, which is arranged at the outlet of the buffer tank.

[0014] The present invention also provides a method for processing a semiconductor structure, comprising:

[0015] Providing the above-mentioned processing equipment;

[0016] A substrate to be processed is provided and placed in the reaction chamber; the substrate to be processed comprises a base layer arranged on a substrate, a plurality of openings are arranged on the base layer, and a first metal layer is arranged on the inner wall surface of the opening and the upper surface of the base layer;

[0017] Gas holding step: closing the gas valve and introducing a treatment gas from a remote plasma source into the buffer tank; the treatment gas contains halogen active free radicals;

[0018] Gas supply step: introducing the halogen active free radicals into the reaction chamber at a first process pressure through a gas shower head, wherein the halogen active free radicals react with the first metal layer on the surface of the substrate to be processed to generate gas products;

[0019] Purging step: introducing a purge gas to discharge the gaseous product out of the reaction chamber.

[0020] Optionally, the first process pressure is 50 torr to 500 torr.

[0021] Optionally, the halogen active free radical is a fluorine-containing active free radical or a chlorine-containing active free radical.

[0022] Optionally, the flow rate of the halogen active free radicals is 5 sccm-100 sccm.

[0023] Optionally, the processing gas further includes a carrier gas, and the carrier gas is an inert gas.

[0024] Optionally, the flow rate of the carrier gas is 200sccm-5000sccm.

[0025] Optionally, in the gas supply step, the gas supply time is 0.1s to 5s.

[0026] Optionally, the following steps are repeated multiple times: breath holding step, gas supply step and purging step.

[0027] Optionally, the base layer is a multi-layer structure, and a first metal layer is formed between two adjacent upper and lower layers.

[0028] Optionally, the substrate to be processed further comprises: a barrier layer, which is arranged between the surface of the base layer and the first metal layer.

[0029] Optionally, the substrate to be processed further includes: a second metal layer, which is arranged between the barrier layer and the first metal layer, and the resistivity of the first metal layer is smaller than that of the second metal layer.

[0030] Optionally, the metal material of the first metal layer and the second metal layer is at least one of tungsten, cobalt, molybdenum, ruthenium and rhodium, and the material of the first metal layer is the same as or different from that of the second metal layer.

[0031] Optionally, the opening has a high aspect ratio structure, and the aspect ratio is greater than 3:1.

[0032] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:

[0033] The present invention provides a buffer tank to hold the pressure of the processing gas first, and then releases the gas to the reaction chamber of the processing equipment instantaneously after reaching a predetermined pressure. The processing gas with a certain pressure can enter the semiconductor structure deeply, not only etching and thinning the top area of ​​the semiconductor structure, but also etching and thinning the bottom area of ​​the structure with a high aspect ratio. Since the concentration of the processing gas in the top area is high, the concentration of the processing gas diffuses to the bottom area under pressure driving, and the concentration gradually decreases. Therefore, the thickness of etching and thinning is a gradual process, which can not only achieve a step coverage rate of 100%, but also achieve a conformal effect.

[0034] In addition, the present invention can flexibly control the etching depth and etching rate by adjusting the gas holding pressure and / or gas supply time according to the process requirements.

[0035] Furthermore, the present invention can avoid excessive etching and achieve a better conformal effect by diluting the halogen active free radicals as much as possible, quickly switching the gas source, performing etching / flushing in multiple cycles, and performing etching and thinning in small amounts multiple times. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A partial cross-sectional view of a 3D NAND structure.

[0037] Figure 2 FIG. 4 is a schematic diagram of a process of filling W in a 3D NAND structure according to the present invention.

[0038] Figure 3 The present invention is a flowchart of a method for processing a semiconductor structure.

[0039] Figure 4 It is a schematic structural diagram of the processing equipment of the semiconductor structure of the present invention.

[0040] Figure 5 The schematic diagram is a mechanism diagram of a method for processing a semiconductor structure according to the present invention.

[0041] Figure ID:

[0042] Substrate w

[0043] Base layer 11

[0044] Dielectric layer 111

[0045] Opening 112

[0046] Gap 113

[0047] Filling layer 12

[0048] Barrier layer 121

[0049] Tungsten seed layer 122

[0050] Bulk tungsten layer 123

[0051] Reaction chamber 41

[0052] Base 42

[0053] Gas sprinkler head 43

[0054] Air supply device 44

[0055] Remote Plasma Source 441

[0056] Buffer tank 45

[0057] Flow metering element 46

[0058] Air valve 47. DETAILED DESCRIPTION

[0059] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0060] In the description of the present invention, it should be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0061] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0062] like Figure 1As shown, a 3D NAND structure includes a base layer 11 formed on a substrate, and the base layer is composed of a plurality of dielectric layers 111 stacked up and down. The dielectric layers shown in this example are 3 layers, which is only an example, and the multi-layer repeated structure is omitted. The structure is also provided with a plurality of openings 112 (only one opening is shown in the figure) penetrating the dielectric layers stacked up and down. There is a gap 113 between adjacent dielectric layers, and the gap 113 is filled with a filling layer 12. The filling layer 12 includes a barrier layer 121, a tungsten seed layer 122 and a block tungsten layer 123 deposited in sequence. Since the filling is formed by diffusing process gas through the opening 112 and then depositing, while the filling layer 12 is filled in the gap, the filling layer 12 is also formed on the top surface of the base layer 11 and the sidewall of the opening. As an example, in the process of filling the 3D NAND structure, a barrier layer 121 is first deposited on the sidewall of the opening 112 and the sidewall of the gap 113 between two adjacent dielectric layers (i.e., the surface of the dielectric layer). The thickness of the barrier layer 121 may be about 100 angstroms. In some embodiments, the barrier layer 121 may be deposited by atomic layer deposition (ALD). For example, the barrier layer 121 may be formed by sequentially introducing TiCl4, purge gas, NH3, and purge gas into the reaction chamber. Then, a tungsten seed layer (NUC W) 122 is deposited on the barrier layer 121. B2H6 and WF6 may be introduced respectively by ALD technology to form the tungsten seed layer 122 through the reaction of the two. The barrier layer 121 can not only provide an ohmic contact for the tungsten filling layer, making the nucleation of tungsten easier, but also prevent the fluorine-containing precursor gas from entering the dielectric layer 111 and damaging the device performance. The barrier layer 121 may also be composed of TaN, Ta, or other materials, as long as the effect of making the nucleation of tungsten easier and preventing the fluorine-containing precursor gas from entering the dielectric layer 111 can be achieved. Finally, a bulk tungsten layer (bulk tungsten) 123 is deposited on the tungsten seed layer 122 to completely fill the gaps 113 between the dielectric layers. The bulk tungsten layer 123 can be filled by the ALD process, and H2 and WF6 are introduced respectively, and the bulk tungsten layer 123 is formed by the reaction of the two. The resistance of the bulk tungsten layer 123 is less than that of the tungsten seed layer 122. When the gap 113 between the dielectric layers is completely filled, the sidewalls of the opening 112 in the dielectric layer need to be wet cleaned to remove the excess deposited bulk tungsten layer 123, tungsten seed layer 122, and TiN barrier layer 121, and then polysilicon is filled in the opening 112 to form a source line. This requires that the sidewalls of the opening 112 have conformal features and the step coverage rate reaches 100%, otherwise the residual tungsten layer on the sidewall will cause a short circuit between the filling layers 12 and cause the device to fail.

[0063] In order to fill the horizontal through-hole structure in 3D NAND, an ALD process with higher step coverage is usually used. Although the tungsten layer deposited by the ALD method is introduced in the manner of ALD, that is, the reaction gas is introduced in the form of tungsten precursor gas, purge gas, reducing gas, and purge gas, the tungsten growth process is actually still a CVD process, rather than the self-limiting growth method of traditional ALD. If the reaction chamber is not fully purged, the dead zone of the equipment gas pipeline will cause severe CVD reaction, making it difficult to achieve 100% step coverage of the 3D NAND structure. Because the thickness of tungsten deposited in the top area of ​​the 3D NAND structure is thicker than that in the bottom area. If only the tungsten layer in the top area is etched and thinned, on the one hand, it may cause excessive etching; on the other hand, the top area and the bottom area have poor conformality and unevenness, which is not conducive to subsequent wet etching.

[0064] In order to solve the above problems, it is necessary to allow the etching gas to enter a deeper depth of the 3D NAND structure, and at the same time, it is necessary to reduce the thickness of the tungsten layer in the top area more than the thickness of the tungsten layer in the bottom area. The present invention utilizes halogen-active free radicals with a certain pressure to etch the tungsten layer on the sidewall of the opening, so that the thickness of the tungsten layer in the top area of ​​the sidewall is equivalent to that in the bottom area, thereby achieving the purpose of conformality. The present invention first suppresses the halogen-active free radicals for a short time, and then sends them into the 3D NAND structure to etch the tungsten layer. Finally, the excess halogen-active free radicals are purged by a purge gas, and the process flow is cycled to achieve better process effects. The process is as follows: Figure 2 shown.

[0065] Since the concentration of halogen active radicals in the top area is higher, the tungsten layer in the top area of ​​the 3D NAND structure is easier to etch, and the thickness will be reduced more, which can improve the step coverage of the 3D NAND structure. At the same time, due to the high feeding process pressure of the halogen active radicals, driven by the process pressure, the halogen active radicals can diffuse to the bottom area, and the concentration gradient of the halogen active radicals gradually decreases from top to bottom, and the corresponding thickness thinning degree gradually decreases, thereby achieving a conformal effect. By diluting the concentration of halogen active radicals as much as possible and going through multiple cycles, it is possible to achieve a small amount of thinning multiple times, avoiding excessive etching and improving the step coverage of metal filling in the 3D NAND structure. The following is a detailed explanation.

[0066] like Figure 3 As shown, a method for processing a semiconductor structure includes:

[0067] Step S1, providing a processing device for a semiconductor structure.

[0068] like Figure 4 As shown, the processing equipment of the semiconductor structure includes:

[0069] Reaction chamber 41;

[0070] A base 42, which is arranged at the bottom of the reaction chamber and is used to carry the substrate w;

[0071] A gas shower head 43, which is disposed at the top of the reaction chamber 41 and is disposed opposite to the base 42;

[0072] A gas supply device 44 is connected to the gas inlet channel of the gas shower head 43 and the corresponding reaction gas source through corresponding gas pipelines, and supplies gas to the reaction chamber 41 through the gas shower head 43; wherein the gas supply device further comprises a remote plasma source 441, one end of which is connected to the processing gas source, and the remote plasma source 441 is used to excite the processing gas from the processing gas source into plasma;

[0073] The buffer tank 45 is disposed between the remote plasma source 441 and the gas shower head 43 , and is used to deliver the processing gas from the remote plasma source 441 to the reaction chamber 41 at a certain process pressure.

[0074] In some embodiments, the processing device further includes: a flow metering element 46 , which is disposed on a communication pipe between the remote plasma source 441 and the buffer tank 45 and is used to meter the amount of the processing gas flowing into the buffer tank 45 .

[0075] In some embodiments, the processing equipment further includes: a gas valve 47 , which is disposed at the outlet of the buffer tank 45 and is used to control the delivery of the pressurized gas in the buffer tank 45 .

[0076] Step S2, providing a substrate to be processed and placing it in the reaction chamber; the substrate to be processed includes a base layer arranged on a substrate, the base layer is provided with a plurality of openings, and the inner wall surfaces of the openings and the upper surface of the base layer are provided with a first metal layer.

[0077] The material of the substrate may be at least one of silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), and the like.

[0078] The base layer is a multilayer structure formed by stacking a plurality of stacked layers up and down. The more stacked layers there are, the higher the integration of the device is. The present invention does not limit the number of stacked layers. There is a gap between the upper and lower adjacent stacked layers. The process gas enters the gap through the opening of the base layer to fill it and form a first metal layer. In the process of filling the gap with the first metal layer, a first metal layer is also formed on the upper surface of the base layer (the surface on the top of the base layer) and the inner wall surface of the opening.

[0079] The material of the first metal layer may be at least one of tungsten, cobalt, molybdenum, ruthenium and rhodium.

[0080] The material of each stacked layer may be a silicon-containing material, for example, silicon nitride (Si3N4), silicon oxide (SiO2) or polysilicon. It is understood that the material of the stacked layer is not limited to the above, and the present invention is not limited thereto. The materials of each stacked layer may be the same or different. For example, in some embodiments, the base layer may be formed by stacking a plurality of silicon oxide layers up and down. In other embodiments, the base layer may be formed by alternating stacks of silicon nitride layers and silicon oxide layers, or by alternating stacks of silicon oxide layers and polysilicon layers.

[0081] In some embodiments, in order to prevent the process gas for forming the first metal layer from entering the base layer and causing contamination, a barrier layer is further formed between the surface of the base layer and the first metal layer. As an example, the barrier layer can be first formed on the surface of the base layer, and then the process gas for forming the first metal layer is introduced to form the first metal layer on the surface of the barrier layer.

[0082] The material of the barrier layer is TiN, TaN or Ta. The thickness of the barrier layer is in the range of 1 to 4 nm. The barrier layer can be deposited on the surface of the base layer by ALD, CVD, PVD or other deposition methods.

[0083] In some embodiments, the substrate to be processed further comprises: a second metal layer, which is disposed between the barrier layer and the first metal layer, and the resistivity of the first metal layer is smaller than that of the second metal layer. As an example, a barrier layer can be first formed on the surface of the base layer, and then a process gas for forming a second metal layer is introduced to form the second metal layer on the surface of the barrier layer, and then a process gas for forming a first metal layer is introduced to form the first metal layer on the surface of the second metal layer, and the function of the second metal layer is to make the first metal layer nucleate better.

[0084] The metal material of the second metal layer is at least one of tungsten, cobalt, molybdenum, ruthenium and rhodium. The thickness of the second metal layer ranges from 1 to 6 nm, and the second metal layer can be deposited on the surface of the barrier layer by ALD, CVD, PVD or other deposition methods.

[0085] In some embodiments, the first metal layer and the second metal layer are made of the same material. For example, the second metal layer is a tungsten seed crystal layer, and the first metal layer is a bulk tungsten layer.

[0086] In some embodiments, the first metal layer and the second metal layer are made of different materials. For example, the second metal layer is a ruthenium metal layer, and the first metal layer is a bulk tungsten layer.

[0087] The openings described herein generally have a high aspect ratio structure, with an aspect ratio greater than 3:1. The feature size in the 3D NAND structure is deep relative to the width, and it is easy for the top area of ​​the opening structure to be thicker than the bottom area due to the CVD parasitic effect. In this structure, it is difficult to achieve a conformal effect by simply etching the top area. Especially for the ALD deposited metal layer, which is thin, conventional etching methods can easily lead to excessive etching of the top area while the bottom area is not etched, and the thickness of the sidewalls of the opening is uneven.

[0088] Step S3, a gas-holding step: closing the gas valve and introducing a processing gas from a remote plasma source into the buffer tank; the processing gas contains halogen active free radicals.

[0089] The halogen active free radicals are active free radicals from fluorine-containing plasma or chlorine-containing plasma, for example, active free radicals from NF3 gas.

[0090] Since the thickness of the first metal layer is relatively thin, and the present invention needs to maintain the uniformity of its surface while etching the first metal layer of the side wall of the opening, the halogen active free radicals used for etching should be diluted as much as possible to avoid etching too fast or excessively. Therefore, the processing gas also includes a carrier gas as a dilution gas, and the carrier gas is an inert gas. For example, the inert gas can be argon or helium, but is not limited thereto. As an example, in the processing gas, the flow rate of the halogen active free radicals is 5sccm-100sccm. The flow rate of the carrier gas is 200sccm-5000sccm.

[0091] The gas valve connected to the gas shower head is closed, and the processing gas from the remote plasma source is continuously introduced into the buffer tank to hold the pressure until the pressure of the processing gas in the buffer tank reaches the set pressure. In some embodiments, the total amount of gas introduced into the buffer tank can be measured by a flow metering element, so that the pressure of the processing gas in the buffer tank reaches the set pressure, and then the introduction of the processing gas is stopped.

[0092] Step S4, gas supply step: introducing the processing gas into the reaction chamber at a first process pressure through a gas shower head, and the processing gas reacts with the first metal layer on the surface of the substrate to be processed to generate a gas product.

[0093] In the gas supply step, the gas supply time is 0.1s to 5s. The longer the gas supply time is, the more the thickness of the area where the processing gas can reach is reduced.

[0094] The first process pressure is the set pressure of the holding step, and the pressure can be 50 torr to 500 torr. Within this pressure range, since the process gas is quickly released into the reaction chamber at one time after being held in pressure in the buffer tank, the process gas can enter the bottom of the high aspect ratio structure to perform a process on the first metal layer at the bottom. The greater the first process pressure, the deeper the etching depth and the faster the etching rate. Under the first process pressure, the process gas can easily diffuse to the bottom area of ​​the device structure, and can etch the top area, middle area and bottom area of ​​the opening at the same time, and the etching thickness gradually decreases from top to bottom. The conformality of the side wall of the opening can be achieved by the holding pressure gas supply method of the present invention, such as Figure 5 shown.

[0095] If the tungsten layer is etched in a normal flow mode, that is, without holding the pressure, the process gas is introduced at a pressure similar to that of the deposition process. In the reaction chamber, the process gas diffuses into the device structure in a gradient due to different gas concentrations. Such a diffusion depth is relatively shallow, and it is difficult for the process gas to enter the 3D NAND structure with a high aspect ratio. If the required depth needs to be reached, it is generally achieved by setting a bias voltage, which undoubtedly increases the cost.

[0096] In the processing equipment of the present invention, although the instantaneous gas supply pressure through pressure holding is very large, usually several hundred Torr, since the volume of the reaction chamber is much larger than the volume of the buffer tank, after the gas is supplied, the pressure in the reaction chamber is generally several Torr or more than ten Torr, which is basically equivalent to the chamber pressure of the ALD equipment. Therefore, the processing equipment of the present invention can be conveniently integrated with the ALD equipment for use, reducing the process cost.

[0097] The present invention can control the etching depth and etching rate by adjusting the first process pressure and the gas supply time.

[0098] Step S5, a purge step: introducing a purge gas to discharge the gas product out of the reaction chamber.

[0099] The purge gas may be an inert gas such as argon or helium.

[0100] In some embodiments, the following steps can be cycled multiple times: a gas holding step, a gas supply step, and a purging step to avoid over-etching, so that the sidewalls of the opening have conformal features, so as to maintain the contour of the opening in subsequent wet etching and avoid over-etching of the sidewalls or residual tungsten layer.

[0101] In summary, the present invention is provided with a buffer tank for storing processing gas between the remote plasma source and the gas shower head of the ALD atomic layer deposition equipment, which can hold the pressure of the processing gas for etching and cleaning treatment, and then supply the processing gas with a certain pressure to the reaction chamber. Under the pressure drive, the processing gas is easy to diffuse to the bottom area of ​​the device structure. That is, after supplying the gas, the concentration of the processing gas in the top area, middle area and bottom area of ​​the opening gradually decreases, and the thinning thickness formed by etching also gradually decreases. The steps of holding the gas, supplying the gas, and purging are repeated for many times, so that the step coverage rate can reach 100% while maintaining the conformal characteristics of the structure. Furthermore, the present invention can avoid excessively fast etching of metals such as tungsten by diluting the halogen active free radicals as much as possible, quickly switching the gas source, and etching or flushing the structure.

[0102] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A semiconductor structure processing device, characterized in that: The equipment includes: Reaction chamber; A base, which is arranged at the bottom of the reaction chamber and is used to carry the substrate; A gas shower head, which is arranged at the top of the reaction chamber and is arranged opposite to the base; A gas supply device, connected to the gas inlet channel of the gas shower head through a pipeline, and supplies gas to the reaction chamber through the gas shower head; wherein the gas supply device includes a remote plasma source; A buffer tank is disposed between the remote plasma source and the gas shower head and is used to deliver the processing gas from the remote plasma source to the reaction chamber at a certain process pressure, wherein the processing gas contains halogen active free radicals.

2. The semiconductor structure processing equipment according to claim 1, characterized in that: The processing equipment further includes: a flow metering element, which is arranged on a communication pipeline between the remote plasma source and the buffer tank and is used to measure the amount of the processing gas flowing into the buffer tank.

3. The semiconductor structure processing equipment according to claim 1, characterized in that: The processing equipment further includes: a gas valve, which is arranged at the outlet of the buffer tank.

4. A method for processing a semiconductor structure, characterized in that: include: Providing the processing device according to claim 3; Providing a substrate to be processed and placing it in the reaction chamber; The substrate to be processed comprises a base layer arranged on a substrate, a plurality of openings are arranged on the base layer, and a first metal layer is arranged on the inner wall surfaces of the openings and the upper surface of the base layer; Gas holding step: closing the gas valve and introducing a treatment gas from a remote plasma source into the buffer tank; the treatment gas contains halogen active free radicals; Gas supply step: introducing the halogen active free radicals into the reaction chamber at a first process pressure through a gas shower head, wherein the halogen active free radicals react with the first metal layer on the surface of the substrate to be processed to generate gas products; Purging step: introducing a purge gas to discharge the gaseous product out of the reaction chamber.

5. The method for processing a semiconductor structure according to claim 4, wherein: The first process pressure is 50 torr to 500 torr.

6. The method for processing a semiconductor structure according to claim 4, wherein: The halogen active free radical is a fluorine-containing active free radical or a chlorine-containing active free radical.

7. The method for processing a semiconductor structure according to claim 4, wherein: The flow rate of the halogen active free radicals is 5 sccm-100 sccm.

8. The method for processing a semiconductor structure according to claim 7, wherein: The processing gas further includes a carrier gas, and the carrier gas is an inert gas.

9. The method for processing a semiconductor structure according to claim 8, wherein: The flow rate of the carrier gas is 200 sccm-5000 sccm.

10. The method for processing a semiconductor structure according to claim 4, wherein: In the gas supply step, the gas supply time is 0.1s to 5s.

11. The method for processing a semiconductor structure according to claim 4, wherein: Repeat the following steps multiple times: The steps include breath holding, air supply and purging.

12. The method for processing a semiconductor structure according to claim 4, wherein: The base layer is a multi-layer structure, and a first metal layer is formed between two adjacent upper and lower layers.

13. The method for processing a semiconductor structure according to claim 4 or 12, characterized in that: The substrate to be processed further comprises: a barrier layer, which is arranged between the surface of the base layer and the first metal layer.

14. The method for processing a semiconductor structure according to claim 13, wherein: The substrate to be processed further includes: a second metal layer, which is arranged between the barrier layer and the first metal layer, and the resistivity of the first metal layer is smaller than that of the second metal layer.

15. The method for processing a semiconductor structure according to claim 14, wherein: The metal material of the first metal layer and the second metal layer is at least one of tungsten, cobalt, molybdenum, ruthenium and rhodium, and the material of the first metal layer is the same as or different from that of the second metal layer.

16. The method for processing a semiconductor structure according to claim 4, wherein: The opening has a high aspect ratio structure, and the aspect ratio is greater than 3:1.

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