Apparatus and method for device mismatch measurement
By designing an adjustable series ring oscillator, the problem that the prior art cannot accurately distinguish and measure the global mismatch and local mismatch of semiconductor devices is solved, and the accurate measurement and distinction of these mismatches is achieved, and the stability of mismatch values is improved.
Patent Information
- Application Number
- CN202510214690.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-05-09
AI Technical Summary
The prior art cannot accurately distinguish and measure global mismatch and local mismatch in semiconductor devices, resulting in the inability to obtain accurate mismatch values.
A ring oscillator with adjustable series is designed to measure the mismatch value of the device by changing the series of the oscillator, and distinguish between global mismatch and local mismatch by analyzing the relationship between these values.
Accurate distinction and measurement of global mismatch and local mismatch are achieved, the corresponding oscillator series are determined, and the stability of mismatch values is improved.
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Figure CN119959722A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a device for measuring device mismatch. The present invention also relates to a method for measuring device mismatch. Background Art
[0002] Since process fluctuations can cause device mismatch, the traditional method of measuring mismatch is to use a large number of device arrays to perform single-tube DC testing. Figure 1 , which is a device array layout in an existing mismatch measurement method;
[0003] Figure 1 The multiple semiconductor devices 101 are arranged to form an array structure, the gates of the semiconductor devices 101 in the same row are connected to the same gate test line 102, the sources of the semiconductor devices 101 in the same column are connected to the same source test line 103, and the drains of the semiconductor devices 101 in the same column are connected to the same drain test line 104. By applying voltage to the selected gate test line 102, source test line 103 and drain test line 104, the test signal of the corresponding semiconductor device 101 can be obtained. In the single-tube DC test, the gate test line 102 will add a DC control signal, and the single-tube DC test can obtain the source-drain current Ids and threshold voltage (Vth) of the corresponding semiconductor device 101. Process fluctuations can cause semiconductor devices 101 at different positions to have different corresponding Ids or Vth under the same gate voltage and source-drain voltage, so device mismatch will occur. Device mismatch includes local mismatch and global mismatch. Local mismatch refers to the mismatch between different locations within a chip (die), and global mismatch refers to the mismatch between chips, wafers, or lots.
[0004] The existing method performs DC testing on logic devices, extracts process fluctuations through test data, and finally verifies the mismatch value by AC testing using a ring oscillator.
[0005] When the number of ring oscillators is different, the corresponding frequency of the AC test is also different. Based on existing experience, when the number of ring oscillators is less than 9, the test results include global mismatch and local mismatch; when the number of ring oscillators is greater than 25, due to the complementary local mismatch, only the global mismatch is reflected. For the 28nm process, the number of ring oscillators ≥ 20 reflects the global mismatch. Therefore, the existing methods cannot accurately distinguish between global mismatch and local mismatch, and cannot obtain the precise transition between global mismatch and local mismatch. Summary of the invention
[0006] The technical problem to be solved by the present invention is to provide a device for measuring device mismatch, which can distinguish between global mismatch and local mismatch. To this end, the present invention also provides a method for measuring device mismatch.
[0007] To solve the above technical problem, the device for device mismatch measurement provided by the present invention includes: a ring oscillator for providing an AC test signal.
[0008] The ring oscillator comprises n stages of inverters, the output end of the kth stage inverter is connected to the input end of the k+1th stage inverter, k and n are both integers and 1≤k≤n, and n is an odd number.
[0009] The input end of the first-stage inverter is connected to the output end of the i-th-stage inverter through a corresponding switch. When the switch corresponding to the i-th-stage inverter is turned on, an i-stage ring oscillator connected end to end is formed between the first-stage inverter and the i-th-stage inverter; i is an odd number selected from 3 to n, i has j selection values, the number of the switches is j, and j is an integer.
[0010] A further improvement is that the switch comprises a transmission gate.
[0011] A further improvement is that each of the switches is controlled by a corresponding selection signal and an inverted selection signal that is inverted with respect to the selection signal.
[0012] A further improvement is that it also includes: a first decoder, wherein the input end of the first decoder is connected to the m-bit input signal and the output end outputs j of the selection signals and j of the inverted selection signals.
[0013] A further improvement is that the first-stage inverter is implemented by a NAND gate, a first input terminal of the NAND gate is connected to a first enable signal, and a second input terminal of the NAND gate serves as an input terminal of the first-stage inverter.
[0014] A further improvement is that it further includes: a control module, wherein the control module is used to implement:
[0015] The m-bit input signal is controlled to select the corresponding switch to set the number of stages of the ring oscillator, and the ring oscillator of the selected number of stages is used to measure the mismatch value of the device.
[0016] The number of stages of the ring oscillator is changed in sequence to obtain a mismatch value corresponding to the number of stages of the ring oscillator.
[0017] A further improvement is that it further includes: an analysis module, wherein the analysis module is used to realize: distinguishing between global mismatch and local mismatch based on the relationship between mismatch values corresponding to the levels of the ring oscillator.
[0018] In order to solve the above technical problems, the present invention provides a method for measuring device mismatch, comprising:
[0019] A ring oscillator is provided to provide an AC test signal.
[0020] The ring oscillator comprises n stages of inverters, the output end of the kth stage inverter is connected to the input end of the k+1th stage inverter, k and n are both integers and 1≤k≤n, and n is an odd number.
[0021] The input end of the first-stage inverter is connected to the output end of the i-th-stage inverter through a corresponding switch. When the switch corresponding to the i-th-stage inverter is turned on, an i-stage ring oscillator connected end to end is formed between the first-stage inverter and the i-th-stage inverter; i is an odd number selected from 3 to n, i has j selection values, the number of the switches is j, and j is an integer.
[0022] The number of stages of the ring oscillator device is changed to measure mismatch values of the devices in sequence and obtain mismatch values corresponding to the number of stages of the ring oscillator.
[0023] The global mismatch and the local mismatch are distinguished according to the relationship between the mismatch values corresponding to the levels of the ring oscillator.
[0024] A further improvement is that the switch comprises a transmission gate.
[0025] A further improvement is that each of the switches is controlled by a corresponding selection signal and an inverted selection signal that is inverted with respect to the selection signal.
[0026] A further improvement is that the j selection signals and the j inverted selection signals are output from the output end of the first decoder, and the input end of the first decoder is connected to the m-bit input signal.
[0027] A further improvement is that the first-stage inverter is implemented by a NAND gate, a first input terminal of the NAND gate is connected to a first enable signal, and a second input terminal of the NAND gate serves as an input terminal of the first-stage inverter.
[0028] A further improvement is that the number of stages of the ring oscillator is set by controlling the m-bit input signal to select the corresponding switch.
[0029] A further improvement is that when the mismatch value measurement is performed, the first enable signal is enabled.
[0030] The present invention sets a ring oscillator used for providing an AC test signal for an AC test of a device mismatch as a structure with an adjustable order. In this way, during the mismatch value measurement process of the device, the order of the ring oscillator can be changed in sequence, so that the relationship between the order of the ring oscillator and the mismatch value can be obtained, so that the global mismatch and the local mismatch can be distinguished and the order of the ring oscillator corresponding to the global mismatch and the local mismatch can be determined, and the order at which the mismatch value tends to be more stable can be further determined. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0032] Figure 1 It is the device array layout in the existing mismatch measurement method;
[0033] Figure 2A is a circuit diagram of a ring oscillator in an apparatus for device mismatch measurement according to an embodiment of the present invention;
[0034] Figure 2B It is a structural schematic diagram of a first decoder of a ring oscillator in an apparatus for device mismatch measurement according to an embodiment of the present invention;
[0035] Figure 3 It is the trend chart of mismatch test as the number of stages increases in device mismatch measurement;
[0036] Figure 4 It is a diagram of Monte Carlo simulation results of different levels obtained by using the device for device mismatch measurement according to an embodiment of the present invention. DETAILED DESCRIPTION
[0037] like Figure 2A , which is a circuit diagram of a ring oscillator in an apparatus for device mismatch measurement according to an embodiment of the present invention; Figure 2B , which is a schematic diagram of the structure of the first decoder 203 of the ring oscillator in the device for device mismatch measurement according to an embodiment of the present invention; the device for device mismatch measurement according to an embodiment of the present invention includes: a ring oscillator for providing an AC test signal.
[0038] The ring oscillator comprises n-stage inverters 201 , the output end of the k-th stage inverter 201 is connected to the input end of the k+1-th stage inverter 201 , k and n are both integers and 1≤k≤n, and n is an odd number.
[0039] The input end of the first-stage inverter 201 is connected to the output end of the i-th-stage inverter 201 through the corresponding switch 202. When the switch 202 corresponding to the i-th-stage inverter 201 is turned on, an i-stage ring oscillator connected end to end is formed between the first-stage inverter 201 and the i-th-stage inverter 201; i is an odd number selected from 3 to n, i has j selection values, and the number of the switches 202 is j, where j is an integer. Figure 2A In the corresponding example, j is 4. In other embodiments, the specific value of j can be set as needed.
[0040] The switch 202 includes a transmission gate.
[0041] Each of the switches 202 is controlled by a corresponding selection signal Sel and an inverted selection signal Se1b that is inverted from the selection signal Sel. Figure 2A In the figure, the selection signals Sel and the inverted selection signals Selb corresponding to the four switches 202 are respectively followed by corresponding digits, which are: <0> 、Sel <1> 、Sel <2> and Sel <3> and the inverted selection signal Selb <0> , Selb <1> , Selb <2> and Selb <3> .
[0042] It also includes: a first decoder 203, wherein the input end of the first decoder 203 is connected to the m-bit input signal IN and the output end outputs j selection signals Sel and j inverted selection signals Selb. Figure 2A In the corresponding example, since j is 4, m can be set to 2, and the 2-bit input signals are IN <0> and IN <1> .
[0043] The first stage inverter 201 is implemented by a NAND gate 201a, the first input end of the NAND gate 201a is connected to the first enable signal ENB, and the second input end of the NAND gate 201a is used as the input end of the first stage inverter 201. It can be seen that when the first enable signal ENB is 1, the ring oscillator works, and the output end and the second input end of the NAND gate 201a are inverted, so at this time the NAND gate 201a is actually used as an inverter. When the first enable signal ENB is 0, the ring oscillator stops working.
[0044] It also includes: a control module, the control module is used to implement:
[0045] The m-bit input signal IN is controlled to select the corresponding switch 202 to set the number of stages of the ring oscillator, and the ring oscillator of the selected number of stages is used to measure the mismatch value of the device.
[0046] The number of stages of the ring oscillator is changed in sequence to obtain a mismatch value corresponding to the number of stages of the ring oscillator.
[0047] The method further comprises: an analysis module, wherein the analysis module is used to distinguish between global mismatch and local mismatch based on the relationship between mismatch values corresponding to the levels of the ring oscillator.
[0048] like Figure 3 As shown in the figure, it is a mismatch test trend chart with the increase of the number of stages in the device mismatch measurement; the data corresponding to the mark 301 is FF data, which contains local deviations, and the local deviations are the deviations between different positions inside the chip (die); the data corresponding to the mark 302 is FFG data, and the FFG data is global deviation data, and the FFG data does not include local variation. Global deviations include the deviations between dies, the deviations between wafers, and the deviations between lots. The data corresponding to the mark 302 is GMC+LMC data, GMC represents granular epoxy molding compound, and LMC represents liquid molding compound. From the data corresponding to the mark 302, it can be seen that as the number of stages of the ring oscillator increases, the local deviation will gradually decrease, that is, the mismatch value will decrease and tend to be stable, and stabilize to the value corresponding to FFG.
[0049] like Figure 4 As shown, it is a Monte Carlo simulation result diagram of different series obtained by using the device for device mismatch measurement of the embodiment of the present invention. Through the device for device mismatch measurement of the embodiment of the present invention, it is possible to implement device mismatch measurement on the selected ring oscillators of various series. When measuring device mismatch at each level of the ring oscillator, multiple devices, i.e. semiconductor devices, will be measured at the same time, and finally the corresponding device mismatch measurement value can be obtained by using the Monte Carlo simulation method. It can be seen from the data corresponding to the mark 304 that as the series increases, the local deviation value will gradually decrease, and after the series is greater than or equal to a certain value such as 18, the local deviation value is 0, so that the device mismatch only has a global mismatch, thereby realizing the distinction between global mismatch and local mismatch.
[0050] The embodiment of the present invention sets the ring oscillator used for providing an AC test signal for an AC test of a device mismatch as a structure with an adjustable order. In this way, during the mismatch value measurement process of the device, the order of the ring oscillator can be changed in sequence, so that the relationship between the order of the ring oscillator and the mismatch value can be obtained, so that the global mismatch and the local mismatch can be distinguished and the order of the ring oscillator corresponding to the global mismatch and the local mismatch can be determined, and the order at which the mismatch value is more stable can be further determined.
[0051] The method for device mismatch measurement provided by the present invention comprises:
[0052] A ring oscillator is provided to provide an AC test signal.
[0053] The ring oscillator comprises n-stage inverters 201 , the output end of the k-th stage inverter 201 is connected to the input end of the k+1-th stage inverter 201 , k and n are both integers and 1≤k≤n, and n is an odd number.
[0054] The input end of the first-stage inverter 201 is connected to the output end of the i-th-stage inverter 201 through the corresponding switch 202. When the switch 202 corresponding to the i-th-stage inverter 201 is turned on, an i-stage ring oscillator connected end to end is formed between the first-stage inverter 201 and the i-th-stage inverter 201; i is an odd number selected from 3 to n, i has j selection values, and the number of the switches 202 is j, where j is an integer. Figure 2A In the corresponding example, j is 4. In other embodiments, the specific value of j can be set as needed.
[0055] The switch 202 includes a transmission gate.
[0056] Each of the switches 202 is controlled by a corresponding selection signal Sel and an inverted selection signal Se1b that is inverted from the selection signal Sel. Figure 2A In the figure, the selection signals Sel and the inverted selection signals Selb corresponding to the four switches 202 are respectively followed by corresponding digits, which are: <0> 、Sel <1> 、Sel <2> and Sel <3> and the inverted selection signal Selb <0> , Selb <1> , Selb <2> and Selb <3> .
[0057] It also includes: a first decoder 203, wherein the input end of the first decoder 203 is connected to the m-bit input signal IN and the output end outputs j selection signals Sel and j inverted selection signals Selb. Figure 2A In the corresponding example, since j is 4, m can be set to 2, and the 2-bit input signals are IN <0> and IN <1> .
[0058] The first stage inverter 201 is implemented by a NAND gate 201a, the first input end of the NAND gate 201a is connected to the first enable signal ENB, and the second input end of the NAND gate 201a is used as the input end of the first stage inverter 201. It can be seen that when the first enable signal ENB is 1, the ring oscillator works, and the output end and the second input end of the NAND gate 201a are inverted, so at this time the NAND gate 201a is actually used as an inverter. When the first enable signal ENB is 0, the ring oscillator stops working.
[0059] The number of stages of the ring oscillator device is changed to measure mismatch values of the devices in sequence and obtain mismatch values corresponding to the number of stages of the ring oscillator.
[0060] The global mismatch and the local mismatch are distinguished according to the relationship between the mismatch values corresponding to the levels of the ring oscillator.
[0061] like Figure 3 As shown, as the number of ring oscillator stages increases, the mismatch value tends to be stable, the mismatch is reduced, and the final mismatch value is more conservative.
[0062] The embodiment of the present invention provides an oscillator circuit with different selectable levels, uses transmission gates as a fixed number of switches, selects inverters of different levels through a decoder, and then uses the Monte Carlo measurement method to intuitively analyze the data one by one. Not only can the number of levels of global mismatch and local mismatch be found level by level, but also the level with more stable mismatch value can be found.
[0063] The embodiment of the present invention selects different series for measurement row by row in an optional manner, and finally finds the mismatch value of the frequency system of the RO, ie, the ring oscillator, through the measurement results of different series. The Monte Carlo simulation results of different series are distinguished into global mismatch and local mismatch.
[0064] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. A device for measuring device mismatch, characterized in that: include: a ring oscillator for providing an AC test signal; The ring oscillator comprises n-stage inverters, the output end of the k-th stage inverter is connected to the input end of the k+1-th stage inverter, k and n are both integers and 1≤k≤n, and n is an odd number; The input end of the first-stage inverter is connected to the output end of the i-th-stage inverter through a corresponding switch, and when the switch corresponding to the i-th-stage inverter is turned on, an i-th-stage ring oscillator connected end to end is formed between the first-stage inverter and the i-th-stage inverter; i is an odd number selected from 3 to n, i has j selection values, the number of the switches is j, and j is an integer.
2. The device for device mismatch measurement according to claim 1, characterized in that: The switch includes a transmission gate.
3. The device for device mismatch measurement according to claim 2, characterized in that: Each of the switches is controlled by a corresponding selection signal and an inverted selection signal that is inverted from the selection signal.
4. The device for device mismatch measurement according to claim 3, characterized in that: Also includes: A first decoder, wherein the input terminal of the first decoder is connected to an m-bit input signal and the output terminal outputs j selection signals and j inverted selection signals.
5. The device for device mismatch measurement according to claim 1, characterized in that: The first-stage inverter is implemented by a NAND gate, a first input end of the NAND gate is connected to a first enable signal, and a second input end of the NAND gate serves as an input end of the first-stage inverter.
6. The device for device mismatch measurement according to claim 4, characterized in that: Also includes: A control module, wherein the control module is used to implement: Controlling the m-bit input signal to select the corresponding switch to set the number of stages of the ring oscillator, and using the ring oscillator of the selected number of stages to measure the mismatch value of the device; The number of stages of the ring oscillator is changed in sequence to obtain a mismatch value corresponding to the number of stages of the ring oscillator.
7. The device for device mismatch measurement according to claim 6, characterized in that: Also includes: An analysis module is used to realize: distinguishing global mismatch and local mismatch from the relationship between mismatch values corresponding to the number of stages of the ring oscillator.
8. A method for measuring device mismatch, characterized in that: include: A ring oscillator is provided for providing an AC test signal; The ring oscillator comprises n-stage inverters, the output end of the k-th stage inverter is connected to the input end of the k+1-th stage inverter, k and n are both integers and 1≤k≤n, and n is an odd number; The input end of the first-stage inverter is connected to the output end of the i-th-stage inverter through a corresponding switch, and when the switch corresponding to the i-th-stage inverter is turned on, an i-th-stage ring oscillator connected end to end is formed between the first-stage inverter and the i-th-stage inverter; i is an odd number selected from 3 to n, i has j selection values, the number of switches is j, and j is an integer; Changing the number of stages of the ring oscillator device to measure mismatch values of the devices in turn and obtaining mismatch values corresponding to the number of stages of the ring oscillator; The global mismatch and the local mismatch are distinguished according to the relationship between the mismatch values corresponding to the levels of the ring oscillator.
9. The method for device mismatch measurement according to claim 8, characterized in that: The switch includes a transmission gate.
10. The method for device mismatch measurement according to claim 9, characterized in that: Each of the switches is controlled by a corresponding selection signal and an inverted selection signal that is inverted from the selection signal.
11. The method for device mismatch measurement according to claim 10, characterized in that: The j selection signals and the j inverted selection signals are output from the output end of the first decoder, and the input end of the first decoder is connected to the m-bit input signal.
12. The method for device mismatch measurement according to claim 8, characterized in that: The first-stage inverter is implemented by a NAND gate, a first input end of the NAND gate is connected to a first enable signal, and a second input end of the NAND gate serves as an input end of the first-stage inverter.
13. The method for device mismatch measurement according to claim 11, characterized in that: The m-bit input signal is controlled to select the corresponding switch to set the number of stages of the ring oscillator.
14. The method for device mismatch measurement according to claim 12, characterized in that: When performing the mismatch value measurement, the first enable signal is enabled.