Transistor performance test method and transistor performance test system

Abstract

The invention provides a transistor performance test method and a transistor performance test system, and the method comprises the steps: obtaining a signal state of a test signal after a preset oscillation time period based on the test signal outputted by an even-stage ring oscillator; obtaining a performance deviation result of the transistor according to the signal state; if the signal state is that the high level is maintained, the performance deviation result is that the performance of the PMOS transistor is superior to that of the NMOS transistor, if the signal state is that the low level is maintained, the performance deviation result is that the performance of the NMOS transistor is superior to that of the PMOS transistor, and if the signal state is that the oscillation is maintained, the performance deviation result is that the performance of the PMOS transistor and the performance of the NMOS transistor are balanced. Therefore, the preparation technology of the transistor is adjusted based on the performance deviation result of the transistor, and the preparation yield of the transistor is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology and relates to a transistor performance tendency testing technology, and in particular to a transistor performance testing method and a transistor performance testing system. Background Art

[0002] In the manufacturing process of transistors, the performance of NMOS (N-type metal oxide semiconductor) tubes and PMOS (P-type metal oxide semiconductor) tubes obtained from the same batch, specifically, the switching speed of NMOS tubes and PMOS tubes, usually has differences. Taking silicon crystal as a transistor material as an example, since the mobility of its electrons is higher than the mobility of holes, the switching speed of NMOS tubes is faster and the delay time is shorter, that is, the performance of NMOS tubes is better than that of PMOS tubes. When designing chip circuits, in order to ensure the yield of the chip, it is usually necessary to ensure that the performance difference between NMOS tubes and PMOS tubes is within a certain range to reduce the difficulty of design. Based on this, in the actual production and manufacturing of transistors, it is usually necessary to perform performance tests on transistors to evaluate the performance characteristics of transistors.

[0003] In the prior art, the performance test of transistors is usually performed by generating an oscillation signal through a ring oscillator including an odd number of inverters to obtain a corresponding oscillation period based on the frequency of the oscillation signal, wherein each inverter includes a PMOS tube and an NMOS tube. Since the oscillation period can reflect the delay time of the inverter, the performance characteristics of the PMOS tube and the NMOS tube can be indirectly evaluated. However, since the oscillation period of the inverter module is affected by both the PMOS tube and the NMOS tube, the transistor performance characteristics obtained based on this method are actually the average performance status of the PMOS tube and the NMOS tube, and it is impossible to determine which of the NMOS tube and the PMOS tube has better performance, so it is difficult to make corresponding improvements and adjustments. Summary of the invention

[0004] The purpose of the present application is to provide a transistor performance testing method and a transistor performance testing system, which are used to solve the problem that in the existing transistor performance testing method, only the average performance status of PMOS tubes and NMOS tubes can be obtained, but the performance of NMOS tubes and PMOS tubes cannot be compared, which makes it difficult to improve and adjust the transistor.

[0005] In a first aspect, the present application provides a transistor performance test method, comprising: based on a test signal output by an even-numbered ring oscillator, obtaining a signal state of the test signal after a preset oscillation period;

[0006] According to the signal state, a performance bias result of the transistor is obtained; if the signal state is to maintain a high level, the performance bias result is that the performance of the PMOS tube is better than that of the NMOS tube; if the signal state is to maintain a low level, the performance bias result is that the performance of the NMOS tube is better than that of the PMOS tube; if the signal state is to maintain oscillation, the performance bias result is that the performance of the PMOS tube and the NMOS tube is balanced;

[0007] The even-numbered ring oscillator comprises an even number of inverting modules connected end to end, each of the inverting modules comprises a PMOS tube and an NMOS tube, and the time of the oscillation period is an integer multiple of the basic oscillation period.

[0008] In one embodiment of the present application, the even-numbered ring oscillator is connected to a conjugate pair of control signals;

[0009] The method for acquiring the test signal includes: setting the control signal to an initial level so that the even-numbered ring oscillator is in an initial state;

[0010] The control signal is set to a test level to put the even-numbered ring oscillator in a test state, and the even-numbered ring oscillator generates and outputs the test signal based on the initial state.

[0011] In one embodiment of the present application, the method for acquiring the signal status includes:

[0012] Acquire a first oscillation number of the test signal within a preset observation period, and if the first oscillation number of the test signal is greater than 0, then after the oscillation period, the signal state of the test signal is to maintain oscillation;

[0013] Otherwise, the voltage level of the test signal in the observation period is obtained; if the voltage level of the test signal is a high level, then after the oscillation period, the signal state of the test signal is to maintain a high level; if the voltage level of the test signal is a low level, then after the oscillation period, the signal state of the test signal is to maintain a low level;

[0014] The time of the observation period is not shorter than the basic oscillation period of the even-numbered ring oscillator, and the observation period is an adjacent period after the oscillation period.

[0015] In one embodiment of the present application, after obtaining the first oscillation number of the test signal within the preset observation period, the method further includes:

[0016] Obtaining the total number of oscillations of the test signal during the oscillation period and the observation period;

[0017] According to the total number of oscillations, the performance of the PMOS transistor and the NMOS transistor is quantitatively analyzed to obtain a quantitative performance result of the transistor;

[0018] The performance quantification result and the performance bias result are combined to serve as the performance test result of the transistor.

[0019] In a second aspect, the present application provides a transistor performance testing system, comprising:

[0020] an even-numbered ring oscillator for generating and outputting a test signal;

[0021] A signal display device, connected to the output end of the even-numbered ring oscillator, for obtaining the test signal;

[0022] The even-numbered ring oscillator comprises an even number of inverting modules connected end to end, and each of the inverting modules comprises a PMOS tube and an NMOS tube.

[0023] In one embodiment of the present application, the type of the inverting module is any one of a control inverting module and an oscillation inverting module, and the control inverting module is connected to the conjugate pair of the control signal, and is used to put the even-numbered ring oscillator in an initial state or a test state according to the control signal;

[0024] The even-numbered ring oscillator includes at least one control inversion module.

[0025] In one embodiment of the present application, the even-numbered ring oscillator includes two control inversion modules, namely a first control inversion module and a second control inversion module;

[0026] A first preset number of oscillation inversion modules are connected in series between the output end of the first control inversion module and the input end of the second control inversion module, and a second preset number of oscillation inversion modules are connected in series between the input end of the first control inversion module and the output end of the second control inversion module;

[0027] When the first preset number and the second preset number are both even numbers, the control signal is at an initial level, and the first control inverting module and the second control inverting module output the same signal; when the control signal is at a test level, the first control inverting module and the second control inverting module both output signals that are inverted from their corresponding input signals;

[0028] When the first preset number and the second preset number are both odd numbers, the control signal is at an initial level, the first control inversion module and the second control inversion module output opposite signals, the control signal is at a test level, and the first control inversion module and the second control inversion module both output signals that are inverted from their corresponding input signals.

[0029] In one embodiment of the present application, the first control inversion module and the second control inversion module both include:

[0030] A switch unit is connected between the high potential terminal and the ground terminal, the switch unit is connected to the conjugate pair of the control signal, the input end of the switch unit serves as the input end of the control inversion module, when the control signal is at an initial level, the switch unit does not output a signal, and when the control signal is at a test level, the switch unit outputs a signal that is inverted from the input signal;

[0031] A first PMOS tube, a source electrode connected to the high potential end, and a drain electrode connected to the output end of the switch unit;

[0032] A first NMOS tube, a source electrode connected to the ground terminal, and a drain electrode connected to the output terminal of the switch unit;

[0033] The drains of the first PMOS tube and the first NMOS tube are connected together as the output end of the control inversion module;

[0034] When the first preset number and the second preset number are both even numbers, in the first control inversion module and the second control inversion module, the gate of the first PMOS tube is connected to the conjugate signal of the control signal, and the gate of the first NMOS tube is connected to the ground terminal, or the gate of the first PMOS tube is connected to the high potential terminal, and the gate of the first NMOS tube is connected to the control signal;

[0035] When the first preset number and the second preset number are both odd numbers, in the first control inversion module, the gate of the first PMOS tube is connected to the conjugate signal of the control signal, and the gate of the first NMOS tube is connected to the ground end; in the second control inversion module, the gate of the first PMOS tube is connected to the high potential end, and the gate of the first NMOS tube is connected to the control signal.

[0036] In one embodiment of the present application, the switch unit includes:

[0037] A control PMOS tube, wherein the source is connected to the high potential terminal and the gate is connected to the control signal;

[0038] An input PMOS tube, whose source is connected to the drain of the control PMOS tube;

[0039] An input NMOS tube, a drain of which is connected to the drain of the input PMOS tube, and a gate of which is connected to the gate of the input PMOS tube;

[0040] A control NMOS tube, the drain of which is connected to the source of the input NMOS tube, the gate of which is connected to the conjugate signal of the control signal, and the source of which is connected to the ground terminal.

[0041] The gates of the input PMOS tube and the input NMOS tube are connected to serve as the input end of the switch unit, and the drains of the input PMOS tube and the input NMOS tube are connected to serve as the output end of the switch unit.

[0042] In one embodiment of the present application, the signal display device includes:

[0043] an oscilloscope, connected to the output end of the even-numbered ring oscillator, for displaying the signal state of the test signal;

[0044] And / or, a counter connected to the output end of the even-numbered ring oscillator, for obtaining the first oscillation number and the total oscillation number of the test signal.

[0045] As described above, the present application provides a transistor performance test method and a transistor performance test system, which accurately reflects the performance deviation of the transistor by obtaining the signal state of the test signal after the oscillation period, so as to improve and adjust the manufacturing process of the transistor, which is conducive to improving the production yield of the transistor. At the same time, the transistor performance test system provided by the present application generates a test signal through an even-numbered ring oscillator, thereby realizing the test of transistor performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A process corner diagram showing a transistor.

[0047] Figure 2 Shown is a flow chart of a transistor performance testing method described in an embodiment of the present application.

[0048] Figure 3 Shown is a schematic structural diagram of an even-numbered ring oscillator according to an embodiment of the present application.

[0049] Figure 4 Shown is a structural schematic diagram of a transistor performance testing system described in an embodiment of the present application.

[0050] Figure 5 Shown is a schematic diagram of the test results of the test signal described in the embodiment of the present application.

[0051] Figure 6 Shown is a flow chart of a signal status acquisition method described in an embodiment of the present application.

[0052] Figure 7 Shown is a flow chart of a method for obtaining performance quantification results of a transistor described in an embodiment of the present application.

[0053] Figure 8 Shown is a flow chart of a test signal acquisition method described in an embodiment of the present application.

[0054] Fig. 9 Shown is a structural schematic diagram of another even-numbered ring oscillator described in an embodiment of the present application.

[0055] Fig.10 Shown is a structural schematic diagram of an oscillation inversion module described in an embodiment of the present application.

[0056] Fig.11 Shown is a structural schematic diagram of a control inversion module described in an embodiment of the present application.

[0057] Fig.12 Shown is a structural schematic diagram of another control inversion module described in an embodiment of the present application.

[0058] Description of Reference Numerals

[0059] 30 Even-numbered Ring Oscillators

[0060] 31 Inverter module

[0061] 32 Control Inverter Module

[0062] 32' First control inverter module

[0063] 32” Second Control Inverter Module

[0064] 321 Switching unit

[0065] 3211 Control PMOS tube

[0066] 3212 Input PMOS tube

[0067] 3213 Input NMOS tube

[0068] 3214 Control NMOS tube

[0069] 322 First POMS Tube

[0070] 323 First NOMS Tube

[0071] 33 Oscillation inversion module

[0072] 331 Inverting PMOS tube

[0073] 332 Inverting NMOS tube

[0074] 40 Signal display device DETAILED DESCRIPTION

[0075] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0076] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application, and thus the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0077] like Figure 1As shown, it is a process angle diagram of a transistor, where TT (Typical-Typical), FF (Fast-Fast), SS (Slow-Slow), FS (Fast-Slow), and SF (Slow-Fast) are used to characterize the performance deviation of the transistor. The first letter represents the NMOS tube, and the second letter represents the PMOS tube. Generally speaking, the process angle of the transistor generally needs to be controlled within the TT range to avoid the risk of unstable chip circuit performance and even scrapping due to excessive differences in transistor delays. Specifically, for example, the different carrier mobility between the NMOS tube and the PMOS tube will lead to different switching speeds between the NMOS tube and the PMOS tube, resulting in inconsistent circuit response time, thereby affecting the performance and stability of the overall circuit. Based on this, transistors usually need to be tested for performance differences before mass production, such as differences in carrier mobility, to ensure that the performance of the transistor is within an appropriate range, and adjust the transistor manufacturing process based on the test results to improve the performance deviation of the transistor. The existing transistor performance test method usually obtains the oscillation frequency of the ring oscillator, thereby obtaining the oscillation period of each inverter in the ring oscillator to reflect the delay time of each inverter, and then evaluates the performance of the transistor. However, since the inverter includes a PMOS tube and an NMOS tube, the transistor performance obtained based on this method is actually the average performance of the PMOS tube and the NMOS tube, and cannot reflect the performance deviation of the PMOS tube and the NMOS tube, that is, it is impossible to confirm which of the PMOS tube and the NMOS tube has better performance, thereby increasing the difficulty of adjusting the transistor manufacturing process.

[0078] The following embodiments of the present application provide a transistor performance testing method and a transistor performance testing system, which obtain the accurate performance deviation of PMOS and NMOS tubes through the test signal of an even-numbered ring oscillator, thereby facilitating the adjustment of the transistor manufacturing process, thereby improving the production yield of the transistor, and having great industrial application value.

[0079] The following will describe in detail the principles and implementation methods of a transistor performance testing method and a transistor performance testing system of this embodiment in conjunction with the accompanying drawings, so that those skilled in the art can understand the transistor performance testing method and the transistor performance testing system described in this embodiment without creative work.

[0080] like Figure 2 As shown, this embodiment provides a transistor performance testing method for measuring the performance deviation of a transistor, specifically, comprising:

[0081] S100 , based on the test signal output by the even-numbered ring oscillator 30 , obtaining a signal state of the test signal after a preset oscillation period.

[0082] Among them, Figure 3 As shown, the even-numbered ring oscillator 30 includes an even number of inverting modules 31 connected end to end, that is, each inverting module 31 is connected in series to form a ring. Further, each inverting module 31 includes a PMOS tube and an NMOS tube.

[0083] It should be noted that the test signal output by the even-numbered ring oscillator 30 is generated based on the pulse signal. Specifically, the pulse wave is cyclically transmitted through each inverting module 31 inside the even-numbered ring oscillator 30, and the test signal is output at the output end. Based on the change of the test signal over time, the performance deviation of the PMOS tube and the NMOS tube can be determined.

[0084] The following will explain the principle and specific implementation method of how the change of the test signal over time reflects the performance deviation between the PMOS tube and the NMOS tube.

[0085] The even-numbered ring oscillator 30 includes an even number of inverting modules 31 connected end to end. For any inverting module 31, the signal output by the inverting module 31 is inverted an odd number of times and then re-input into the inverting module 31. The signal is the same as the signal input into the same inverting module 31 the last time, that is, the signal output by the inverting module 31 remains unchanged each time. Therefore, under ideal conditions, the test signal output by the even-numbered ring oscillator 30 is a constant pulse wave signal.

[0086] However, each inverting module 31 includes a PMOS tube and an NMOS tube, wherein, since the PMOS tube is turned on at a high level, the time required for the pulse wave to change from a low level to a high level when passing through the inverting module 31 is actually affected by the switching speed of the PMOS tube, that is, the rising edge time of the pulse wave after passing through the inverting module 31 is affected by the switching speed of the PMOS tube. The faster the switching speed of the PMOS tube, the shorter the rising edge time of the pulse wave after passing through the inverting module 31, and the earlier the time when the pulse wave is at a high level. Similarly, the NMOS tube is turned on at a low level, so the faster the switching speed of the NMOS tube, the shorter the falling edge time of the pulse wave after passing through the inverting module 31, and the earlier the time when the pulse wave is at a low level.

[0087] Based on this, if the performance of the PMOS tube is better, the rising edge time becomes shorter than the falling edge time after the pulse wave is transmitted through the reverse module, thereby extending the time when the pulse wave is at a high level, and the pulse wave will eventually converge to a high level after the cyclic transmission of the even-numbered ring oscillator 30. Similarly, if the performance of the NMOS tube is better, the pulse wave will eventually converge to a low level after the cyclic transmission of the even-numbered ring oscillator 30.

[0088] Furthermore, if the performance of the PMOS tube and the NMOS tube are relatively balanced, the extent to which the rising edge time and the falling edge time of the test signal are extended or shortened is substantially the same, and after cyclic transmission of the even-numbered ring oscillator 30, the pulse wave eventually keeps oscillating.

[0089] Therefore, by observing the test signal changing with time and finally converging to a high level / low level or maintaining oscillation, the performance deviation between the PMOS tube and the NMOS tube can be determined.

[0090] Furthermore, a signal state after a preset oscillation period is obtained to determine the performance deviation of the transistor.

[0091] Among them, the oscillation period is an integer multiple of the basic oscillation period. The basic oscillation period refers to the time required for the pulse wave signal to circulate once in the even-numbered ring oscillator 30, that is, the product of the time required for a single pulse wave signal and the number of inverting modules 31. The signal state of the test signal after the oscillation period is actually the signal state after multiple cycles in the even-numbered ring oscillator 30. Based on this, the signal state after the oscillation period is used to reflect the performance deviation of the transistor.

[0092] It should be noted that the specific duration of the oscillation period can be adjusted by technical personnel in this field according to actual needs. Generally speaking, the longer the oscillation period, the more times the pulse signal circulates in the even-numbered ring oscillator 30, and the more it can reflect the subtle deviations in transistor performance.

[0093] S200, obtaining a performance bias result of the transistor according to the signal state.

[0094] Specifically, if the signal state is to maintain a high level, the performance bias result is that the performance of the PMOS tube is better than that of the NMOS tube; if the signal state is to maintain a low level, the performance bias result is that the performance of the NMOS tube is better than that of the PMOS tube; if the signal state is to maintain oscillation, the performance bias result is that the performance of the PMOS tube and the NMOS tube is balanced.

[0095] It should be noted that those skilled in the art can set an appropriate oscillation period according to actual needs, and the performance bias result is that the performance of the PMOS tube and the NMOS tube is balanced, which means that the performance deviation between the PMOS tube and the NMOS tube is within the range that meets the actual use needs. Similarly, the performance bias result is that the performance of the PMOS tube is better than that of the NMOS tube, which means that the performance deviation between the PMOS tube and the NMOS tube exceeds the range that meets the actual use needs, and the performance of the PMOS tube is better; the performance bias result is that the performance of the NMOS tube is better than that of the PMOS tube, which means that the performance deviation between the PMOS tube and the NMOS tube exceeds the range that meets the actual use needs, and the performance of the NMOS tube is better.

[0096] Based on this, operators can adjust the manufacturing process of transistors or conduct mass production according to the performance deviation results to ensure that the performance deviation of transistors meets the actual use requirements, thereby improving the production yield of transistors. Furthermore, operators can also perform aging experiments on transistors to obtain the performance deviation of transistors after aging, so as to realize transistor aging monitoring.

[0097] It should be noted that in order to obtain the signal status of the test signal, such as Figure 4 As shown, the present application also provides a transistor performance test system for executing a transistor performance test method, wherein the transistor performance test system includes: an even-numbered ring oscillator 30 and a signal display device 40, wherein the even-numbered ring oscillator 30 is used to generate and output a test signal, and the signal display device 40 is connected to the output end of the even-numbered ring oscillator 30 for obtaining a test signal.

[0098] In some optional embodiments, the signal display device 40 includes an oscilloscope, which is connected to the output end of the even-numbered ring oscillator 30 to display the test signal through a waveform diagram, so that the operator can easily obtain the signal state of the test signal. Specifically, the test signal waveform after the oscillation period is found on the time axis of the waveform diagram to determine the performance deviation of the transistor and obtain the performance deviation result of the transistor.

[0099] like Figure 5 As shown in the figure, the test signal displayed by the oscilloscope is executed by the transistor performance test system provided by the present embodiment to perform the aforementioned transistor performance test method. The oscillation period is determined based on the actual use requirements, and the signal state of the subsequent test signal is obtained to obtain the performance bias result of the transistor. For example, if the oscillation period is Figure 5 If all time periods are shown in , then: Figure 5 The test results shown in rows 2-6 in the figure show that the performance of the corresponding transistors is balanced between the PMOS and NMOS transistors. Figure 5 The test results shown in rows 7-8 of the table show that the performance of the corresponding transistors is biased towards the PMOS transistor being better than that of the NMOS transistor. Figure 5 The test results shown in the first row of FIG. 8 show that the corresponding transistor performance bias result is that the performance of the NMOS tube is better than that of the PMOS tube.

[0100] In some other optional embodiments, the signal display device 40 also includes a counter, which is connected to the output end of the even-stage ring oscillator 30, and obtains the first oscillation number of the test signal after the oscillation period to obtain the signal state of the test signal, thereby determining the performance bias result of the transistor.

[0101] Specifically, Figure 6As shown, the signal status acquisition method includes:

[0102] S111, obtaining a first oscillation number of a test signal within a preset observation period.

[0103] Among them, the observation period is the adjacent period after the oscillation period. If the first oscillation number of the test signal in the observation period is greater than 0, it means that after the oscillation period, the test signal is still oscillating, that is, the signal state of the test signal is maintaining oscillation; otherwise, if the first oscillation number of the test signal in the observation period is 0, it means that after the oscillation period, the test signal no longer oscillates, that is, the signal state of the test signal is converging to a high level or a low level.

[0104] Furthermore, the time of the observation period is not shorter than the basic oscillation period of the even-numbered ring oscillator 30, so that the test signal completes at least one complete cycle in the even-numbered ring oscillator 30 after the oscillation period, so as to avoid the test signal having a large pulse width after multiple cycles of transmission, and the observation period is too short to cover a single pulse wave.

[0105] Exemplarily, the observation period is 1-2 times the basic oscillation period.

[0106] S112, when the first oscillation number of the test signal in the observation period is 0, obtaining the voltage level of the test signal in the observation period to obtain the performance bias result of the transistor based on the voltage level.

[0107] Specifically, if the voltage level of the test signal is a high level, then after the oscillation period, the test signal converges to a high level, that is, the signal state is to maintain a high level, and the performance bias result is that the performance of the PMOS tube is better than that of the NMOS tube; if the voltage level of the test signal is a low level, then after the oscillation period, the test signal converges to a low level, that is, the signal state is to maintain a low level, and the performance bias result is that the performance of the NMOS tube is better than that of the PMOS tube.

[0108] Exemplarily, by displaying the waveform of the test signal during the observation period on an oscilloscope, the voltage level of the test signal during the observation period can be obtained.

[0109] It should be noted that the performance bias results of transistors are used to qualitatively characterize the performance bias of transistors, that is, the performance bias results only characterize the advantages and disadvantages of PMOS and NMOS transistors, but cannot quantitatively reflect the performance bias of PMOS and NMOS transistors. Based on this, in order to further improve the accuracy of the obtained transistor performance bias, the transistor performance bias is quantitatively analyzed, thereby improving the accuracy of the adjustment of the transistor manufacturing process, such as Figure 7 As shown, after obtaining the first oscillation number of the test signal within the preset observation period, the method further includes:

[0110] S121, obtaining the total number of oscillations of the test signal during the oscillation period and the observation period.

[0111] It should be noted that, for ease of understanding, this embodiment places the step of obtaining the total number of oscillations after the step of obtaining the first number of oscillations within the observation period. However, in the actual execution process, the second number of oscillations within the oscillation period is usually obtained before the first number of oscillations within the observation period, and the sum of the first number of oscillations and the second number of oscillations is taken as the total number of oscillations.

[0112] S122, quantitatively analyzing the performance of the PMOS transistor and the NMOS transistor according to the total number of oscillations to obtain a quantitative performance result of the transistor.

[0113] Specifically, the performance deviation of the transistor leads to the convergence of the pulse signal, and the greater the deviation, the greater the change in pulse width after the pulse wave passes through the inverting module 31 each time, that is, the faster the speed of converging to the high level / low level, and the fewer the oscillation times of the test signal before convergence. Based on this, the performance deviation of the transistor is numerically characterized by the total number of oscillations, thereby obtaining the performance quantification result of the transistor.

[0114] Generally speaking, the greater the total number of oscillations, the more balanced the performance of the PMOS tube and the NMOS tube, that is, the total number of oscillations is inversely proportional to the balance of the transistor. Based on this, this embodiment exemplarily provides a method for quantitatively analyzing the performance of the PMOS tube and the NMOS tube, which is: the size of the transistor balance can be characterized by the inverse of the total number of oscillations.

[0115] S123, combining the performance quantification result and the performance bias result as the performance test result of the transistor.

[0116] Among them, through the performance bias results, it is possible to obtain whether the transistor meets the actual application requirements, and based on the performance quantification results, the crystal manufacturing process is accurately adjusted, which not only improves the production yield of transistor manufacturing, but also improves the adjustment efficiency of the transistor manufacturing process, thereby effectively reducing the cost of transistor manufacturing and facilitating the actual application of transistor manufacturing.

[0117] It should be noted that in order to improve the accuracy of transistor performance testing, it is usually necessary to ensure that the pulse signal used to generate the test signal has good symmetry, that is, the length of the rising edge time and the falling edge time are consistent, so as to avoid the difference in the rising edge time and the falling edge time itself affecting the accuracy of the test. Therefore, it is usually necessary to modulate the pulse signal, which makes it difficult to obtain the test signal and the operation is not convenient.

[0118] Based on this, in some optional implementations, in order to simplify the transistor performance test method described in this application, this application generates a test signal by self-triggering the even-numbered ring oscillator 30, specifically, as Figure 8 As shown, the method of obtaining the test signal includes:

[0119] S101 , setting the control signal to an initial level so that the even-numbered ring oscillator 30 is in an initial state.

[0120] The control signal is an external input signal for controlling the even-numbered ring oscillator 30 to start generating a test signal or stop generating a test signal. When the control signal is at an initial level, the even-numbered ring oscillator 30 does not generate a test signal and is in an initial state.

[0121] Specifically, each inversion module 31 in the even-numbered ring oscillator 30 is any one of a control inversion module 32 and an oscillation inversion module 33, wherein the control inversion module 32 is connected to the conjugate pair of the control signal, and is used to control whether the even-numbered ring oscillator 30 generates a test signal according to the control signal, and the even-numbered ring oscillator 30 includes at least one control inversion module 32. The oscillation inversion module 33 is used to invert the input signal and output it to the next module to form an oscillation in the even-numbered ring oscillator 30. Further, each control inversion module 32 and each oscillation inversion module 33 includes a PMOS tube and an NMOS tube.

[0122] In this embodiment, when the control signal is at the initial level, the control inversion module 32 continuously outputs the corresponding specific signal according to the control signal, so that the even-numbered ring oscillator 30 is in the initial state, and when the test starts, the control inversion module 32 is actually equivalent to the inversion module 31, that is, the output signal is inverted with its input signal. Based on this, the control inversion module 32 mutates the signal at the moment of starting the test, that is, it self-triggers a pulse signal, thereby causing the even-numbered ring oscillator 30 to generate a test signal.

[0123] For example, Fig. 9As shown in the figure, the inverting module 31 framed by the dotted line is the control inverting module 32 , and the remaining inverting modules 31 not framed by the dotted line are the oscillation inverting modules 33 . Specifically, the even-numbered ring oscillator 30 includes two control inversion modules 32, which are respectively used as a first control inversion module 32' and a second control inversion module 32", and a plurality of oscillation inversion modules 33. Since the inversion modules 31 in the even-numbered ring oscillator 30 are connected end to end, the output end of the first control inversion module 32' and the input end of the second control inversion module 32" are connected in series by a first preset number of oscillation inversion modules 33, and the input end of the first control inversion module 32' and the output end of the second control inversion module 32" are connected in series by a second preset number of oscillation inversion modules 33, so as to form a ring structure. It should be noted that since the number of inversion modules 31 in the even-numbered ring oscillator 30 is an even number, the number of oscillation inversion modules 33 is also an even number, that is, the first preset number and the second preset number are both even numbers, or the first preset number and the second preset number are both odd numbers.

[0124] When the first preset number and the second preset number are both even numbers and the control signal is at the initial level, the first control inversion module 32' and the second control inversion module 32" output the same signal. It should be noted that since the oscillation inversion module 33 always outputs a signal that is the inversion of its input signal, after passing through an even number of oscillation inversion modules 33, the final output signal is the same signal as the input signal. Based on this, the output signal of the first control inversion module 32' is input into the second control inversion module 32" through an even number of oscillation inversion modules 33, and the output signal of the second control inversion module 32" is input into the first control inversion module 32' through an even number of oscillation inversion modules 33, that is, the output signal of the first control inversion module 32' and the input signal of the second control inversion module 32" The input signal of the first control inverting module 32' is the same as the output signal of the second control inverting module 32". Since the output signals of the first control inverting module 32' and the second control inverting module 32" are the same when the control signal is at the initial level, that is, the input signal and output signal of the first control inverting module 32' and the input signal and output signal of the second control inverting module 32" are the same, when the test starts, the first control inverting module 32' and the second control inverting module 32" are equivalent to the inverting module 31, and the output signal is inverted with the input signal thereof. Therefore, the output signals of the first control inverting module 32' and the second control inverting module 32" must change suddenly, thereby self-triggering a pulse signal when the test starts, thereby realizing the generation of the test signal.

[0125] Similarly, when the first preset number and the second preset number are both odd numbers and the control signal is at the initial level, the first control inversion module 32' and the second control inversion module 32" output opposite signals. Among them, since after passing through an odd number of oscillation inversion modules 33, the final output signal is an opposite signal to the input signal, that is, the output signal of the first control inversion module 32' is opposite to the input signal of the second control inversion module 32", and the input signal of the first control inversion module 32' is opposite to the output signal of the second control inversion module 32". Since when the first control inversion module 32' and the second control inversion module 32" have opposite output signals when the control signal is at the initial level, that is, the input signal and output signal of the first control inversion module 32' are the same, and the input signal and output signal of the second control inversion module 32" are the same, when the test starts, the output signals of the first control inversion module 32' and the second control inversion module 32" must change suddenly, thereby self-triggering a pulse signal at the start of the test to achieve the generation of the test signal. For the specific principle, please refer to the above content when the first preset number and the second preset number are both even numbers, which will not be elaborated here.

[0126] For example, Fig.10 As shown, the oscillation inversion module 33 includes an inversion PMOS tube 331 and an inversion NMOS tube 332 between a high potential end and a ground end, wherein the source of the inversion PMOS tube 331 is connected to the high potential end, the source of the inversion NMOS tube 332 is connected to the ground end, and the gates of the inversion PMOS tube 331 and the inversion NMOS tube 332 are connected to serve as the input end of the oscillation inversion module 33, and the drains of the inversion PMOS tube 331 and the inversion NMOS tube 332 are connected to serve as the output end of the oscillation inversion module 33. When the input signal is at a high level, the inversion NMOS tube 332 is turned on, and its drain outputs a low level signal, that is, the oscillation inversion module 33 outputs a low level signal, and when the input signal is at a low level, the inversion PMOS tube 331 is turned on, and its drain outputs a high level signal, that is, the oscillation inversion module 33 outputs a high level signal, based on which, the oscillation inversion module 33 can invert and output the input signal. Of course, the oscillation inversion module 33 can also be other structures for inverting the input signal, as long as it includes a PMOS tube and an NMOS tube, and this embodiment does not make any specific limitation here.

[0127] S102 , setting the control signal to a test level so that the even-numbered ring oscillator 30 is in a test state, and the even-numbered ring oscillator 30 generates and outputs a test signal based on an initial state.

[0128] Specifically, when the control signal is at a test level, the control inverting module 32 is equivalent to an inverting module 31. At this time, the output signal is inverted with respect to its input signal, which is different from the specific signal output by the control inverting module 32 in the initial state, thereby causing a mutation on the basis of the initial state to form a pulse signal, thereby enabling the even-numbered ring oscillator 30 to generate and output a test signal based on the initial state, that is, the even-numbered ring oscillator 30 is in a test state.

[0129] In some optional implementations, the even-numbered ring oscillator 30 includes two control inversion modules 32, namely a first control inversion module 32' and a second control inversion module 32", and the specific structure and working principle of the first control inversion module 32' and the second control inversion module 32" are illustrated below.

[0130] like Fig.11 As shown, the control inversion module 32 includes: a switch unit 321 and a first PMOS tube and a first NMOS tube 323 connected to the output end of the switch unit 321 .

[0131] Among them, the switch unit 321 is connected between the high potential end and the ground end, and is connected to the conjugate pair of the control signal, and its input end is the input end of the control inversion module 32, which is used for disconnecting the switch unit 321 based on the control signal when the control signal is at the initial level, that is, not outputting the signal. When the control signal is at the test level, the switch unit 321 outputs a signal that is inverted to the input signal based on the control signal, thereby realizing that the control inversion module 32 is equivalent to an inversion module 31 only when the control signal is at the test level.

[0132] The first PMOS tube 322 and the first NMOS tube 323 are connected in series between the high potential end and the ground end. Specifically, the source of the first PMOS tube 322 is connected to the high potential end, and the drain is connected to the output end of the switch unit 321. The source of the first NMOS tube 323 is connected to the ground end, and the drain is connected to the output end of the switch unit 321. Further, the drains of the first PMOS tube 322 and the first NMOS tube 323 are connected together as the output end of the control inversion module 32. The first PMOS tube 322 and the first NMOS tube 323 are used to make the control inversion module 32 output a specific signal when the control signal is at the initial level, so that the even-numbered ring oscillator 30 is in the initial state.

[0133] For example, the initial level is a high level, the test level is a low level, and when the specific signal to be output is a high level signal, such as Fig.11As shown on the left side, the gate of the first PMOS tube 322 is connected to the conjugate signal of the control signal, and the gate of the first NMOS tube 323 is connected to the ground terminal. At this time, the first NMOS tube 323 is always cut off. When the control signal is at the initial level, the gate of the first PMOS tube 322 is connected to the low level and turned on, and the drain output of the first PMOS tube 322 is at a high level, that is, the control inversion module 32 outputs a high level signal. Of course, when the control signal is at the test level, the first PMOS tube 322 is also cut off. At this time, since the drain of the first PMOS tube 322 and the drain of the first NMOS tube 323 are both connected to the output end of the switch unit 321 and serve as the output end of the control inversion module 32, that is, the signal output by the control inversion module 32 is the signal output by the switch unit 321, thereby realizing that the control inversion module 32 is equivalent to an inversion module 31 only when the control signal is at the test level.

[0134] Similarly, when the specific signal to be output is a low-level signal, such as Fig.11 As shown on the right, the gate of the first PMOS tube 322 is connected to the high potential end, and the gate of the first NMOS tube 323 is connected to the control signal. The first PMOS tube 322 is always cut off. When the control signal is at the initial level, that is, at a high level, the first NMOS tube 323 is turned on, and the drain output of the first NMOS tube 323 is low level, that is, the control inverting module 32 outputs a low level signal. At the same time, when the control signal is at a test level, that is, at a low level, the first NMOS tube 323 is also cut off, and the signal output by the control inverting module 32 is the signal output by the switch unit 321, which is equivalent to an inverting module 31. For the specific working principle, please refer to the above-mentioned output of the specific signal at a high level, which will not be repeated here.

[0135] Based on this, when the even-numbered ring oscillator 30 includes a first control inversion module 32' and a second control inversion module 32", if the first preset number and the second preset number are both even numbers, when the control signal is at the initial level, the first control inversion module 32' and the second control inversion module 32" output the same signal, that is, in the first control inversion module 32' and the second control inversion module 32", the gate of the first PMOS tube 322 is connected to the conjugate signal of the control signal, and the gate of the first NMOS tube 323 is connected to the ground terminal, or the gate of the first PMOS tube 322 is connected to the high potential terminal, and the gate of the first NMOS tube 323 is connected to the control signal; if the first preset number and the second preset number are both odd numbers, the control signal When it is the initial level, the first control inversion module 32' and the second control inversion module 32" output opposite signals, the first control module outputs a high level signal, and the second control module outputs a low level signal, that is, in the first control inversion module 32', the gate of the first PMOS tube 322 is connected to the conjugate signal of the control signal, and the gates of the first NMOS tube 323 are connected to the ground terminal, and in the second control inversion module 32", the gates of the first PMOS tube 322 are connected to the high potential terminal, and the gates of the first NMOS tube 323 are connected to the control signal. Of course, the above is exemplarily explained for ease of understanding, and those skilled in the art should know that the first control module can actually output a low level signal and the second control module can output a high level signal.

[0136] It should be noted that, in the above example, the even-numbered ring oscillator 30 includes two control inversion modules 32, namely, a first control inversion module 32' and a second control inversion module 32", but the even-numbered ring oscillator 30 may also include more control inversion modules 32 or only one control inversion module 32. For the specific configuration method, please refer to the above content, which will not be specifically explained in this embodiment.

[0137] In a specific implementation manner, the even-numbered ring oscillator 30 provided in this embodiment includes a first control inverting module 32′ and a second control inverting module 32″, and the first preset number is equal to the second preset number, so as to improve the symmetry of the even-numbered ring oscillator 30, thereby improving the anti-interference ability of the even-numbered ring oscillator 30, and further improving the accuracy of the transistor performance deviation obtained by the test.

[0138] Based on this, the test signal acquisition method provided in this embodiment can make the even-numbered ring oscillator 30 self-trigger to form a pulse signal by setting the control signal, and then generate a test signal, avoiding manual debugging of the pulse signal, thereby simplifying the operation steps of the test method, which is beneficial to improving the test efficiency of the test method, and the pulse signal formed by self-triggering has good symmetry, which is beneficial to improving the accuracy and reliability of the test results, thereby achieving a better test effect. At the same time, this embodiment also provides an even-numbered ring oscillator 30, by controlling the inverting module 32, so that the even-numbered ring oscillator 30 is in an initial state or a test state according to the control signal, so that the even-numbered oscillator can self-trigger to generate a test signal without external input to achieve the test of transistor performance.

[0139] In order to facilitate those skilled in the art to further understand the even-numbered ring oscillator 30 of this embodiment, a structure of a switch unit 321 is exemplarily given below, and its working principle is specifically explained.

[0140] In a specific implementation, the initial level is a high level, and the test level is a low level, such as Fig.12 As shown, the switch unit 321 includes a control PMOS tube 3211, an input PMOS tube 3212, an input NMOS tube 3213, and a control NMOS tube 3214, which are sequentially connected between the high potential end and the ground end. Among them, the source of the control PMOS tube 3211 is connected to the high potential end, and the gate is connected to the control signal; the source of the input PMOS tube 3212 is connected to the drain of the control PMOS tube 3211; the drain of the input NMOS tube 3213 is connected to the drain of the input PMOS tube 3212, and the gate is connected to the gate of the input PMOS tube 3212; the drain of the control NMOS tube 3214 is connected to the source of the input NMOS tube 3213, the gate is connected to the conjugate signal of the control signal, and the source is connected to the ground end. Furthermore, the gates of the input PMOS tube 3212 and the input NMOS tube 3213 are connected to serve as the input end of the switch unit 321, that is, to control the input end of the inverting module 32, and the drains of the input PMOS tube 3212 and the input NMOS tube 3213 are connected to serve as the output end of the switch unit 321.

[0141] When the control signal is at the initial level, i.e., a high level, the control PMOS tube 3211 and the control NMOS tube 3214 are both cut off. At this time, no matter what signal is input to the input end of the switch unit 321 or whether a signal is input, the output end of the switch unit 321 actually has no output, which is equivalent to the switch unit 321 being disconnected. The control inverting module 32 outputs a specific signal based on the first PMOS tube 322 and the first NMOS tube 323.

[0142] When the control signal is at a test level, i.e., a low level, the control PMOS tube 3211 and the control NMOS tube 3214 are both turned on. At this time, when a high level signal is input to the input end of the switch unit 321, the input PMOS tube 3212 is cut off, the input NMOS tube 3213 is turned on, and the drain of the input NMOS tube 3213 outputs a low level signal, i.e., the output end of the switch unit 321 outputs a low level signal. When a low level signal is input to the input end of the switch unit 321, the input NMOS tube 3213 is cut off, the input PMOS tube 3212 is turned on, and the drain of the input PMOS tube 3212 outputs a high level signal, i.e., the output end of the switch unit 321 outputs a high level signal, thereby realizing that the control inverting module 32 is equivalent to an inverting module 31 only when the control signal is at a test level.

[0143] It should be noted that the above is an exemplary description of the structure of the switch unit 321 described in this embodiment. According to the actual application requirements, the switch unit 321 can also be other controllable inverting structures, as long as it is disconnected when the control signal is at the initial level and is equivalent to an inverting module 31 when the control signal is at the test level. This embodiment does not make any specific restrictions here.

[0144] In summary, the transistor performance test method provided by the present application obtains the signal state of the test signal after the oscillation period to determine the performance deviation of the PMOS tube and the NMOS tube, so that the operator can accurately obtain the performance deviation of the transistor, and then adjust the manufacturing process of the transistor to improve the production yield of the transistor, which has a high industrial application value. At the same time, the present application also provides a transistor performance test system, which generates a test signal through an even-level ring oscillator 30 to realize the performance test of the PMOS tube and the NMOS tube, so as to determine the performance deviation of the transistor.

[0145] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0146] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A transistor performance testing method, characterized in that: include: Based on the test signal output by the even-numbered ring oscillator, obtaining a signal state of the test signal after a preset oscillation period; According to the signal state, a performance bias result of the transistor is obtained; if the signal state is to maintain a high level, the performance bias result is that the performance of the PMOS tube is better than that of the NMOS tube; if the signal state is to maintain a low level, the performance bias result is that the performance of the NMOS tube is better than that of the PMOS tube; if the signal state is to maintain oscillation, the performance bias result is that the performance of the PMOS tube and the NMOS tube is balanced; The even-numbered ring oscillator comprises an even number of inverting modules connected end to end, each of the inverting modules comprises a PMOS tube and an NMOS tube, and the time of the oscillation period is an integer multiple of the basic oscillation period.

2. The method according to claim 1, characterized in that The even-numbered ring oscillators are connected to the conjugate pairs of control signals; The method for acquiring the test signal includes: setting the control signal to an initial level so that the even-numbered ring oscillator is in an initial state; The control signal is set to a test level to put the even-numbered ring oscillator in a test state, and the even-numbered ring oscillator generates and outputs the test signal based on the initial state.

3. The method according to claim 1, characterized in that The method for obtaining the signal status includes: Acquire a first oscillation number of the test signal within a preset observation period, and if the first oscillation number of the test signal is greater than 0, then after the oscillation period, the signal state of the test signal is to maintain oscillation; Otherwise, the voltage level of the test signal in the observation period is obtained; if the voltage level of the test signal is a high level, then after the oscillation period, the signal state of the test signal is to maintain a high level; if the voltage level of the test signal is a low level, then after the oscillation period, the signal state of the test signal is to maintain a low level; The time of the observation period is not shorter than the basic oscillation period of the even-numbered ring oscillator, and the observation period is an adjacent period after the oscillation period.

4. The method according to claim 3, characterized in that After obtaining the first oscillation number of the test signal within the preset observation period, the method further includes: Obtaining the total number of oscillations of the test signal during the oscillation period and the observation period; According to the total number of oscillations, the performance of the PMOS transistor and the NMOS transistor is quantitatively analyzed to obtain a quantitative performance result of the transistor; The performance quantification result and the performance bias result are combined to serve as the performance test result of the transistor.

5. A transistor performance test system, characterized in that: include: An even-numbered ring oscillator for generating and outputting a test signal; A signal display device, connected to the output end of the even-numbered ring oscillator, for obtaining the test signal; The even-numbered ring oscillator comprises an even number of inverting modules connected end to end, and each of the inverting modules comprises a PMOS tube and an NMOS tube.

6. The system according to claim 5, characterized in that The type of the inversion module is any one of a control inversion module and an oscillation inversion module, and the control inversion module is connected to the conjugate pair of the control signal, and is used to put the even-numbered ring oscillator in an initial state or a test state according to the control signal; The even-numbered ring oscillator includes at least one control inversion module.

7. The system according to claim 6, characterized in that The even-numbered ring oscillator comprises two control inversion modules, namely a first control inversion module and a second control inversion module; A first preset number of oscillation inversion modules are connected in series between the output end of the first control inversion module and the input end of the second control inversion module, and a second preset number of oscillation inversion modules are connected in series between the input end of the first control inversion module and the output end of the second control inversion module; When the first preset number and the second preset number are both even numbers, the control signal is at an initial level, and the first control inverting module and the second control inverting module output the same signal; when the control signal is at a test level, the first control inverting module and the second control inverting module both output signals that are inverted from their corresponding input signals; When the first preset number and the second preset number are both odd numbers, the control signal is at an initial level, the first control inversion module and the second control inversion module output opposite signals, the control signal is at a test level, and the first control inversion module and the second control inversion module both output signals that are inverted from their corresponding input signals.

8. The system according to claim 7, characterized in that The first control inverting module and the second control inverting module both include: A switch unit is connected between the high potential terminal and the ground terminal, the switch unit is connected to the conjugate pair of the control signal, the input end of the switch unit serves as the input end of the control inversion module, when the control signal is at an initial level, the switch unit does not output a signal, and when the control signal is at a test level, the switch unit outputs a signal that is inverted from the input signal; A first PMOS tube, a source electrode connected to the high potential end, and a drain electrode connected to the output end of the switch unit; A first NMOS tube, a source electrode connected to the ground terminal, and a drain electrode connected to the output terminal of the switch unit; The drains of the first PMOS tube and the first NMOS tube are connected together as the output end of the control inversion module; When the first preset number and the second preset number are both even numbers, in the first control inversion module and the second control inversion module, the gate of the first PMOS tube is connected to the conjugate signal of the control signal, and the gate of the first NMOS tube is connected to the ground terminal, or the gate of the first PMOS tube is connected to the high potential terminal, and the gate of the first NMOS tube is connected to the control signal; When the first preset number and the second preset number are both odd numbers, in the first control inversion module, the gate of the first PMOS tube is connected to the conjugate signal of the control signal, and the gate of the first NMOS tube is connected to the ground end; in the second control inversion module, the gate of the first PMOS tube is connected to the high potential end, and the gate of the first NMOS tube is connected to the control signal.

9. The system according to claim 8, characterized in that The switch unit comprises: A control PMOS tube, wherein the source is connected to the high potential terminal and the gate is connected to the control signal; An input PMOS tube, whose source is connected to the drain of the control PMOS tube; An input NMOS tube, a drain of which is connected to the drain of the input PMOS tube, and a gate of which is connected to the gate of the input PMOS tube; A control NMOS tube, the drain of which is connected to the source of the input NMOS tube, the gate of which is connected to the conjugate signal of the control signal, and the source of which is connected to the ground terminal. The gates of the input PMOS tube and the input NMOS tube are connected to serve as the input end of the switch unit, and the drains of the input PMOS tube and the input NMOS tube are connected to serve as the output end of the switch unit.

10. The system according to claim 5, characterized in that The signal display device comprises: an oscilloscope, connected to the output end of the even-numbered ring oscillator, for displaying the signal state of the test signal; And / or, a counter connected to the output end of the even-numbered ring oscillator, for obtaining the first oscillation number and the total oscillation number of the test signal.

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