Direct-current voltage nonlinearity calibrator

Abstract

The invention discloses a direct-current voltage nonlinearity calibrator which comprises a main control module, nine full-suspension voltage source modules FVSM, an internal zero detector and a constant-temperature system. The nine FVSM are respectively numbered as No. 0 to No. 8 according to different output voltages, each FVSM outputs a fixed voltage value, and the nine FVSM outputs various voltage values after being connected in series and superposed; when the calibrator outputs 0V, only the output positive electrode and the output negative electrode need to be short-circuited, and an FVSM does not need to participate; the FVSMs are connected in series and superposed, so that a plurality of different voltage values are generated through permutation and combination; and each FVSM is leveled by the internal zero detector, so that the uniformity among the FVSM is ensured, and the nonlinearity index of the output voltage of the calibrator is ensured. According to the invention, nine different voltage level FVSMs are connected in series and superposed to output various voltage values, and high-linearity output is generated, so that the voltage can be accurately calibrated; and besides, 1 / f noise can be greatly reduced, so that the nonlinearity index of the output voltage of the calibrator is ensured within a certain calibration period.

Description

Technical Field

[0001] The invention relates to a direct current voltage nonlinearity calibrator, belonging to the technical field of direct current voltage nonlinearity calibration. Background Art

[0002] Nonlinearity (INL) is an important indicator for ultra-high performance integrated circuit ADCs and ultra-high performance digital multimeters (DMMs). In the latest high performance integrated circuit ADCs, the nonlinearity indicator is better than ±1ppm. In an 8.5-digit digital multimeter, the nonlinearity indicator can reach ±0.1ppm using discrete device ADCs.

[0003] When developing high-performance integrated circuit ADCs and ultra-high-performance digital multimeters, a calibrator with nonlinearity indicators better than the R&D products is needed to accurately measure and calibrate the nonlinear performance of the R&D products. When the calibrator performance is 4 times better than the measured product, the measured product can be calibrated.

[0004] When using a calibrator to calibrate a multimeter, the calibrator outputs multiple high-linearity DC voltage values ​​(such as 1V, 2V, 3V...10V) in sequence, and then the multimeter is used to detect the above DC voltage values ​​in sequence. By measuring multiple DC voltage values, the nonlinearity of the multimeter is evaluated. Therefore, in order to improve the accuracy of the calibrator, it is necessary to output a high-linearity DC voltage value, and the output DC voltage value must be stable within a certain measurement time.

[0005] There are several ways to calibrate DC voltage nonlinearity: The KVD resistor divider method has an INL of about ±0.2ppm. It requires complex calibration before use and cannot output voltage directly. It needs to be used in conjunction with an external voltage source and requires complete manual operation. A dedicated multimeter calibrator, with an INL of about ±0.2ppm, can directly output any voltage, and is easy to use, but its INL performance does not exceed that of an eight-and-a-half-digit multimeter; The audio analyzer method has an INL of about ±1ppm and outputs a standard sine wave. It is a low-frequency AC method for indirect INL measurement. It can be used for integrated circuit ADCs with relatively high acquisition speeds, but is not suitable for eight-and-a-half-digit multimeters that acquire DC voltages. "Golden Product" calibration method, with its own INL < ±0.1ppm. This method is that the company selects a meter with the best nonlinearity from its highest performance 8.5-digit multimeter products and uses it as a comparison benchmark. It is called a "golden product", but it cannot directly output voltage; Saturated battery method, INL>±0.1ppm, standard saturated battery has high maintenance cost, high temperature requirement, and each battery has a fixed output of 1V. Only 1-10 points can be measured in series within the ±10V range. There are too few calibration points and the calibration curve is rough. The Josephson junction quantum voltage standard method has a performance of up to 0.001ppm, but it is too expensive, complicated to maintain, and inconvenient to use. It is difficult to use it as a national standard and for corporate research and development.

[0006] The above DC voltage nonlinearity calibration methods cannot meet the requirements for the calibration of ultra-high performance digital multimeters. A DC voltage nonlinearity calibrator that meets the requirements needs to solve two key problems: First: Produce high linearity output with INL < ±0.05ppm; If a digital-to-analog converter (DAC) is used to generate a voltage signal, the nonlinearity of the DAC itself is much greater than ±0.1ppm. To calibrate the DAC, an external high-performance DMM is needed to ensure the INL of the DAC, which leads to a loop. Therefore, the DAC cannot be used directly for output, and solutions such as KVD cannot meet the requirements. A new method is needed to generate a highly linear DC voltage.

[0007] Second: Eliminate the effects of temperature and 1 / f noise to maintain constant INL performance within the specified calibration time; Approximately calculated with a 10V output range, INL < ± ​​0.05ppm, the corresponding voltage fluctuation is < 1uV, peak-to-peak. It is estimated that under normal circumstances, it takes 1000 seconds to calibrate the external device in full range (8.5-digit DMM measures one point every 5 seconds, and the ± 10V range can measure 200 points).

[0008] Even if the calibration instrument has been internally calibrated to be completely linear, the output voltage of the calibration instrument will still fluctuate during 1000 seconds. The reasons are: the internal temperature change of the instrument during this period causes the temperature drift and thermoelectric potential change of the reference circuit and the amplifier circuit; the 1 / f noise of the reference component and the amplifier circuit itself.

[0009] The high-performance reference element (ADR1399 chip) has its own heating element to achieve constant temperature. After the heating is turned on, its typical temperature drift is 0.2ppm / ℃ (the value is relative to its output 7V, and the actual output of each reference after proportional conversion is less than 7V). Adding an external thermostat to it and stabilizing it to 0.01℃ can reduce its temperature drift to 0.0025ppm. The temperature drift of the high-performance self-zeroing op amp (MAX44251) can be 5nV / ℃, and no additional thermostat is required. Therefore, the instrument only needs to perform constant temperature control on the internal key circuits. The calibrator needs to use low thermal potential connections, and symmetrical connections are used to eliminate thermal potential at different metal connections (copper gold-plated copper connected to copper gold-plated copper). After these measures, the impact of temperature fluctuations is controlled to below 0.005ppm.

[0010] At this time, the factor affecting the output fluctuation is the 1 / f noise of the system. Under normal circumstances, the voltage fluctuates by 1uVpp within 1000 seconds, and the equivalent 1 / f noise at 0.1-10Hz is 460nVpp (0.46uVpp).

[0011] Therefore, the total 1 / f noise of the entire output voltage path needs to be controlled within this range.

[0012] In summary, the prior art obviously has inconveniences and defects in practical use, so it is necessary to improve it. Summary of the invention

[0013] In view of the deficiencies in the background technology, the present invention provides a DC voltage nonlinearity calibrator, which outputs a variety of voltage values ​​after superimposing 9 different voltage level FVSMs in series, thereby generating a high linearity output, thereby being able to accurately calibrate the voltage; in addition, it can greatly reduce 1 / f noise, thereby ensuring that the nonlinearity index of the calibrator output voltage is guaranteed within a certain calibration period.

[0014] In order to solve the above technical problems, the present invention adopts the following technical solutions: A DC voltage nonlinearity calibrator, comprising a main control module, 9 fully suspended voltage source modules FVSM, an internal zero detector and a constant temperature system; The main control module includes a main CPU, a human-machine interface and a USB communication interface; The 9 FVSMs are numbered from 0 to 8 according to their output voltages. Each FVSM outputs a fixed voltage value. The 9 FVSMs are connected in series and stacked to output multiple voltage values. The output voltage values ​​of the 9 FVSMs are as follows: No. 0 outputs 0.05V; No. 1 outputs 0.05V; No. 2 outputs 0.1V; No. 3 outputs 0.2V; No. 4 outputs 0.4V; No. 5 outputs 0.8V; No. 6 outputs 1.6V; No. 7 outputs 3.2V; No. 8 outputs 6.4V; FVSM No. 0 is only used for leveling and not for output. When the calibrator outputs 0V, it only needs to short-circuit the positive and negative poles of the output without the involvement of FVSM. FVSMs are connected in series and stacked to generate a variety of different voltage values. The internal zero detector levels each FVSM to ensure uniformity between the FVSMs, thereby ensuring the nonlinearity index of the calibrator output voltage.

[0015] Furthermore, the internal zero detector mainly includes a voltage measurement circuit with a very small range, high resolution and very low 1 / f noise; when the internal zero detector does not meet the requirements, a high-performance external zero detector is connected through the external zero detector interface of the calibrator to complete the voltage leveling of each FVSM, and the leveling methods of the external zero detector and the internal zero detector are exactly the same.

[0016] Furthermore, when the self-leveling process is performed, the process is fully automatically controlled by the main control module and includes the following steps: Step 1: disconnect all the contacts of the relays inside the calibrator, and preheat the calibrator through the constant temperature system to keep the temperature constant; Step 2: short-circuit the positive and negative electrodes of the zero detector, and disconnect the positive and negative electrodes after clearing the zero detector; Step 3: Short-circuit the negative poles of FVSM No. 0 and No. 1, connect the positive pole of FVSM No. 0 to the negative input of the zero detector, connect the positive pole of FVSM No. 1 to the positive input of the zero detector, and do not make any connection to other FVSMs; Step 4: If the difference between the output voltages of the No. 0 and No. 1 FVSMs measured by the zero detector is less than 10nV, it is considered that the output voltages of the No. 0 and No. 1 FVSMs are balanced. If it is greater than 10nV, the main CPU of the main control module sends an instruction to the No. 1 FVSM to fine-tune its output voltage until the value measured by the zero detector falls within the set range. Step 5: Disconnect all internal connections of the calibrator; Step 6, short-circuit the positive and negative poles of the zero checker again, reset the zero checker and disconnect the positive and negative poles; Step seven, from No. 0 to No. n, the positive output of each FVSM is connected to the negative output of the one higher than it, so that No. 0 to No. n FVSM are connected in series, the negative output of No. 0 is short-circuited with the negative pole of No. n+1 FVSM, the positive output of No. n is connected to the negative pole of the zero detector, and the positive output of No. n+1 is connected to the positive pole of the zero detector, n=1,2...7; use the zero detector to level the No. n+1 FVSM until all FVSMs are leveled.

[0017] Furthermore, the zero gauge has the function of exchanging positive and negative poles. During the leveling process, when the FVSM is connected to the zero gauge, the positive and negative poles of the zero gauge are exchanged with the connection with the FVSM, and the positive and negative directions are changed to perform secondary leveling, thereby further improving the leveling accuracy.

[0018] Furthermore, each FVSM includes a power supply module, a reference module, a DAC fine-tuning module, an addition operational amplifier circuit and an inversion operational amplifier circuit, a constant internal resistance output circuit, a CPU and a communication module.

[0019] Furthermore, the reference module includes a reference circuit, which includes 16 ADR1399 chips stacked in parallel, and after the 16 chips are stacked, the 1 / f noise is reduced to 1 / 4 of that of a single chip; Increase the current of the ADR1399 chip to 12mA to reduce the 1 / f noise to 1 / 2 of the default current (3mA); The reference module adds an RC low-pass filter circuit with a cutoff frequency of 0.1Hz to filter out the high-frequency components in the reference voltage; the 1 / f noise corner frequency of the ADR1399 chip is about 1Hz, and filtering out the part above 0.1Hz can reduce the 1 / f noise by more than 1 / 2.

[0020] Furthermore, the DAC fine-tuning module includes a 16-bit DAC fine-tuning voltage circuit, the DAC output range is ±10V, the DAC output resolution is 0.3mV, and the DAC fine-tuning voltage circuit reduces the DAC output range by 3000 times, so that the adjustment voltage resolution of the fine-tuning module is 100nV; After the adder in the DAC fine-tuning voltage circuit performs calculations, the voltage resolution will be reduced by 20 times again, so the output voltage resolution of the fine-tuning module is 5nV, thereby achieving precise adjustment of each level of FVSM.

[0021] Furthermore, the main control CPU sends instructions to the FVSM, and through the constant internal resistance output circuit, ensures that no matter how many FVSMs are connected in series, the total output internal resistance is a fixed value of 8R; The constant internal resistance output circuit includes a multi-channel parallel circuit composed of 16 operational amplifiers connected in parallel and an output impedance adjustment circuit. The multi-channel parallel circuit reduces the output impedance and reduces the internal resistance difference between each FVSM. The parallel output internal resistance of the 16 operational amplifiers in the multi-channel parallel circuit is R; The output impedance adjustment circuit includes 7 adjustment resistors with different resistance values, which are: 7R, 3R, 5R / 3, R, 3R / 5, R / 3, R / 7. Each adjustment resistor is connected to a magnetic latching relay. When the switch of the magnetic latching relay is closed, the adjustment resistor connected in series with it is connected to the output circuit. An adjustment resistor is selected by the magnetic latching relay to be connected to the output circuit and connected in series with the parallel output internal resistance. The adjustment resistor connected to the magnetic latching relay in each FVSM is connected in series with the parallel output internal resistance to serve as a single FVSM output internal resistance, and the other adjustment resistors in the FVSM are in an open circuit state; When there are n FVSMs connected in series, the output resistance of a single FVSM needs to be adjusted to 8R / n. At this time, under the control of the magnetic latching relay, the resistance of the adjustment resistor in series with the parallel output internal resistance is 8R / nR, thereby satisfying the total output resistance of the fixed value of 8R.

[0022] Furthermore, the nine FVSMs, the internal zero detector, the external zero detector and the voltage output interface are interconnected via a magnetic latching relay connection matrix; the magnetic latching relays are used inside the connection matrix.

[0023] Furthermore, the connection matrix has three main paths, namely MainPath+, MainPath-, and MainPath0; each FVSM output has three connection points: a positive pole point VoP, a negative pole point VoN, and a cascade point VoC; The positive electrode interface of the voltage output interface is connected to MainPath+ through relay S01, the positive electrode interface of the voltage output interface is also connected to MainPath0 through relay S02, the negative electrode interface of the voltage output interface is connected to MainPath+ through relay S03, and the negative electrode interface of the voltage output interface is also connected to MainPath0 through relay S04; The positive and negative poles of the internal zero detector and the external zero detector are connected with the same polarity. The positive pole of the zero detector is connected to MainPath+ through relay SN1, and the positive pole of the zero detector is also connected to MainPath- through relay SN2. The negative pole of the zero detector is connected to MainPath+ through relay SN3, and the negative pole of the zero detector is also connected to MainPath- through relay SN4. The VoN of FVSM No. 0 is connected to MainPath0 through relay SF01, the VoP of FVSM No. 0 is connected to MainPath- through relay SF02, and the VoP of FVSM No. 0 is also connected to MainPath+ through relay SF03. The VoN of FVSM No. 0 is connected to the VoC of FVSM No. 0 through relay SFN0, and the VoP of FVSM No. 0 is also connected to the VoC of FVSM No. 0 through relay SFP0. The VoC of FVSM No. 0 is short-circuited with the VoN of FVSM No. 1, the VoN of FVSM No. 1 is connected to MainPath0 through relay SF11, the VoP of FVSM No. 1 is connected to MainPath- through relay SF12, and the VoP of FVSM No. 1 is also connected to MainPath+ through relay SF13. The connection method between the remaining FVSMs and the three main paths is the same as the connection method between FVSM No. 0 and No. 1 and the three main paths, and the VoC of each FVSM is connected to the VoN of the FVSM that is one step larger.

[0024] After adopting the above technical solution, the present invention has the following advantages compared with the prior art: 1. The 9 FVSMs are numbered from 0 to 8 according to their output voltages. Each FVSM outputs a fixed voltage value. The 8 FVSMs are connected in series and stacked to output multiple voltage values. Any voltage output with an interval of 0.05V can be obtained within the range of ±12.75V, and the total number of output voltage points is 511. The DAC fine-tuning voltage circuit makes the adjustment voltage resolution of the DAC fine-tuning module 5nV, thereby realizing precise adjustment of each FVSM and generating a high linearity output with INL<±0.05ppm.

[0025] 2. The ultra-high sensitivity of the zero detector can be used to fine-tune the output voltage of the FVSM to a balance, ensuring the uniformity between the FVSMs, thereby ensuring the proportional accuracy of the output voltage of each FVSM after being connected in series, thereby ensuring the non-linearity index of the calibrator's output voltage.

[0026] 3. The typical 1 / f noise of a single ADR1399 is 1.44uVpp. By stacking 16 ADR1399 chips, increasing the current and adding an RC low-pass filter circuit, the overall 1 / f noise is reduced to <0.1uVpp, corresponding to a total output INL of <0.01ppm. Within 1000 seconds, the target of INL <±0.05ppm is fully met, and there is room for improvement of one-fold.

[0027] 4. The constant internal resistance output circuit includes a multi-channel parallel circuit and an output impedance adjustment circuit connected in parallel by 16 operational amplifiers. The multi-channel parallel circuit reduces the output impedance and reduces the internal resistance difference between each FVSM. The parallel output resistance of the multi-channel parallel circuit after the 16 operational amplifiers are connected in parallel is R; the output impedance adjustment circuit includes 7 adjustment resistors with different resistance values. The resistance values ​​of the 7 adjustment resistors are as follows: 7R, 3R, 5R / 3, R, 3R / 5, R / 3, R / 7. Each adjustment resistor is connected to a magnetic latching relay. When the switch of the magnetic latching relay is closed, the adjustment resistor connected in series with it is connected to the output circuit. An adjustment resistor is selected by the magnetic latching relay to be connected to the output circuit and connected in series with the parallel output internal resistance; the main control CPU sends an instruction to the FVSM, and the constant internal resistance output circuit ensures that no matter how many FVSMs are connected in series, the total output internal resistance is a fixed value of 8R, thereby ensuring that the internal resistance of the calibrator does not change during the entire calibration process.

[0028] 5. The 9 FVSMs, the internal zero detector, the external zero detector and the voltage output interface are interconnected through a magnetic latching relay connection matrix. The magnetic latching relay is used inside the connection matrix. The normally closed or normally open state of the magnetic latching relay is completely dependent on the action of the permanent magnet. There is no static power consumption and no heat generation, which can reduce the thermal potential error.

[0029] The present invention is described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is the logic flow chart of the FVSM self-leveling process; Figure 2 It is a schematic diagram of the connection method of each FVSM during the self-leveling process; Figure 3 This is the wiring diagram of the magnetic latching relay connection moment; Figure 4 This is the wiring diagram of the reference circuit, DAC fine-tuning voltage circuit, adding operational amplifier circuit and reverse operational amplifier circuit. Figure 5 It is the wiring diagram of multi-way parallel circuit and output impedance adjustment circuit. DETAILED DESCRIPTION

[0031] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, specific embodiments of the present invention are now described with reference to the accompanying drawings.

[0032] The present invention provides a DC voltage nonlinearity calibrator, comprising a main control module, 9 fully floating voltage source modules (hereinafter referred to as FVSM), an internal zero detector and a constant temperature system; The main control module includes a main CPU, a human-machine interface (including a display screen, buttons, indicator lights) and a USB communication interface; The internal zero check meter mainly includes a voltage measurement circuit with a very small range (1mV), high resolution (1nV), and very low 1 / f noise (<50nVpp). When the internal zero check meter does not meet the requirements, a high-performance external zero check meter (34420A) can be connected through the zero check meter interface outside the calibrator to complete the voltage leveling inside the reference instrument. The leveling methods of the external zero check meter and the internal zero check meter are exactly the same.

[0033] The 9 FVSMs are numbered from 0 to 8 according to their output voltages. Each FVSM outputs a fixed voltage value. The 8 FVSMs are connected in series and stacked to output multiple voltage values. The corresponding output voltage value of each FVSM is: No. 0 outputs 0.05V; No. 1 outputs 0.05V; No. 2 outputs 0.1V; No. 3 outputs 0.2V; No. 4 outputs 0.4V; No. 5 outputs 0.8V; No. 6 outputs 1.6V; No. 7 outputs 3.2V; No. 8 outputs 6.4V; as shown in the following table: In the voltage distribution method in the above table, FVSM No. 0 is symmetrical with FVSM No. 1, which is called initial symmetry (equal); after FVSM No. 0 is connected in series with FVSM No. 1, it is symmetrical with FVSM No. 2; after FVSM No. 0, 1, and 2 are connected in series, they are symmetrical with FVSM No. 3, and so on. The sum of the voltages of all FVSMs before a certain FVSM (starting from No. 0) after being connected in series is symmetrical with this FVSM.

[0034] When providing voltage, the No. 0 FVSM only acts as a leveling reference and does not output. When the calibrator needs to output 0V, just short-circuit the positive and negative poles of the calibrator output; FVSMs of different voltages are connected in series and superimposed, so that they can be arranged and combined to generate a variety of different voltage values. The FVSM has an integrated CPU and a circuit for fine adjustment, which is used to send commands to the FVSM to fine-tune its output voltage.

[0035] When 1V output is required, the No. 5 FVSM (0.8V) and the No. 3 FVSM (0.2V) are connected in series to the output circuit.

[0036] Similarly, when 1.15V output is required, FVSM No. 1, 2, 3, and 5 are connected in series to the output circuit.

[0037] When all FVSMs 1-8 are connected in series, the maximum output is 12.75V. Negative voltage can be obtained by exchanging the positive and negative poles of the calibrator output through the S01-S04 relay. Therefore, any voltage output with an interval of 0.05V can be obtained within the range of ±12.75V, and the total output voltage points are 511.

[0038] Because the output voltage of the calibrator is the sum of the series superposition of each FVSM, as long as the output voltage of each FVSM is double uniform, the nonlinearity of the calibrator output voltage can be guaranteed. The accuracy of the absolute value of the calibrator output voltage is not important. The absolute value error of 0.01%FS does not affect the calibration of the instrument under test at all, because the INL of the instrument under test is not abrupt.

[0039] The uniformity between each FVSM is achieved by leveling step by step. The ultra-high sensitivity of the zero detector can be used to fine-tune the output voltage of the FVSM to balance (equal). The internal zero detector includes a CPU and ultra-low 1 / f noise, high amplification factor amplifier circuit, 32BitADC, and the leveling program is executed through the main control module.

[0040] You can also use an ultra-high sensitivity zero detector (such as 34420A) to perform leveling. Its minimum voltage range resolution can reach 0.1nV, corresponding to a ±10V range of 0.01ppb, and its detection capability far exceeds the given target INL. When using an external zero detector, you need to use a computer to connect the communication ports of the 34420A and the calibrator to the computer respectively, use the computer to read the data of the 34420A, and then forward it to the calibrator, so that the calibrator can achieve self-leveling.

[0041] When the self-leveling process is executed, the process is automatically completed by the main control module. Figure 1 , Figure 2 , including the following steps: Step 1: disconnect all the contacts of the relays inside the calibrator, and preheat the calibrator through the constant temperature system to keep the temperature constant; Step 2: short-circuit the positive and negative electrodes of the zero detector, and disconnect the positive and negative electrodes after clearing the zero detector; Step 3: Short-circuit the negative poles of FVSM No. 0 and No. 1, connect the positive pole of FVSM No. 0 to the negative input of the zero detector, connect the positive pole of FVSM No. 1 to the positive input of the zero detector, and do not make any connection to other FVSMs; Step 4: If the difference between the output voltages of the No. 0 and No. 1 FVSMs measured by the zero detector is less than 10nV, it is considered that the output voltages of the No. 0 and No. 1 FVSMs are balanced. If it is greater than 10nV, the main CPU of the main control module sends an instruction to the No. 1 FVSM to fine-tune its output voltage until the value measured by the zero detector falls within the set range. Step 5: Disconnect all internal connections of the calibrator; Step 6, short-circuit the positive and negative poles of the zero checker again, reset the zero checker and disconnect the positive and negative poles; Step seven, from No. 0 to No. n, the positive output of each FVSM is connected to the negative output of the one higher than it, so that No. 0 to No. n FVSM are connected in series, the negative output of No. 0 is short-circuited with the negative pole of No. n+1 FVSM, the positive output of No. n is connected to the negative pole of the zero detector, and the positive output of No. n+1 is connected to the positive pole of the zero detector, n=1,2...7; use the zero detector to level the No. n+1 FVSM until all FVSMs are leveled.

[0042] After leveling, the main control module displays that the leveling is completed and enters the ready state, ready to receive output voltage instructions.

[0043] The zero checker has the function of exchanging positive and negative poles. During the leveling process, when the FVSM is connected to the zero checker, the positive and negative poles of the zero checker are exchanged with the connection with the FVSM, and the positive and negative directions are changed to perform secondary leveling, thereby further improving the leveling accuracy.

[0044] Each FVSM includes a power module, a reference module, a DAC fine-tuning module, an adding operational amplifier circuit and an inverting operational amplifier circuit, a constant internal resistance output circuit, a CPU (STM32F103VET6) and a communication module.

[0045] The power module converts 24V to 15V through an isolated DCDC module, and then generates 12V, 10V, 5V, and 3.3V through multiple LDOs to supply analog circuits and CPUs. The analog part uses ultra-low 1 / f noise LDO.

[0046] The reference module includes a reference circuit, which includes 16 ADR1399 chips connected in parallel and stacked with each other (to simplify the circuit diagram, only two are drawn in the figure, and the 16-way connection is the same as the two shown). The purpose of connecting multiple ADR1399 chips in parallel is to reduce the total 1 / f noise. When 16 chips are stacked, the 1 / f noise can be reduced to 1 / 4 of a single ADR1399 (the 1 / f noise is inversely proportional to the square root of the number of stacked chips).

[0047] The default current of the ADR1399 chip is 3mA. When the current of the ADR1399 is increased to 12mA, the 1 / f noise is reduced by half compared with the 1 / f noise under the default current state, because the 1 / f noise is inversely proportional to the square root of the current. The ADR1399 in this solution uses a 10V power supply, so 249Ω resistors (R1 and R2) are used here.

[0048] The reference module adds an RC low-pass filter circuit with a cut-off frequency of 0.1Hz to filter the high-frequency components in the reference voltage. The RC low-pass filter circuit includes R3, R4 and C3 (such as Figure 4 The 1 / f noise corner frequency of ADR1399 is about 1Hz. Filtering out noise above 0.1Hz can reduce the total 1 / f noise by more than 1 / 2.

[0049] The typical 1 / f noise of a single ADR1399 is 1.44uVpp (3mA). By stacking 16 ADR1399 chips, increasing the current, and adding an RC low-pass filter circuit, the overall 1 / f noise is reduced to <0.1uVpp, corresponding to a total output INL <0.01ppm. Further 1 / f noise optimization measures include: the internal heating of the reference uses a constant temperature of 40°C or lower. The lower the temperature of the semiconductor component, the smaller the 1 / f noise, and there is still a significant effect. Therefore, within 1000 seconds, the goal of INL <±0.05ppm is fully met, and there is a doubling of room for improvement.

[0050] The DAC fine-tuning module includes a 16-bit DAC (AD5422) fine-tuning voltage circuit. The output range of the DAC is ±10V, and the output resolution of the DAC is 0.3mV. The DAC fine-tuning voltage circuit reduces the DAC output range by 3000 times (R17 and R19, metal foil resistors), so that the adjustment voltage resolution of the fine-tuning module is 100nV. After the adder in the DAC fine-tuning voltage circuit performs calculations, the voltage resolution will be further reduced by 20 times, so the output voltage resolution of the fine-tuning module is 5nV, accounting for 0.5ppb of the total range of the calibrator. The DAC fine-tuning module is used to achieve precise fine-tuning of each FVSM. Since the DAC output value is reduced by 60,000 times, the influence of the DAC's own temperature drift, nonlinearity, and 1 / f noise are all reduced by 60,000 times, and no special treatment is required.

[0051] The addition operational amplifier circuit adds the voltage output by the reference circuit and the DAC fine-tuning voltage circuit at a ratio of 20:1 (including resistors R7, R8, R10, and metal foil resistors), and after adjustment by the inverting operational amplifier circuit, it is divided by proportional resistors (R12, R13, R14, R16, R20, and metal foil resistors) to adjust to the preset voltage, and output through the operational amplifier buffer. Since the DAC's fine-tuning range is very small, there are initial errors in the resistors and other components on the circuit when leaving the factory. At this time, the initial errors of each FVSM cannot be leveled by simply relying on the DAC's adjustment output. Therefore, it is necessary to add a variable resistor R18 at the proportional resistor voltage divider to adjust the initial error at the factory to ensure that the DAC's fine-tuning range is sufficient when used after leaving the factory.

[0052] When using a calibrator to calibrate a multimeter, the accuracy of voltage transmission must be ensured. The internal resistance of the calibrator must be much smaller than that of the multimeter, and the internal resistance of both must not change during the entire calibration process. When using multiple FVSM outputs, since the FVSMs are in series, the internal resistance increases after the series connection. At this time, the output internal resistance of each FVSM needs to be reduced to keep the total output internal resistance of the calibrator unchanged. The main control CPU sends a command to the FVSM, and the constant internal resistance output circuit ensures that no matter how many FVSMs are connected in series, the total output internal resistance is a fixed value of 8R.

[0053] The constant internal resistance output circuit includes a multi-channel parallel circuit composed of 16 operational amplifiers connected in parallel and an output impedance adjustment circuit, such as Figure 5 , the multi-channel parallel circuit reduces the output impedance and the internal resistance difference between each FVSM. The parallel output resistance of the multi-channel parallel circuit after 16 operational amplifiers are connected in parallel is R (R is the measured value of the actual circuit); The output impedance adjustment circuit includes 7 adjustment resistors with different resistance values, which are: 7R, 3R, 5R / 3, R, 3R / 5, R / 3, R / 7. Each adjustment resistor is connected to a magnetic latching relay. When the switch of the magnetic latching relay is closed, the adjustment resistor connected in series with it is connected to the output circuit. An adjustment resistor is selected by the magnetic latching relay to be connected to the output circuit and connected in series with the parallel output internal resistance. The adjustment resistor connected to the magnetic latching relay in each FVSM is connected in series with the parallel output internal resistance to serve as a single FVSM output internal resistance, and the other adjustment resistors in the FVSM are in an open circuit state; When there are n FVSMs in series, the output resistance of a single FVSM needs to be adjusted to 8R / n. At this time, under the control of the magnetic latching relay, the resistance of the adjustment resistor in series with the parallel output internal resistance is 8R / nR, so that the total output resistance is a fixed value of 8R. The specific corresponding relationship is shown in the following table: Number of FVSM series 1 2 3 4 5 6 7 8 The resistance value of the adjustment resistor connected to the output loop 7R 3R 5R / 3 R 3R / 5 R / 3 R / 7 none Single FVSM output internal resistance 8R 4R 8R / 3 2R 8R / 5 8R / 6 8R / 7 R Total output internal resistance 8R 8R 8R 8R 8R 8R 8R 8R The power module and communication module in the FVSM are all suspended. The power module is isolated from the outside world through an isolated power supply, and the communication module is isolated from the outside world through an optical coupler, so that the power module and the communication module are all suspended. The connection matrix with the magnetic latching relay is flexibly connected through three magnetic latching relays SFx1-SFx3 (controlled by the main control module CPU). Full suspension can realize free series and parallel connection between FVSMs.

[0054] The 9 FVSMs, the internal zero detector, the external zero detector and the voltage output interface are interconnected through a magnetic latching relay connection matrix, such as Figure 3 .

[0055] The connection matrix uses a magnetic latching relay inside. The normally closed or normally open state of the magnetic latching relay completely relies on the action of the permanent magnet. There is no static power consumption and no heat generation, which can reduce the thermoelectric potential error.

[0056] The connection matrix has three main paths, which are defined as MainPath+, MainPath-, and MainPath0 respectively; each FVSM has three output connection points: a positive output point VoP, a negative output point VoN, and a cascade point VoCascade (VoC for short).

[0057] The positive electrode of the voltage output interface is connected to MainPath+ through relay S01, the positive electrode interface of the voltage output interface is also connected to MainPath0 through relay S02, the negative electrode interface of the voltage output interface is connected to MainPath+ through relay S03, and the negative electrode interface of the voltage output interface is also connected to MainPath0 through relay S04; The positive and negative poles of the internal zero detector and the external zero detector are connected with the same polarity. The positive pole of the zero detector is connected to MainPath+ through relay SN1, and the positive pole of the zero detector is also connected to MainPath- through relay SN2. The negative pole of the zero detector is connected to MainPath+ through relay SN3, and the negative pole of the zero detector is also connected to MainPath- through relay SN4. The VoN of FVSM No. 0 is connected to MainPath0 through relay SF01, the VoP of FVSM No. 0 is connected to MainPath- through relay SF02, and the VoP of FVSM No. 0 is also connected to MainPath+ through relay SF03. The VoN of FVSM No. 0 is connected to the VoC of FVSM No. 0 through relay SFN0, and the VoP of FVSM No. 0 is also connected to the VoC of FVSM No. 0 through relay SFP0. The VoC of FVSM No. 0 is short-circuited with the VoN of FVSM No. 1, the VoN of FVSM No. 1 is connected to MainPath0 through relay SF11, the VoP of FVSM No. 1 is connected to MainPath- through relay SF12, and the VoP of FVSM No. 1 is also connected to MainPath+ through relay SF13. The connection method between the remaining FVSMs and the three main paths is the same as the connection method between FVSM No. 0 and No. 1 and the three main paths, and the VoC of each FVSM is connected to the VoN of the FVSM that is one step larger.

[0058] By controlling the state of the magnetic latching relay switch to change the connection mode between FVSM and the three main paths, FVSM has 11 working modes: non-operating, single-stage output, cascade output starting point, cascade path, cascade output relay, cascade output end point, leveling reference single-stage output, leveling reference output starting point, leveling reference output relay, leveling reference output end point, waiting for leveling. The 11 working modes of FVSM are used to meet the leveling process and different voltage outputs.

[0059] The corresponding relationship between the FVSM working mode and its related relay status is shown in the following table: Not working: The FVSM does not participate in output and leveling.

[0060] Single-stage output: This FVSM outputs by itself and does not require other FVSMs to be connected in series.

[0061] Cascade output starting point: This FVSM participates in the output series connection and is the first in the series connection.

[0062] Cascade path: This FVSM does not participate in the series connection, but it needs to build a series path for the series-connected FVSM.

[0063] Cascade output relay: The FVSM participates in the output series connection and is located in the middle of the series connection.

[0064] Cascade output destination: This FVSM participates in the output series connection and is the last one in the series connection.

[0065] Leveling reference single-stage output: This FVSM is used as a reference for leveling and does not require other FVSMs to be connected in series. The FVSM to be leveled needs to be aligned to it.

[0066] Leveling reference output starting point: This FVSM is used as a reference for leveling and as the first in a series connection.

[0067] Leveling Reference Output Relay: This FVSM serves as a leveling reference and is located in the middle of the series connection.

[0068] Leveling reference output end point: This FVSM is used as a reference for leveling and is the last one in series.

[0069] To be leveled: This FVSM is the one to be adjusted during leveling.

[0070] The chip model in this solution is not the only one that does not change. Other models of the same or higher level can be selected. In the calculation, 1 / f noise, thermoelectric potential, temperature drift and other aspects are taken into account, and conservative design values ​​are given. In actual products, the number of parallel connections can be further increased to improve performance through this solution. In actual products, when such high indicators are not required, the number of FVSM modules can be reduced. For example, 7 FVSMs can output any voltage within the range of ±12.6V with a step of 0.2V. The total number of output points is 127 points, which fully meets the calibration needs of most high-performance integrated circuit ADCs and eight-and-a-half-bit DMMs. It is also possible to delete the internal zero detector and reduce the number of parallel reference chips to reduce costs.

[0071] The above is an example of the best implementation of the present invention, and the parts not described in detail are common knowledge of ordinary technicians in the field. The protection scope of the present invention shall be based on the content of the claims, and any equivalent transformation based on the technical enlightenment of the present invention is also within the protection scope of the present invention.

Claims

1. A DC voltage nonlinearity calibrator, characterized in that: It includes a main control module, 9 fully suspended voltage source modules FVSM, an internal zero detector and a constant temperature system; The main control module includes a main CPU, a human-machine interface and a USB communication interface; The 9 FVSMs are numbered from 0 to 8 according to their output voltages. Each FVSM outputs a fixed voltage value. The 9 FVSMs are connected in series and stacked to output multiple voltage values. The output voltage values ​​of the 9 FVSMs are as follows: No. 0 outputs 0.05V; No. 1 outputs 0.05V; No. 2 outputs 0.1V; No. 3 outputs 0.2V; No. 4 outputs 0.4V; No. 5 outputs 0.8V; No. 6 outputs 1.6V; No. 7 outputs 3.2V; No. 8 outputs 6.4V; FVSM No. 0 is only used for leveling and not for output. When the calibrator outputs 0V, it only needs to short-circuit the positive and negative poles of the output without the involvement of FVSM. FVSMs are connected in series and stacked to generate a variety of different voltage values. The internal zero detector levels each FVSM to ensure uniformity between the FVSMs, thereby ensuring the nonlinearity index of the calibrator output voltage.

2. A DC voltage nonlinearity calibrator as claimed in claim 1, characterized in that: The internal zero detector mainly includes a voltage measurement circuit with a very small range, high resolution and very low 1 / f noise. When the internal zero detector does not meet the requirements, a high-performance external zero detector is connected through the external zero detector interface of the calibrator to complete the voltage leveling of each FVSM. The leveling methods of the external zero detector and the internal zero detector are exactly the same.

3. A DC voltage nonlinearity calibrator as claimed in claim 2, characterized in that: When executing the self-leveling process, the process is fully automatically controlled by the main control module and includes the following steps: Step 1: disconnect all the contacts of the relays inside the calibrator, and preheat the calibrator through the constant temperature system to keep the temperature constant; Step 2: short-circuit the positive and negative electrodes of the zero detector, and disconnect the positive and negative electrodes after clearing the zero detector; Step 3: Short-circuit the negative poles of FVSM No. 0 and No. 1, connect the positive pole of FVSM No. 0 to the negative input of the zero detector, connect the positive pole of FVSM No. 1 to the positive input of the zero detector, and do not make any connection to other FVSMs; Step 4: If the difference between the output voltages of the No. 0 and No. 1 FVSMs measured by the zero detector is less than 10nV, it is considered that the output voltages of the No. 0 and No. 1 FVSMs are balanced. If it is greater than 10nV, the main CPU of the main control module sends an instruction to the No. 1 FVSM to fine-tune its output voltage until the value measured by the zero detector falls within the set range. Step 5: Disconnect all internal connections of the calibrator; Step 6, short-circuit the positive and negative poles of the zero checker again, reset the zero checker and disconnect the positive and negative poles; Step seven, from No. 0 to No. n, the positive output of each FVSM is connected to the negative output of the one higher than it, so that No. 0 to No. n FVSM are connected in series, the negative output of No. 0 is short-circuited with the negative pole of No. n+1 FVSM, the positive output of No. n is connected to the negative pole of the zero detector, and the positive output of No. n+1 is connected to the positive pole of the zero detector, n=1,2...7; use the zero detector to level the No. n+1 FVSM until all FVSMs are leveled.

4. A DC voltage nonlinearity calibrator as claimed in claim 3, characterized in that: The zero checker has the function of automatically exchanging the positive and negative poles. During the leveling process, when the FVSM is connected to the zero checker, the main control module exchanges the positive and negative poles of the zero checker with the connection of the FVSM, changes the positive and negative directions for secondary leveling, and further improves the leveling accuracy.

5. A DC voltage nonlinearity calibrator as claimed in claim 1, characterized in that: Each FVSM includes a power module, a reference module, a DAC fine-tuning module, an addition operational amplifier circuit and an inversion operational amplifier circuit, a constant internal resistance output circuit, a CPU and a communication module.

6. A DC voltage nonlinearity calibrator as claimed in claim 1, characterized in that: The reference module includes a reference circuit, which includes 16 ADR1399 chips stacked in parallel. After the 16 chips are stacked, the 1 / f noise is reduced to 1 / 4 of that of a single chip. Increase the current of the ADR1399 chip to 12mA to reduce the 1 / f noise to 1 / 2 of the default current (3mA); The reference module adds an RC low-pass filter circuit with a cutoff frequency of 0.1Hz to filter out the high-frequency components in the reference voltage; the 1 / f noise corner frequency of the ADR1399 chip is about 1Hz, and filtering out the part above 0.1Hz can reduce the 1 / f noise by more than 1 / 2.

7. A DC voltage nonlinearity calibrator as claimed in claim 1, characterized in that: The DAC fine-tuning module includes a 16-bit DAC fine-tuning voltage circuit, the DAC output range is ±10V, the DAC output resolution is 0.3mV, and the DAC fine-tuning voltage circuit reduces the DAC output range by 3000 times, so that the adjustment voltage resolution of the fine-tuning module is 100nV; After the adder in the DAC fine-tuning voltage circuit performs calculations, the voltage resolution will be reduced by 20 times again, so the output voltage resolution of the fine-tuning module is 5nV, thereby achieving precise adjustment of each level of FVSM.

8. A DC voltage nonlinearity calibrator as claimed in claim 1, characterized in that: The main control CPU sends instructions to the FVSM, and the constant internal resistance output circuit inside the FVSM ensures that no matter how many FVSMs are connected in series, the total output internal resistance is a fixed value of 8R; The constant internal resistance output circuit includes a multi-channel parallel circuit composed of 16 operational amplifiers connected in parallel and an output impedance adjustment circuit. The multi-channel parallel circuit reduces the output impedance and reduces the internal resistance difference between each FVSM. The parallel output internal resistance of the 16 operational amplifiers in the multi-channel parallel circuit is R; The output impedance adjustment circuit includes 7 adjustment resistors with different resistance values, which are: 7R, 3R, 5R / 3, R, 3R / 5, R / 3, R / 7. Each adjustment resistor is connected to a magnetic latching relay. When the switch of the magnetic latching relay is closed, the adjustment resistor connected in series with it is connected to the output circuit. An adjustment resistor is selected by the magnetic latching relay to be connected to the output circuit and connected in series with the parallel output internal resistance. The adjustment resistor connected to the magnetic latching relay in each FVSM is connected in series with the parallel output internal resistance as a single FVSM output internal resistance, and the other adjustment resistors in the FVSM are in an open circuit state; When there are n FVSMs connected in series, the output resistance of a single FVSM needs to be adjusted to 8R / n. At this time, under the control of the magnetic latching relay, the resistance of the adjustment resistor in series with the parallel output internal resistance is 8R / nR, thereby satisfying the total output resistance of the fixed value of 8R.

9. A DC voltage nonlinearity calibrator as claimed in claim 2, characterized in that: The 9 FVSMs, the internal zero detector, the external zero detector and the voltage output interface are interconnected via a magnetic latching relay connection matrix; the magnetic latching relay is used inside the connection matrix.

10. A DC voltage nonlinearity calibrator as claimed in claim 9, characterized in that: The connection matrix has three main paths, namely MainPath+, MainPath-, and MainPath0; each FVSM output has three connection points: a positive pole point VoP, a negative pole point VoN, and a cascade point VoC; The positive electrode interface of the voltage output interface is connected to MainPath+ through relay S01, the positive electrode interface of the voltage output interface is also connected to MainPath0 through relay S02, the negative electrode interface of the voltage output interface is connected to MainPath+ through relay S03, and the negative electrode interface of the voltage output interface is also connected to MainPath0 through relay S04; The positive and negative poles of the internal zero detector and the external zero detector are connected with the same polarity. The positive pole of the zero detector is connected to MainPath+ through relay SN1, and the positive pole of the zero detector is also connected to MainPath- through relay SN2. The negative pole of the zero detector is connected to MainPath+ through relay SN3, and the negative pole of the zero detector is also connected to MainPath- through relay SN4. The VoN of FVSM No. 0 is connected to MainPath0 through relay SF01, the VoP of FVSM No. 0 is connected to MainPath- through relay SF02, and the VoP of FVSM No. 0 is also connected to MainPath+ through relay SF03. The VoN of FVSM No. 0 is connected to the VoC of FVSM No. 0 through relay SFN0, and the VoP of FVSM No. 0 is also connected to the VoC of FVSM No. 0 through relay SFP0. The VoC of FVSM No. 0 is short-circuited with the VoN of FVSM No. 1, the VoN of FVSM No. 1 is connected to MainPath0 through relay SF11, the VoP of FVSM No. 1 is connected to MainPath- through relay SF12, and the VoP of FVSM No. 1 is also connected to MainPath+ through relay SF13. The connection method between the remaining FVSMs and the three main paths is the same as the connection method between FVSM No. 0 and No. 1 and the three main paths, and the VoC of each FVSM is connected to the VoN of the FVSM that is one step larger.

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