Instruction processing method and device, electronic equipment and storage medium

Abstract

The invention provides an instruction processing method, and relates to the technical field of artificial intelligence, in particular to the technical field of chips and the technical field of instruction emission. The specific implementation scheme is as follows: in response to determining that a source storage space identifier of a to-be-transmitted calculation instruction in an instruction queue is consistent with index sub-information of target storage mapping information in at least one piece of storage mapping information, replacing the source storage space identifier of the to-be-transmitted calculation instruction with content sub-information of the target storage mapping information, the content sub-information of the target storage mapping information is a source storage space identifier of a previous movement instruction of the to-be-transmitted calculation instruction, and the index sub-information of the target storage mapping information is consistent with a target storage space identifier of the previous movement instruction; the processed computing instructions are provided to a processing unit. The invention further provides an instruction processing device, electronic equipment and a storage medium.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, in particular to the field of chip technology and instruction transmission technology. More specifically, the present disclosure provides an instruction processing method, device, electronic device and storage medium. Background Art

[0002] With the development of artificial intelligence technology, the application of artificial intelligence chips is increasing. Artificial intelligence chips can include one or more processing units. The processing unit can be a vector processing unit that can perform vector operations. Summary of the invention

[0003] The present disclosure provides an instruction processing method, apparatus, device and storage medium.

[0004] According to one aspect of the present disclosure, an instruction processing method is provided, the method comprising: in response to determining that a source storage space identifier of a computing instruction to be transmitted in an instruction queue is consistent with an index sub-information of a target storage mapping information in at least one storage mapping information, replacing the source storage space identifier of the computing instruction to be transmitted with the content sub-information of the target storage mapping information to obtain a processed computing instruction, wherein the content sub-information of the target storage mapping information is the source storage space identifier of a preceding move instruction of the computing instruction to be transmitted, and the index sub-information of the target storage mapping information is consistent with the destination storage space identifier of the preceding move instruction; and providing the processed computing instruction to a processing unit.

[0005] According to another aspect of the present disclosure, an instruction processing device is provided, which includes: a processing unit; an instruction issuing unit, configured to: in response to determining that a source storage space identifier of a computing instruction to be issued in an instruction queue is consistent with an index sub-information of a target storage mapping information in at least one storage mapping information, replace the source storage space identifier of the computing instruction to be issued with the content sub-information of the target storage mapping information to obtain a processed computing instruction, wherein the content sub-information of the target storage mapping information is the source storage space identifier of a previous move instruction of the computing instruction to be issued, and the index sub-information of the target storage mapping information is consistent with the destination storage space identifier of the previous move instruction; and provide the processed computing instruction to the processing unit.

[0006] According to another aspect of the present disclosure, an instruction processing device is provided, including the instruction processing apparatus provided by the present disclosure.

[0007] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method provided according to the present disclosure.

[0008] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided. The computer instructions are used to cause a computer to execute the method provided according to the present disclosure.

[0009] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the method provided according to the present disclosure is implemented.

[0010] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0012] Figure 1 is a schematic flow chart of an instruction processing method according to an embodiment of the present disclosure;

[0013] Figure 2 is a schematic diagram of an instruction queue according to an embodiment of the present disclosure;

[0014] Figure 3A and Figure 3B is a schematic diagram of an artificial intelligence chip according to an embodiment of the present disclosure;

[0015] Figure 4 is a block diagram of an instruction processing device according to an embodiment of the present disclosure;

[0016] Figure 5 is a block diagram of an instruction processing device according to an embodiment of the present disclosure; and

[0017] Figure 6 is a block diagram of an electronic device to which the instruction processing method can be applied according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0019] Artificial intelligence chips can be various processors such as general-purpose graphics processing units (GPGPUs), tensor processing units (TPUs), and neural network processing units (NPUs). Artificial intelligence chips can include vector computing units. Vector computing units can obtain data from vector registers to perform vector calculations. The bit width of vector registers is greater than 64 bits, and the chip area occupied is large.

[0020] During the execution of multiple instructions in the instruction queue, data dependencies may exist between multiple registers used for different instructions. Data dependencies include read after write (raw) dependencies, write after read (war) dependencies, etc. For example, the instruction queue may include a first move instruction and an addition instruction. The first move instruction may copy the data in the first register to the second register. The addition instruction may add the data in the second register to the data in the second register to obtain the addition result, and may write the addition result to the third register. In the instruction queue, the first move instruction may be an instruction before the addition instruction. The source register of the addition instruction (the second register) is the same as the destination register of the first move instruction (the second register), and there is a data dependency between the destination register of the addition instruction and the source register of the move instruction. In order to accurately execute the instructions in the instruction queue, the addition instruction may be issued after the first move instruction is executed, resulting in the addition instruction being blocked at the head of the instruction queue and unable to be executed quickly, resulting in low instruction execution efficiency. It can be understood that the first to third registers may be architectural registers.

[0021] In order to determine whether data dependencies are determined between different instructions, a scoreboard may be set. The scoreboard may include multiple score table entries. The score table entry may indicate whether data is to be written to the architecture register. For example, before the above-mentioned first move instruction is executed, the score table entry corresponding to the second register may include a first indication value. The first indication value may be, for example, 1, which may indicate that data is to be written to the second register. In this case, there is data dependency between the above-mentioned addition calculation instruction and the first move instruction, and the addition calculation instruction cannot be issued. After the first move instruction is executed, the score table entry corresponding to the second register may be updated. After the update, the score table entry may include a second indication value. The second indication value may be, for example, 0, which may indicate that the second register is idle. At this time, the addition calculation instruction may be issued. The scoreboard can detect data dependencies, but cannot eliminate data dependencies, nor can it achieve early issuance of subsequent calculation instructions.

[0022] In order to speed up the instruction issuance efficiency, the number of architectural registers can also be increased to reduce the probability of data dependency, but data dependency cannot be eliminated and it is difficult to fully improve the instruction issuance efficiency.

[0023] Therefore, in order to fully improve the efficiency of instruction issuance, the present disclosure provides an instruction processing method, which will be described below.

[0024] Figure 1 is a schematic flow chart of an instruction processing method according to an embodiment of the present disclosure.

[0025] like Figure 1 As shown, method 100 may include operations S110 to S120.

[0026] In operation S110, in response to determining that the source storage space identifier of the computing instruction to be issued in the instruction queue is consistent with the index sub-information of the target storage mapping information in at least one storage mapping information, the source storage space identifier of the computing instruction to be issued is replaced with the content sub-information of the target storage mapping information to obtain a processed computing instruction.

[0027] In the embodiment of the present disclosure, the instruction queue may include a move instruction and a non-move instruction. The non-move instruction may be a calculation instruction. The calculation instruction to be issued may be a calculation instruction at the head of the instruction queue. For example, the instruction queue may include the first move instruction and the addition calculation instruction.

[0028] In the embodiment of the present disclosure, the storage mapping information may be at least one index sub-information of the storage mapping information, which is consistent with the destination storage space identifier of the move instruction before the computing instruction to be issued.

[0029] In the disclosed embodiment, it is possible to search in at least one index sub-information according to the source storage space identifier of the computing instruction to be transmitted. If the index sub-information of a storage mapping information is found to be consistent with the source storage space identifier of the computing instruction to be transmitted. The storage mapping information can be used as the target storage mapping information corresponding to the computing instruction to be transmitted. Thus, it can be determined that the source storage space identifier of the computing instruction to be transmitted is consistent with the destination storage space identifier of a previous move instruction. There is a data dependency relationship between the computing instruction to be transmitted and the previous move instruction.

[0030] In an embodiment of the present disclosure, the computing instruction to be transmitted may include a source storage space identifier and a destination storage space identifier. The content sub-information of the destination storage mapping information is the source storage space identifier of the preceding move instruction of the computing instruction to be transmitted. The source storage space identifier of the computing instruction to be transmitted may be replaced with the content sub-information of the destination storage mapping information to obtain the processed computing instruction. Thus, data may be obtained from the source storage space of the preceding move instruction so as to execute the processed computing instruction.

[0031] In operation S120 , the processed computing instruction is provided to a processing unit.

[0032] In the embodiments of the present disclosure, the processing unit may be various computing units of an artificial intelligence chip. For example, the processing unit may be a vector computing unit.

[0033] In the embodiment of the present disclosure, the processed computing instruction can be transmitted to the processing unit. After receiving the processed computing instruction, the processing unit can execute the processed computing instruction.

[0034] Through the disclosed embodiment, the source storage space identifier of the computation instruction to be issued is replaced by the source storage space identifier of a previous move instruction. Thus, the computation instruction with data dependency on the move instruction can be issued without actually executing the move instruction in the instruction queue, which can effectively improve the instruction issuance efficiency and further improve the instruction execution efficiency.

[0035] It can be understood that the method of the present disclosure is described above, and the instruction queue of the present disclosure will be described below.

[0036] Figure 2 is a schematic diagram of an instruction queue according to an embodiment of the present disclosure.

[0037] like Figure 2 As shown, the instruction queue queue20 may include a first move (mov) instruction i200, an addition (add) instruction i201, and a multiplication (mul) instruction i202. The first move instruction i200 may write the data in register r0 to register r1. The addition instruction may obtain the data in register r1 and add the two data to obtain an addition result. The addition result may be written to register r2. The multiplication instruction may multiply the data in register r3 and the data in register r7 to obtain a multiplication result. The multiplication result may be written to register r0.

[0038] Register r0, register r1, register r2, register r3 and register r7 can be architectural registers. The destination register of the first move instruction i200 is register r1, and the source register is register r0. The destination register of the addition calculation instruction i201 is register r2, and the source register is register r1. The source register number of the addition calculation instruction is the same as the destination register number of the first move instruction. There is a data dependency relationship between the addition calculation instruction i201 and the first move instruction i200. The destination register of the multiplication calculation instruction i202 is register r0, and the two source registers are register r3 and register r7 respectively.

[0039] It can be understood that the above describes the instruction queue of the present invention, and the following will be described in conjunction with an artificial intelligence chip that executes the method.

[0040] Figure 3A and Figure 3B is a schematic diagram of an artificial intelligence chip according to an embodiment of the present disclosure.

[0041] like Figure 3A As shown, the chip 300 may include an instruction issuing unit and a register file rf30. The instruction issuing unit may include an instruction buffer unit instr_buffer30. The instruction buffer unit instr_buffer30 may store an instruction queue. The instruction queue may be the above-mentioned instruction queue queue20.

[0042] In some embodiments, the storage mapping information may be information stored in a valid mapping table entry in a mapping table. The mapping table may include at least one mapping table entry. The mapping table mov_map30 may include, for example, 32 mapping table entries. The mapping table entry may include a validity field, which may indicate whether the mapping table entry is valid. Figure 3A As shown, the value of the validity field of the mapping table entry e301 may be an invalid value 0, which may indicate that the mapping table entry 301 is an invalid mapping table entry. The number of mapping table entries may be consistent with the number of architecture registers of the thread.

[0043] In some embodiments, the mapping table entry includes an index field and a content field, the value of the index field is consistent with the destination storage space identifier of the move instruction, and the value of the content field is the destination storage space identifier of the move instruction. In a valid mapping table entry, the value of the index field may be the storage mapping information index sub-information, and the value of the content field may be the storage mapping information content sub-information. The source storage space identifier may be the source register number. The destination storage space identifier may be the destination register number. Figure 3A As shown, the value of the index field of mapping table item e300 can be 0, which can represent register r0. The value of the content field of mapping table item e300 can be 7, which can represent register r7. The value of the index field of mapping table item e301 is 1, which can represent register r1. The value of the content field of mapping table item e301 is 12, which can represent register r12. Through the embodiment of the present disclosure, a mapping table related to move instructions is set, which can improve the processing efficiency of move instructions, reduce the probability of move instructions blocking the instruction queue, and also improve the efficiency of transmitting calculation instructions in the instruction queue.

[0044] In some embodiments, at least one storage mapping information is generated according to at least one move instruction in the instruction queue. For example, when the first move instruction i200 is located at the head of the instruction queue queue20, a storage mapping information can be generated according to the first move instruction.

[0045] In some embodiments, the storage mapping information is generated according to the move instruction by the following operation: in response to determining that the move instruction is located at the head of the instruction queue and determining that there is no data dependency relationship between the multiple storage spaces used for the move instruction and the storage spaces used for the issued instruction, the source storage space identifier of the move instruction is written into the content field of the mapping table entry corresponding to the move instruction. The mapping table entry corresponding to the move instruction is: a mapping table entry whose index field value is consistent with the destination storage space identifier of the move instruction. As shown in FIG3 , when the first move instruction i200 is located at the head of the instruction queue queue20, the scoreboard sc30 can be queried. If the score table entry corresponding to the register r0 includes the second indication value (0), it can be determined that there is no data dependency relationship between the source register of the first move instruction i200 and the register of the issued instruction. If the score table entry corresponding to the register r1 includes the second indication value, it can be determined that there is no data dependency relationship between the destination register of the first move instruction i200 and the register of the issued instruction. The value of the index field of the mapping table entry e301 is 1, which is consistent with the destination register number (1) of the first move instruction i200. The mapping table entry e301 can be used as the mapping table entry corresponding to the first move instruction. The source register number (0) of the first move instruction i200 can be written into the content field of the mapping table entry e301. The value of the validity field of the mapping table entry e301 can also be set to a valid value (1), so as to obtain Figure 3B The mapping table entry e301' is shown. Figure 3B As shown, the value of the content field of mapping entry e301' is 0, indicating register r0. The value of the validity field of mapping entry e301' is 1, indicating that mapping entry e301' is a valid mapping entry. It can be understood that when writing the register number to the content field, the register number can be used to overwrite the value in the content field.

[0046] In some embodiments, after the storage mapping information is generated, the move instruction can be removed from the instruction queue. Figure 3AAs shown, after writing the source register number (0) of the first move instruction i200 into the content field of the mapping table entry e301, the first move instruction i200 can be removed from the instruction queue queue20. That is, the first move instruction i200 may not be provided to the processing unit, so that the processing unit does not execute the first move instruction i200, nor does it read the register stack rf30 based on the first move instruction i200. Through the disclosed embodiment, the move instruction is removed from the instruction queue. As a result, the instruction queue will not be blocked, the processing unit does not need to execute the move instruction, the computing resources of the chip can be saved, and the update of the score table entries related to the move instruction in the scoreboard can be avoided. The subsequent calculation instructions that have data dependency on the move instruction can be quickly emitted from the instruction queue without waiting for the move instruction to be executed and then emitted, which can improve the instruction emission efficiency.

[0047] It can be understood that the above describes the processing method of the move instruction of the present disclosure, and the processing method of the calculation instruction will be described below.

[0048] For example, after the first move instruction i200 is moved out of the instruction queue queue20, the addition calculation instruction i201 may be located at the head of the instruction queue i200 and may be used as a calculation instruction to be issued.

[0049] In some embodiments, in some implementations of the above operation S110, a mapping table entry that is hit by the source storage space identifier of the computing instruction to be emitted is determined from the mapping table to obtain a target mapping table entry. The information stored in the target mapping table entry can be used as the above target storage information. The target mapping table entry can be a valid mapping table entry. Figure 3B As shown, the value (1) of the index field of the mapping table entry e301 ′ is consistent with the source register number (1) of the addition calculation instruction i201 , and the mapping table entry e301 ′ may be the mapping table entry hit by the addition calculation instruction i201 .

[0050] In some embodiments, in some implementations of the above operation S110, replacing the source storage space identifier of the computing instruction to be transmitted with the content sub-information of the target storage mapping information to obtain the processed computing instruction may include: replacing the source storage space identifier of the computing instruction to be transmitted with the value of the target content field to obtain the processed computing instruction. The target content field is the content field of the target mapping table entry. Figure 3B As shown, for the addition calculation instruction i201, the target content field can be the value of the content field of the mapping table entry e301'. The source register number (1) of the addition calculation instruction can be replaced with the value (0) of the content field in the mapping table entry e301' to obtain the processed addition calculation instruction.

[0051] Next, the above operation S120 may be performed to provide the processed addition calculation instruction to the processing unit. For example, the processed addition calculation instruction may be transmitted to the processing unit.

[0052] In some embodiments, the above method may further include: reading the data to be processed from the source storage space of the previous move instruction. According to the data to be processed, the processed calculation instruction is executed by the processing unit. For example, the processing unit may obtain data from register r0 as the first data to be processed. The processing unit may add two first data to be processed to obtain an addition result. The addition result may be written into register r2. Through the embodiments of the present disclosure, based on the storage mapping information, the data to be processed of the calculation instruction can be accurately determined, the calculation accuracy of the chip can be improved, and the utilization rate of the register resources can also be improved.

[0053] It can be understood that the above description uses the example that the source storage space identifier of the computing instruction is consistent with the index sub-information of the storage mapping information to illustrate the present disclosure. The following description will further illustrate the present disclosure using the example that the source storage space identifier of the computing instruction is consistent with the content sub-information of the storage mapping information.

[0054] In some embodiments, the above method may further include: in response to determining that the destination storage space identifier of the calculation instruction to be transmitted is consistent with a content sub-information of a storage mapping information, blocking the calculation instruction to be transmitted. For example, after the addition calculation instruction i201 is transmitted to the processing unit, the multiplication calculation instruction i202 may be located at the head of the instruction queue. The destination register number (0) of the multiplication calculation instruction i202 is consistent with the value (0) of the content field of the mapping table entry e301'. In this case, the addition calculation instruction i201 may not have been executed by the processing unit, and the multiplication calculation instruction i202 may be blocked to avoid the multiplication calculation instruction i202 being executed before the addition calculation instruction i201. Through the embodiments of the present disclosure, when the destination storage space identifier of the calculation instruction is consistent with a content sub-information, the calculation instruction can be blocked to improve the calculation accuracy of the chip.

[0055] It can be understood that the above describes the valid mapping table entries of the present disclosure, and some methods of releasing the valid mapping table entries will be described below.

[0056] In some embodiments, the above method may further include: in response to determining that the register file is idle, providing a valid mapping table entry in the mapping table to the register file. Using the register file, write the data in the register corresponding to the index field of the valid mapping table entry to the register corresponding to the content field of the valid mapping table entry. Adjust the valid mapping table entry to an invalid mapping table entry to release the valid mapping table entry. For example, when the register file RF30 is not read or written, it can be determined that the register file RF30 is idle. The mapping table entry E301' can be provided to the register file RF30. The register corresponding to the value (1) of the index field of the mapping table entry can be register R1. The register corresponding to the value (0) of the content field of the mapping table entry can be register R0. The register file RF30 can write the data in register R0 to register R1. Next, the value of the effectiveness field of the mapping table entry E301' can be adjusted to 0 to release the mapping table entry E301'. Through the embodiments of the present disclosure, mapping table entries are released and data movement is implemented by a register stack, which can save computing resources of the processing unit and improve the utilization rate of the entries in the mapping table to facilitate processing of subsequent movement instructions.

[0057] The storage mapping information may be information stored in a valid mapping field. After the mapping table entry e301' is released, the destination register number of the multiplication calculation instruction i202 is different from the value of the content field of any valid mapping table entry in the mapping table mov_map30. Moreover, the source register number of the multiplication calculation instruction i202 does not hit a valid mapping table entry in the mapping table mov_map30. If the multiple score table entries corresponding to the registers r3, r7, and r0 of the multiplication calculation instruction i202 all include the second indication value (0), it can be determined that there is no data dependency relationship between the multiple registers of the multiplication calculation instruction and the registers of the issued instruction. The multiplication calculation instruction i202 may be provided to the processing unit. The processing unit may multiply the data in the register r3 and the data in the register r7 to obtain a multiplication calculation result. The multiplication calculation result is written into the register r0.

[0058] Next, for other move instructions (such as the second move instruction) in the instruction queue, they can be processed in the same or similar manner as the first move instruction i200. For non-move instructions in the instruction queue, they can be processed in the same or similar manner as the addition calculation instruction i201 or the multiplication calculation instruction i202, which will not be described in detail in this disclosure.

[0059] It can be understood that the above description uses the storage space identifier as a register number as an example to illustrate the present disclosure, but the present disclosure is not limited thereto, and the storage space identifier may also be a storage address, which may indicate a storage space in a local memory unit (local memory) or a global memory unit (global memory).

[0060] It can be understood that the method of the present disclosure is described above, and the device of the present disclosure will be described below.

[0061] Figure 4 is a block diagram of an instruction processing device according to an embodiment of the present disclosure.

[0062] like Figure 4 As shown, the device 400 may include a processing unit 410 and an instruction transmitting unit 420 .

[0063] The processing unit 410 may be various processing units, such as a systolic array or a vector computing unit.

[0064] The instruction emission unit 420 may be configured to: in response to determining that the source storage space identifier of the computing instruction to be emitted in the instruction queue is consistent with the index sub-information of the target storage mapping information in at least one storage mapping information, replace the source storage space identifier of the computing instruction to be emitted with the content sub-information of the target storage mapping information to obtain a processed computing instruction; and provide the processed computing instruction to the processing unit. The instruction emission unit 420 may perform operations S110 and S120 in the above method 100.

[0065] In some embodiments, the content sub-information of the target storage mapping information is the source storage space identifier of the preceding move instruction of the computation instruction to be issued, and the index sub-information of the target storage mapping information is consistent with the destination storage space identifier of the preceding move instruction.

[0066] In some embodiments, at least one storage mapping information is generated based on at least one move instruction in the instruction queue. After the storage mapping information is generated, the move instruction is removed from the instruction queue.

[0067] In some embodiments, the instruction queue includes at least one move instruction, the storage mapping information is the information stored in a valid mapping table entry in a mapping table, the mapping table includes at least one mapping table entry, the at least one mapping table entry includes at least one of a valid mapping table entry and an invalid mapping table entry, the mapping table entry includes an index field and a content field, the value of the index field is consistent with the destination storage space identifier of the move instruction, and the value of the content field is the source storage space identifier of the move instruction.

[0068] In some embodiments, the storage mapping information is generated by the instruction issuing unit according to the move instruction by performing the following operations: in response to determining that the move instruction is located at the head of the instruction queue and determining that there is no data dependency relationship between the multiple storage spaces used for the move instruction and the storage spaces used for the issued instructions, writing the source storage space identifier of the move instruction into the content field of the mapping table entry corresponding to the move instruction. The mapping table entry corresponding to the move instruction is: a mapping table entry whose index field value is consistent with the destination storage space identifier of the move instruction.

[0069] In some embodiments, the target storage mapping information is information represented by a target mapping table entry in a mapping table, and the target mapping table entry is a mapping table entry hit by a source storage space identifier of a computing instruction to be transmitted. The instruction transmitting unit is further configured to perform the following operations to replace the source storage space identifier of the computing instruction to be transmitted with the content sub-information of the target storage mapping information, and obtain a processed computing instruction: replace the source storage space identifier of the computing instruction to be transmitted with the value of the target content field, and obtain a processed computing instruction. The target content field is the content field of the target mapping table entry.

[0070] In some embodiments, the instruction issuing unit is further configured to: in response to determining that the destination storage space identifier of the computing instruction to be issued is consistent with content sub-information of a storage mapping information, block the computing instruction to be issued.

[0071] In some embodiments, the source storage space is identified as a source register number, the destination storage space is identified as a destination register number, and the device further includes a register stack. The instruction issuing unit is further configured to: in response to determining that the register stack is idle, provide a valid mapping table entry in the mapping table to the register stack. The register stack is configured to: write the data in the register corresponding to the index field of the valid mapping table entry to the register corresponding to the content field of the valid mapping table entry; and adjust the valid mapping table entry to an invalid mapping table entry to release the valid mapping table entry.

[0072] In some embodiments, the processing unit is further configured to: read the data to be processed from the source storage space of the previous move instruction, and execute the processed computing instruction using the processing unit according to the data to be processed.

[0073] It can be understood that the above describes the apparatus of the present disclosure, and the following will describe the device of the present disclosure.

[0074] Figure 5 is a block diagram of an instruction processing device according to an embodiment of the present disclosure.

[0075] like Figure 5 As shown, the device 50 may include an instruction processing device 500 .

[0076] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0077] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0078] Figure 6 A schematic block diagram of an example electronic device 600 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0079] like Figure 6 As shown, the device 600 includes a computing unit 601, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 to a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the device 600 can also be stored. The computing unit 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0080] A number of components in the device 600 are connected to the I / O interface 605, including: an input unit 606, such as a keyboard, a mouse, etc.; an output unit 607, such as various types of displays, speakers, etc.; a storage unit 608, such as a disk, an optical disk, etc.; and a communication unit 609, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 609 allows the device 600 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0081] The computing unit 601 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSP), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 601 performs the various methods and processes described above, such as the instruction processing method. For example, in some embodiments, the instruction processing method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 600 via the ROM 602 and / or the communication unit 609. When the computer program is loaded into the RAM 603 and executed by the computing unit 601, one or more steps of the instruction processing method described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to execute the instruction processing method in any other appropriate manner (eg, by means of firmware).

[0082] Various embodiments of the systems and techniques described above herein may be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard parts (ASSPs), system on chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0083] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0084] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media may include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories, read-only memories, erasable programmable read-only memories (EPROM) or flash memories, optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0085] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a cathode ray tube (CRT) display or a liquid crystal display (LCD)) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0086] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a Local Area Network (LAN), a Wide Area Network (WAN), and the Internet.

[0087] A computer system may include clients and servers. Clients and servers are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship to each other.

[0088] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0089] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A command processing method, comprising: In response to determining that a source storage space identifier of a computing instruction to be transmitted in the instruction queue is consistent with an index sub-information of a target storage mapping information in at least one storage mapping information, the source storage space identifier of the computing instruction to be transmitted is replaced with the content sub-information of the target storage mapping information to obtain a processed computing instruction, wherein the content sub-information of the target storage mapping information is the source storage space identifier of a preceding move instruction of the computing instruction to be transmitted, and the index sub-information of the target storage mapping information is consistent with the destination storage space identifier of the preceding move instruction; The processed computing instructions are provided to a processing unit.

2. The method according to claim 1, wherein: At least one of the storage mapping information is generated based on at least one move instruction in the instruction queue, After the storage mapping information is generated, the move instruction is moved out of the instruction queue.

3. The method according to claim 1, wherein: The instruction queue includes at least one move instruction, the storage mapping information is the information stored in a valid mapping table entry in a mapping table, the mapping table includes at least one mapping table entry, at least one of the valid mapping table entry and the invalid mapping table entry, the mapping table entry includes an index field and a content field, the value of the index field is consistent with the destination storage space identifier of the move instruction, and the value of the content field is the source storage space identifier of the move instruction.

4. The method according to claim 3, wherein: The storage mapping information is generated according to the move instruction by the following operations: In response to determining that the move instruction is located at the head of the instruction queue and determining that there is no data dependency between the multiple storage spaces used for the move instruction and the storage spaces used for the issued instructions, the source storage space identifier of the move instruction is written into the content field of the mapping table entry corresponding to the move instruction, wherein the mapping table entry corresponding to the move instruction is: a mapping table entry whose value of the index field is consistent with the destination storage space identifier of the move instruction.

5. The method according to claim 3, wherein: The target storage mapping information is information represented by a target mapping table entry in the mapping table, and the target mapping table entry is a mapping table entry hit by a source storage space identifier of the computing instruction to be emitted, The step of replacing the source storage space identifier of the to-be-transmitted computing instruction with the content sub-information of the target storage mapping information to obtain the processed computing instruction comprises: The source storage space identifier of the to-be-transmitted computing instruction is replaced with the value of the target content field to obtain a processed computing instruction, wherein the target content field is the content field of the target mapping table entry.

6. The method according to claim 1, further comprising: In response to determining that the destination storage space identifier of the to-be-issued computing instruction is consistent with one of the content sub-information of the storage mapping information, the to-be-issued computing instruction is blocked.

7. The method according to claim 3, wherein: The source storage space identifier is a source register number, and the destination storage space identifier is a destination register number. Also includes: In response to determining that the register file is free, providing a valid mapping table entry in the mapping table to the register file; Using the register stack, writing the data in the register corresponding to the index field of the valid mapping table entry into the register corresponding to the content field of the valid mapping table entry; The valid mapping table entry is adjusted to an invalid mapping table entry to release the valid mapping table entry.

8. The method according to claim 1, further comprising: Reading the data to be processed from the source storage space of the previous move instruction; The processed computing instructions are executed by the processing unit according to the data to be processed.

9. An instruction processing device, comprising: Processing unit; The command transmission unit is configured as follows: In response to determining that a source storage space identifier of a computing instruction to be transmitted in the instruction queue is consistent with an index sub-information of a target storage mapping information in at least one storage mapping information, the source storage space identifier of the computing instruction to be transmitted is replaced with the content sub-information of the target storage mapping information to obtain a processed computing instruction, wherein the content sub-information of the target storage mapping information is the source storage space identifier of a preceding move instruction of the computing instruction to be transmitted, and the index sub-information of the target storage mapping information is consistent with the destination storage space identifier of the preceding move instruction; The processed computing instructions are provided to the processing unit.

10. The device according to claim 9, wherein: At least one of the storage mapping information is generated based on at least one move instruction in the instruction queue, After the storage mapping information is generated, the move instruction is moved out of the instruction queue.

11. The device according to claim 9, wherein: The instruction queue includes at least one move instruction, the storage mapping information is the information stored in a valid mapping table entry in a mapping table, the mapping table includes at least one mapping table entry, at least one of the valid mapping table entry and the invalid mapping table entry, the mapping table entry includes an index field and a content field, the value of the index field is consistent with the destination storage space identifier of the move instruction, and the value of the content field is the source storage space identifier of the move instruction.

12. The device according to claim 11, wherein The storage mapping information is generated by the instruction issuing unit by performing the following operations according to the move instruction: In response to determining that the move instruction is located at the head of the instruction queue and determining that there is no data dependency between the multiple storage spaces used for the move instruction and the storage spaces used for the issued instructions, the source storage space identifier of the move instruction is written into the content field of the mapping table entry corresponding to the move instruction, wherein the mapping table entry corresponding to the move instruction is: a mapping table entry whose value of the index field is consistent with the destination storage space identifier of the move instruction.

13. The device according to claim 11, wherein: The target storage mapping information is information represented by a target mapping table entry in the mapping table, and the target mapping table entry is a mapping table entry hit by a source storage space identifier of the computing instruction to be emitted, The instruction transmitting unit is further configured to perform the following operations to replace the source storage space identifier of the to-be-transmitted computing instruction with the content sub-information of the target storage mapping information, to obtain a processed computing instruction: The source storage space identifier of the to-be-transmitted computing instruction is replaced with the value of the target content field to obtain a processed computing instruction, wherein the target content field is the content field of the target mapping table entry.

14. The device according to claim 9, wherein: The instruction transmitting unit is further configured as: In response to determining that the destination storage space identifier of the to-be-issued computing instruction is consistent with one of the content sub-information of the storage mapping information, the to-be-issued computing instruction is blocked.

15. The device according to claim 11, wherein The source storage space identifier is a source register number, the destination storage space identifier is a destination register number, and the device further includes a register file. The instruction issuing unit is further configured to: in response to determining that the register file is idle, provide a valid mapping table entry in the mapping table to the register file; The register stack is configured to: write data in a register corresponding to an index field of the valid mapping table entry into a register corresponding to a content field of the valid mapping table entry; The valid mapping table entry is adjusted to an invalid mapping table entry to release the valid mapping table entry.

16. The device according to claim 9, wherein: The processing unit is further configured to: Reading the data to be processed from the source storage space of the previous move instruction; The processed computing instructions are executed by the processing unit according to the data to be processed.

17. An instruction processing device, comprising the apparatus according to any one of claims 9 to 16.

18. An electronic device, comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 8.

19. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 8.

20. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 8.

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