A method, apparatus and device for processing a bitstream

Abstract

The application relates to the technical field of FPGA, and discloses a bit stream processing method, device and equipment, the method is applied to a target FPGA chip, the target FPGA chip comprises a CSRAM module, the method comprises the following steps: acquiring application requirements of the target FPGA chip, the application requirements comprising at least one of read operation requirements and write operation requirements; dividing the CSRAM module into a plurality of CSRAM sub-modules based on the application requirements; acquiring a target address of the CSRAM sub-module, and sending an operation instruction to the target address to drive the CSRAM sub-module to execute the operation instruction; and generating bit stream processing information of the target FPGA chip based on an execution result. The application can improve the efficiency of bit stream processing.

Description

TECHNICAL FIELD

[0001] The present application relates to the FPGA technical field, and particularly relates to a bit stream processing method, device and equipment. BACKGROUND

[0002] In the power-on initialization phase of an FPGA (Field Programmable Gate Array, field programmable gate array) chip, configuration data is loaded into a CSRAM (Configuration Static Random Access Memory, configuration static random access memory) in the FPGA through a bit stream. In the bit stream processing process, these components need to be configured and tested to ensure that they can correctly implement the predetermined subscription function and avoid unnecessary losses.

[0003] With the continuous increase in the size of the FPGA chip, the number of components contained therein increases rapidly. The time required for bit stream programming also increases. In the related art, the components on the FPGA chip are usually tested one by one in a certain order, although the test coverage is high, but the time is long and the efficiency is low.

[0004] Therefore, there is a need for a high-efficiency bit stream processing method. SUMMARY

[0005] Therefore, the present application provides a bit stream processing method to improve the efficiency of bit stream processing.

[0006] In a first aspect, the present application provides a bit stream processing method, the method is applied to a target FPGA chip, the target FPGA chip includes a CSRAM module, and the method includes: obtaining an application requirement of the target FPGA chip, the application requirement including at least one of a read operation requirement and a write operation requirement; dividing the CSRAM module into a plurality of CSRAM sub-modules based on the application requirement; obtaining a target address of the CSRAM sub-module, and sending an operation instruction to the target address to drive the CSRAM sub-module to execute the operation instruction.

[0007] In this embodiment, the application requirement of the target FPGA chip is obtained, and then the CSRAM module is divided according to the application requirement to obtain a plurality of CSRAM sub-modules. The operation instruction is sent to the target address of the CSRAM sub-module to drive the CSRAM sub-module to execute the corresponding operation instruction. Through the above scheme, the operation instruction can be sent to a plurality of CSRAM sub-modules at the same time, thereby shortening the time of bit stream processing and improving the efficiency of bit stream processing.

[0008] In an optional implementation, when the application requirement comprises a read operation requirement, the application requirement of the target FPGA chip is obtained, including: obtaining a read operation key parameter; the read operation key parameter comprises at least one of a speed requirement of the read operation, a sensitivity requirement of the read operation, and a control line layout.

[0009] In the embodiment, when the application requirement comprises a read operation requirement, the application requirement is determined by obtaining the read operation key parameter, and the sub-module can be verified in a targeted manner. Thus, the flexibility of the method is improved.

[0010] In an optional implementation, when the application requirement comprises a write operation requirement, the application requirement of the target FPGA chip is obtained, including: obtaining a write operation key parameter; the write operation key parameter comprises at least one of a speed requirement of the write operation and a control line layout.

[0011] In the embodiment, when the application requirement comprises a write operation requirement, the application requirement is determined by obtaining the write operation key parameter, and the sub-module can be verified in a targeted manner. Thus, the flexibility of the method is improved.

[0012] In an optional implementation, the operation instruction is sent to the target address, including: obtaining a task requirement of the CSRAM sub-module; generating the operation instruction based on the task requirement, and sending the operation instruction to the target address.

[0013] In the embodiment, the target address is determined according to the position range of the CSRAM sub-module in the system memory space and the application requirement, and the operation instruction is generated and sent to the target address according to the task requirement. Thus, the accuracy of the bit stream processing is improved, and the time waste caused by the addressing deviation is reduced.

[0014] In an optional implementation, the operation instruction comprises at least one of a read operation and a write operation.

[0015] In the embodiment, the operation instruction comprises at least one of a read operation and a write operation, so that the bit stream data can be processed, and the accuracy of the sub-module verification is improved.

[0016] In an optional implementation, when the operation instruction comprises a read operation, the operation instruction is executed, including: establishing an initial potential state of a target bit line; turning on a word line corresponding to the target address to obtain target voltage difference information; the target voltage difference information represents a voltage difference between bit line pairs; and the target voltage difference information is sent to a shift register.

[0017] In the embodiment, when the operation instruction comprises a read operation, the initial point of the target bit line is set to a state, and the target potential difference information is obtained by opening the word line corresponding to the target address. The read data can be quickly implemented, and the execution speed of the read instruction is improved.

[0018] In an alternative embodiment, when the operation instruction comprises a write operation, the operation instruction is executed, including: obtaining the bit stream data, and sending the bit stream data to the shift register; and opening the word line corresponding to the target address to drive the bit stream data to be written to the target address through the bit line.

[0019] In the embodiment, when the operation instruction comprises a write instruction, the bit stream data is obtained, and the bit stream data is written to the target address through the bit line. The write data can be quickly implemented, and the execution speed of the write data is improved.

[0020] In an alternative embodiment, before the bit stream data is sent to the shift register, the method further comprises: applying a reset signal to the shift register.

[0021] In the embodiment, by applying the reset signal to the shift register, the register is cleared, so that the initialization and clearing operation of the CSRAM storage unit is achieved, and the processing efficiency of the bit stream is improved.

[0022] In a second aspect, the application provides a bit stream processing device, the device comprising: an obtaining module, configured to obtain application requirements of a target FPGA chip, the application requirements comprising at least one of a read operation requirement and a write operation requirement; a dividing module, configured to divide a CSRAM module into a plurality of CSRAM sub-modules based on the application requirements; and an executing module, configured to obtain a target address of the CSRAM sub-module, and send an operation instruction to the target address to drive the CSRAM sub-module to execute the operation instruction.

[0023] In a third aspect, the application provides a computer device, comprising: a memory and a processor, which are in communication connection with each other, and the memory stores computer instructions; and the processor executes the computer instructions to execute the bit stream processing method of the first aspect or any one of the corresponding embodiments thereof. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the specific embodiments of the application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings described below are some embodiments of the application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0025] Figure 1Fig. 1 is a schematic diagram of a division of a C S R A module in a conventional target FPGA chip;

[0026] Figure 2 Fig. 1 is a schematic diagram of a division of a C S R A module in a conventional target FPGA chip;

[0027] Figure 3 Fig. 1 is a schematic diagram of a division of a C S R A module in a conventional target FPGA chip;

[0028] Figure 4 Fig. 1 is a schematic diagram of a division of a C S R A module in a conventional target FPGA chip;

[0029] Figure 5 Fig. 1 is a schematic diagram of a division of a C S R A module in a conventional target FPGA chip;

[0030] Figure 6 Fig. 1 is a schematic diagram of a division of a C S R A module in a conventional target FPGA chip;

[0031] Figure 7 Fig. 1 is a schematic diagram of a division of a C S R A module in a conventional target FPGA chip;

[0032] Figure 8 Fig. 1 is a schematic diagram of a division of a C S R A module in a conventional target FPGA chip. DETAILED DESCRIPTION

[0033] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0034] With the increasing size of FPGA chips, the number of components contained therein grows rapidly. The time required for bitstream programming also increases. In the related art, the components on the FPGA chip are usually tested one by one in a certain order, although the test coverage is high, but it is time-consuming and inefficient.

[0035] In the power-on initialization stage, configuration data is loaded into the CSRAM in the FPGA through a bit stream, but as the capacity of the SRAM (Static Random Access Memory) type FPGA increases, the configuration and readback verification of the bit stream becomes the key to limiting the configuration speed and readback test. By grouping the configuration CSRAM module and the configuration readback module in the FPGA into a CSRAM block, these modular units can be highly multiplexed, designed to have a suitable size and area, and the CSRAM block can be programmed and readback at the same time, which can improve the configuration and readback efficiency and yield.

[0036] In the related art, the CSRAM module in the FPGA chip is evenly divided to more effectively manage and utilize the resources of the CSRAM module, as shown in Figure 1 As shown in the figure, the CSRAM module in the FPGA chip is evenly divided into several CSRAM sub-modules, and there is an AMP (Amplifier) between every two CSRAM sub-modules, and a Shift Register is arranged at the right side of the CSRAM sub-module, the test bit stream is sent from the Test Bitstream Input & Output to the HCR (Horizontal Clock Row), and then flows into the Shift Register, and then is sent to the Bitcell (storage unit) in the corresponding CSRAM sub-module along the BitLine (BitLine) according to the address, and in the readback, the data stored in the Bitcell of the corresponding CSM sub-module is output through the Shift Register in turn, and the BitLine signal is amplified through several AMPs in the middle. But as the capacity of the FPGA increases, the length of the BitLine will increase and the number of the AMPs will increase, resulting in long time and high cost of bit stream configuration and readback verification.

[0037] The embodiment of the present application provides a bit stream processing method, by obtaining the application requirement of the target FPGA chip, and then dividing the CSRAM module according to the application requirement to obtain several CSRAM sub-modules. By sending an operation instruction to the target address of the CSRAM sub-module, the CSM sub-module is driven to execute the operation instruction. Through the above scheme, the operation instruction can be sent to several CSM sub-modules at the same time, thereby shortening the time of bit stream processing and improving the efficiency of bit stream processing.

[0038] According to an embodiment of the present application, a bitstream processing method is provided. It should be noted that the steps shown in the flowcharts of the drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0039] In this embodiment, a bitstream processing method is provided. The method is applied to a target FPGA chip, and the target FPGA chip includes a C SRAM module, Figure 2 is a flowchart of a bitstream processing method according to an embodiment of the present application, as shown in Figure 2 The flowchart includes the following steps:

[0040] In step S101, the application requirements of the target FPGA chip are obtained, and the application requirements include at least one of read operation requirements and write operation requirements.

[0041] Among them, according to the functional architecture of the entire system of the target FPGA chip, the data flow between different functional modules can be determined, and the application requirements of different modules in the target FPGA chip can be determined.

[0042] In step S102, based on the application requirements, the C SRAM module is divided into a plurality of C SRAM sub-modules.

[0043] When the FPGA chip is powered on and initialized, the modules on the FPGA chip need to be processed by the bitstream. Bitstream processing includes bitstream configuration and bitstream readback verification. By obtaining the application requirements of the target FPGA chip, the C SRAM module is divided into a plurality of C SRAM sub-modules, each C SRAM sub-module can independently perform read and write operations, and do not interfere with each other, which can improve the efficiency of bitstream processing.

[0044] Among them, according to the application requirements, the requirements of the target FPGA chip for the word line and the bit line can be determined. According to the requirements for the bit line and the word line, the word line load capacitance and the bit line load capacitance can be obtained to determine the array area and the array size of the C SRAM sub-module, so as to divide the C SRAM module. For target FPGA chips of different capacities, the C SRAM sub-module can be quickly reused, and the dynamic power consumption can be saved, and a single operation instruction can operate multiple C SRAM sub-modules at the same time. For example, a single read and write operation can realize configuration and readback of multiple C SRAM sub-modules.

[0045] In a specific implementation, the CSRAM sub-modules can have similar array sizes and array areas as much as possible, so that the CSRAM module has a proper bit line length, and each CSRAM sub-module can execute operation instructions in a short time. This brings additional dynamic power consumption savings. The operation instructions can include write operations and read-back operations. Since the CSRAM module has a multiplexing size and area, the CSRAM modules in different areas have the same read and write speeds, improving efficiency.

[0046] In some optional embodiments, the application requirement includes a bit stream transmission distance. Simply increasing the driving of the buffer can cause a time delay, which can not meet the timing requirements and design frequency requirements of the bit stream input end to the CSRAM sub-module. A one-level register can be added to cache a beat, and then the bit stream data is transmitted to the CSRAM sub-module at the next clock edge, so as to realize long-distance data transmission. In an actual application, the design specification is 200M frequency, that is, the clock period is 5ns. By delaying calculation, a one-level register is added to cache a beat before the signal transmission delay is 5ns, and then the data is transmitted to the CSRAM sub-module at the next clock edge (rising edge or falling edge). This always meets the requirement that each CSRAM sub-module is ready for bit stream before configuration, and then starts local configuration of the CSRAM, that is, write operation. This makes the expansion of the CSRAM sub-module have better flexibility, and easily realizes fast loading of the bit stream and read-back comparison and verification.

[0047] In step S103, the target address of the CSRAM sub-module is obtained, and an operation instruction is sent to the target address to drive the CSRAM sub-module to execute the operation instruction.

[0048] The total address range occupied by the CSRAM module in the address mapping system of the target FPGA chip can be obtained first. Then the corresponding address space of the CSRAM sub-module is allocated, so as to obtain the target address corresponding to the CSRAM sub-module. Then the corresponding operation instruction is sent to the target address to drive the CSRAM sub-module corresponding to the target address to execute the corresponding operation instruction.

[0049] The operation instruction can include a read operation instruction and a write operation instruction. In a specific implementation, if the operation instruction is a read operation instruction, the CSRAM sub-module pre-charges the bit line BL and the anti-bit line (BLB, Bit Line Bar) to the power supply voltage, then opens the word line, forms a pressure difference between the bit line and the anti-bit line (BL / BLB), then closes the word line, then amplifies the pressure difference to a logic level through an amplifier, and then transmits it to the shift register.

[0050] In some optional embodiments, the data stored in the shift register can be sent to the bit stream back reading module, and bit stream checking and comparison can be performed. By comparing the read bit stream and the originally loaded bit stream bit by bit, it can be determined whether the configuration of the bit stream is accurate.

[0051] If the operation instruction is a write instruction, the bit stream data to be written needs to be obtained first, and then the bit stream data to be written is sent to the shift register. Then, according to the target address of the CSRAM sub-module, the word line corresponding to the CSRAM sub-module is opened, so that the bit stream data is transmitted to the CSRAM sub-module through the bit line, and the write instruction is completed.

[0052] The bit stream processing method provided in the embodiment can obtain the application requirements of the target FPGA chip, and then divide the CSRAM module according to the application requirements to obtain a plurality of CSRAM sub-modules. The operation instruction is sent to the target address of the CSRAM sub-module to drive the CSRAM sub-module to execute the operation instruction. Through the above scheme, the operation instruction can be sent to a plurality of CSRAM sub-modules at the same time, thereby shortening the time of bit stream processing and improving the efficiency of bit stream processing.

[0053] In the embodiment, a bit stream processing method is provided, Figure 3 The flowchart of the bit stream processing method according to the embodiment of the application is shown in Figure 3 The flowchart includes the following steps:

[0054] In step S201, the application requirements of the target FPGA chip are obtained, and the application requirements include at least one of read operation requirements and write operation requirements.

[0055] For details, refer to step S101 of the embodiment shown in Figure 2 which will not be described here again.

[0056] In some optional embodiments, the application requirements include write operation requirements, and step S201 includes:

[0057] In step S2011, the read operation key parameters are obtained, and the read operation key parameters include at least one of the speed requirement of the read operation, the sensitivity requirement of the read operation, and the control line layout.

[0058] In the case where the application requirements of the target FPGA chip include read operation requirements, the key parameters of the read operation can be obtained, and the array size and the array area of the CSRAM sub-module can be determined according to the key parameters of the read operation.

[0059] The control line layout can include a word line layout and a bit line layout.

[0060] In the case where the application requirement includes a read requirement, the application requirement can be determined by obtaining key parameters of the read operation, and the sub-modules can be verified in a targeted manner, thereby improving the flexibility of the method.

[0061] In some optional embodiments, the application requirement includes a read operation requirement, and the step S201 includes:

[0062] In step S2012, key parameters of the write operation are obtained. The key parameters of the write operation include at least one of a speed requirement of the write operation and a control line layout.

[0063] In the case where the application requirement of the target FPGA chip includes a write operation requirement, the key parameters of the write operation can be obtained, and the array size and the array area of the CSRAM sub-module can be determined according to the key parameters of the write operation.

[0064] The control line layout can include a word line layout and a bit line layout.

[0065] In the case where the application requirement includes a write requirement, the application requirement can be determined by obtaining key parameters of the write operation, and the sub-modules can be verified in a targeted manner, thereby improving the flexibility of the method.

[0066] In step S202, the CSRAM module is divided into a plurality of CSRAM sub-modules based on the application requirement.

[0067] For details, please refer to Figure 2 The step S102 of the embodiment shown will not be described here.

[0068] In some optional embodiments, a structural diagram of the CSRAM sub-module is as shown in Figure 4 As shown in the structural diagram, the CSRAM sub-module includes a CSRAM storage unit array (CSRAM BitCell array), a shift register (Shift Register), and an amplifier (AMP). Storage units in the same row are connected to the same word line, and each column of storage units is connected to a corresponding bit line. The CSRAM BitCell is composed of a pair of cross-coupled inverters and a pair of NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor) transistors. The two ends of the NMOS transistor are respectively connected to a pair of bit lines, and the pair of bit lines are a bit line (BL) and a complementary bit line (BLB). In some optional embodiments, the number of connections of the CSRAM sub-module on the Bitline and the length of the Bitline determine the capacitance size of the Bitline, which affects the discharge speed of the Bitline.

[0069] Step S203, obtaining a target address of the CSRAM submodule, and sending an operation instruction to the target address to drive the CSRAM submodule to execute the operation instruction.

[0070] Specifically, the above step S203 comprises:

[0071] Step S2031, obtaining a target address of the CSRAM submodule.

[0072] Wherein, the total address range occupied by the CSRAM module in the address mapping system of the target FPGA chip can be obtained first. Then the corresponding address space is allocated to the CSRAM submodule, so as to obtain the target address corresponding to each CSRAM submodule.

[0073] In specific implementation, the corresponding address space can be allocated to the CSRAM submodule according to the importance or arrangement of each CSRAM submodule.

[0074] Step S2032, obtaining the task requirement of the CSRAM submodule.

[0075] Wherein, the task requirement of the CSRAM submodule can include bit stream configuration and bit stream readback verification. In specific implementation, the task requirement can be determined by the staff.

[0076] Step S2033, generating an operation instruction based on the task requirement, and sending the operation instruction to the target address.

[0077] Wherein, the task requirement can be decomposed to determine the input information, output information, etc. Then the content of the operation instruction is filled according to the basic format of the operation instruction. The basic format of the operation instruction can be set by the staff.

[0078] In the case where the task requirement includes bit stream configuration, the configuration of the bit stream can be completed by generating the corresponding write operation instruction. In specific implementation, the write operation instruction can include bit stream data to be written, write mode, etc.

[0079] In the case where the task requirement includes bit stream readback verification, the reading of the bit stream can be completed by generating the corresponding read operation instruction. The read operation instruction can include bit stream reading mode, reading length, etc.

[0080] In some optional embodiments, the operation instruction includes at least one of read operation and write operation.

[0081] The operation instruction includes at least one of read operation and write operation to process bit stream data, which can improve the accuracy of submodule verification.

[0082] Step S2034, the CSRAM submodule executes the operation instruction.

[0083] In some optional embodiments, in the case where the operation instruction comprises a read operation, step S2033 comprises:

[0084] Step a1, establishing an initial potential state of the target bit line.

[0085] In a specific application, the target bit line can be pre-charged to the power supply voltage, so that the initial potential state of the target bit line is high.

[0086] Step a2, turning on the word line corresponding to the target address to obtain target voltage difference information; the target voltage difference information represents the voltage difference between the bit line pairs.

[0087] The address decoder inside the CSRAM sub-module will parse the target address based on the storage capacity and the number of address lines of the CSRAM sub-module, and convert it into a corresponding row selection signal, and then pull up the corresponding word line level. Each storage unit corresponding to the target address will present the data stored by itself in the form of voltage difference on the bit line. The voltage difference is the voltage difference between the bit line pairs, i.e. the voltage difference between the bit line and the anti-bit line. In a specific implementation, in the case where the stored data is "1", the bit line voltage can be relatively raised; in the case where the stored data is "0", the bit line voltage can be relatively lowered.

[0088] Step a3, sending the target voltage difference information to the shift register.

[0089] The target voltage difference information contains the storage data information inside the CSRAM sub-module, which can be amplified by the amplifier to amplify the target voltage difference information into a logic level and transmitted to the shift register.

[0090] In one practical application, in the case where the operation instruction comprises a read operation instruction, as shown in Figure 5 (a) group represents the level state of WL (Wordline), BL / BLB, SAEN (Sense Amplifier Enable) and dout (Data Out) that can be recognized by the present method, and (b) group represents the level state of WL, BL / BLB, SAEN and dout that can be recognized in the related art. It can be seen that the present method can read the bit stream stored in the CSRAM sub-module through a small bit line swing, i.e. △(BL / BLB), through the amplifier. In the related art, a wider word line pulse width is needed to achieve a bit line swing close to the power supply voltage to ensure correct data reading. Although this method can read the correct data, it will cause a large dynamic power loss because the bit line pair BL / BLB needs to be pre-charged from a lower voltage to the power supply voltage for the next read operation.

[0091] In the case that the operation instruction includes a read operation, an initial potential state of the target bit line is established, and the target potential difference information is obtained by opening the word line corresponding to the target address. The read data can be quickly implemented, and the execution speed of the read instruction is improved.

[0092] In some optional embodiments, in the case that the operation instruction includes a write instruction, step S2033 includes:

[0093] Step b1, obtaining the bit stream data and sending the bit stream data to the shift register.

[0094] The bit stream data can be generated by using a related bit stream generator according to the encoding format of the target FPGA chip.

[0095] In the specific implementation, before the bit stream data is sent to the shift register, the storage data in the shift register can be cleared to ensure that the shift register does not store the remaining bit stream, so as to prevent data errors when the bit stream data is written into the corresponding CSM module. In some optional embodiments, a zero bit stream can be written to the shift register first.

[0096] In some optional embodiments, step b1 further includes:

[0097] Step c1, applying a reset signal to the shift register.

[0098] The type of the reset signal can be selected according to the actual situation, and the type of the reset signal can be synchronous reset and asynchronous reset. Before executing the write instruction each time, the reset signal can be applied to the shift register first to prevent the data stored in the shift register from affecting the writing of the correct data.

[0099] The reset signal in the shift register can not only reset the storage value in the shift register to 0, but also can be used to initialize and clear all CSM storage units to 0 when it is necessary to write 0 to all CSM storage units. The zero bit stream does not need to be sent from the Test Bitstream Input & Output, and the reset signal can provide the all-zero writing operation, so as to achieve the initialization and clearing operation of the CSM storage unit.

[0100] Step b2, opening the word line corresponding to the target address to drive the bit stream data to be written to the target address through the bit line.

[0101] According to the target address, the target address is converted into a corresponding row selection signal and a column selection signal, and then the level of the word line corresponding to the target address is pulled high according to the target address, so that the bit unit of the corresponding CSM module enters a writable state, and then a corresponding voltage is applied to the bit line according to the bit stream data.

[0102] In a case that the operation instruction comprises a write instruction, the bitstream data is acquired and written into the target address through the bit line. The write data can be quickly implemented, and the execution speed of the write data is improved.

[0103] The bitstream processing method provided in the embodiment can determine the target address according to the position range of the CSRAM submodule in the system memory space and the application requirement, and generate and send the operation instruction to the target address according to the application requirement. The accuracy of the bitstream processing can be improved, and the time waste caused by the addressing deviation can be reduced.

[0104] In the embodiment, a bitstream configuration and readback verification method is also provided. As shown in Figure 6 The CSRAM module is split into eight CSRAM submodules, each of which comprises a CSRAM bitcell for storing bitstream data. The CSRAM module further comprises four Shift Registers and an AMP arranged between the CSRAM submodules. An HCR is arranged below every four CSRAM submodules.

[0105] In loading the bitstream data, the bitstream can be loaded to each direction on the target FPGA chip, and then delivered to the vicinity of each CSRAM submodule through the Shift Register. After the delivery is completed, a read-write operation is performed on the specified address of each CSRAM submodule to realize the bitstream configuration and bitstream readback of multiple CSRAM submodules. In the bitstream configuration, a write operation can be performed to configure multiple CSRAM submodules. The specific implementation steps of the write operation comprise: delivering the bitstream to the Shift Register beside each CSRAM submodule along the HCR through the Test Bitstream Input&Output, delivering and storing the bitstream data in the Shift Register, then sending an address signal to select the corresponding Wordline (WL) of multiple CSRAM submodules to open, i.e. the NMOS transmission tube in the CSRAM Bitcell is opened, and the data is written into the CSRAM submodule through the Bitline. In the bitstream verification, a read operation can be performed to realize the readback of multiple CSRAM submodules. The BL / BLB is pre-charged to the power supply voltage, an address signal is sent to select the corresponding Wordline of multiple CSRAM to open, the BL / BLB forms a pressure difference after the WL is closed, the amplifier amplifies the pressure difference to a logic level 0 / 1 and transmits it to the Shift Register, and finally the value in the Shift Register is delivered to the bitstream readback module for verification and comparison.

[0106] The CSRAM region block has high multiplexing, and the short BitLine length in the CSRAM Bitcell realizes fast configuration writing and readback verification of bit stream data, and brings additional dynamic power consumption saving.

[0107] In some optional embodiments, when the CSDRAM memory unit is initialized and cleared, that is, all 0s are written, the reset function of the register can be used, that is, the value in the register is reset to 0 by using the reset operation on the register, and the zero bit stream is not input, and the zero clearing can be performed.

[0108] In the embodiment, a bit stream processing apparatus is also provided, which is used to implement the above-described embodiments and preferred embodiments, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware can also be implemented and conceived.

[0109] The embodiment provides a bit stream processing apparatus, as shown in the following Figure 7 The bit stream processing apparatus comprises:

[0110] The obtaining module 701 is configured to obtain application requirements of a target FPGA chip, and the application requirements comprise at least one of read operation requirements and write operation requirements.

[0111] The dividing module 702 is configured to divide the CSDRAM module into a plurality of CSDRAM sub-modules based on the application requirements.

[0112] The executing module 703 is configured to obtain a target address of the CSDRAM sub-module, and send an operation instruction to the target address, so as to drive the CSDRAM sub-module to execute the operation instruction.

[0113] In some optional embodiments, the obtaining module 701 comprises:

[0114] The read operation parameter obtaining unit is configured to obtain read operation key parameters; the read operation key parameters comprise at least one of a speed requirement of the read operation, a sensitivity requirement of the read operation, and a control line layout.

[0115] In some optional embodiments, the obtaining module 701 comprises:

[0116] The write operation parameter obtaining unit is configured to obtain write operation key parameters; the write operation key parameters comprise at least one of a speed requirement of the write operation and a control line layout.

[0117] In some optional embodiments, the executing module 703 comprises:

[0118] The task requirement obtaining unit is configured to obtain a task requirement of the CSRAM sub-module.

[0119] The sending unit is configured to generate an operation instruction based on the task requirement and send the operation instruction to the target address.

[0120] In some optional embodiments, the operation instruction comprises at least one of a read operation and a write operation.

[0121] In some optional embodiments, when the operation instruction comprises the read operation, the execution module 703 comprises:

[0122] The establishing unit is configured to establish an initial potential state of the target bit line.

[0123] The voltage difference obtaining unit is configured to open a word line corresponding to the target address to obtain target voltage difference information, the target voltage difference information representing a voltage difference between bit line pairs.

[0124] The sending unit is configured to send the target voltage difference information to the shift register.

[0125] In some optional embodiments, when the operation instruction comprises the write operation, the execution step 703 comprises:

[0126] The bit stream sending unit is configured to obtain bit stream data and send the bit stream data to the shift register.

[0127] The bit stream writing unit is configured to open a word line corresponding to the target address to drive the bit stream data to be written to the target address through the bit line.

[0128] In some optional embodiments, the execution module 703 comprises:

[0129] The reset unit is configured to apply a reset signal to the shift register.

[0130] Further function descriptions of the above-mentioned various modules and units are the same as those of the above-mentioned corresponding embodiments, and will not be described here again.

[0131] The bit stream processing apparatus in the embodiment is presented in the form of a functional unit, and the unit herein refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory executing one or more software or fixed programs, and / or other devices that can provide the above-mentioned functions.

[0132] The embodiment of the application further provides a computer device with the above-mentioned Figure 7 bit stream processing apparatus.

[0133] Please refer to Figure 8 ,Figure 8 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 8 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 8 Take a processor 10 as an example.

[0134] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0135] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0136] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0137] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0138] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 can be connected by a bus or other means, Figure 8 The bus connection is taken as an example.

[0139] The input device 30 can receive inputted digital or character information, and generate key signal input related to user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 can include a display device, an auxiliary lighting device (e.g., an LED), a tactile feedback device (e.g., a vibration motor), etc. The display device includes but is not limited to a liquid crystal display, a light-emitting diode, a display, and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0140] The embodiments of the present application also provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and stored in a local storage medium, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk or a solid state disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that the computer, processor, microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code, which, when accessed and executed by the computer, processor or hardware, implements the method shown in the above embodiments.

[0141] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, the method and / or technical solutions according to the present application can be called or provided. Those skilled in the art should understand that the form of computer program instructions in computer readable medium includes but is not limited to source file, executable file, installation package file, etc., and accordingly, the way of computer program instructions executed by computer includes but is not limited to: the computer directly executes the instructions, or the computer executes the corresponding compiled program after compiling the instructions, or the computer reads and executes the instructions, or the computer executes the corresponding installed program after reading and installing the instructions. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0142] While embodiments of the application have been described in connection with the preferred embodiments of the various figures, those of ordinary skill in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the application, and that such modifications and changes fall within the scope of the appended claims.

Claims

1. A method of bitstream processing, the method comprising: The method is applied to a target FPGA chip including a CSRAM module, and the method comprises: obtaining application requirements of the target FPGA chip, the application requirements comprising at least one of read operation requirements and write operation requirements; dividing the CSRAM module into a plurality of CSRAM sub-modules based on the application requirements; the CSRAM sub-modules comprising a CSRAM memory cell array and a shift register, the same row of memory cells being connected to the same word line, and each column of memory cells being connected to a corresponding bit line; obtaining a target address of the CSRAM sub-module and sending an operation instruction to the target address to drive the CSRAM sub-module to execute the operation instruction; wherein the total address range occupied by the CSRAM module in the address mapping system of the target FPGA chip is obtained, a corresponding address space is allocated to the CSRAM sub-module, and the target address corresponding to the CSRAM sub-module is obtained; in the case that the operation instruction comprises a read operation, the execution of the operation instruction comprises: establishing an initial potential state of a target bit line; wherein the target bit line is pre-charged to a power supply voltage; turning on a word line corresponding to the target address to obtain target voltage difference information; the target voltage difference information representing the voltage difference between the bit line pairs; sending the target voltage difference information to the shift register.

2. The method of claim 1, wherein, in the case that the application requirements comprise read operation requirements, the obtaining of the application requirements of the target FPGA chip comprises: obtaining read operation key parameters; the read operation key parameters comprising at least one of the speed requirement of the read operation, the sensitivity requirement of the read operation, and the control line layout.

3. The method of claim 1, wherein, in the case that the application requirements comprise write operation requirements, the obtaining of the application requirements of the target FPGA chip comprises: obtaining write operation key parameters; the write operation key parameters comprising at least one of the speed requirement of the write operation and the control line layout.

4. The method of claim 1, wherein, the sending of the operation instruction to the target address comprises: obtaining task requirements of the CSRAM sub-module; generating an operation instruction based on the task requirements and sending the operation instruction to the target address.

5. The method according to any of claims 1 to 4, characterized in that the operation instruction comprises at least one of a read operation and a write operation.

6. The method of claim 5, wherein, in the case that the operation instruction comprises a write operation, the execution of the operation instruction comprises: obtaining bit stream data and sending the bit stream data to the shift register; turning on a word line corresponding to the target address to drive the bit stream data to be written to the target address through the bit line.

7. The method of claim 6, wherein, before the sending of the bit stream data to the shift register, the method further comprises: applying a reset signal to the shift register.

8. An apparatus for processing a bitstream, the apparatus comprising: the device comprises: an obtaining module configured to obtain application requirements of a target FPGA chip, the application requirements comprising at least one of read operation requirements and write operation requirements; a dividing module configured to divide a CSRAM module into a plurality of CSRAM sub-modules based on the application requirements; the CSRAM sub-modules comprising a CSRAM memory cell array and a shift register, the same row of memory cells being connected to the same word line, and each column of memory cells being connected to a corresponding bit line; An execution module is configured to acquire a target address of the CSRAM submodule and send an operation instruction to the target address to drive the CSRAM submodule to execute the operation instruction; wherein the total address range occupied by the CSRAM module in the address mapping system of the target FPGA chip is acquired, the corresponding address space of the CSRAM submodule is allocated, and the target address corresponding to the CSRAM submodule is obtained; In the case where the operation instruction comprises a read operation, the execution module is further configured to: establish an initial potential state of a target bit line; wherein the target bit line is pre-charged to a power supply voltage; turn on a word line corresponding to the target address to acquire target voltage difference information; the target voltage difference information represents the voltage difference between bit line pairs; send the target voltage difference information to a shift register.

9. A computer device, comprising: Comprise: a memory and a processor, which are in communication connection with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the bit stream processing method in any one of claims 1 to 7.

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