Storage sharing method, sharing device and processing system

Abstract

The invention discloses a storage sharing method, a sharing device and a processing system. The method comprises the steps that a first block request instruction is obtained, the first block request instruction is structurally converted by a first processor to obtain a first block structure, the first block structure is generated on the basis of the first block structure, and the first block request instruction is used for operating a memory; transmitting the first block request instruction to a virtual memory layer, and analyzing and reconstructing the first block request instruction to generate a reconstructed request instruction; transmitting the reconstruction request instruction to a first transmission layer, and constructing request information based on the reconstruction request instruction and a preset transmission protocol; the request information is sent to a second processor, so that the second processor processes the request information, and operation on a memory corresponding to the first request instruction is realized; and receiving response information sent by the second processor, wherein the response information comprises feedback information corresponding to the first request instruction. In this way, the construction cost of the processing system can be reduced.

Description

Technical Field

[0001] The present application relates to the field of storage, and in particular to a storage sharing method, a sharing device and a processing system. Background Art

[0002] In the embedded field, as the demand for computing power and application scenarios increases, multiple different chips are integrated into a system to meet functional requirements. These different chips run their own operating systems, such as Linux, Android, etc. The operation of each chip depends on its own external devices, such as running memory DDR, non-volatile memory, display devices, etc. For example, if there are two chips, then two sets of corresponding running memory DDR, non-volatile memory, display devices, etc. are required. This configuration increases the construction cost of the system. Summary of the invention

[0003] The main purpose of this application is to provide a storage sharing method, a sharing device and a processing system, which can reduce the construction cost of the processing system.

[0004] The first technical solution adopted in the present application is: to provide a storage sharing method. The method is applied to a first processor, the first processor is applied to a processing system, the processing system includes at least two processors and a memory, the at least two processors include a first processor and a second processor, the first processor is connected to the second processor, the second processor is connected to the memory, and the system architecture of the first processor includes a virtual memory layer and a first transmission layer. The method includes: obtaining a first block of request instructions, the first block of request instructions is obtained by the first processor by structurally transforming the first request instructions to obtain a first block of structures, and then generated based on the first block of structures, the first request instructions are used to operate the memory; the first block of request instructions are transmitted to the virtual memory layer, the first block of request instructions are parsed and reconstructed to generate a reconstruction request instruction; the reconstruction request instruction is transmitted to the first transmission layer, and the request information is constructed based on the reconstruction request instruction and the preset transmission protocol; the request information is sent to the second processor, so that the second processor processes the request information and implements the operation on the memory corresponding to the first request instruction; and the response information sent by the second processor is received, and the response information includes feedback information corresponding to the first request instruction.

[0005] The second technical solution adopted in the present application is: to provide a storage sharing method. The method is applied to a second processor, the second processor is applied to a processing system, the processing system includes at least two processors and a memory, the at least two processors include a first processor and a second processor, the first processor is connected to the second processor, the second processor is connected to the memory, and the system architecture of the second processor includes a remapping layer and a second transmission layer, the method includes: receiving a request message sent by the first processor, the request message is converted by the first processor to obtain a first block structure by structural conversion of the first request instruction, and then generated based on the first block structure, the first request instruction is used to operate the memory; inputting the request message to the second transmission layer, parsing and reconstructing the request message based on the request message and the preset transmission protocol to generate a second request instruction, the second request instruction corresponds to the first request instruction; inputting the second request instruction to the remapping layer, parsing the second request instruction to obtain basic instruction information, and converting the structure based on the basic instruction information to generate a second block structure; processing the second block structure, generating feedback information according to the processing result, and generating response information based on the feedback information; sending the response information to the first processor.

[0006] The third technical solution adopted in the present application is to provide a sharing device. The sharing device includes an information acquisition module, which is used to acquire a first block of request instructions. The first block of request instructions is generated based on the first block of structures by the sharing device performing structural transformation on the first request instructions. The first request instructions are used to operate the memory; a virtual storage module, which is used to parse and reconstruct the first block of request instructions to generate a reconstructed request instruction; a first transmission module, which is used to construct request information based on the reconstructed request instruction and a preset transmission protocol, and send the request information to another sharing device, so that the other sharing device processes the request information, implements the operation on the memory corresponding to the first request instruction, and receives the response information sent by another sharing device, and the response information includes feedback information corresponding to the first request instruction.

[0007] The fourth technical solution adopted in the present application is to provide a sharing device. The sharing device includes a second transmission module, which is used to receive request information sent by another sharing device, parse and reconstruct the request information based on the request information and the preset transmission protocol to generate a second request instruction, the request information is generated based on the first block structure by another sharing device performing structural transformation on the first request instruction, the first request instruction is used to operate the memory, and the second request instruction corresponds to the first request instruction; a remapping module, which is used to parse the second request instruction to obtain basic instruction information, and perform structural transformation based on the basic instruction information to generate a second block structure; an information processing module, which is used to process the second block structure, generate feedback information according to the processing result, and send the feedback information to the second transmission module, so that the second transmission module generates response information based on the feedback information, and sends the response information to another sharing device.

[0008] The fifth technical solution adopted in the present application is: providing a processing system, which includes at least two processors and a memory, the at least two processors include a first processor and a second processor, the first processor is connected to the second processor, the second processor is connected to the memory, the system architecture of the first processor includes a virtual memory layer and a first transmission layer, the system architecture of the second processor includes a remapping layer and a second transmission layer, the first processor and the second processor establish a communication connection to implement the method in the first technical solution and / or the second technical solution.

[0009] The beneficial effects of the present application are as follows: a virtual memory layer and a first transmission layer are constructed in the system architecture of a first processor, a first block of request instructions obtained from a first request instruction is transmitted to the virtual memory layer for parsing and reconstruction to obtain a reconstructed request instruction, and then the reconstructed request instruction is transmitted to the first transmission layer to construct request information according to a preset transmission protocol, so that the request information can be sent to a second processor according to the preset transmission protocol, so that the second processor can implement the operation on the memory corresponding to the first request instruction based on the request information, thereby enabling the first processor to use the memory connected to the second processor, achieving storage sharing, and reducing system construction costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 It is a processing diagram of operating the memory according to the operation instructions under the Linux system architecture;

[0012] Figure 2 It is a flowchart of the first embodiment of the storage sharing method of the present application;

[0013] Figure 3 This is a schematic diagram of the memory logical address planning of this application;

[0014] Figure 4 This is another schematic diagram of the memory logical address planning of the present application;

[0015] Figure 5 is a schematic diagram of a system architecture of a first processor of the present application;

[0016] Figure 6 This is a schematic diagram of the structure of the request information of this application;

[0017] Figure 7 It is a schematic diagram of the structure of the request instruction code in the request information of this application;

[0018] Figure 8 It is a flowchart of the second embodiment of the storage sharing method of the present application;

[0019] Fig. 9 is a schematic diagram of an embodiment of a system architecture of a second processor of the present application;

[0020] Fig.10 is a schematic diagram of another embodiment of the system architecture of the second processor of the present application;

[0021] Fig.11 It is a structural diagram of the first embodiment of the sharing device of the present application;

[0022] Fig.12 is a schematic diagram of the structure of the second embodiment of the sharing device of the present application;

[0023] Fig.13 It is a structural diagram of an embodiment of the processing system of the present application;

[0024] Fig.14 It is a structural diagram of another embodiment of the processing system of the present application;

[0025] Fig.15 It is a structural schematic diagram of the first embodiment of the electronic device of the present application;

[0026] Fig.16 is a structural schematic diagram of a second embodiment of the electronic device of the present application;

[0027] Fig.17 It is a structural diagram of the third embodiment of the electronic device of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0030] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0031] Before describing the technical solution of this application, a brief introduction to the related technologies is given. Taking the Linux system as an example, the operation flow of the processor on the memory is first described. Figure 1 , Figure 1The present invention is a processing diagram of operating the memory according to the operation instruction under the Linux system architecture. The Linux kernel receives the request instruction sent by the user layer, and then processes it, and sends the processed request instruction to the hardware, so that the hardware performs the corresponding action, thereby realizing the operation of the hardware. After the request instruction of the user layer is sent, it passes through the virtual file system (Virtual File System, VFS) of the kernel. The layer where the virtual file system is located is a software layer in the kernel, which is used to provide a file system interface to the application program of the user layer. The request instruction is passed to the mapping layer. The mapping layer mainly includes the file system component of the kernel. It mainly includes the disk file system, the block device file system, etc. In this layer, the request instruction will be initialized into a bio structure and submitted to the generic block layer. The bio (block input output) structure is a data structure in the Linux kernel, which is used to represent I / O operations. In the generic block layer, the obtained bio structure will be merged into the existing request instruction, or a new request instruction will be created to carry or include the information in the bio structure, and then the new request instruction will be inserted into the device request queue. The hardware driver, in this layer, converts the request instructions obtained from the general block layer into operation instructions that can be recognized by the hardware device. After the conversion, the hardware driver sends the operation instructions to the hardware, so that the hardware device can perform the corresponding operation.

[0032] Reference Figure 2 , Figure 2 This is a flow chart of the first embodiment of the storage sharing method of the present application. The method is applied to a first processor, the first processor is applied to a processing system, the processing system includes at least two processors and a memory, the at least two processors include a first processor and a second processor, the first processor is connected to the second processor, the second processor is connected to the memory, and the system architecture of the first processor includes a virtual memory layer and a first transport layer. The method includes but is not limited to the following steps.

[0033] S11: Obtain a first block of request instructions. The first block of request instructions is obtained by a first processor through structural transformation of the first request instructions to obtain a first block structure, and then generated based on the first block structure. The first request instruction is used to operate the memory.

[0034] The first request instruction is a request instruction issued by the user layer. The instruction is processed by structural conversion to obtain a first block structure. The first block structure includes relevant parameters corresponding to the operation of the first request instruction. The first block structure may include a bio structure. The first block request instruction is obtained based on the first block structure. The first block request instruction can be merged from the first block structure into an existing request instruction, or a new request instruction can be created to carry or include the information in the first block structure.

[0035] S12: transmitting the first block of request instructions to the virtual memory layer, parsing and reconstructing the first block of request instructions to generate reconstructed request instructions.

[0036] In the system, the first processor transmits the obtained first block of request instructions to the virtual memory layer, and parses and reconstructs the first block of request instructions in the virtual memory layer to obtain a reconstructed request instruction. The purpose of parsing and reconstructing is to parse out the key data to be transmitted, and then reconstruct the instruction based on the key data. The transmitted key data may include the type, offset, size, data, etc. of the request instruction.

[0037] S13: Transmit the reconstruction request instruction to the first transmission layer, and construct request information based on the reconstruction request instruction and the preset transmission protocol.

[0038] After reconstruction, the reconstruction request instruction is transmitted to the first transmission layer, and the request information is constructed in the first transmission layer. The reconstruction request instruction needs to be constructed into a format suitable for the transmission protocol in the transmission layer, so as to be transmitted on the transmission line between the first processor and the second processor.

[0039] S14: Send the request information to the second processor, so that the second processor processes the request information and implements an operation on the memory corresponding to the first request instruction.

[0040] S15: Receive response information sent by the second processor, where the response information includes feedback information corresponding to the first request instruction.

[0041] The request information is used to exchange information with the second processor. The first processor sends the request information to the second processor through the transmission interface and the external transmission line (or external transmission device), and obtains the response information sent by the second processor based on the request information.

[0042] In this embodiment, a virtual memory layer and a first transmission layer are constructed in the system architecture of the first processor, and the first block of request instructions obtained from the first request instruction is transmitted to the virtual memory layer for parsing and reconstruction to obtain a reconstructed request instruction, and then the reconstructed request instruction is transmitted to the first transmission layer to construct request information according to a preset transmission protocol, so that the request information can be sent to the second processor according to the preset transmission protocol, so that the second processor can implement the operation of the memory corresponding to the first request instruction based on the request information, thereby enabling the first processor to use the memory connected to the second processor, realizing storage sharing, and reducing system construction costs.

[0043] In some embodiments, the method of the present application is applied to a Linux system.

[0044] In some embodiments, the logical address of the memory includes at least a first logical partition and a second logical partition, the first logical partition is used to store data related to the first processor, and the second logical partition is used to store data related to the second processor.

[0045] Reference Figure 3 , Figure 3 A schematic diagram of the memory logical address planning for this application. Figure 3 As shown, the logical address in the memory originally corresponds to one processor, namely the second processor. Its logical partitions may include small partitions such as preloader_2, Trustzone_2, LK_2, Boot_2, Recovery_2, System_2, Vendor_2, Data2, etc. Since the first processor and the second processor share storage, the logical addresses in the memory are replanned and divided into the first logical partition and the second logical partition. The first logical partition may include preloader_1, Trustzone_1, LK_1, Boot_1, Recovery_1, System_1, Vendor_1, Data1, and the second logical partition includes preloader_2, Trustzone_2, LK_2, Boot_2, Recovery_2, System_2, Vendor_2, Data2, etc. The second processor implements the operation on the first logical partition by receiving the request information sent by the first processor and combining the data related to the first processor in the first logical partition, so that the first processor performs the operation on the memory through the second processor.

[0046] By planning the partitions, the data processing flows of the first processor and the second processor are separated, thereby avoiding the complication of the data processing flow or data processing errors caused by mixed use of logical addresses.

[0047] In some embodiments, the first processor may also be connected to a memory, and the first processor places a portion of the corresponding logical partition in the memory connected to the second processor. Figure 4 , Figure 4 This is another schematic diagram of the memory logical address planning of the present application. Figure 4 In the embodiment, only the data logical address corresponding to the first processor is placed in the memory connected to the second memory.

[0048] In some embodiments, the system architecture of the first processor further includes a virtual file system layer, a mapping layer, and a general block layer. Figure 5 , Figure 5 This is a schematic diagram of the system architecture of the first processor of the present application. The virtual file system layer is used to receive the first request instruction and transmit the first request instruction to the mapping layer. The mapping layer is used to parse the first request instruction to obtain basic instruction information and perform structural transformation based on the basic instruction information to generate a first block structure. The general block layer generates a first block request instruction according to the first block structure, and then inputs the first block request instruction to the virtual memory layer.

[0049] Basic instruction information includes specific block device information, offset, request size, request type, data storage location and other information.

[0050] In some embodiments, the request information includes a request instruction code and context parameters. Figure 6 , Figure 6 This is a schematic diagram of the structure of the request information of this application. The context parameter is a parameter related to the request instruction code and is a parameter required to execute the corresponding request instruction.

[0051] In some embodiments, the request instruction code may include a transmission direction indication code, a transmission device indication code, and a command indication code. Figure 7 , Figure 7 The structure diagram of the request instruction code in the request information of this application. The transmission direction indicator code indicates the initialization direction of data transmission. The transmission device indicator code indicates the data device used for transmission. The request command indicator code indicates the corresponding request instruction.

[0052] After receiving the request information, the second processor will perform corresponding processing and then send corresponding response information to the first processor. The response information includes a response instruction code and feedback information. The response instruction code may include a transmission direction indication code, a transmission device indication code and a command indication code.

[0053] In some embodiments, each type of request information corresponds to a request instruction code, and the types of request information include data requests and non-data requests. Data requests include at least one of the following: read data requests, write data requests, and non-data requests include erase requests.

[0054] In some embodiments, the preset transmission protocol may include a Protocol data transmission protocol.

[0055] In some embodiments, before sending the request information, the first processor sends a handshake request to the second processor. The process includes but is not limited to the following steps.

[0056] The first processor sends a handshake request to the second processor, the handshake request includes a first preset sequence and first random data; receives a handshake response sent by the second processor, the handshake response includes a second preset sequence and second random data; compares the first random data and the second random data, and if they are the same, determines that the handshake is successful; in response to at least one successful handshake, determines that the communication connection between the first processor and the second processor is successfully established.

[0057] Multiple handshakes are performed to ensure the stability of the communication connection. After the communication connection is successfully established, the first processor sends a request message to the second processor.

[0058] The first preset sequence corresponds to the second preset sequence. The first preset sequence is a handshake request instruction code, including a transmission direction indication code, a transmission device indication code, and a handshake command indication code. The second preset sequence is a handshake response instruction code, including a transmission direction indication code, a transmission device indication code, and a handshake command indication code.

[0059] For example, the first processor sends "0x0001+random data" to the second processor to establish a handshake. 0x0001 is the first preset sequence.

[0060] After receiving the random data, the second processor returns "0x8001+random data" to the first processor, where 0x8001 is the second preset sequence. After receiving the random data, the first processor compares the random data sent to the second processor. If they are consistent, the handshake is defined as successful for the first time. If not, the handshake can be initiated again.

[0061] The above process is executed three times. If all three times are successful, the first processor and the second processor are connected successfully.

[0062] For different transmission devices, due to different transmission device indication codes, the corresponding first preset sequence and second preset sequence may be different.

[0063] If it is an SPI device transmission, then send "0x1001 + data" and return "0x9001 + data". If it is a PCIe device transmission, then send "0x2001 + data" and return "0xa001 + data". If it is a Uart device transmission, then send "0x3001 + data" and return "0xb001 + data". If it is a GMAC device transmission, then send "0x4001 + data" and return "0xc001 + data".

[0064] In some embodiments, after the request information is sent, the first processor sends an interrupt request to the second processor. The process includes but is not limited to the following steps.

[0065] The first processor sends an interrupt request to the second processor, the interrupt request includes a third preset sequence and third random data; receives a handshake response sent by the second processor, the interrupt response includes a fourth preset sequence and fourth random data; compares the third random data and the fourth random data, and if they are the same, determines that the interrupt is successful; in response to at least one successful interrupt, determines that the communication connection between the first processor and the second processor is successfully interrupted.

[0066] Multiple interruptions are performed to ensure the accuracy of the communication connection interruption. After the request information and the corresponding data transmission are completed, the first processor sends an interrupt request to the second processor.

[0067] The third preset sequence corresponds to the fourth preset sequence, the third preset sequence is an interrupt request instruction code, including a transmission direction indication code, a transmission device indication code and an interrupt command indication code. The fourth preset sequence is an interrupt response instruction code, including a transmission direction indication code, a transmission device indication code and an interrupt command indication code.

[0068] For example, the first processor sends "0x0003+random data" to the second processor to establish a handshake. 0x0003 is the third preset sequence.

[0069] After receiving the random data, the second processor returns "0x8003+random data" to the first processor, where 0x8003 is the fourth preset sequence. After receiving the random data, the first processor compares the random data sent to the second processor. If they are consistent, the interrupt is defined as successful for the first time. If not, the interrupt can continue to be initiated.

[0070] If the interruption is successful, it can be directly determined that the first processor and the second processor are disconnected, or the above process can be executed three times. If all three times are successful, the first processor and the second processor are disconnected successfully.

[0071] For different transmission devices, due to different transmission device indication codes, the corresponding third preset sequence and fourth preset sequence may be different.

[0072] If it is an SPI device transmission, then send "0x1003 + data", return "0x9003 + data". If it is a PCIe device transmission, then send "0x2003 + data", return "0xa003 + data". If it is a Uart device transmission, then send "0x3003 + data", return "0xb003 + data". If it is a GMAC device transmission, then send "0x4003 + data", return "0xc003 + data".

[0073] The first preset sequence and the third preset sequence are similar to the definition of the request instruction code, and the structure of the request instruction code can be referred to, except that in the first preset sequence and the third preset sequence, their respective command indication codes are fixed. The command indication code in the first preset sequence is a handshake command indication code, and the request command indication code in the third preset sequence is an interrupt command indication code.

[0074] The second preset sequence and the fourth preset sequence are similar to the definition of the response instruction code, and the structure of the above-mentioned response instruction code can be referred to, except that in the second preset sequence and the fourth preset sequence, their respective command indication codes are fixed. The command indication code in the second preset sequence is a handshake request command indication code, and the command indication code in the fourth preset sequence is an interrupt command indication code.

[0075] In some embodiments, the request information includes a request to write data. After sending the request information, the data to be written is then sent.

[0076] For example, the first processor sends "0x0200+parameters" to the second processor, and the parameters include: the boot area "boot1", "boot2", "user" where data is written to the memory; the starting address offset where data is written to the memory; and the data size where data is written to the memory.

[0077] The parameters may also include a verification requirement parameter for determining whether the written data requires a CRC check, where 0 indicates that the integrity of the received data is not required to be checked, and 1 indicates that the integrity of the received data is required to be checked.

[0078] If CRC check is required, the CRC value of this segment of data also needs to be included.

[0079] The parameters may also include a compression requirement parameter for determining whether the written data requires data compression, where 0 indicates that the transmitted data is uncompressed, and 1 indicates that the output data is compressed.

[0080] If data compression is required, the size of the data after compression must also be included.

[0081] Parameters may also include a maximum timeout for writing data.

[0082] The first processor sends the written data to the second processor, or sends the compressed data to the second processor.

[0083] After receiving the request information and data, the second processor parses the parameters. If the data is compressed, it first decompresses the data, and finally writes the data corresponding to the data size into the memory and sends "0x8200+Result", where the feedback information Result includes the result of writing the data. 0 means success, non-0 means failure.

[0084] If it is an SPI device transmission, then send "0x1200 + parameter" and return "0x9200 + Result". If it is a PCIe device transmission, then send "0x2200 + parameter" and return "0xa200 + Result". If it is a Uart device transmission, then send "0x3200 + parameter" and return "0xb200 + Result". If it is a GMAC device transmission, then send "0x4200 + parameter" and return "0xc200 + Result".

[0085] In some embodiments, the request information includes a read data request. After sending the response information, the second processor then sends the data that needs to be read by the first processor.

[0086] For example, the first processor sends "0x0100+parameters" to the second processor, and the parameters include: the read data in the boot area "boot1", "boot2", "user" of the memory; the starting address offset of the data in the memory; and the data size of the data in the memory.

[0087] The parameters may also include a verification requirement parameter for determining whether the written data requires a CRC check, where 0 indicates that the integrity of the received data is not required to be checked, and 1 indicates that the integrity of the received data is required to be checked.

[0088] If CRC check is required, the CRC value of this segment of data also needs to be included.

[0089] The parameters may also include a compression requirement parameter for determining whether the written data requires data compression, where 0 indicates that the transmitted data is uncompressed, and 1 indicates that the output data is compressed.

[0090] If data compression is required, the size of the data after compression must also be included.

[0091] The parameters can also include a maximum timeout for reading data.

[0092] After receiving the request information, the second processor parses the parameters, reads the data corresponding to the data size from the memory, and sends "0x8100+Result", where the feedback information Result includes the following: the result of reading the data. 0 indicates success, and non-0 indicates failure; if the read data requires CRC check, the CRC value of this segment of data is returned; if the read data requires data compression, the compressed data size is returned; if data compression is not required, the actual data size of the data is returned.

[0093] If the result of the second processor reading the data is a failure, a failure message is fed back and the process ends.

[0094] If the result of the second processor reading the data is successful, the read data or the compressed read data is sent to the first processor.

[0095] If it is SPI device transmission, then send "0x1100 + parameter", return "0x9100 + Result". If it is PCIe device transmission, then send "0x2100 + parameter", return "0xa100 + Result". If it is Uart device transmission, then send "0x3100 + parameter", return "0xb100 + Result". If it is GMAC device transmission, then send "0x4100 + parameter", return "0xc100 + Result".

[0096] In some embodiments, the request information includes an erase request.

[0097] For example, the first processor initiates "0x0002+parameters" to the second processor, and the parameters include: the boot area "boot1", "boot2", "user" of the erased data in the memory; the starting address offset of the erased data in the memory; the data size of the erased data in the memory; and the maximum timeout of the erase.

[0098] After receiving the request information, the second processor parses the parameters, performs the erase operation, and returns "8002+Result" to the first processor. The first processor parses the feedback information Result to confirm whether the operation is successfully executed.

[0099] If it is SPI device transmission, then send "0x1002+parameters" and return "0x9002+result". If it is PCIe device transmission, then send "0x2001+parameters" and return "0xa002+result". If it is Uart device transmission, then send "0x3002+parameters" and return "0xb002+result". If it is GMAC device transmission, then send "0x4002+parameters" and return "0xc002+result".

[0100] Reference Figure 8 , Figure 8 This is a flow chart of the second embodiment of the storage sharing method of the present application. The method is applied to a second processor. The second processor is applied to a processing system, the processing system includes at least two processors and a memory, the at least two processors include a first processor and a second processor, the first processor is connected to the second processor, the second processor is connected to the memory, and the system architecture of the second processor includes a remapping layer and a second transmission layer. The method includes but is not limited to the following steps.

[0101] S21: receiving request information sent by a first processor, where the request information is obtained by the first processor performing structural transformation on a first request instruction, where the first request instruction is used to operate a memory.

[0102] S22: Input the request information into the second transmission layer, parse and reconstruct the request information based on the request information and the preset transmission protocol to generate a second request instruction, where the second request instruction corresponds to the first request instruction.

[0103] After receiving the request information sent by the first processor, the request information will be transmitted to the second transmission layer for parsing. The request information will be parsed and reconstructed into a second request instruction in the second transmission layer, corresponding to the first request instruction, and used to implement the operation corresponding to the first request instruction on the memory.

[0104] S23: Input the second request instruction to the remapping layer, parse the second request instruction to obtain basic instruction information, and perform structural transformation based on the basic instruction information to generate a second block structure.

[0105] The second request instruction is a request instruction reconstructed to conform to the request instruction structure in the second processor system architecture. The second request instruction is transmitted to the remapping layer for processing to obtain a second block structure. The basic instruction information includes specific block device information, offset, request size, request type, data storage location and other information. The second block structure may include a bio structure.

[0106] S24: Process the second block structure, generate feedback information according to the processing result, and generate response information based on the feedback information.

[0107] S25: Send the response information to the first processor.

[0108] The second processor processes the second block structure to obtain corresponding response information and sends it to the first processor. In some embodiments, the response information is sent to the first transmission layer of the first processor via the second transmission layer.

[0109] In some embodiments, the system architecture of the second processor further includes a general block layer and a memory driver layer. Fig. 9 , Fig. 9 The schematic diagram of an embodiment of the system architecture of the second processor of the present application. Processing the second block structure and generating feedback information according to the processing result includes: inputting the second block structure to the general block layer to generate a second block request instruction; inputting the second block request instruction to the memory driver layer to generate a memory operation instruction; sending the memory operation instruction to the memory to obtain the processing result after the memory executes the operation; and generating feedback information according to the processing result.

[0110] The second block of request instructions is obtained based on the second block structure. The second block of request instructions can be merged into the existing request instructions by the second block structure, or a new request instruction is created to carry or include the information in the second block structure.

[0111] In some embodiments, the system architecture of the second processor further includes a virtual file system layer and a mapping layer. Fig.10 , Fig.10 This is a schematic diagram of another embodiment of the system architecture of the second processor of the present application. The virtual file system layer is used to receive the third request instruction and transmit the third request instruction to the mapping layer. The mapping layer is used to parse the third request instruction to obtain basic instruction information, and perform structural transformation based on the basic instruction information to generate a third block structure. The third block structure is used to input to the general block layer to generate a third block request instruction. The third block request instruction is input to the memory driver layer to generate a memory operation instruction, and the memory operation instruction is sent to the memory to implement the operation on the memory.

[0112] The virtual file system layer and the mapping layer in the second processor are used to process the third request instruction sent by the user layer corresponding to the second processor.

[0113] Similar contents may refer to the above processing flow for the first request instruction.

[0114] In some embodiments, the logical address of the memory includes at least a first logical partition and a second logical partition, the first logical partition is used to store data related to the first processor, and the second logical partition is used to store data related to the second processor.

[0115] In some embodiments, the response information includes a response instruction code and feedback information.

[0116] In some embodiments, the response instruction code may include a transmission direction indication code, a transmission device indication code, and a command indication code. The transmission direction indication code indicates the initialization direction of data transmission. The transmission device indication code indicates the data device used for transmission. The command indication code is the same as the command indication code in the corresponding request information, that is, if the response information is a response to the A request information, the response instruction code is the same as the command instruction code in the A request information.

[0117] For other similar contents, please refer to the description in the above embodiments, which will not be repeated here.

[0118] Reference Fig.11 , Fig.11 This is a schematic diagram of the structure of the first embodiment of the sharing device of the present application.

[0119] The sharing device includes an information acquisition module, a virtual storage module and a first transmission module.

[0120] The information acquisition module is used to acquire a first block of request instructions. The first block of request instructions is obtained by the sharing device through structural transformation of the first request instructions to obtain a first block of structures, and then generated based on the first block of structures. The first request instructions are used to operate the memory.

[0121] The virtual storage module is used to parse and reconstruct the first block of request instructions to generate a reconstruction request instruction.

[0122] The first transmission module is used to construct request information based on the reconstruction request instruction and the preset transmission protocol, send the request information to another shared device so that the other shared device processes the request information, implements the operation on the memory corresponding to the first request instruction, and receives response information sent by the other shared device, the response information includes feedback information corresponding to the first request instruction.

[0123] In some embodiments, the above-mentioned sharing device is connected to another sharing device, and the other sharing device is connected to a storage device.

[0124] In some embodiments, the above-mentioned sharing device may also be connected to a storage device.

[0125] In some embodiments, the logical address of the memory connected to another shared device includes at least a first logical partition and a second logical partition, the first logical partition is used to store data related to the shared device, and the second logical partition is used to store data related to another shared device.

[0126] In some embodiments, the information acquisition module includes a virtual file system module, a mapping module and a common block module. The virtual file system module is used to receive a first request instruction and transmit the first request instruction to the mapping module. The mapping module is used to parse the first request instruction to obtain basic instruction information, and perform structural transformation based on the basic instruction information to generate a first block structure. The common block module is used to generate a first block request instruction based on the first block structure.

[0127] The same or similar descriptions in this embodiment can refer to the descriptions in the above embodiments and will not be repeated here.

[0128] Reference Fig.12 , Fig.12This is a schematic diagram of the structure of the second embodiment of the sharing device of the present application.

[0129] The sharing device includes a second transmission module, a remapping module, and an information processing module.

[0130] A second transmission module is used to receive request information sent by another sharing device, parse and reconstruct the request information based on the request information and a preset transmission protocol to generate a second request instruction, the request information is generated based on the first block structure after another sharing device performs structural transformation on the first request instruction, the first request instruction is used to operate the memory, and the second request instruction corresponds to the first request instruction;

[0131] A remapping module, used for parsing the second request instruction to obtain basic instruction information, and performing structural transformation based on the basic instruction information to generate a second block structure;

[0132] The information processing module is used to process the second block structure, generate feedback information according to the processing result, and send the feedback information to the second transmission module, so that the second transmission module generates response information based on the feedback information and sends the response information to another shared device. The second transmission module constructs the response information according to the feedback information and a preset transmission protocol.

[0133] In some embodiments, the sharing device is connected to a storage device, and the sharing device is also connected to another sharing device.

[0134] In some embodiments, another shared device is also connected to the storage.

[0135] In some embodiments, the logical address of the memory connected to the shared device includes at least a first logical partition and a second logical partition, the first logical partition is used to store data related to another shared device, and the second logical partition is used to store data related to the shared device.

[0136] In some embodiments, the information processing module further includes a general block module and a memory driver module. The general block module generates a second block request instruction according to the second block structure. The memory driver module generates a memory operation instruction according to the second block request instruction. The memory driver module sends the memory operation instruction to the memory. Then the information processing module obtains the processing result after the memory executes the operation, and further generates feedback information according to the processing result.

[0137] In some embodiments, the sharing device further includes an information acquisition module, which includes a virtual file system module and a mapping module. The virtual file system module is used to receive a third request instruction and transmit the third request instruction to the mapping module, and the third request instruction is used to operate the memory. The mapping module is used to perform structural transformation on the third request instruction to generate a third block structure, and then generate a third block request instruction based on the third block structure, and the third block request instruction is used to be input into the general block module, and the memory is operated based on the third block request instruction.

[0138] The same or similar descriptions in this embodiment can refer to the descriptions in the above embodiments and will not be repeated here.

[0139] Reference Fig.13 , Fig.13 This is a schematic diagram of the structure of an embodiment of a processing system of the present application. The processing system includes at least two processors and a memory, the at least two processors include a first processor and a second processor, the first processor is connected to the second processor, the second processor is connected to the memory, the system architecture of the first processor includes a virtual memory layer and a first transmission layer, the system architecture of the second processor includes a remapping layer and a second transmission layer, and the first processor establishes a communication connection with the second processor to implement any one of the methods in the above embodiments.

[0140] Reference Fig.14 , Fig.14 The schematic diagram of the structure of another embodiment of the processing system of the present application is shown in FIG. 1 , wherein the first processor further includes a virtual file system layer, a mapping layer and a common block layer. The second processor further includes a common block layer, a memory driver layer, a virtual file system layer and a mapping layer.

[0141] In the transmission protocol used in this application, in order to ensure the integrity of data transmission, a CRC check mechanism, a timeout detection mechanism, an error retransmission mechanism, etc. can be designed.

[0142] In the CRC verification mechanism, the CRC value calculated by the receiving end is compared with the CRC value of the sending end. If they are consistent, the data is complete; if they are inconsistent, the data is incomplete.

[0143] In the timeout detection mechanism, a maximum timeout is designed in erase requests, read data requests, write data requests, etc. If the second processor exceeds the maximum time when executing an operation, the feedback information is a time error and a starvation problem is requested.

[0144] In the error retransmission mechanism, for example, if the data is incomplete or the time is wrong, the request information that failed last time will be resent, and the maximum number of retransmissions can be defined.

[0145] In order to ensure data transmission performance, compressed transmission and support for multiple transmission devices can be designed.

[0146] Data compression can effectively reduce transmission time.

[0147] Supporting multiple transmission devices means that the transmission connection between the first processor and the second processor can support multiple devices at the same time, that is, the connection between the first transmission layer and the second transmission layer can support multiple devices at the same time, and the first processor and the second processor can improve the transmission performance through the transmission combination of different transmission devices.

[0148] If multiple device transmissions such as USB, SPI, PCIe, Uart, GMAC are supported, simultaneous transmission can be achieved. For example, transmission requests can be completed on two transmission devices at the same time. For example, if there are two data requests, the USB device executes one data request, and the PICe device executes another data request at the same time.

[0149] The transmission performance of transmission devices is different, and corresponding requests can be configured accordingly. There are high-speed devices, such as USB / PCIe / GMAC, and low-speed devices, such as SPI / Uart. You can configure low-speed devices to send non-data requests and high-speed devices to send data requests.

[0150] You can also configure a low-speed device to send a data request with a smaller data volume, and configure a high-speed device to send a data request with a larger data volume.

[0151] In the present application, the connection between the first processor and the second processor can be a board-level connection or a pin-to-pin connection inside the chip. Board-level connection is to connect the processors on the board using physical signal lines such as USB, SPI, UART, PCIe, GMAC, etc., which will occupy board-level layout resources.

[0152] The second processor may also be connected to multiple first processors. Each first processor may be connected to a corresponding memory or may not be connected to a memory. The first processor may place part or all of the logical partitions in a memory connected to the second processor.

[0153] like Fig.15 As shown, Fig.15 This is a schematic structural diagram of the first embodiment of the electronic device of the present application.

[0154] The electronic device includes a processor 110 .

[0155] The processor 110 controls the operation of the electronic device, and the processor 110 may also be referred to as a CPU (Central Processing Unit). The processor 110 may be an integrated circuit chip having the ability to process a signal sequence. The processor 110 may also be a general-purpose processor, a digital signal sequence processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a system on a chip (SOC) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0156] The processor 110 is used to execute instructions to implement the method provided by any one of the embodiments and possible combinations of the first embodiment of the storage sharing method in the present application.

[0157] Reference Fig.16 , Fig.16 This is a schematic diagram of the structure of the second embodiment of the electronic device of the present application. The electronic device may further include a memory 120 .

[0158] like Fig.17 As shown, Fig.17 This is a schematic structural diagram of the third embodiment of the electronic device of the present application.

[0159] The electronic device includes a processor 210 and a memory 220 .

[0160] The processor 210 controls the operation of the electronic device, and the processor 210 may also be referred to as a CPU (Central Processing Unit). The processor 210 may be an integrated circuit chip having the ability to process a signal sequence. The processor 210 may also be a general-purpose processor, a digital signal sequence processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a system on a chip (SOC) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0161] The memory 220 stores instructions and program data required for the processor 210 to operate.

[0162] The processor 210 is used to execute instructions to implement the method provided by any embodiment and possible combination of the second embodiment of the storage sharing method in the present application.

[0163] To summarize, a virtual memory layer and a first transmission layer are constructed in the system architecture of the first processor, and the first block of request instructions obtained by the first request instruction is transmitted to the virtual memory layer for parsing and reconstruction to obtain a reconstructed request instruction, and then the reconstructed request instruction is transmitted to the first transmission layer to construct request information according to a preset transmission protocol, so that the request information can be sent to the second processor according to the preset transmission protocol, so that the second processor can implement the operation of the memory corresponding to the first request instruction based on the request information, thereby enabling the first processor to use the memory connected to the second processor, realizing storage sharing, and reducing the system construction cost.

[0164] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation described above is only illustrative, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0165] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0166] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0167] If the integrated units in the above other embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk and other media that can store program codes.

[0168] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A storage sharing method, characterized in that: The method is applied to a first processor, the first processor is applied to a processing system, the processing system includes at least two processors and a memory, the at least two processors include the first processor and a second processor, the first processor is connected to the second processor, the second processor is connected to the memory, the system architecture of the first processor includes a virtual memory layer and a first transmission layer, the method includes: Obtaining a first block request instruction, where the first processor performs structural transformation on the first request instruction to obtain a first block structure, and then generates based on the first block structure, where the first request instruction is used to operate the memory; transmitting the first block request instruction to the virtual memory layer, parsing and reconstructing the first block request instruction to generate a reconstruction request instruction; Transmitting the reconstruction request instruction to the first transmission layer, and constructing request information based on the reconstruction request instruction and a preset transmission protocol; Sending the request information to the second processor, so that the second processor processes the request information and implements an operation on the memory corresponding to the first request instruction; Receive response information sent by the second processor, where the response information includes feedback information corresponding to the first request instruction.

2. The method according to claim 1, characterized in that The logical address of the memory includes at least a first logical partition and a second logical partition, the first logical partition is used to store data related to the first processor, and the second logical partition is used to store data related to the second processor.

3. The method according to claim 1, characterized in that The system architecture of the first processor also includes a virtual file system layer, a mapping layer and a common block layer. The virtual file system layer is used to receive the first request instruction and transmit the first request instruction to the mapping layer. The mapping layer is used to parse the first request instruction to obtain basic instruction information, and perform structural transformation based on the basic instruction information to generate a first block structure. The common block layer is used to generate the first block request instruction according to the first block structure.

4. A storage sharing method, characterized in that: The method is applied to a second processor, the second processor is applied to a processing system, the processing system includes at least two processors and a memory, the at least two processors include a first processor and the second processor, the first processor is connected to the second processor, the second processor is connected to the memory, the system architecture of the second processor includes a remapping layer and a second transmission layer, the method includes: receiving request information sent by the first processor, the request information being generated by the first processor performing structural transformation on a first request instruction to obtain a first block structure, and then based on the first block structure, the first request instruction being used to operate the memory; Input the request information into the second transmission layer, parse and reconstruct the request information based on the request information and a preset transmission protocol to generate a second request instruction, where the second request instruction corresponds to the first request instruction; Inputting the second request instruction into the remapping layer, parsing the second request instruction to obtain basic instruction information, and performing structural transformation based on the basic instruction information to generate a second block structure; Processing the second block structure, generating feedback information according to the processing result, and generating response information based on the feedback information; The response information is sent to the first processor.

5. The method according to claim 4, characterized in that The system architecture of the second processor further includes a general block layer and a memory driver layer, and the processing of the second block structure and generating feedback information according to the processing result includes: inputting the second block structure into the common block layer to generate a second block request instruction; Inputting the second block request instruction to the memory driver layer to generate a memory operation instruction; Sending the memory operation instruction to the memory to obtain a processing result after the memory executes the operation; Feedback information is generated according to the processing result.

6. The method according to claim 5, characterized in that The system architecture of the second processor also includes a virtual file system layer and a mapping layer. The virtual file system layer is used to receive a third request instruction and transmit the third request instruction to the mapping layer. The third request instruction is used to operate the memory. The mapping layer is used to perform structural transformation on the third request instruction to generate a third block structure. The third block structure is used to be input into the general block layer to generate a third block request instruction.

7. The method according to claim 6, characterized in that The logical address of the memory includes at least a first logical partition and a second logical partition, the first logical partition is used to store data related to the first processor, and the second logical partition is used to store data related to the second processor.

8. A sharing device, characterized in that: include: an information acquisition module, configured to acquire a first block of request instructions, wherein the first block of request instructions is generated by the sharing device performing structural transformation on the first request instruction to obtain a first block structure, and then based on the first block structure, wherein the first request instruction is used to operate the memory; A virtual storage module, used for parsing and reconstructing the first block of request instructions to generate a reconstruction request instruction; A first transmission module is used to construct request information based on the reconstruction request instruction and a preset transmission protocol, and send the request information to another shared device, so that the other shared device processes the request information, implements the operation on the memory corresponding to the first request instruction, and receives response information sent by the other shared device, wherein the response information includes feedback information corresponding to the first request instruction.

9. A sharing device, characterized in that: include: a second transmission module, configured to receive request information sent by another sharing device, parse and reconstruct the request information based on the request information and a preset transmission protocol to generate a second request instruction, wherein the request information is generated based on the first block structure after the first request instruction is structurally transformed by the other sharing device, wherein the first request instruction is used to operate the memory, and the second request instruction corresponds to the first request instruction; a remapping module, configured to parse the second request instruction to obtain basic instruction information, and perform structural transformation based on the basic instruction information to generate a second block structure; An information processing module is used to process the second block structure, generate feedback information according to the processing result, and send the feedback information to the second transmission module, so that the second transmission module generates response information based on the feedback information and sends the response information to the other shared device.

10. A processing system, characterized in that: The processing system includes at least two processors and a memory, the at least two processors include a first processor and a second processor, the first processor is connected to the second processor, the second processor is connected to the memory, the system architecture of the first processor includes a virtual memory layer and a first transmission layer, the system architecture of the second processor includes a remapping layer and a second transmission layer, and the first processor and the second processor establish a communication connection to implement any one of claims 1-7.

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