Random excitation generation method, system and equipment for chip verification test

Abstract

The invention discloses a random excitation generation method, system and device for a chip verification test, and relates to the technical field of chip verification, and the method comprises the steps: determining the priority of all variables in excitation according to the constraint condition of excitation needed by a to-be-tested chip verification test case; whether inequality constraints exist in the constraint conditions or not is detected, if yes, the inequality constraints are equivalently replaced with a unified representation form, then subsequent steps are executed, and if not, the subsequent steps are directly executed; on the basis of the priorities of the variables, intersection of all the related constraints of each variable in the constraint conditions is solved, all the related constraints of each variable are converted into a range constraint, and thus an optimized constraint condition is generated; and on the basis of the optimized constraint conditions, according to the priorities of the variables, the random excitation required by the verification test case of the to-be-tested chip is obtained through successive stochastic operation from high to low.

Description

Technical Field

[0001] The present application belongs to the field of chip verification technology, and specifically relates to a random stimulus generation method, system and device for chip verification testing. Background Art

[0002] In chip verification technology, one of the core functions of the verification platform is to generate random stimuli and input the random stimuli into the object under test, so as to evaluate the performance or quality of the object under test by monitoring the difference between the output of the object under test and the expected output.

[0003] At present, as the scale of chips continues to increase, the scale of test cases is also increasing, and the number and range of random excitation points are also expanding. If only stimuli are generated without effective constraints on the stimuli, the verification time will be greatly increased, even exponentially, until the final result cannot be obtained. It may also generate a lot of invalid stimuli, which consumes verification time and reduces the efficiency of chip verification. Therefore, in chip verification, it is necessary not only to generate stimuli, but also to constrain them. In practical applications, the constraints of random stimuli can be divided into the following categories according to whether the range is determined: One is the constant range constraint, for example: a: [1:100] / / a is randomly between 1 (inclusive) and 100 (inclusive); b: [100:3000] / / b is randomly between 100 (inclusive) and 3000 (inclusive); c: [90:700] / / c is randomly between 90 (inclusive) and 700 (inclusive); As shown in the above example, this constraint causes the variables to be randomly distributed within their respective ranges, and there is no correlation between the variables, and they are independent of each other.

[0004] The second is the variable expression range constraint, for example: a: [-100: b+c] / / a is random between -100 (inclusive) and b+c (inclusive); b: [64:1522-c] / / b is randomly between 64 (inclusive) and 1522-c (inclusive); c: [2:100] / / c is randomly between 2 (inclusive) and 100 (inclusive); As shown in the above example, the variables in this constraint are related to and constrained by each other.

[0005] The third is the inequality constraint, for example: a+b+3c<=300 / / The random result must satisfy this inequality; a+b>=100 / / The random result must satisfy this inequality; As shown in the above example, the variables of this constraint no longer change independently, but are constrained to each other in the random process.

[0006] In actual application, the constraints of random excitation are any combination of the above three constraint forms. It should be noted that the variable elements in chip verification have fixed data types, and the input excitations are all integers or combinations of integers. Decimals or other types of data can be obtained through integer conversion.

[0007] The existing constraint-based random stimulus generation technology mainly includes: (1) first randomize according to the range, then bring in the constraint conditions, if they are satisfied, the randomization succeeds, if they are not satisfied, the randomization fails, and then randomizes until it succeeds; however, when the constraint conditions are complex, this method may require a lot of randomization to obtain a compliant solution, which consumes a lot of verification time and reduces chip verification efficiency. (2) first randomize according to the range, then bring in the random results into the constraint conditions, if they are satisfied, the randomization succeeds, if they are not satisfied, the correction algorithm is used to correct the results to satisfy the constraint conditions; however, this method requires a separate correction algorithm to be designed for each constraint condition, and when the constraints are complex or dynamically changing, the algorithm design difficulty and execution complexity are significantly increased. Summary of the invention

[0008] In order to solve the problems existing in random technology under existing constraints, the present application proposes a random stimulus generation method, system and device for chip verification testing.

[0009] This application is implemented through the following technical solutions: A random stimulus generation method for chip verification testing, the method comprising: Determine the priority of all variables in the stimulus according to the constraint conditions of the stimulus required by the test case for verifying the chip under test; the constraint conditions include at least one of a constant range constraint, a variable expression range constraint and an inequality constraint; Detect whether there is an inequality constraint in the constraint condition, if yes, replace the inequality constraint with a unified representation and then execute the subsequent steps, otherwise directly execute the subsequent steps; the unified representation of the inequality constraint is a form represented by ">=" and / or "<="; Based on the priority of the variables, all the related constraints of each variable in the constraint condition are intersected, and all the related constraints of each variable are converted into a range constraint, thereby generating an optimized constraint condition; Based on the optimized constraint conditions, the variables are randomly assigned from high to low priorities, thereby obtaining the random stimulus required for the verification test case of the chip under test.

[0010] In some implementations, the priority of the variables is determined as follows: The variables are prioritized according to the range constraints in the constraints. The following conditions must be met during the sorting process: The priority of the relying party is lower than that of the relied party; The principle that independent changes have the highest priority; When two or more variables have the same priority, they are sorted in alphabetical order; When a dependency loop occurs, the entire random constraint has no solution, and feedback is sent to the client to modify the requirements; When a variable appears to be dependent on itself, the entire random constraint has no solution, and feedback is then given to the client to modify the requirements.

[0011] In some implementations, the priority of the variables is based on finding the intersection of all the related constraints of each variable in the constraint condition, converting all the related constraints of each variable into a range constraint, thereby generating the optimized constraint condition, specifically including: According to the constraint conditions, new inequality constraints are generated by simplification, and the generated new inequality constraints are substituted into the range constraints of the constraint conditions to obtain the first simplification result; Simplifying to generate new inequality constraints according to the first simplification result, substituting the generated new inequality constraints into the first simplification result to obtain a second simplification result; This process continues until no new inequality constraints can be generated by simplification. The simplification ends and the result of the last simplification is used as the optimized constraint condition. Among them, in each simplification process, low priority must depend on high priority.

[0012] In some implementations, the step of finding the intersection of all related constraints of each variable in the constraint condition based on the priority of the variable, converting all related constraints of each variable into a range constraint, thereby generating the optimized constraint condition, further includes: In each simplification process, the inequality constraints that always hold true are discarded.

[0013] In some implementations, the step of finding the intersection of all related constraints of each variable in the constraint condition based on the priority of the variable, converting all related constraints of each variable into a range constraint, thereby generating the optimized constraint condition, further includes: When an inequality constraint that is never true appears during the simplification process, feedback is given to the client to modify the requirements.

[0014] In some implementations, the optimization-based constraint conditions are randomly selected from high to low priority variables, specifically including: Randomize the variable with the highest priority to obtain the random value of the variable with the highest priority; Based on the random value of the edge with the highest priority, the variable with the second highest priority is randomized to obtain the random value of the variable with the second highest priority, and so on, to obtain the random values ​​of all variables in sequence.

[0015] In some implementations, before the step of determining the priority of all variables in the stimulus according to the constraint conditions of the stimulus required for the chip to be tested verification test case, the step further includes: It is detected whether there is an "or" constraint in the constraint conditions. If so, the constraint conditions are split into parallel constraint conditions, and a group of constraint conditions are randomly selected from the parallel constraint conditions for subsequent processing.

[0016] In a second aspect, the present application proposes a random stimulus generation system for chip verification testing, the system comprising: A priority sorting unit, wherein the priority sorting unit determines the priority of all variables in the stimulus according to the constraint conditions of the stimulus required for the verification test case of the chip to be tested; the constraint conditions include at least one of a constant range constraint, a variable expression range constraint and an inequality constraint; A normalization unit, the normalization unit is used to detect whether there is an inequality constraint in the constraint condition, if yes, then drive the simplification conversion unit to work after all inequality constraints are equivalently replaced with a unified representation form, otherwise directly drive the simplification conversion unit to work; the unified representation form of the inequality constraint is a form represented by ">=" and / or "<="; A simplification conversion unit, wherein the simplification conversion unit obtains the intersection of all related constraints of each variable in the constraint condition based on the priority of the variable, converts all related constraints of each variable into a range constraint, thereby generating an optimized constraint condition; And, a first random unit, which is based on the optimized constraint conditions and is randomized successively according to the priority of the variables from high to low, so as to obtain the random stimulus required for the verification test case of the chip under test.

[0017] In some embodiments, the system further comprises: a splitting unit, wherein when detecting that an "or" constraint exists in the constraint condition, the splitting unit splits the constraint condition into parallel constraint conditions; and, a second random unit, which randomly selects a set of inputs from the parallel constraints to the priority ranking unit.

[0018] In a third aspect, the present application proposes a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0019] The present application proposes a random stimulus generation method, system and device for chip verification testing. According to the range constraints in the constraint conditions, the priority of each variable is determined, and all constraints in the constraint conditions are simplified to obtain the intersection, and all relevant constraints of each variable in the constraint conditions are converted into a range constraint, so as to obtain a constraint condition consisting only of the range constraints of each variable. After that, random values ​​of all variables are obtained directly by performing random operations one by one according to the priority, without repeated random operations or setting additional revision algorithms, thus avoiding large consumption of CPU and memory, and improving computing efficiency and chip testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the embodiments of the present application, constitute a part of the present application, and do not constitute a limitation on the embodiments of the present application. In the drawings: Figure 1 A schematic diagram of the flow chart of the random excitation generation method proposed in the embodiment of the present application; Figure 2 This is a diagram of the measured results of the embodiment of the present application; Figure 3 This is a functional block diagram of the random excitation generation system proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with examples and drawings. The illustrative implementation scheme of the present application and its description are only used to explain the present application and are not intended to limit the present application.

[0022] Embodiment: On the one hand, the existing random stimulus generation technology under constraint conditions cannot determine in advance whether the constraint has a solution. It can only give a conclusion on whether it has a solution after repeated iterative calculations during the actual execution process. The repeated iterative calculation process is very time-consuming and requires a large amount of CPU and memory. On the other hand, the use of optimization algorithms to revise the random results to meet the constraint conditions requires the design of additional complex algorithms, which also requires a large amount of CPU and memory. In view of this, this embodiment proposes a random stimulus generation method for chip verification testing.

[0023] Specific as Figure 1 As shown, the method proposed in this embodiment includes the following steps: Step 1, according to the constraints of the stimulus required by the test case for verifying the chip under test, determine the priority of all variables in the stimulus. The variable described in this embodiment is an element that represents the element used to generate the stimulus signal, which can generate the stimulus signal independently or in combination with other variables. For example, when verifying an adder, the variable can directly generate the stimulus signal; while when verifying a network card, dozens of variables may be required to combine to generate the stimulus signal.

[0024] Step 2, check whether there is an inequality constraint in the constraint condition, if so, replace the inequality constraint with a unified representation and then execute the subsequent steps, otherwise directly execute the subsequent steps. Among them, the constraint conditions of the verification stimulus required for the chip verification test case include at least one of the constant range constraint, variable expression range constraint, and inequality constraint, and the comparison symbols that can be used in the inequality constraint include "==", ">", ">=", "<", "<=", "!=", etc., and the inequality constraint is an and relationship, that is, the random result needs to satisfy all the inequality constraints, which is convenient for subsequent simplification. First, the inequality constraints represented by different comparison symbols are converted into a unified representation of ">=" and / or "<=". Of course, if it is represented by ">=" or "<=", there is no need to perform equivalent replacement. For example, X+Y==m is equivalent to X+Y>=m and X+Y<=m; X+Y>n is equivalent to X+Y>=n+1; X+Y<1 is equivalent to X+Y<=0; X+Y!=m is equivalent to X+Y<20 || X+Y>20, which is equivalent to X+Y<=19|| X+Y>=21.

[0025] Step 3, based on the priority of the variable, find the intersection of all relevant constraints of each variable in the constraint condition, convert all relevant constraints of each variable into a range constraint, and thus generate the optimized constraint condition.

[0026] Step 4: Based on the optimized constraint conditions, randomize the variables from high to low priority to obtain the random stimulus required for the verification test case of the chip under test.

[0027] In an optional implementation, step 1 specifically performs variable priority sorting according to the range constraints (including constant range constraints and variable expression range constraints) in the constraint conditions, which needs to satisfy: (1) The priority of the relying party is lower than that of the relying party; (2) The principle that independent changes have the highest priority; (3) When two or more variables have the same priority, they are sorted in alphabetical order; (4) When a dependency loop occurs, the entire random constraint has no solution, and feedback is sent to the client to modify the requirements. (5) The variable cannot depend on itself, otherwise the entire random constraint will have no solution. At this time, feedback is given to the client to modify the requirements.

[0028] For example, the verification stimulus required for test case 1 includes three variables a, b, and c, and its constraints include: a : [-100 : b + c] b : [64 : 1522 - c] c : [2 : 100] a + b + 3c <= 300 a + b>= 100 From the above records, it can be seen that the constraints of the verification stimulus required for this test case 1 include range constraints and inequality constraints. Among them, according to the range constraints, it can be determined that: According to a : [-100 : b + c], a depends on b and c; According to b: [64: 1522 - c], b depends on c; According to c: [2: 100], we can see that c is independent.

[0029] Then, according to the above priority sorting method, it can be determined that c has the highest priority, and a's priority is lower than b's priority. Therefore, it can be determined that the priority of all variables in the verification stimulus required for test case one is: c>b>a.

[0030] The verification stimulus required for test case 2 includes three variables a, b, and c, and its constraints include: a : [b+10 : c-10] b : [a : a+c] c : [1:100] According to the scope constraints of the verification stimulus required for the above test case 2, it can be determined that: a depends on b and c, b depends on c and a, and c is independent, so a loop is formed between variables a and b, and the entire random constraint has no solution. At this time, feedback needs to be given to the client to modify the requirements in order to modify the constraints.

[0031] The verification stimulus required for test case 3 includes two variables a and b, and its constraints include: a : [100:b+10] b : [b:b+200] According to the scope constraints of the verification stimulus required by the above test case three, it can be determined that: a depends on b, and b depends on b, then a variable depends on itself, resulting in an unsolvable random constraint. At this time, feedback needs to be given to the client to modify the requirements in order to modify the constraints.

[0032] In an optional implementation, the process of finding the intersection of all relevant constraints for each variable in step 3 is as follows: First simplification: According to the constraints, simplify to generate new inequality constraints. In the simplification process, low priority needs to depend on high priority. For example, taking the constraints of the stimulus required for the above test case 1 as an example, new inequality constraints can be generated according to its constraints, as follows: a:[-100:b+c] -->-100<=b+c -->b>=-100-c b:[64:1522-c] -->64<=1522-c -->c<=1522-64 c:[2:100] -->2<=100 a+b+3c<=300 -->a<=300-b-3c a+b>=100 -->a>=100-b c>=100-b cannot be generated here, otherwise it will violate the priority principle.

[0033] Furthermore, if there are no variables on the left and right sides during the simplification process, then the inequality constraint is either always true or always false. The inequality constraint that is always true can be discarded, and once the inequality constraint that is always false appears, the entire random constraint has no solution, and it needs to be fed back to the client for demand modification. For example, the inequality constraint 2<=100 that is always true in the above example can be discarded.

[0034] Substitute the four new inequality constraints generated by simplification into the range constraints of the original constraints, and the first simplification result is: a:[max(-100,100-b):min(b+c,300-b-3c)] b:[max(max(64,-100-c):1522-c] c:[2:min(100,1522-64)] The literal value can be further simplified to: a:[max(-100,100-b):min(b+c,300-b-3c)] b:[max(max(64,-100-c):1522-c] c:[2:100] Among them, the max() function is used to find the maximum value, and the min() function is used to find the minimum value. The input parameters can be one or more.

[0035] Second simplification: Based on the results of the first simplification, new inequality constraints can be generated as follows: a:[max(-100,100-b):min(b+c,300-b-3c)] -->-100<=b+c --> Already has -->-100<=300-b-3c -->b<=400-3c (new) -->100-b<=b+c -->b>=(100-c) / 2 (new) -->100-b<=300-b-3c -->c<=200 / 3 -->c<=66.7 -->c<=66 (new) b:[max(max(64,-100-c):1522-c] -->64<=1522-c --> Already has -->-100-c<=1522-c -->-100<=1522 --> Always true, discarded c:[2:100] -->2<=100 --> Always true, discard The simplification produces three new inequality constraints. Substituting them into the result of the first simplification, the result of the second simplification is: a:[max(-100,100-b):min(b+c,300-b-3c)] b:[max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)] c:[2:min(100,66)] The literal value can be further simplified to: a:[max(-100,100-b):min(b+c,300-b-3c)] b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)] c:[2:66] Third simplification: Based on the results of the second simplification, new inequality constraints can be generated as follows: a:[max(-100,100-b):min(b+c,300-b-3c)] -->-100<=b+c --> Already has -->-100<=300-b-3c --> Already have -->100-b<=b+c --> Already has -->100-b<=300-b-3c --> Already have b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)] -->64<=1522-c --> Already has -->64<=400-3c -->c<=112 (new) -->-100-c<=1522-c --> Already has -->-100-c<=400-3c -->c<=250 (new) -->(100-c) / 2)<= 1522-c -->c<=2944 (new) -->(100-c) / 2)<=400-3c -->c<=140 (new) c:[2:66] -->2<=66 --> Always true, discard The simplification produces four new inequality constraints. Substituting them into the result of the second simplification, the result of the third simplification is: a:[max(-100,100-b):min(b+c,300-b-3c)] b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)] c:[2:min(66,112,250,2944,140] The literal value can be further simplified to: a:[max(-100,100-b):min(b+c,300-b-3c)] b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)] c:[2:66] Fourth simplification: Based on the results of the third simplification, no new inequality constraints can be generated by simplification, so the simplification ends here, as follows: a:[max(-100,100-b):min(b+c,300-b-3c)] -->-100<=b+c --> Already has -->-100<=300-b-3c --> Already have -->100-b<=b+c --> Already has -->100-b<=300-b-3c --> Already have b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)] -->64<=1522-c --> Already has -->64<=400-3c --> Already has -->-100-c<=1522-c --> Already has -->-100-c<=400-3c --> Already have -->(100-c) / 2)<= 1522-c --> Already has -->(100-c) / 2)<=400-3c --> Already have c:[2:66] -->2<=66 --> Always true, discard Finally, the range constraints of each variable are obtained, and the optimized constraints are: a:[max(-100,100-b):min(b+c,300-b-3c)] b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)] c:[2:66].

[0036] In an optional implementation manner, the successive random process of step 4 is specifically as follows: First, randomize the variable with the highest priority to obtain the random value of the variable with the highest priority; Then, based on the random value of the variable with the highest priority, the variable with the second highest priority is randomized to obtain the random value of the variable with the second highest priority, and so on, the random values ​​of all variables can be obtained in sequence.

[0037] For example, taking the constraint conditions of the stimulus required for the above test case 1 as an example, according to the above step 1, the priority of each variable is determined from high to low as: c, b, a; according to the above step 3, the optimized constraint conditions are: a:[max(-100,100-b):min(b+c,300-b-3c)] b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)] c:[2:66].

[0038] According to the variable priority, variable c is first randomized: c:[2:66] --> Assume that the random number is 29 Substitute the random value 29 of c into the inequality of b and perform randomization on the variable b: b:[ max(max(64,-100-c,(100-c) / 2):min(1522-c,400-3c)] -->b:[ max(max(64,-100-29,(100-29) / 2):min(1522-29,400-3*29)] -->b:[ max(max(64,-129,35.5):min(1493,313)] -->b:[ 64:313] -->Assume that this random number is 273 Substitute the random values ​​of b and c into the inequality of variable a, and make variable a random: a:[max(-100,100-b):min(b+c,300-b-3c)] -->a:[max(-100,100-273):min(273+29,300-273-3*29)] -->a:[-100:min(302,-60)] -->a:[-100:-60] -->Assume this random number is -67 You can get a random value {a,b,c} = {-67,273,29}.

[0039] The random excitation generation method proposed in this embodiment determines the priority of each variable according to the range constraints in the constraint conditions, simplifies all the constraints in the constraint conditions (finds the intersection), and converts all the relevant constraints of each variable in the constraint conditions into a range constraint, that is, finally obtaining a constraint condition consisting only of the range constraints of each variable, and then performing randomization one by one according to the priority, it is possible to directly obtain the random values ​​of all variables without repeated randomization and without the need for additional revision algorithms; and the constraint simplification and conversion algorithm involved in this method is a simple logical reasoning algorithm, which is only related to the number of variables, and the algorithm only needs to be executed once, and can be randomized one by one according to the priority (this process does not require the above-mentioned logical reasoning algorithm to be executed again), so it does not consume a lot of hardware and greatly improves the computing efficiency.

[0040] Figure 2The measured results of four common use cases (i.e., use case 1, use case 2, use case 3, and use case 4) using the random stimulus generation method proposed in the embodiment of the present application and implemented using SystemVerilog are given respectively.

[0041] Depend on Figure 2 It can be seen that this application randomly divides the solution and calculation stages. According to the measured results, in a complete simulation, the calculation stage accounts for about 1% to 3%, that is, the time consumption of this application is concentrated in the solution stage, and the solution can be reused, that is to say, no matter how many times the use case is executed, it only needs to be solved once. According to statistics, for ordinary use cases, the speed can be increased by 3 to 10 times after using the random excitation generation method proposed in the embodiment of this application. Once the solution reuse mechanism is enabled, the overall random performance will be extremely advantageous and can be accelerated by dozens of times.

[0042] An optional implementation method should also include before step 1: when it is detected that there is an "or" constraint in the constraint conditions, first split it into parallel constraints, then arbitrarily (randomly) select a group from the parallel constraints, and then generate random values ​​​​of each variable for the randomly selected constraint conditions according to the process described in steps 1 to 4 above.

[0043] Based on the same technical concept as above, this embodiment also proposes a random stimulus generation system for chip verification testing.

[0044] like Figure 3 As shown, the random incentive generation system proposed in this embodiment includes: A priority sorting unit, which determines the priority of all variables in the stimulus according to the constraint conditions of the stimulus required by the chip under test verification test case; A normalization unit, which is used to detect whether there is an inequality constraint in the constraint condition. If yes, the inequality constraint is equivalently replaced with a unified representation form and then the simplification conversion unit is driven to work. Otherwise, the simplification conversion unit is directly driven to work. A simplification conversion unit, which, based on the priority of the variable, obtains the intersection of all the related constraints of each variable in the constraint condition, converts all the related constraints of each variable into a range constraint, thereby generating an optimized constraint condition; And, a first random unit, which, based on the optimized constraint conditions, performs random operations successively from high to low according to the priority of the variables, so as to obtain the random stimulus required for the verification test case of the chip under test.

[0045] It should be noted that the specific implementation methods of each functional module unit of the system are as described in the above steps 1 to 4, and will not be repeated here.

[0046] In an optional implementation manner, the random incentive generation system proposed in this embodiment further includes: A splitting unit, which splits the constraint condition into parallel constraint conditions when detecting that there is an "or" constraint in the constraint condition; and, a second random unit that arbitrarily (randomly) selects a set of inputs to the priority ranking unit from the parallel constraints.

[0047] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0048] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0049] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0050] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0051] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above description is only the specific implementation method of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A random stimulus generation method for chip verification testing, characterized in that: The method comprises: Determine the priority of all variables in the stimulus according to the constraint conditions of the stimulus required by the test case for verifying the chip under test; the constraint conditions include at least one of a constant range constraint, a variable expression range constraint and an inequality constraint; Detect whether there is an inequality constraint in the constraint condition, if yes, replace the inequality constraint with a unified representation and then execute the subsequent steps, otherwise directly execute the subsequent steps; the unified representation of the inequality constraint is in the form of ">=" and / or "<="; Based on the priority of the variables, all the related constraints of each variable in the constraint condition are intersected, and all the related constraints of each variable are converted into a range constraint, thereby generating an optimized constraint condition; Based on the optimized constraint conditions, the variables are randomly assigned from high to low priorities, thereby obtaining the random stimulus required for the verification test case of the chip under test.

2. A random stimulus generation method for chip verification testing according to claim 1, characterized in that: The priority of the variables is determined as follows: The variables are prioritized according to the range constraints in the constraints. The following conditions must be met during the sorting process: The priority of the relying party is lower than that of the relied party; The principle that independent changes have the highest priority; When two or more variables have the same priority, they are sorted in alphabetical order; When a dependency loop occurs, the entire random constraint has no solution, and feedback is sent to the client to modify the requirements; When a variable appears to be dependent on itself, the entire random constraint has no solution, and feedback is then given to the client to modify the requirements.

3. A random stimulus generation method for chip verification test according to claim 1, characterized in that: The variable priority-based method is to find the intersection of all relevant constraints of each variable in the constraint condition, convert all relevant constraints of each variable into a range constraint, and thus generate the optimized constraint condition, which specifically includes: According to the constraint conditions, new inequality constraints are generated by simplification, and the generated new inequality constraints are substituted into the range constraints of the constraint conditions to obtain the first simplification result; Simplifying to generate new inequality constraints according to the first simplification result, substituting the generated new inequality constraints into the first simplification result to obtain a second simplification result; This process continues until no new inequality constraints can be generated by simplification. The simplification ends and the result of the last simplification is used as the optimized constraint condition. Among them, in each simplification process, low priority must depend on high priority.

4. A random stimulus generation method for chip verification test according to claim 3, characterized in that: The method of finding the intersection of all related constraints of each variable in the constraint condition based on the priority of the variable, converting all related constraints of each variable into a range constraint, thereby generating the optimized constraint condition, further includes: In each simplification process, the inequality constraints that always hold true are discarded.

5. The random stimulus generation method for chip verification test according to claim 3, characterized in that: The method of finding the intersection of all related constraints of each variable in the constraint condition based on the priority of the variable, converting all related constraints of each variable into a range constraint, thereby generating the optimized constraint condition, further includes: When an inequality constraint that is never true appears during the simplification process, feedback is given to the client to modify the requirements.

6. A random stimulus generation method for chip verification testing according to claim 1, characterized in that: The above-mentioned optimization-based constraint conditions are randomized successively according to the priority of variables from high to low, specifically including: Randomize the variable with the highest priority to obtain the random value of the variable with the highest priority; Based on the random value of the edge with the highest priority, the variable with the second highest priority is randomized to obtain the random value of the variable with the second highest priority, and so on, to obtain the random values ​​of all variables in sequence.

7. A random stimulus generation method for chip verification testing according to any one of claims 1 to 6, characterized in that: Before the step of determining the priority of all variables in the stimulus according to the constraint conditions of the stimulus required by the test case for verifying the chip under test, the method further includes: Check whether there is an "or" constraint in the constraint conditions, if so, split the constraint conditions into parallel constraint conditions, and randomly select a group of constraint conditions from the parallel constraint conditions for subsequent processing.

8. A random stimulus generation system for chip verification testing, characterized in that: The system comprises: A priority sorting unit, wherein the priority sorting unit determines the priority of all variables in the stimulus according to the constraint conditions of the stimulus required for the verification test case of the chip to be tested; the constraint conditions include at least one of a constant range constraint, a variable expression range constraint and an inequality constraint; A normalization unit, the normalization unit is used to detect whether there is an inequality constraint in the constraint condition, if yes, then drive the simplification conversion unit to work after equivalently replacing all inequality constraints into a unified representation form, otherwise directly drive the simplification conversion unit to work; the unified representation form of the inequality constraint is a form represented by ">=" and / or "<="; A simplification conversion unit, wherein the simplification conversion unit obtains the intersection of all related constraints of each variable in the constraint condition based on the priority of the variable, converts all related constraints of each variable into a range constraint, thereby generating an optimized constraint condition; And, a first random unit, which is based on the optimized constraint conditions and is randomized successively according to the priority of the variables from high to low, so as to obtain the random stimulus required for the verification test case of the chip under test.

9. A random stimulus generation system for chip verification testing according to claim 8, characterized in that: The system further comprises: a splitting unit, wherein when detecting that an "or" constraint exists in the constraint condition, the splitting unit splits the constraint condition into parallel constraint conditions; and, a second random unit, which randomly selects a set of inputs from the parallel constraints to the priority ranking unit.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

Images