Image processing method, apparatus, device, storage medium and program product

Abstract

The present disclosure provides an image processing method, device, equipment, storage medium and program product. The method is applied to a multi-core GPU; the image processing method comprises: dividing a plurality of cores of the multi-core GPU into at least two groups, each group comprising at least one core; transmitting image rendering instructions of a plurality of picture frames to the cores of each group of the multi-core GPU respectively; wherein one picture frame corresponds to one group of image rendering instructions; and at least two groups of the cores of the multi-core GPU are used to process at least two groups of the image rendering instructions in parallel respectively. Through the above method, the GPU utilization can be improved, and the rendering performance can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of image processing, and particularly relates to an image processing method and device, equipment, a storage medium and a program product. BACKGROUND

[0002] GPU (Graphics Processing Unit, image processor) is also called display chip, which is a kind of microprocessor specially used for image and graphics related operation processing on devices with display function. GPU can realize the display of complex images on the display interface by rendering processing on image or video information.

[0003] GPU can adopt multi-core architecture, which enables GPU to efficiently and in parallel process a large number of graphics computing tasks. That is, by distributing different tasks of each frame image to different cores for processing respectively, the processing speed is improved. However, the execution rate of different rendering tasks is different, resulting in low utilization of each core and insufficient rendering performance. SUMMARY

[0004] Therefore, the embodiments of the present disclosure provide an image processing method, device, equipment, storage medium and program product to solve at least one problem in the prior art.

[0005] To achieve the above-mentioned purpose, the technical scheme of the embodiments of the present disclosure is as follows:

[0006] In one aspect, the embodiments of the present disclosure provide an image processing method applied to a multi-core GPU, and the image processing method comprises:

[0007] dividing a plurality of cores of the multi-core GPU into at least two groups, each group comprising at least one core;

[0008] transmitting image rendering instructions of a plurality of picture frames to each group of cores of the multi-core GPU respectively; wherein one picture frame corresponds to one group of image rendering instructions; and at least two groups of cores of the multi-core GPU are used to process at least two groups of image rendering instructions in parallel respectively.

[0009] In some embodiments, the step of dividing a plurality of cores of the multi-core GPU into at least two groups, each group comprising at least one core, comprises:

[0010] configuring at least two hardware queues of the multi-core GPU; the hardware queues are used to temporarily store the image rendering instructions;

[0011] dividing the plurality of cores into at least two groups corresponding to the hardware queues, each group comprising at least one core.

[0012] In some embodiments, the transmitting the image rendering instructions of the plurality of picture frames to the cores of the multi-core GPU respectively comprises:

[0013] transmitting the image rendering instructions to the cores in sequence according to the order of the picture frames; wherein the image rendering instructions corresponding to two adjacent picture frames are transmitted to different groups of the cores.

[0014] In some embodiments, the multi-core GPU comprises two groups of cores; and the transmitting the image rendering instructions to the cores in sequence according to the order of the picture frames comprises:

[0015] transmitting the image rendering instructions corresponding to odd-numbered picture frames to the first group of cores of the multi-core GPU and transmitting the image rendering instructions corresponding to even-numbered picture frames to the second group of cores of the multi-core GPU according to the order of the picture frames.

[0016] In some embodiments, the transmitting the image rendering instructions of the plurality of picture frames to the cores of the multi-core GPU respectively comprises:

[0017] transmitting the image rendering instructions corresponding to the next picture frame to be processed to any idle core in the multi-core GPU.

[0018] In some embodiments, the method further comprises:

[0019] indicating the multi-core GPU to send the buffered to-be-displayed data to the display device in sequence according to the order of the picture frames, wherein the to-be-displayed data is obtained by processing the image rendering instructions by the multi-core GPU.

[0020] In another aspect, the embodiments of the present disclosure further provide a GUP device, comprising a multi-core GPU and a driving device.

[0021] The driving device is configured to:

[0022] divide a plurality of cores of the multi-core GPU into at least two groups, each group comprising at least one core;

[0023] transmit image rendering instructions of a plurality of picture frames to the cores of the multi-core GPU respectively; wherein one picture frame corresponds to one group of image rendering instructions; and at least two groups of the cores of the multi-core GPU are used to process at least two groups of the image rendering instructions in parallel respectively.

[0024] In another aspect, the embodiments of the present disclosure further provide an image processing device, comprising a memory, a processor and a computer program stored in the memory; the processor implements any of the above image processing methods when executing the computer program.

[0025] In another aspect, the embodiments of the present disclosure further provide a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to implement any of the above image processing methods.

[0026] In another aspect, the embodiments of the present disclosure further provide a computer program product, which comprises a computer program. The computer program is executed by a processor to implement any of the above image processing methods.

[0027] In the technical solutions provided by the present disclosure, the cores of the multi-core GPU are grouped, and the cores in different groups are used to process the image rendering instructions of different picture frames. In this way, the parallel processing of the image rendering instructions of different picture frames can be realized, and the difference between the utilization rates of the cores caused by the different rendering rates of the image rendering instructions of the same picture frame can be reduced, so that the utilization rates of the cores of the GPU and the overall rendering performance of the GPU can be effectively improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 a flowchart of the image processing method provided by the embodiments of the present disclosure;

[0029] Figure 2 a principle schematic diagram of the image processing method provided by the embodiments of the present disclosure;

[0030] Figure 3 a structural block diagram of the GPU device provided by the embodiments of the present disclosure;

[0031] Figure 4 a structural block diagram of the image processing device provided by the embodiments of the present disclosure. DETAILED DESCRIPTION

[0032] Exemplary embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms, and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood, and the scope of the present disclosure can be accurately conveyed to those skilled in the art.

[0033] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present disclosure. However, it should be apparent to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid obscuring the present disclosure, some technical features known in the art are not described; that is, not all features of the actual embodiments are described herein, and well-known functions and structures are not described in detail.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of associated items.

[0035] GPU rendering mode, generally in a single GPU card in sequence processing multiple frame rendering, that is, each GPU at a time point only render a frame of picture. This way is suitable for most desktop and mobile application and game.

[0036] Specifically, the rendering process of GPU mainly includes:

[0037] Render the first frame: initialization processing, clear the rendering target, set the rendering state, send the rendering instruction, and finally present the rendering result;

[0038] Next, the next frame is processed in a loop.

[0039] For multi-core GPU architecture, it has the characteristics of efficient parallel processing of a large number of graphics computing tasks. Generally, the rendering task of each frame can be sent to all cores of the GPU to execute at the same time. Different cores can be used to process different instructions of the same frame picture. When all cores execute the rendering task, the rendering task execution ends, and the GPU receives the rendering task of the next frame.

[0040] For complex image processing scenarios such as games, there are many image rendering instructions for a frame of picture, which may be sent to the GPU for rendering multiple times, and the task of each rendering cannot be guaranteed to be evenly distributed to each core. However, in this case, all cores still need to execute all image rendering instructions before the rendering task of a frame of picture is completed, and then the rendering of the next frame of picture can continue. This unbalanced scheduling causes a lot of resource waste and makes the rendering performance of the GPU cannot be doubled with the increase of the number of cores.

[0041] Therefore, the embodiment of the disclosure groups the multiple cores of the GPU, optimizes the task scheduling of the GPU through the alternate frame rendering mode, so as to achieve the purpose of improving the performance.

[0042] As shown in Figure 1 The embodiment of the disclosure provides an image processing method applied to a multi-core GPU, and the image processing method comprises the following steps:

[0043] Step S101, dividing a plurality of cores of the multi-core GPU into at least two groups, each group including at least one core;

[0044] Step S102, transmitting image rendering instructions of a plurality of picture frames to each group of the cores of the multi-core GPU respectively; wherein one picture frame corresponds to one group of image rendering instructions; at least two groups of the cores of the multi-core GPU are used to process at least two groups of the image rendering instructions respectively in parallel.

[0045] When the GPU performs rendering of an image, it will sequentially receive rendering instructions corresponding to each picture frame. One picture frame can need one or more image rendering instructions, which are sequentially provided to the core of the GPU for processing. When the core of the GPU executes all image rendering instructions of one picture frame, the rendering of the picture frame is completed, and the picture frame can be displayed on the display screen.

[0046] Here, the picture frame refers to one frame of picture displayed by one refresh of the display screen. The image rendering instruction can be any instruction that the GPU needs to execute to render one picture frame.

[0047] It can be understood that a plurality of cores process different image rendering instructions of one picture frame respectively, and the rendering tasks executed by each core are different, resulting in different processing speeds. If a plurality of cores are used for rendering of the same picture frame, some cores need a shorter processing time, and some cores need a longer processing time. Each time a picture frame is rendered, it needs to wait for all the cores to process all the image rendering instructions corresponding to the picture frame, so the required time is the time required by the slowest core among all the cores. The fastest core will be idle for a long time, resulting in reduced utilization.

[0048] Therefore, in the embodiments of the present disclosure, the plurality of cores in the multi-core GPU can be grouped by the GPU driver, and each group of cores processes image rendering instructions of different picture frames. In this way, a plurality of groups of cores can process in parallel, effectively reducing the waiting time.

[0049] Here, the GPU driver (GPU Driver) is a software driver that allows communication between the operating system and the GPU hardware. Its main functions include: instruction translation, i.e., converting high-level instructions from the operating system and application programs into low-level instructions that the GPU can understand; optimizing the execution order and method of instructions to improve the performance and efficiency of the GPU; handling hardware errors and exceptions to ensure stable system operation; providing support for hardware features and APIs, and ensuring that the GPU is compatible with different operating systems and applications, etc. In the embodiments of the present disclosure, the GPU driver can be used to implement the above method.

[0050] Further, it should be noted that when displaying, the pictures are displayed in the order of picture frames. Since each group of cores can synchronously render multiple picture frames, the order of picture frame rendering and the order of picture frame display can be different. Therefore, when actually displaying, the picture frame that is rendered first but is in the later order can wait until the picture frame that is in the earlier order is rendered and displayed, and then be displayed in the next refresh cycle. Specifically, in some embodiments, the method further includes:

[0051] indicating the multi-core GPU to sequentially send the buffered to-be-displayed data to the display device in the order of picture frames, wherein the to-be-displayed data is data obtained by processing each group of image rendering instructions by the multi-core GPU.

[0052] Each group of GPUs processes the received image rendering instructions. The order of processing completion can be different from the order of image frames. Therefore, each group of core can temporarily store the rendered picture in the buffer, and then the GPU driver can instruct the GPU core to provide the buffered data to the display device in the order of picture frames for sequential display. In this way, the abnormal display order caused by synchronous rendering can be prevented.

[0053] For the above grouping operation, the cores of one GPU can be divided into two groups, and the image rendering instructions of two picture frames can be received. Specifically, the instructions of two picture frames can be received simultaneously, sequentially, or after the image rendering instructions of one picture frame are received. Two groups of cores process the instructions of two picture frames in parallel, so that the processing period of the image rendering instructions of two picture frames can have a partially or fully overlapped period.

[0054] It should be noted that one group of image rendering instructions of one picture frame can include one or more, and the number can be greater than the number of one group of cores. If the number of one group of image rendering instructions is greater than the number of one group of cores, some cores in one group of cores can process multiple image rendering instructions, and some cores can process only one image rendering instruction.

[0055] In actual application, each instruction can be sequentially assigned to one group of cores for processing. The remaining unprocessed image rendering instructions can wait for the core in the group of cores that completes the previous processing. For example, when an idle core in one group of cores is detected, the unprocessed image rendering instruction is transmitted to the idle core for processing. In this way, the utilization rate of the core can be effectively improved, so that the image rendering instruction with fast processing speed is more likely to be assigned to the same core for processing, that is, some cores process multiple simple image rendering instructions, and some cores process only one complex image rendering instruction.

[0056] In addition, it is also possible that the number of a group of image rendering instructions is less than or equal to the number of a group of cores. If the number of a group of image rendering instructions is equal to the number of a group of cores, the group of image rendering instructions can be distributed to each core for processing respectively; if the number of a group of image rendering instructions is less than the number of a group of cores, there are idle cores when processing a group of image rendering instructions. Of course, considering the maximum utilization of cores, when grouping, it can be considered that the number of each group of cores is as small as possible. The number of a group of image rendering instructions.

[0057] In some embodiments, in the step S101, the division of the plurality of cores of the multi-core GPU into at least two groups, each group including at least one core, comprises:

[0058] At least two hardware queues of the multi-core GPU are configured; the hardware queues are used to temporarily store the image rendering instructions;

[0059] The plurality of cores are divided into at least two groups corresponding to the hardware queues, each group including at least one core. The hardware queue of the GPU refers to the work flow queue in the GPU hardware for managing and scheduling execution tasks. The hardware queue is responsible for storing and blocking the commands and tasks to be executed in the GPU architecture, so that the GPU can efficiently process these tasks. In the embodiments of the present disclosure, the hardware queue of the GPU can be configured by a driver, and at least two hardware queues of the GPU can be configured by the driver, and these hardware queues can schedule different work flows, i.e., different image rendering instructions, respectively.

[0060] In addition, the embodiments of the present disclosure also divide the plurality of cores into at least two groups by the driver, so that each hardware queue corresponds to a group of GPU cores.

[0061] As shown in the figure, taking an 8-core GPU as an example, the 8 cores are divided into two groups (group 0 and group 1) corresponding to hardware queue 0 and hardware queue 1 respectively, wherein group 0 includes cores 0 to 3, and group 1 includes cores 4 to 7. Figure 2 The group image rendering instructions of the picture frame 0 to the picture frame 5 are alternately transmitted to the above-mentioned hardware queue in sequence, so that each group of cores can execute the image rendering instructions provided by the corresponding hardware queue in sequence through the image rendering instructions.

[0062] In actual application, the number of core groups and the number of cores in each group can be set according to requirements, which is not limited here. In addition, the number of hardware queues can be consistent with the number of core groups, and each group corresponds to a hardware queue. In the above example, each hardware queue can fixedly receive image rendering instructions in the order of odd and even frames, as shown in the figure.

[0063] Figure 2 ​As shown, hardware queue 0 is used to receive image rendering instructions of even frames, i.e. picture frame 0, picture frame 2, picture frame 4, etc.; and hardware queue 1 is used to receive image rendering instructions of odd frames, i.e. picture frame 1, picture frame 3, picture frame 5, etc.

[0064] In some other embodiments, the grouping of GPU cores can be other numbers, for example, 3 groups, corresponding to hardware queue 0, hardware queue 1, and hardware queue 2 respectively. Each hardware queue can sequentially receive image rendering instructions of each picture frame in order.

[0065] In this way, by grouping hardware queues, image rendering instructions corresponding to each frame can be sequentially transmitted to the corresponding core group through the hardware queue, facilitating parallel processing of each core group.

[0066] In some embodiments, the image rendering instructions of the plurality of picture frames are transmitted to each group of cores of the multi-core GPU, comprising:

[0067] Each group of image rendering instructions is sequentially transmitted to each group of cores in order of picture frames; wherein the image rendering instructions corresponding to adjacent two picture frames are transmitted to different groups of cores.

[0068] Here, the order of picture frames is the order of picture playback, and the processor (such as CPU) issues image rendering instructions according to the order of picture frames. After the driver receives the image rendering instructions in order, it can sequentially transmit them to the GPU hardware queue, and then provide them to the GPU core for processing. Here, the driver can sequentially provide each group of image rendering instructions to each hardware queue according to the order of multiple core groups, or provide image rendering instructions of different groups to different hardware queues in random order. Moreover, since the image rendering instructions of adjacent two picture frames are provided to different groups of cores, each group of cores can alternately render, avoiding the situation that two adjacent frames need to be queued for processing, thereby effectively improving the processing efficiency.

[0069] In actual application, multiple groups of cores can be numbered, and the image rendering instructions of each picture frame are sequentially received according to the order of numbering corresponding to the order of each picture frame.

[0070] For example, the GPU cores are divided into 4 groups, namely the 0th group, the 1st group, the 2nd group, and the 3rd group. The 0th group processes the 0th frame, the 4th frame, the 8th frame, etc. in turn, the 1st group processes the 1st frame, the 5th frame, the 9th frame, etc. in turn, the 2nd group processes the 2nd frame, the 6th frame, the 10th frame, etc. in turn, and the 3rd group processes the 3rd frame, the 7th frame, the 11th frame, etc. in turn. Each group can perform parallel processing, for example, the above 4 groups of cores process the image rendering instructions of the 0th to 3rd frames. These 4 frames can be rendered simultaneously or sequentially.

[0071] It can be understood that although multiple groups of cores can process multiple picture frames in parallel, when displaying, the picture frames still need to be displayed in sequence. For example, if the 0th to 3rd picture frames are rendered at the same time, the 0th to 3rd picture frames are displayed in sequence. However, if the previous picture frame has not been rendered, and the subsequent picture frame has been rendered, the subsequent picture frame needs to be displayed after the previous picture frame is rendered and displayed.

[0072] In this way, the image rendering instructions corresponding to each picture frame are sequentially provided to different groups, without additional processing operations, which can effectively improve the processing efficiency.

[0073] In some embodiments, the grouping of GPU cores can be set according to actual needs, at least two grouping modes are provided, and the grouping mode is switched according to different scenes or application programs, or the grouping mode is switched according to user settings. For example, a "grouping mode" and a "normal mode (not grouped)" are provided for user selection. When the user selects the "grouping mode", a fixed grouping mode is adopted, for example, the multi-core GPU is divided into two groups. Specifically, for an 8-core GPU, the 0th to 3rd cores are divided into a first group, and the 4th to 7th cores are divided into a second group. When the user selects the "normal mode", the normal display is performed without grouping.

[0074] For example, a plurality of grouping modes can also be provided, each grouping mode has a different number of groups, or each group has a different number of cores, and the like. The specific grouping mode can be designed according to the number of cores of the GPU and the applicable scene, and the embodiments of the present disclosure are not limited.

[0075] In some embodiments, the multi-core GPU includes two groups of cores; and the step of sequentially transmitting the image rendering instructions corresponding to each picture frame to the cores in the groups according to the order of the picture frames includes: transmitting the image rendering instructions corresponding to the odd-numbered picture frames to the first group of cores of the multi-core GPU, and transmitting the image rendering instructions corresponding to the even-numbered picture frames to the second group of cores of the multi-core GPU.

[0076] Here, the case of dividing the GPU cores into two groups is provided, and then the picture frames can be sequentially provided to different groups according to the odd-even order of the picture frames. For example, the first group of cores processes the image rendering instructions of the odd-numbered frames (i.e., the above-mentioned odd-numbered picture frames); and the second group of cores processes the image rendering instructions of the even-numbered frames (i.e., the above-mentioned even-numbered picture frames). In other embodiments, the first group of cores can process the image rendering instructions of the even-numbered frames, and the second group of cores can process the image rendering instructions of the odd-numbered frames.

[0077] The above-mentioned first group of cores and the second group of cores in the embodiments of the present disclosure are only used to distinguish the two groups of cores, and are not used to limit the order of the two groups of cores.

[0078] In this way, the alternately rendering by the two groups of cores can effectively improve the processing efficiency, and the grouping structure is simple and easy to implement.

[0079] In some embodiments, the transmitting the image rendering instructions of the plurality of picture frames to the groups of cores of the multi-core GPU respectively comprises:

[0080] transmitting the image rendering instructions corresponding to the next picture frame to be processed to any idle core in the multi-core GPU.

[0081] Considering that the image rendering instructions of different picture frames can be different, and the processing speed of different cores for each instruction is also different, for example, the first group of cores takes t1 time to process the first picture frame, and the second group of cores takes t2 time to process the second picture frame, and t2 time can be less than t1 time. That is, the second group of cores can complete the current rendering task before the first group of cores. If the allocation is in order, the first group of cores may need to wait for the processing to end, and the two groups of cores can receive the image rendering instructions of the next two frames in turn. In this way, the cores in the second group can be in an idle state for a period of time.

[0082] Therefore, another grouping processing implementation is provided here, that is, after a group of cores completes a group of image rendering instructions, the next group of image rendering instructions is received. That is, in the case of the above example, the second group of cores processes a group of image rendering instructions of the second picture frame first, and then receives a group of image rendering instructions of the third picture frame. The first group of cores continues to process the image rendering instructions of the first picture frame, and then receives a group of image rendering instructions of the next frame (the fourth picture frame) after the first group of cores finishes processing.

[0083] Taking three groups of cores (group 0, group 1, and group 2) as an example, after initialization, the driver provides the image rendering instructions corresponding to the 0th, 1st, and 2nd frames of pictures to the above group 0, group 1, and group 2 in turn for processing. Assuming that group 1 finishes processing first and enters an idle state, the driver provides the image rendering instructions corresponding to the next frame (the 3rd frame) of picture to group 1, at this time, group 0, group 1, and group 2 are processing the 0th frame, the 3rd frame, and the 2nd frame of picture respectively. Next, the 0th frame finishes processing, group 0 enters an idle state, and the driver provides the image rendering instructions corresponding to the next frame (the 4th frame) of picture to group 0.

[0084] Thus, the driver can not assign the image rendering instructions to the cores in the order of the core group numbers, but provide each group of image rendering instructions to any idle core. Alternatively, the driver can provide the next group of image rendering instructions to be processed to the idle core in response to any group of cores completing the image rendering instructions and entering the idle state, so as to further improve the overall processing efficiency and reduce the probability of core idling. Since the rendering completed data obtained after each group of cores is processed is temporarily stored in the cache and further displayed in the order of the picture frames based on the instructions of the driver, the processing order of the image rendering instructions does not affect the display order.

[0085] Based on the same inventive concept, the embodiments of the present disclosure also provide a GPU device, as shown in the figure, the GPU device 300 comprises a multi-core GPU 301 and a driver device 302. Figure 3 The driver device 302 is configured to:

[0086] The driver device 302 is configured to:

[0087] divide the plurality of cores of the multi-core GPU into at least two groups, each group comprising at least one core;

[0088] transmit image rendering instructions of a plurality of picture frames to the cores of each group of the multi-core GPU respectively; wherein one picture frame corresponds to one group of image rendering instructions; and the at least two groups of cores of the multi-core GPU are used to process at least two groups of image rendering instructions in parallel respectively.

[0089] In some embodiments, the driver device is specifically configured to:

[0090] configure at least two hardware queues of the multi-core GPU; the hardware queues are used to temporarily store the image rendering instructions; and divide the plurality of cores into at least two groups corresponding to the hardware queues, each group comprising at least one core.

[0091] In some embodiments, the driver device is specifically configured to:

[0092] transmit each group of image rendering instructions to the cores of each group in the order of the picture frames; wherein the image rendering instructions corresponding to two adjacent picture frames are transmitted to the cores of different groups.

[0093] In some embodiments, the multi-core GPU comprises two groups of cores; and the driver device is further configured to:

[0094] transmit the image rendering instructions corresponding to the odd-numbered picture frames to the first group of cores of the multi-core GPU and transmit the image rendering instructions corresponding to the even-numbered picture frames to the second group of cores of the multi-core GPU in the order of the picture frames.

[0095] In some embodiments, the driving device is specifically configured as follows:

[0096] The image rendering instruction corresponding to the next frame to be processed is transmitted to any set of idle cores in the multi-core GPU.

[0097] In some embodiments, the GPU device further includes a cache unit, and the driver is further configured to:

[0098] The multi-core GPU is instructed to send the cached data to be displayed frame by frame to the display device in the order of the screen frames, wherein the data to be displayed is the data obtained by the multi-core GPU after processing each set of image rendering instructions.

[0099] Based on the same inventive concept, this disclosure also discloses an image display device 400, such as... Figure 4 As shown, the image display device 400 includes a processor 401 and a memory 402, wherein the memory 402 stores a computer program 4021 that can run on the processor 401, and the processor 401 can implement the image processing method in any of the above embodiments when executing the computer program 4021.

[0100] In some embodiments, memory 402 stores a computer program 4021 that can run on a processor. Memory 402 is configured to store instructions and applications executable by processor 401. It can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in processor 401 and various modules in image display device 400. It can be implemented using flash memory or random access memory (RAM).

[0101] In some embodiments, when the processor 401 executes the program, it implements the steps of any of the above-described task processing methods. The processor 401 generally controls the overall operation of the image display device 400.

[0102] Based on the same inventive concept, this disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements any of the above-described image processing methods.

[0103] Based on the same inventive concept, this disclosure also provides a computer program product, which includes a computer program that, when executed by a processor, implements any of the above-described image processing methods.

[0104] In some specific examples, the processor described above can be at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a Central Processing Unit (CPU), a controller, a microcontroller, or a microprocessor. It can be understood that the electronic device that implements the functions of the processor described above can also be other devices, and the embodiments of the present disclosure are not limited specifically.

[0105] In some specific examples, the computer storage medium / memory described above can be a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Ferromagnetic Random Access Memory (FRAM), a Flash Memory, a magnetic surface memory, an optical disc, a Compact Disc Read-Only Memory (CD-ROM), or the like. It can also be various terminals including one or any combination of the above memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, and the like.

[0106] The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments.

[0107] The features disclosed in the several device embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new device embodiments.

[0108] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. An image processing method, characterized by, The application is applied to a multi-core image processor GPU; the image processing method comprises: dividing a plurality of cores of the multi-core GPU into at least two groups, each group comprising at least one core; transmitting image rendering instructions of a plurality of picture frames to each group of the cores of the multi-core GPU respectively; wherein one picture frame corresponds to one group of image rendering instructions; at least two groups of the cores of the multi-core GPU are used to process at least two groups of the image rendering instructions in parallel respectively.

2. The image processing method of claim 1, wherein, The dividing of the plurality of cores of the multi-core GPU into at least two groups, each group comprising at least one core, comprises: configuring at least two hardware queues of the multi-core GPU; the hardware queues are used to temporarily store the image rendering instructions; dividing the plurality of cores into at least two groups corresponding to the hardware queues, each group comprising at least one core.

3. The image processing method of claim 1, wherein, The transmitting of the image rendering instructions of the plurality of picture frames to each group of the cores of the multi-core GPU comprises: transmitting each group of the image rendering instructions to each group of the cores in sequence according to the order of the picture frames; wherein the image rendering instructions corresponding to two adjacent picture frames are transmitted to different groups of the cores.

4. The image processing method of claim 3, wherein, The multi-core GPU comprises two groups of cores; the transmitting of each group of the image rendering instructions to each group of the cores in sequence according to the order of the picture frames comprises: transmitting the image rendering instructions corresponding to odd-numbered picture frames to a first group of cores of the multi-core GPU and transmitting the image rendering instructions corresponding to even-numbered picture frames to a second group of cores of the multi-core GPU according to the order of the picture frames.

5. The image processing method of claim 1, wherein, The transmitting of the image rendering instructions of the plurality of picture frames to each group of the cores of the multi-core GPU comprises: transmitting the image rendering instructions corresponding to a next picture frame to be processed to any idle core in the multi-core GPU.

6. The image processing method according to any one of claims 1 to 5, characterized in that, The method further comprises: indicating the multi-core GPU to send cached to-be-displayed data to a display device in sequence frame by frame according to the order of the picture frames, wherein the to-be-displayed data is data obtained by processing each group of image rendering instructions by the multi-core GPU.

7. A GUP device, characterized by comprise a multi-core GPU and a driving device; The driving device is configured to: divide a plurality of cores of the multi-core GPU into at least two groups, each group comprising at least one core; transmit image rendering instructions of a plurality of picture frames to each group of the cores of the multi-core GPU respectively; wherein one picture frame corresponds to one group of image rendering instructions; at least two groups of the cores of the multi-core GPU are used to process at least two groups of the image rendering instructions in parallel respectively.

8. An image processing apparatus characterized by comprising: The computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the image processing method in any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The computer program product comprises a computer program, and the computer program is executed by a processor to implement the image processing method in any one of claims 1 to 7.

10. A computer program product, characterised in that, The computer program product comprises a computer program, and the computer program is executed by a processor to implement the image processing method in any one of claims 1 to 7.

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