A flip chip packaging structure and packaging method

Abstract

The present invention relates to the field of chip packaging technology, and specifically to a flip-chip packaging structure and packaging method. The present invention constructs an identification module and a detection module to detect the video of the chip placement and welding process and the chip image data after packaging. Timely detection of problems and issuance of alarms can enable operators to quickly take measures to make adjustments, avoiding further waste of resources and time consumption due to errors in continuing subsequent processes, thereby improving chip production efficiency. Storing and backing up the welding records of chips in the same batch facilitates subsequent tracing and analysis of the production process, further improving packaging quality and production efficiency. This solves the problem of reduced yield of existing flip-chip packaging methods.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a flip chip packaging structure and a packaging method. Background Art

[0002] Chip packaging refers to the process of assembling an integrated circuit die into a final product. Simply put, it involves placing the IC die produced by a semiconductor factory onto a supporting substrate, leading out the pins, and then securing and packaging the die into a complete package. This process installs, secures, seals, protects the chip, and enhances electrical and thermal performance. Wires connect the contacts on the chip to the pins of the package housing. These pins, in turn, connect to other components via wires on the printed circuit board, thus connecting the internal chip to external circuits.

[0003] The flip-chip soldering process uses the bumps on the chip to directly interconnect components face-down to a substrate, carrier, or circuit board, achieving efficient electrical and mechanical connections. With the continuous development of technology, flip-chip technology has become a frequently used packaging method in high-end devices and high-density packaging.

[0004] During existing packaging operations, errors in packaging position and packaging process often lead to a significant reduction in chip yield, thereby affecting chip production efficiency. Summary of the Invention

[0005] The object of the present invention is to provide a flip chip packaging structure and packaging method, aiming to solve the problem of reduced yield of the existing flip chip packaging method.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a flip chip packaging method, comprising the following steps:

[0007] Build recognition module and detection module;

[0008] Real-time acquisition of chip placement and welding videos;

[0009] The recognition module performs detection based on the placement video and welding video to obtain the recognition result. If the recognition result exceeds the threshold, an alarm is issued. If it does not exceed the threshold, the module proceeds to the next step.

[0010] Collect chip image data after packaging;

[0011] The detection module performs chip error detection based on chip image data. If the error meets the threshold, the package is completed. If the error exceeds the threshold, an alarm is issued.

[0012] Store and back up the welding records of chips in the same batch.

[0013] Among them, in "Constructing the recognition module and the detection module", the construction of the recognition module includes the following steps:

[0014] Collect images of correct and incorrect placement of inverted chip soldering;

[0015] Mark the center coordinates of the correctly placed images and the incorrectly placed images to obtain a marked image dataset;

[0016] Set training parameters, training set and test set based on labeled image dataset;

[0017] Train the YOLO model based on the training parameters and training set to obtain a primary model;

[0018] The primary model is evaluated based on the test set to obtain the recognition module.

[0019] Among them, in "Constructing the identification module and the detection module", the construction of the detection module includes the following steps:

[0020] Collect normal image datasets and abnormal image datasets after flip chip packaging;

[0021] Mark the error position, type and error value of the normal image dataset and the abnormal image dataset respectively;

[0022] Set training parameters, training set, and test set based on the labeled images;

[0023] Train the SSD model based on the training parameters and training set to obtain a primary model;

[0024] The primary model is evaluated based on the test set to obtain the detection module.

[0025] The process of "real-time acquisition of chip placement and welding videos" includes the following steps:

[0026] Place the chip on the substrate and weld it using welding equipment;

[0027] The chip processing process is captured in real time by industrial cameras to obtain placement video and welding video.

[0028] The following steps are included in the process of "the recognition module performs detection based on the placement video and the welding video to obtain a recognition result. If the recognition result exceeds a threshold, an alarm is issued; if it does not exceed the threshold, the next step is entered":

[0029] The recognition module removes noise, enhances contrast, and adjusts the frame rate of placement and welding videos;

[0030] Extract the placement, outline, and edges of the chip based on the processed video and generate feature items;

[0031] The feature item is judged based on the preset threshold. If it exceeds the threshold, an alarm is issued. If it does not exceed the threshold, the next step is entered.

[0032] The step of "collecting chip image data after packaging" includes the following steps:

[0033] Arrange the chips that have been welded in the same batch in the image acquisition area in sequence;

[0034] Chips from the same batch are collected statically and dynamically using industrial cameras to obtain chip image data.

[0035] The process of "the detection module performs error detection on the chip based on the chip image data, and completes packaging if the error meets the threshold, and issues an alarm if the error exceeds the threshold" includes the following steps:

[0036] The detection module uses image processing algorithms and machine learning models to extract pin connections, solder joints, chip area, solder joint spacing, and solder joint size features from chip images;

[0037] Perform error calculation on the feature information based on a preset threshold to obtain an error value;

[0038] The error value is judged based on the preset error threshold. If it exceeds the preset error threshold, an alarm signal is issued and corresponding error information and position indication are provided. If it meets the preset error threshold, the packaging is completed.

[0039] In a second aspect, a flip chip packaging structure is provided, which is used in the flip chip packaging method described in the first aspect, and is characterized in that it includes a substrate and a packaging film.

[0040] A flip-chip packaging method according to the present invention includes the following steps: constructing an identification module and a detection module; collecting real-time video of chip placement and soldering; the identification module performing detection based on the placement and soldering videos to obtain a recognition result. If the recognition result exceeds a threshold, an alarm is issued; if it does not exceed the threshold, the process proceeds to the next step; collecting chip image data after packaging; the detection module performing error detection on the chip based on the chip image data. If the error meets the threshold, packaging is completed; if it exceeds the threshold, an alarm is issued; and storing and backing up soldering records of chips from the same batch. By constructing the identification module and the detection module, the present invention detects videos of the chip placement and soldering process, as well as the chip image data after packaging. Promptly detecting problems and issuing alarms allows operators to quickly take corrective measures, avoiding further waste of resources and time due to errors in subsequent processes, thereby improving chip production efficiency. Storing and backing up soldering records of chips from the same batch facilitates subsequent tracing and analysis of the production process, further improving packaging quality and production efficiency. This solves the problem of low yield in existing flip-chip packaging methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 The present invention provides a flowchart of a flip chip packaging method.

[0043] Figure 2 It is a flowchart of the recognition module construction.

[0044] Figure 3 It is a flowchart of the detection module construction.

[0045] Figure 4 It is a flowchart for real-time acquisition of chip placement video and welding video.

[0046] Figure 5 The recognition module performs detection based on the placement video and welding video to obtain the recognition result. If the recognition result exceeds the threshold, an alarm is issued. If it does not exceed the threshold, the next step of the flowchart is entered.

[0047] Figure 6 It is a flow chart for collecting chip image data after packaging.

[0048] Figure 7This is a flowchart in which the detection module performs error detection on the chip based on the chip image data. If it meets the threshold, the packaging is completed. If it exceeds the threshold, an alarm is issued. DETAILED DESCRIPTION

[0049] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0050] See also Figures 1 to 7 In a first aspect, the present invention provides a flip chip packaging method, comprising the following steps:

[0051] S1 builds the recognition module and detection module;

[0052] S101 collects images of correct and incorrect placement of inverted chip soldering;

[0053] Specifically, a high-resolution industrial camera was used to capture numerous sample images of inverted chips, both correctly and incorrectly positioned, before soldering. Images of correctly positioned chips should demonstrate proper alignment between the chip and substrate, with pins correctly aligned. Images of incorrectly positioned chips should also include common errors such as misaligned pins, tilted chips, or missing chips.

[0054] S102 marks the center coordinates of the correctly placed images and the incorrectly placed images to obtain a marked image dataset;

[0055] Specifically, we use the image annotation tool LabelImg to mark the center coordinates of the chip in each image and distinguish between labels for correct and incorrect placement. The labeled images and corresponding label information will form a labeled image dataset.

[0056] S103 sets training parameters, a training set, and a test set based on the labeled image dataset;

[0057] Specifically, according to the requirements of the YOLO model, training parameters are set, including learning rate, number of iterations, batch size, etc. The labeled image dataset is divided into a training set and a test set, with the ratio of the training set to the test set being 7:3, and the model performance is evaluated using the test set.

[0058] S104 trains the YOLO model based on the training parameters and the training set to obtain a primary model;

[0059] Specifically, the YOLO model is trained using the training set and the set training parameters. During training, the model learns to distinguish between correctly and incorrectly placed chips. Images from the training set are input into the model, and features are extracted through structures such as convolutional layers and pooling layers. The fully connected layers then output the target's category and location information. The loss function is calculated based on the model's output and annotation information. The loss function typically consists of two parts: classification loss and localization loss. The gradient is calculated based on the loss function value and propagated to each layer of the model using the chain rule. The optimizer is used to update the model's weights based on the gradient. The above steps are repeated until the preset number of iterations is reached.

[0060] S105 evaluates the primary model based on the test set to obtain a recognition module.

[0061] Specifically, the test set data is scaled and normalized to ensure the model can correctly process the input data. The preprocessed test set is then fed into the model for forward propagation to obtain the model's predictions. Based on the model's predictions and the test set's annotations, the selected evaluation metrics are calculated. The calculated evaluation metrics are then analyzed in depth to understand the model's performance in various areas, including accuracy, precision, and recall. Visualization tools such as confusion matrices and receiver operating characteristic (ROC) curves are used to further analyze the model's performance.

[0062] S201 collects a normal image dataset and an abnormal image dataset after the inverted chip is packaged;

[0063] Specifically, an industrial camera was used to capture a large number of normal and abnormal images of inverted chip packages. Normal images showed good chip soldering and reliable pin connections, while abnormal images included poor soldering, broken pins, and chip detachment.

[0064] S202 performs error position marking, type marking, and error value marking on the normal image dataset and the abnormal image dataset respectively;

[0065] Specifically, an image annotation tool is used to mark the error location in each image and distinguish the error type (bad soldering, broken pins, etc.) and error value (number of missing solder joints, length of broken pins, etc.).

[0066] S203 sets training parameters, training sets, and test sets based on the labeled images;

[0067] Specifically, training parameters include the learning rate, batch size, number of iterations, and optimizer. After obtaining labeled images, they are divided into a training set and a test set. The training set is used for model training, while the test set is used to evaluate model performance. The training set and the test set should contain similar data distribution and characteristics. To reduce the impact of randomness in the data partitioning process on model performance, multiple random partitions are used and the results are averaged for evaluation. Cross-validation and other methods are also used to further improve evaluation accuracy.

[0068] S204 trains the SSD model based on the training parameters and the training set to obtain a primary model;

[0069] Specifically, when building the SSD model architecture, the base network can be a pre-trained network such as VGG16 or MobileNetV2. Additional convolutional layers are added to these feature layers to predict bounding boxes and categories. The loss function is defined: the SSD loss function typically consists of two parts: localization loss and classification loss. The SSD model is trained using the training set and the specified training parameters. During training, the model learns how to detect errors in the packaged chip, including their location and category. Regular evaluation of model performance on the validation set is necessary during training to allow for timely adjustment of hyperparameters or refinement of the model architecture.

[0070] S205 evaluates the primary model based on the test set to obtain a detection module.

[0071] Specifically, the trained primary model is evaluated using the test set, and model performance is assessed by calculating metrics such as detection accuracy and false alarm rate. If performance meets the requirements, the model is used as a detection module. Based on the model output and the annotation information of the test set, a series of evaluation metrics are calculated to evaluate the model's performance. Evaluation metrics include detection accuracy, false alarm rate, false negative rate, and mean average precision (APR). Detection accuracy (APR) is the ratio of the number of correctly detected target objects to the total number of target objects in the test set. False positive rate (FPR) is the ratio of the number of non-target objects incorrectly identified as targets to the total number of non-target objects in the test set. Miss rate (MR) is the ratio of the number of undetected target objects to the total number of target objects in the test set. Mean average precision (mAP; precision and recall) is a comprehensive evaluation metric. Based on the calculated evaluation metric values, it is determined whether the model's performance meets the requirements of practical applications. If the performance meets the requirements, the model can be used as a detection module for subsequent application or deployment; if the performance does not meet the requirements, the model needs to be further optimized and improved.

[0072]

[0073] S2 collects chip placement and welding videos in real time;

[0074] S21 places the chip on the substrate and welds the chip using welding equipment;

[0075] Specifically, an automated equipment robot arm is used to accurately place the chip on the substrate and then weld it using a welding machine.

[0076] S22 uses industrial cameras to capture real-time data of the chip processing process, obtaining placement and welding videos.

[0077] Specifically, during the chip placement and welding process, high-resolution industrial cameras are used to capture the processing process in real time, generating placement and welding videos that will be used for subsequent recognition and analysis.

[0078] The S3 recognition module detects the placement video and welding video and obtains the recognition result. If the recognition result exceeds the threshold, an alarm is issued. If it does not exceed the threshold, the module proceeds to the next step.

[0079] The S31 recognition module performs noise reduction, contrast enhancement, and frame rate adjustment on placement and welding videos;

[0080] Specifically, filtering techniques, such as mean, Gaussian, or median filters, are used to process the video frames pixel by pixel to smooth the image and reduce noise. Image contrast is enhanced by adjusting image brightness and contrast parameters or using techniques such as adaptive histogram equalization. The video frame rate is increased or decreased based on actual needs to ensure it meets analysis requirements.

[0081] S32 extracts the placement, outline, and edge of the chip based on the processed video and generates feature items;

[0082] Specifically, techniques such as template matching and color space conversion are used to locate the chip within the video frame. Edge detection algorithms (such as the Canny edge detector) and contour extraction algorithms (such as the Hough transform) are employed to extract the chip's outline and edges within the video frame. Based on actual needs, the extracted information is converted into numerical feature items, such as the chip's area, perimeter, and aspect ratio.

[0083] S33 performs a threshold judgment on the feature item based on a preset threshold. If the threshold is exceeded, an alarm is issued. If the threshold is not exceeded, the process proceeds to the next step.

[0084] Specifically, based on historical data and experience, a threshold range is set for each feature item. The extracted feature item is compared with the preset threshold. If the feature item value exceeds the threshold range, it is considered that there is a problem with the chip placement or soldering, and an alarm signal is issued. If it does not exceed the threshold range, the next step of analysis is carried out.

[0085] S4 collects chip image data after packaging;

[0086] S41 arranges the chips welded in the same batch in sequence in the image acquisition area;

[0087] Specifically, the chips that have been welded in the same batch are neatly arranged in the image acquisition area to ensure that each chip can be clearly photographed.

[0088] S42 uses industrial cameras to perform static and dynamic acquisition of chips from the same batch to obtain chip image data.

[0089] Specifically, an industrial camera is used to perform both static and dynamic image acquisition of chips from the same batch. Static acquisition can obtain clear images of the chips for subsequent analysis; dynamic acquisition can observe changes in the chips under specific conditions (such as temperature changes, vibration, etc.).

[0090] The S5 detection module performs chip error detection based on chip image data. If the error meets the threshold, the package is completed. If the error exceeds the threshold, an alarm is issued.

[0091] The S51 detection module uses image processing algorithms and machine learning models to extract pin connections, solder joints, chip area, solder joint spacing, and solder joint size features from chip images;

[0092] Specifically, image processing algorithms (such as morphological processing, edge detection, etc.) and machine learning models (such as SSD models) are used to extract feature information such as pin connections, solder joints, chip area, solder joint spacing, and solder joint size from chip images.

[0093] S52 performs error calculation on the feature information based on a preset threshold to obtain an error value;

[0094] Specifically, error calculation is performed on the extracted feature information according to a preset threshold value; error values ​​such as the deviation between the welding point and the preset position, the integrity of the pin connection, etc. are calculated.

[0095] S53 judges the error value based on a preset error threshold. If it exceeds the preset error threshold, an alarm signal is issued and corresponding error information and position indication are provided. If it meets the preset error threshold, the packaging is completed.

[0096] Specifically, the calculated error value is judged according to the preset error threshold. If the error value exceeds the preset threshold range, it is considered that the chip has an error problem, an alarm signal is issued, and corresponding error information and position indications are provided; if it does not exceed the preset threshold range, it is considered that the chip packaging is completed and the quality is qualified. Position error calculation: For position features such as welding points and pins, the position error is obtained by calculating the deviation between the actual position and the ideal position. Shape error calculation: For shape features such as the contour and edge of the chip, the shape error is obtained by comparing the difference between the actual shape and the ideal shape. Integrity error calculation: For features such as the integrity of the pin connection, the integrity error is obtained by checking whether the connection status meets the preset requirements.

[0097]

[0098] Among them, x 实际 and y 实际 is the actual position coordinate, x 理想 and y 理想 are the ideal position coordinates.

[0099]

[0100] Among them, (xi, yi) is the point on the actual contour, (x 理想，i ,y 理想，i ) is the corresponding point on the ideal contour, dideal, and i is the shortest distance from the actual point to the ideal contour.

[0101] S6 stores and backs up the welding records of chips in the same batch.

[0102] Specifically, the welding process records (including videos, images, analysis results, etc.) of the same batch of chips are stored and backed up. These records can be used for subsequent quality traceability and problem troubleshooting. At the same time, they can also serve as the basis for subsequent improvement and optimization of production processes. Determine the content and form of the records based on the specific requirements and standards of the welding project. Select appropriate video, image recording equipment and detection equipment based on recording needs. Set the recording parameters to ensure that the parameters of the recording equipment are set correctly, including resolution, frame rate, storage location, etc. Collect and analyze data: After welding is completed, collect data such as videos, images, and analysis results. Organize and analyze the data to evaluate the welding quality. Store the collected data in a safe and reliable storage medium. Back up the data to prevent loss or damage.

[0103] In a second aspect, a flip chip packaging structure is provided, which is used in the flip chip packaging method described in the first aspect, and is characterized in that it includes a substrate and a packaging film.

[0104] The flip chip packaging structure and packaging method provided by the present invention have the following beneficial effects:

[0105] First, the flip-chip packaging structure and packaging method provided by this invention achieves high-precision recognition and detection of chip placement and soldering processes by constructing a recognition module (based on the YOLO model) and a detection module (based on the SSD model). This can accurately distinguish between correctly and incorrectly placed chips, as well as normal and abnormal states after packaging, thereby effectively improving packaging quality.

[0106] Second, the flip-chip packaging structure and packaging method provided by this invention captures real-time video of chip placement and welding. A recognition module performs preprocessing, including noise reduction, contrast enhancement, and frame rate adjustment. Feature extraction is then used for threshold determination. This process enables real-time monitoring of chip processing and, if problems are identified, immediate alerts are issued, ensuring timely discovery and resolution.

[0107] Third, the flip-chip packaging structure and packaging method inspection module provided by this invention uses image processing algorithms and machine learning models to extract various feature information from chip images, including pin connections, solder joints, chip area, solder joint spacing, and solder joint size. It then calculates the error of these feature information based on preset thresholds, achieving comprehensive inspection of chip packaging quality.

[0108] Fourth, the flip-chip packaging structure and packaging method provided by this invention stores and backs up soldering process records for chips from the same batch, including videos, images, and analysis results. This not only facilitates subsequent quality traceability and problem troubleshooting, but also serves as a basis for improving and optimizing production processes, contributing to the continuous improvement of packaging quality.

[0109] The identification and detection modules in the flip-chip packaging structure and packaging method provided by this invention are both built on advanced machine learning models, offering high flexibility and scalability. As technology continues to evolve, the models can be easily updated and optimized to adapt to new packaging requirements and challenges.

[0110] The above disclosure is only a preferred embodiment of a flip chip packaging structure and packaging method of the present invention. Of course, this cannot be used to limit the scope of rights of the present invention. Ordinary technicians in this field can understand that implementing all or part of the processes of the above embodiment and making equivalent changes in accordance with the claims of the present invention still fall within the scope of the invention.

Claims

1. A flip chip packaging method, characterized in that: The following steps are involved: Constructing a recognition module and a detection module, wherein the construction of the recognition module includes the following steps: Collect images of correct and incorrect placement of inverted chip soldering; Mark the center coordinates of the correctly placed images and the incorrectly placed images to obtain a marked image dataset; Set training parameters, training set and test set based on labeled image dataset; Train the YOLO model based on the training parameters and training set to obtain a primary model; The primary model is evaluated based on the test set to obtain a recognition module; the construction of the detection module includes the following steps: Collect normal image datasets and abnormal image datasets after flip chip packaging; Mark the error position, type and error value of the normal image dataset and the abnormal image dataset respectively; Set training parameters, training set, and test set based on the labeled images; Train the SSD model based on the training parameters and training set to obtain a primary model; Evaluate the primary model based on the test set to obtain the detection module; Real-time acquisition of chip placement and welding videos; The recognition module performs detection based on the placement video and welding video to obtain the recognition result. If the recognition result exceeds the threshold, an alarm is issued. If it does not exceed the threshold, the next step is entered, which includes the following steps: The detection module uses image processing algorithms and machine learning models to extract pin connections, solder joints, chip area, solder joint spacing, and solder joint size features from chip images; Perform error calculation on the feature information based on a preset threshold to obtain an error value; The error value is judged based on the preset error threshold. If it exceeds the preset error threshold, an alarm signal is issued and the corresponding error information and position indication are provided. If it meets the preset error threshold, the packaging is completed; Collect chip image data after packaging; The detection module performs chip error detection based on chip image data. If the error meets the threshold, the package is completed. If the error exceeds the threshold, an alarm is issued. Store and back up the welding records of chips in the same batch.

2. The flip chip packaging method according to claim 1, wherein: The following steps are included in the real-time acquisition of chip placement and soldering videos: Place the chip on the substrate and weld it using welding equipment; The chip processing process is captured in real time by industrial cameras to obtain placement video and welding video.

3. The flip chip packaging method according to claim 1, wherein: The following steps are included in the process of "the recognition module performs detection based on the placement video and the welding video to obtain a recognition result. If the recognition result exceeds a threshold, an alarm is issued; if it does not exceed the threshold, the next step is performed": The recognition module removes noise, enhances contrast, and adjusts the frame rate of placement and welding videos; Extract the placement, outline, and edges of the chip based on the processed video and generate feature items; The feature item is judged based on the preset threshold. If it exceeds the threshold, an alarm is issued. If it does not exceed the threshold, the next step is entered.

4. The flip chip packaging method according to claim 1, wherein: The "Acquisition of Post-Packaging Chip Image Data" step includes the following steps: Arrange the chips that have been welded in the same batch in the image acquisition area in sequence; Chips from the same batch are collected statically and dynamically using industrial cameras to obtain chip image data.

5. A flip chip packaging structure, used in the flip chip packaging method according to any one of claims 1 to 4, characterized in that: Including substrate and packaging film.

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