A method, device, and medium for determining a target test scenario

Abstract

This application relates to the field of semiconductor testing technology. In particular, it relates to a method, device, and medium for determining a target test solution. The method includes: obtaining the chip distribution information of the wafer to be tested and the target test conditions, where the chip distribution information includes multiple chips arranged in a matrix and the test requirement information of each chip; generating candidate test steps corresponding to the wafer to be tested according to the test capabilities of the probe card and the position coordinate information of the multiple chips, where the candidate test steps include the position coordinate information of the chips covered by the probe card in a single time; determining the target test solution of the wafer to be tested according to the candidate test steps, where the target test solution includes multiple target test steps, and the target test solution meets the target test conditions. The purpose of automatically and intelligently determining the target test solution that meets the target test conditions is achieved. The intelligent determination of the test path is realized, improving the efficiency.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technologies, and in particular, to a method, device, and medium for determining a target test plan. Background Art

[0002] In the semiconductor manufacturing process, chips (DUT, Device Under Test) are fabricated on wafers. Probe card testing involves contacting the solder joints of the chips with the pins on the probe card to test whether the functions of the chips are normal. Probe card testing is a key link to ensure the quality of chips. Traditional testing methods rely on manual experience to determine the test path and are not intelligent; chips that do not need to be tested are tested, resulting in waste of time and resources. Therefore, there is an urgent need for a method in the prior art that can automatically determine a target test plan. Summary of the Invention

[0003] To solve the above problems, the present application provides a method, device, and medium for determining a target test plan.

[0004] According to one aspect of the present application, a method for determining a target test plan is provided. The method includes:

[0005] Obtaining chip distribution information and target test conditions of a wafer to be tested, where the chip distribution information includes a plurality of chips arranged in a matrix and test requirement information of each chip;

[0006] Generating candidate test steps corresponding to the wafer to be tested according to the test capabilities of the probe card and the position coordinate information of the plurality of chips, where the candidate test steps include the position coordinate information of the chips covered by the probe card in a single time;

[0007] Determining a target test plan for the wafer to be tested according to the candidate test steps, where the target test plan includes a plurality of target test steps and the target test plan meets the target test conditions.

[0008] According to one aspect of the present application, a computer device is provided. The device includes:

[0009] A processor; and

[0010] A memory arranged to store computer-executable instructions, and the executable instructions, when executed, cause the processor to perform the operations of any of the above methods.

[0011] According to one aspect of the present application, a computer-readable medium storing instructions is provided, and the instructions, when executed, cause the system to perform the operations of any of the above methods.

[0012] Compared with the prior art, the present application generates a candidate test step corresponding to the wafer to be tested by obtaining the chip distribution information of the wafer to be tested and the target test conditions, and generating the candidate test step according to the test capabilities of the probe card and the position coordinate information of multiple chips; determines the target test plan for the wafer to be tested according to the candidate test steps. The purpose of automatically and intelligently determining the target test plan that meets the target test conditions is achieved. The intelligent determination of the test path is realized, and the efficiency is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments read in conjunction with the accompanying drawings:

[0014] Figure 1 FIG. shows a flowchart of a method for determining a target test plan according to an embodiment of the present application;

[0015] Figure 2 FIG. shows the chip distribution information according to an embodiment of the present application;

[0016] Figure 3 FIG. shows the chip distribution information according to another embodiment of the present application;

[0017] Figure 4 FIG. shows a schematic structural diagram of a device for determining a target test plan according to an embodiment of the present application;

[0018] Figure 5 FIG. shows an exemplary system that can be used to implement the various embodiments described in the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The present application will be further described in detail below with reference to the accompanying drawings.

[0020] In a typical configuration of the present application, the terminal, the device of the service network, and the trusted party each include one or more processors (e.g., a central processing unit (CPU)), an input / output interface, a network interface, and a memory.

[0021] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of, for example, read only memory (ROM) or flash memory. The memory is an example of a computer-readable medium.

[0022] A computer-readable medium includes both permanent and non-permanent, removable and non-removable media that can store information by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PCM), programmable random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tapes, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to store information that can be accessed by a computing device.

[0023] The devices referred to in this application include, but are not limited to, terminals, network devices, or devices formed by integrating terminals and network devices through a network. The terminals include, but are not limited to, any mobile electronic product that can perform human-computer interaction with users (such as human-computer interaction through a touchpad), such as smartphones, tablets, etc. The mobile electronic products can adopt any operating system, such as the Android operating system, the iOS operating system, etc. Among them, the network devices include an electronic device that can automatically perform numerical calculations and information processing according to pre-set or stored instructions. Its hardware includes, but is not limited to, a microprocessor, an Application Specific Integrated Circuit (ASIC), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), an embedded device, etc. The network devices include, but are not limited to, computers, network hosts, a single network server, a set of multiple network servers, or a cloud composed of multiple servers; here, the cloud is composed of a large number of computers or network servers based on Cloud Computing. Among them, Cloud Computing is a type of distributed computing, consisting of a virtual supercomputer formed by a group of loosely coupled computer sets. The network includes, but is not limited to, the Internet, wide area network, metropolitan area network, local area network, VPN network, wireless ad hoc network (Ad Hoc network), etc. Preferably, the device can also be a program running on the terminal, network device, or a device formed by integrating the terminal and network device, network device, touch terminal, or network device and touch terminal through a network.

[0024] Of course, those skilled in the art should understand that the above devices are only examples. Other existing or future devices that are applicable to this application should also be included within the protection scope of this application and are hereby incorporated by reference.

[0025] In the description of this application, "a plurality of" means two or more, unless otherwise specifically defined.

[0026] Figure 1The figure shows a flowchart of a method for optimizing the contact times of a probe card according to an embodiment of the present application. The method includes step S11, step S12, and step S13. In step S11, chip distribution information of a wafer to be tested and target test conditions are obtained. The chip distribution information includes a plurality of chips arranged in a matrix and test requirement information for each chip. In step S12, candidate test steps corresponding to the wafer to be tested are generated according to the test capabilities of the probe card and the position coordinate information of the plurality of chips. The candidate test steps include the position coordinate information of the chips covered by the probe card in a single pass. In step S13, a target test plan for the wafer to be tested is determined according to the candidate test steps. The target test plan includes a plurality of target test steps, and the target test plan meets the target test conditions.

[0027] Specifically, in step S11, chip distribution information of a wafer to be tested and target test conditions are obtained. The chip distribution information includes a plurality of chips arranged in a matrix and test requirement information for each chip. In some embodiments, the test requirement information includes being required to be tested or not required to be tested. In some embodiments, reference is made to Figure 2 the plurality of chips arranged in a matrix and the test requirement information for each chip as shown. The system uses 1 to represent the chips that need to be tested and 0 to represent the chips that do not need to be tested. By marking the test requirements of the chips, unnecessary tests are avoided. In some embodiments, the method of this solution can be implemented through a corresponding software APP. For example, an input window is set on the system interface, and the user can input information such as target test conditions (for example, the user name and other information can also be input) through the input window. In some embodiments, the target test conditions include but are not limited to test coverage rate and the number of chips with multiple contacts. For example, the test coverage rate needs to reach the target test coverage rate, and the number of chips with multiple contacts needs to be less than the target number of chips with multiple contacts. In some embodiments, the test coverage rate includes the ratio between the number of new chips that can be tested by the test plan and the total number of new chips, where the new chips include the chips that need to be tested. For example, the test plan includes a plurality of test steps, and each test step can test one or more new chips. The test coverage rate includes the ratio between the number of new chips that can be tested by the test plan and the total number of new chips that need to be tested. The number of chips with multiple contacts includes the number of chips that are contacted by the probe card multiple times during the test process. For example, if test step A contacts new chip A and test step B also contacts new chip A, then this new chip A belongs to the chips with multiple contacts.

[0028] In step S12, candidate test steps corresponding to the wafer to be tested are generated according to the test capabilities of the probe card and the position coordinate information of multiple chips. Herein, those skilled in the art can understand that the test capabilities of the probe card include the number and range of chips (DUTs) that the probe card can cover in one test operation. Specifically, the number of needles on the probe card determines the number of chips that can be tested simultaneously in each test (for example, a four-needle probe card can test four chips simultaneously). The needle layout of the probe card determines the chip range covered in each test (for example, a 2x2 area). In some embodiments, the system traverses multiple chips arranged in a matrix according to the test capabilities of the probe card to generate candidate test steps corresponding to the wafer to be tested, so that all candidate test steps can cover multiple chips arranged in a matrix. For example, referring to Figure 2 , the position coordinate information of the chip located in the upper left corner includes (1,1), and so on. The position coordinate information of the chip located in the lower right corner includes (5,6). The system traverses multiple chips arranged in the entire matrix to generate candidate test steps that can cover multiple chips arranged in the entire matrix. For example, the test capabilities of the probe card include being able to test 4 chips at a time, and the test range is a 2x2 area. Figure 2 The candidate test steps corresponding to the multiple chips arranged in the matrix shown in

[0029] In step S13, a target test solution for the wafer to be tested is determined according to the candidate test steps. The target test solution includes multiple target test steps and meets the target test conditions. In some embodiments, the target test solution can be obtained by first generating an initial test solution based on the candidate test steps and then optimizing the initial test solution. For specific descriptions of this part, please refer to the corresponding embodiments below and will not be elaborated here. In some embodiments, the test solution includes multiple test steps, and it can be determined whether the test solution meets the target test conditions by calculating the test coverage rate of the test solution and the number of chips with multiple contacts. For example, the test solution includes test step A: (1,1), (1,2), (2,1), (2,2); test step C: (1,3), (1,4), (2,3), (2,4). The chips to be tested include (1,1), (1,2), (1,3), (2,1), (2,2), (2,3), (1,5), (2,5). Then the test coverage rate of this test solution is 75%, and the number of chips with multiple contacts is 0.

[0030] In some embodiments, before step S13, the method further includes step S14 (not shown). In step S14, if the candidate test step meets the exclusion condition, the candidate test step is excluded to obtain the candidate test steps after exclusion and screening. In some embodiments, in order to improve the analysis speed and accuracy, the test steps that will definitely not be used as the target test solution are excluded. In some embodiments, the exclusion conditions include, but are not limited to, that the candidate test step does not include the chips to be tested, and the candidate test step includes chips outside the valid area. For example, if there is a candidate test step, and the test requirement information of the chips included in the candidate test step is not required to be tested, the candidate test step can be directly excluded. Of course, those skilled in the art can understand that the above-mentioned exclusion conditions are only examples, and other or existing possible exclusion conditions that can be applied to this application are also within the protection scope of this application.

[0031] In some embodiments, the exclusion condition includes that the candidate test step includes chips outside the valid area, and the method further includes step S15 (not shown). In step S15, the diameter of the valid area of the wafer to be tested is determined according to the wafer valid area calculation algorithm, where the calculation algorithm includes , where r includes the diameter of the effective area, R includes the wafer diameter, and L includes the edge width of the wafer to be tested; if there is a target candidate test step in the candidate test steps, the target candidate test step is deleted, where the target candidate test step includes chips outside the effective area. In some embodiments, the edge area of the wafer is generally not suitable for testing because the chips at the edge may be incomplete or defective. The effective area includes the area other than the edge area. If the chips included in a candidate test step exceed the effective area, it may lead to test failure or resource waste. In some embodiments, if a candidate test step includes chips outside the effective area, then the candidate test step is deleted as the target candidate test step. In some embodiments, the system can detect the chips located outside the effective area by calculating the distance of each chip from the center of the wafer according to the position coordinate information of each chip. For example, if there is a target candidate test step, the candidate test step includes chips (6,1), (6,2), (7,1), (7,2), where the distance of (7,1) from the center of the wafer is greater than the radius r of the effective area, then the candidate test step is deleted as the target candidate test step.

[0032] In some embodiments, step S13 includes step S131 (not shown) and step S132 (not shown). In step S131, an initial test plan for the wafer to be tested is generated according to the candidate test steps; in step S132, the initial test plan is optimized by an optimization algorithm to generate a target test plan for the wafer to be tested, where the target test plan meets the target test conditions. In some embodiments, multiple candidate test steps can be randomly selected as the initial test plan. In other embodiments, the initial test plan can be determined according to the number of new chips included in the candidate test steps. For specific descriptions of this part, please refer to the corresponding embodiments below and will not be elaborated here. After determining the initial test plan, the initial test plan is optimized by an optimization algorithm to obtain a target test plan that meets the target test conditions.

[0033] In some embodiments, step S131 includes: initializing a chip set, where the chip set includes the chips to be tested among multiple chips; preferably selecting the candidate test step with the largest number of chips in the chip set as the initial test step in the initial test plan; deleting the chips included in the initial test step from the chip set to update the chip set; preferably selecting the candidate test step with the largest number of chips in the updated chip set from the remaining candidate test steps as the initial test step in the initial test plan; repeating the above steps until the number of chips in the chip set is zero to obtain the initial test plan. For example, the system initializes the chip set to be tested. For example, the chip set to be tested includes (1,1), (1,2), (1,3), (1,5), (2,1), (2,2), (2,3), (2,5). The candidate test steps include candidate test step A: (1,1), (1,2), (2,1), (2,2); candidate test step B: (1,2), (1,3), (2,2), (2,3); candidate test step C: (1,3), (1,4), (2,3), (2,4); candidate test step D: (1,4), (1,5), (2,4), (2,5). Among them, the number of chips to be tested included in candidate test step A is 4, the number of chips to be tested included in candidate test step B is 4, the number of chips to be tested included in candidate test step C is 2, and the number of chips to be tested included in candidate test step D is 2. According to the number of chips to be tested included, preferentially select the candidate test step with a larger number. For example, preferentially select from candidate test steps A and B, and randomly select from candidate test steps A and B. For example, select candidate test step A as a test step in the initial test plan. Update the chip set to be tested to (1,3), (1,5), (2,3), (2,5). In some embodiments, every time a candidate test step is selected, the chips included in the selected candidate test step are deleted from the chip set to be tested to update the chip set in real time. Then, according to the updated chip set, select the candidate test step with the largest number of chips in the chip set from the remaining candidate test steps as the test step in the initial test plan. For example, candidate test steps B, candidate test step C, and candidate test step D all include 2 chips in the chip set, then randomly determine candidate test step B as the test step in the initial test plan. Update the chip set to (1,5), (2,5). The number of chips in the updated chip set included in candidate test step C is 0, and the number of chips in the updated chip set included in candidate test step D is 2, then select candidate test step D as the test step in the initial test plan. The initial test plan includes candidate test step A, candidate test step B, and candidate test step D.

[0034] In some embodiments, step S132 includes: calculating the fitness of each initial test scenario, where, , here, f includes fitness, a includes test coverage rate, b includes the number of test steps, and x includes weight; performing crossover and mutation processing on the initial test scenarios with fitness equal to or greater than the first fitness threshold to obtain a target test scenario that meets the target test conditions, where the target test conditions have fitness equal to or greater than the second fitness threshold. In some embodiments, there may be multiple initial test scenarios, including but not limited to the initial test scenarios determined through the chip set mentioned in the above embodiments, randomly determined initial test scenarios, or initial test scenarios specified by the user (for example, the user specifies an initial test scenario through an input window on the system interface). After obtaining the initial test scenarios, the system calculates the fitness of each initial test scenario. In some embodiments, the test coverage rate includes the ratio of the number of chips that need to be tested and can be tested by the initial test scenario to the total number of chips that need to be tested. For example, the above initial test scenario includes candidate test steps A, candidate test step B, and candidate test step D, the number of steps is 3, the test coverage rate is 100%, and the weight is 0.1, then the fitness f = 1 - 3 * 0.3 = 0.7. The system presets the first fitness threshold and selects the initial test scenarios with fitness equal to or greater than the first fitness threshold for optimization. The optimization algorithm includes but is not limited to crossover and mutation processing in the genetic algorithm. For example, the initial test scenario X includes step B, step E, and step D, and the crossover point is 1, then the new initial test scenario obtained after crossover is: step B, step D, step E. For another example, the initial test scenario X includes step B, step E, and step D, and a mutation point is randomly determined (for example, step D), resulting in step C, then step D is replaced with step C. The initial test scenarios are iteratively processed through the optimization algorithm until a target test scenario that meets the target test conditions is obtained, and the target test scenario is saved to be presented to the user. In some embodiments, there may be multiple target test scenarios, and the multiple target test scenarios can be ranked according to fitness, and the top N target test scenarios are presented to the user through the system interface. In some embodiments, there is also a backtracking mechanism. For example, if the fitness of the test scenario obtained through optimization is smaller than that before optimization, then backtrack to the test scenario before optimization. For example, if the fitness of step B, step D, and step E obtained after the crossover processing of the initial test scenario X is less than that of step B, step E, and step D before the crossover processing, then backtrack to step B, step E, and step D before the crossover processing.

[0035] In some embodiments, step S12 includes: dividing the wafer to be tested into multiple regions; for each region, generating a corresponding candidate test step for the region according to the test capabilities of the probe card, the position coordinate information of multiple chips, and the test requirement information of each chip, where the candidate test step includes the coordinate information of the chips covered by the probe card in a single pass; for each region, determining the target test plan for the region according to the candidate test step corresponding to the region, and for each determined target test plan of a region, querying whether there is an identical region in the regions where the target test plan has not been determined according to the chip layout of the region, and the identical region has the same chip layout as that of the region; if there is an identical region for the region, directly determining the target test plan of the region as the target test plan of the identical region; after determining the target test plan for each region, combining the target test plans of the multiple regions into the target test plan of the wafer to be tested. In some embodiments, in order to improve computing power and reduce the overall computing pressure, the wafer to be tested is divided into multiple regions (for example, the wafer to be tested is evenly divided into four regions), and for each region, the target test plan for each region is determined respectively by the above method. After each determined target test plan of a region, querying whether there is an identical region with the same chip layout in the regions where the target test plan has not been determined according to the chip layout of the region. If there is an identical region for the region, directly determining the target test plan based on the region as the target test plan of the identical region. In some embodiments, the chip layout includes the arrangement of the chips with test requirement information and the test requirement information. For example, refer to Figure 3, the wafer is evenly divided into four regions, namely the upper left region, the upper right region, the lower left region, and the lower right region. Among them, the chip layouts in the lower left region and the lower right region are the same. For example, the chip arrangements and test requirement information in the lower left region and the lower right region are the same. If it is determined that the target test plan for the lower left region includes target test steps (3, 2), (3, 3), (4, 2), (4, 3), and target test steps (3, 1), (3, 2), (4, 1), (4, 2), then directly determine the target test plan for the lower right region according to the target test plan for the lower left region (for example, (3, 5), (3, 6), (4, 5), (4, 6), and target test steps (3, 4), (3, 5), (4, 4), (4, 5)). In some embodiments, the system uses 1 to represent a chip that needs to be tested and 0 to represent a chip that does not need to be tested. By comparing the chip layouts of the regions, for example, by comparing whether the 0 / 1 chip layouts of the two regions coincide, it is determined whether the chip layouts of the two regions are the same. Thus, according to the target test steps of the target test plan for the lower left region, the target test steps for the lower right region are determined. Specifically, the target test plan for the lower right region can be determined according to the order among the various target test steps in the lower left region. For example, if the target test steps included in the target test plan for the lower left region are spread across the lower left region from right to left in sequence, then the target test plan for the lower right region is also spread across the lower right region from right to left in sequence. Of course, those skilled in the art can understand that the specific process of determining the target test plan for the region with the same chip layout as a certain region according to the target test plan of the region described above is only an example, and other existing or future possible specific processes that can be applied to this application are also within the protection scope of this application.

[0036] Figure 4 FIG. shows a schematic structural diagram of a device for determining a target test plan according to an embodiment of the present application. The device includes a module 11, a module 12, and a module 13. The module 11 is used to obtain the chip distribution information and target test conditions of the wafer to be tested. Among them, the chip distribution information includes a plurality of chips arranged in a matrix and the test requirement information of each chip. The module 12 is used to generate candidate test steps corresponding to the wafer to be tested according to the test capabilities of the probe card and the position coordinate information of the plurality of chips. Among them, the candidate test steps include the position coordinate information of the chips covered by the probe card in a single time. The module 13 is used to determine the target test plan of the wafer to be tested according to the candidate test steps. Among them, the target test plan includes a plurality of target test steps, and the target test plan meets the target test conditions.

[0037] Here, the specific implementation manners of the module 11, the module 12, and the module 13 are the same as or similar to the specific embodiments of step S11, step S12, and step S13, and thus will not be elaborated herein and are included herein by reference.

[0038] In addition to the methods and devices described in the above embodiments, the present application also provides a computer-readable storage medium storing computer code, which, when executed, causes the method described in any of the previous items to be executed.

[0039] The present application also provides a computer program product, which, when executed by a computer device, causes the method described in any of the previous items to be executed.

[0040] The present application also provides a computer device, which includes:

[0041] One or more processors;

[0042] A memory for storing one or more computer programs;

[0043] When the one or more computer programs are executed by the one or more processors, the one or more processors are caused to implement the method described in any of the previous items.

[0044] Figure 5 An exemplary system that can be used to implement the various embodiments described in the present application is shown;

[0045] As Figure 5 shown, in some embodiments, system 300 can act as any one of the devices in the various embodiments. In some embodiments, system 300 may include one or more computer-readable media having instructions (e.g., system memory or NVM / storage device 320) and one or more processors (e.g., (one or more) processors 305) coupled to the one or more computer-readable media and configured to execute the instructions to implement modules to perform the actions described in the present application.

[0046] For one embodiment, system control module 310 may include any suitable interface controller to provide any suitable interface to at least one of (one or more) processors 305 and / or any suitable device or component communicating with system control module 310.

[0047] System control module 310 may include a memory controller module 330 to provide an interface to system memory 315. Memory controller module 330 may be a hardware module, a software module, and / or a firmware module.

[0048] System memory 315 may be used, for example, to load and store data and / or instructions for system 300. For one embodiment, system memory 315 may include any suitable volatile memory, e.g., suitable DRAM. In some embodiments, system memory 315 may include double data rate type four synchronous dynamic random access memory (DDR4 SDRAM).

[0049] For one embodiment, the system control module 310 may include one or more input / output (I / O) controllers to interface with the NVM / storage device 320 and the communication interface(s) 325.

[0050] For example, the NVM / storage device 320 may be used to store data and / or instructions. The NVM / storage device 320 may include any suitable non-volatile memory (e.g., flash memory) and / or may include any suitable non-volatile storage device(s) (e.g., one or more hard disk drives (HDDs), one or more optical disc (CD) drives, and / or one or more digital versatile disc (DVD) drives).

[0051] The NVM / storage device 320 may include storage resources that are physically part of the device on which the system 300 is installed, or it may be accessible by the device without being part of the device. For example, the NVM / storage device 320 may be accessed via the communication interface(s) 325 over a network.

[0052] The communication interface(s) 325 may provide an interface for the system 300 to communicate over one or more networks and / or with any other suitable device. The system 300 may communicate wirelessly with one or more components of a wireless network according to any of one or more wireless network standards and / or protocols.

[0053] For one embodiment, at least one of the processor(s) 305 may be logically encapsulated with one or more controllers of the system control module 310 (e.g., the memory controller module 330). For one embodiment, at least one of the processor(s) 305 may be logically encapsulated with one or more controllers of the system control module 310 to form a system-in-package (SiP). For one embodiment, at least one of the processor(s) 305 may be logically integrated with one or more controllers of the system control module 310 on the same die. For one embodiment, at least one of the processor(s) 305 may be logically integrated with one or more controllers of the system control module 310 on the same die to form a system-on-chip (SoC).

[0054] In various embodiments, system 300 can be, but is not limited to, a server, a workstation, a desktop computing device, or a mobile computing device (e.g., a laptop computing device, a handheld computing device, a tablet computer, a netbook, etc.). In various embodiments, system 300 can have more or fewer components and / or a different architecture. For example, in some embodiments, system 300 includes one or more cameras, a keyboard, a liquid crystal display (LCD) screen (including a touch screen display), a non-volatile memory port, multiple antennas, a graphics chip, an application specific integrated circuit (ASIC), and speakers.

[0055] It should be noted that the present application can be implemented in software and / or a combination of software and hardware. For example, it can be implemented using an application specific integrated circuit (ASIC), a general purpose computer, or any other similar hardware device. In one embodiment, the software program of the present application can be executed by a processor to implement the steps or functions described above. Similarly, the software program of the present application (including related data structures) can be stored in a computer-readable recording medium, such as a RAM memory, a magnetic or optical drive, or a floppy disk and similar devices. Additionally, some steps or functions of the present application can be implemented using hardware, for example, as a circuit that cooperates with a processor to execute each step or function.

[0056] In addition, a part of the present application can be applied as a computer program product, such as computer program instructions. When executed by a computer, through the operation of the computer, it can call or provide the methods and / or technical solutions according to the present application. Those skilled in the art should understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to the computer.

[0057] A communication medium includes a medium through which communication signals that include, for example, computer-readable instructions, data structures, program modules, or other data are transmitted from one system to another. The communication medium can include a guided transmission medium (such as cables and wires (e.g., optical fiber, coaxial, etc.)) and a wireless (unguided) medium that can propagate energy waves, such as sound, electromagnetic, RF, microwave, and infrared. The computer-readable instructions, data structures, program modules, or other data can be embodied as, for example, a modulated data signal in a wireless medium (such as a carrier wave or a similar mechanism that is part of what is embodied as spread spectrum technology). The term "modulated data signal" refers to a signal whose one or more characteristics are changed or set in a manner that encodes information in the signal. Modulation can be analog, digital, or a hybrid modulation technique.

[0058] By way of example, and not limitation, a computer-readable storage medium can include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. For example, the computer-readable storage medium includes, but is not limited to, volatile memory such as random access memory (RAM, DRAM, SRAM); and non-volatile memory such as flash memory, various read-only memories (ROM, PROM, EPROM, EEPROM), magnetic and ferromagnetic / ferroelectric memories (MRAM, FeRAM); and magnetic and optical storage devices (hard disks, tapes, CDs, DVDs); or other media now known or later developed that are capable of storing computer-readable information / data for use by a computer system.

[0059] Here, an embodiment according to the present application includes an apparatus that includes a memory for storing computer program instructions and a processor for executing the program instructions, wherein when the computer program instructions are executed by the processor, the apparatus is triggered to operate based on the methods and / or technical solutions according to the foregoing multiple embodiments of the present application.

[0060] For those skilled in the art, it is obvious that the present application is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present application, the present application can be implemented in other specific forms.

Claims

1. A method for determining a target test scheme, characterized in that: The method comprises: Obtain chip distribution information and target test conditions of a wafer to be tested, wherein the chip distribution information includes a plurality of chips arranged in a matrix and test requirement information of each chip; Generate candidate test steps corresponding to the wafer to be tested according to the test capability of the probe card and the position coordinate information of the multiple chips, wherein the candidate test steps include the position coordinate information of the chips covered by the probe card at a single time, and all candidate test steps can cover the multiple chips arranged in the matrix; Initializing a chip set, wherein the chip set includes chips that need to be tested among the multiple chips; Selecting a candidate test step including the largest number of chips in the chip set as an initial test step in an initial test plan; Deleting the chips included in the initial testing step from the chip set to update the chip set; Selecting, from the remaining candidate test steps, the candidate test step including the largest number of chips in the updated chip set as the initial test step in the initial test scheme; Repeat the above steps until the number of chips in the chip set is zero, so as to obtain the initial test plan; Calculate the fitness of each initial test scheme, where f=ab*x, where f includes the fitness, a includes the test coverage, b includes the number of test steps, and x includes the weight; An initial test scheme whose fitness is equal to or greater than a first fitness threshold is subjected to crossover and mutation processing to obtain a target test scheme that meets the target test condition, wherein the fitness of the target test condition is equal to or greater than a second fitness threshold.

2. The method according to claim 1, characterized in that The step of generating candidate tests corresponding to the wafer to be tested according to the test capability of the probe card and the position coordinate information of the plurality of chips includes: According to the test capability of the probe card, the multiple chips arranged in the matrix are traversed to generate candidate test steps corresponding to the wafer to be tested, so that all the candidate test steps can cover the multiple chips arranged in the matrix.

3. The method according to claim 1, characterized in that The method further comprises, before determining the target test scheme of the wafer to be tested according to the candidate test steps: If the candidate test step meets the exclusion condition, the candidate test step is excluded.

4. The method according to claim 3, characterized in that The exclusion condition includes that the candidate test step includes chips outside the effective area, and the method further includes: Determine the diameter of the effective area of ​​the wafer to be tested according to a wafer effective area calculation algorithm, wherein the calculation algorithm includes r=R-2*L, where r includes the diameter of the effective area, R includes the wafer diameter, and L includes the edge width of the wafer to be tested; If there is a target candidate test step in the candidate test steps, the target candidate test step is deleted, wherein the target candidate test step includes chips outside the effective area.

5. The method according to claim 1, characterized in that The step of generating candidate tests corresponding to the wafer to be tested according to the test capability of the probe card and the position coordinate information of the plurality of chips includes: Dividing the wafer to be tested into a plurality of areas; For each area, generating candidate test steps corresponding to the area according to the test capability of the probe card, the position coordinate information of multiple chips in the area, and the test requirement information of each chip, wherein the candidate test steps include the coordinate information of the chips covered by the probe card at a single time; For each region, a target test scheme for the region is determined according to the candidate test steps corresponding to the region. After a target test scheme for a region is determined, a query is made based on the chip layout of the region to determine whether there is an identical region in the region where the target test scheme has not been determined. The identical region has the same chip layout as the region. If the same area exists in the area, the target test scheme directly based on the area is determined as the target test scheme for the same area; After determining the target test scheme for each area, the target test schemes for multiple areas are merged into the target test scheme for the wafer to be tested.

6. A computer device for determining a target test scheme, comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 5.

7. A computer-readable storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instructions are executed by a processor, the steps of the method as claimed in any one of claims 1 to 5 are implemented.

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