Automatic testing method, device and electronic equipment for wafer

Abstract

The present invention provides a method, device and electronic device for automated testing of wafers. The method comprises: generating a test plan, automatically acquiring parameter information of the wafer filled in by the user when generating the test plan, automatically determining the edge cutting result of the wafer based on the parameter information, and associating the edge cutting result with the test plan; wherein the edge cutting result includes the edge result of the die to be tested and the complete result of whether each test structure on the die to be tested has been cut; acquiring the test plan, traversing the die to be tested in the test plan, judging whether the test structure of the die to be tested is testable based on the edge cutting result associated with the test plan, and automatically testing the die to be tested. In this manner, the testable range on the entire wafer can be automatically calculated and automated testing of the wafer can be performed, without relying on manual screening, thereby improving test efficiency and preventing errors.

Description

Technical Field

[0001] The present invention relates to the field of wafer testing technology, and in particular to an automated wafer testing method, device and electronic equipment. Background Art

[0002] Currently, during wafer manufacturing, the yield of effective die at the wafer edge is easily affected by various factors due to significant differences in flatness and other factors compared to the wafer center, resulting in yield loss. Therefore, improving the yield of effective die at the wafer edge is a key research focus in the photolithography process. To ensure that the use of inner-ring dies is not affected, current wafers still have full circuits on the die at the edge. However, due to the circular cutting method, the untestable portion of the die at the wafer edge is cut away, which is unpredictable.

[0003] However, for security and data integrity reasons, existing testing methods completely avoid edge die testing, resulting in a large number of test structures (testkeys) being untestable and wasted. Furthermore, if users in the R&D phase need to know edge die test data to study yield differences between the wafer edge and the interior, existing technology typically requires manual screening of testkeys during testing. This manual screening is time-consuming and labor-intensive, and can lead to errors, resulting in multiple cost wastes. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide an automated testing method, device and electronic equipment for wafers, so as to automatically calculate the testable range on the entire wafer and perform automated testing of the wafer, without relying on manual screening, thereby improving testing efficiency and preventing errors.

[0005] In a first aspect, an embodiment of the present invention provides an automated testing method for wafers, the method comprising: generating a test plan, and automatically obtaining parameter information of the wafer filled in by the user when generating the test plan, automatically determining the edge cutting result of the wafer based on the parameter information, and associating the edge cutting result with the test plan; wherein the edge cutting result includes the edge result of the die to be tested and the complete result of whether each test structure on the die to be tested is cut; obtaining the test plan, traversing the die to be tested in the test plan, and judging whether the die to be tested is an edge die based on the edge cutting result; if the die to be tested is not an edge die, automatically testing all the structures to be tested on the die to be tested; if the die to be tested is an edge die, judging whether the structures to be tested on the edge die are complete, and automatically testing the complete structures to be tested.

[0006] In an optional embodiment of the present application, the above-mentioned automatic determination of the edge cutting result of the wafer based on the parameter information includes: automatically determining the position information of each test structure in the bare chip to be tested on the wafer based on the parameter information of the wafer; automatically determining the edge cutting result of the wafer and / or generating a wafer map of the test structure based on the parameter information of the wafer and the position information of each test structure on the wafer, so that the user can select a testable test structure according to the visually displayed wafer map of the test structure and complete the test plan generation.

[0007] In an optional embodiment of the present application, before traversing the die to be tested in the test plan, the method further includes: determining whether the user selects a testable test structure; if so, automatically testing each test structure; if not, executing the step of traversing the die to be tested in the test plan.

[0008] In an optional embodiment of the present application, the above method also includes: obtaining the test results of the automatic test and the wafer map of the test structure, and checking the test data for abnormalities.

[0009] In an optional embodiment of the present application, the above-mentioned automatic determination of the position information of each test structure in the bare chip to be tested on the wafer based on the parameter information of the wafer includes: based on the wafer parameters and bare chip parameters included in the parameter information, the position coordinates located in the bare chip are automatically converted into position information relative to the wafer.

[0010] In an optional embodiment of the present application, the above-mentioned automatic determination of the edge cutting result of the wafer based on the parameter information includes: determining the edge bare chip located at the edge of the wafer among the bare chips to be tested based on the parameter information of the wafer; determining whether the test structure is cut based on the position information of the test structure on the edge bare chip and the parameter information of the wafer, and determining the complete test structure; and obtaining the edge cutting result of the wafer based on the edge bare chip and the complete test structure.

[0011] In an optional embodiment of the present application, the above method further includes: generating a test report for automated testing, and marking the test structure that has not been tested in the test report; wherein the test structure that has not been tested is an incomplete test structure.

[0012] In an optional embodiment of the present application, the above parameter information includes: the radius of the wafer, the offset value between the center of the wafer and the center of the test structure, the position coordinates of each test structure, and the size and position coordinates of the die.

[0013] In a second aspect, an embodiment of the present invention further provides an automated testing device for wafers, the device comprising: a test generation module for generating a test plan, and automatically obtaining parameter information of the wafer filled in by the user to generate the test plan, automatically determining the edge cutting result of the wafer based on the parameter information, and associating the edge cutting result with the test plan; wherein the edge cutting result includes the edge result of the die to be tested and the complete result of whether each test structure on the die to be tested is cut; an automatic testing module for obtaining a test plan, traversing the die to be tested in the test plan, and judging whether the die to be tested is an edge die based on the edge cutting result; if the die to be tested is not an edge die, automatically testing all structures to be tested on the die to be tested; if the die to be tested is an edge die, judging whether the structures to be tested on the edge die are complete, and automatically testing the complete structures to be tested.

[0014] In a third aspect, an embodiment of the present invention further provides an electronic device comprising a processor and a memory, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the above-mentioned automated wafer testing method.

[0015] The embodiments of the present invention bring the following beneficial effects:

[0016] An embodiment of the present invention provides an automated testing method, device, and electronic device for wafers, which generates a test plan and automatically obtains parameter information of the wafer filled in by the user when generating the test plan, automatically determines the edge cutting result of the wafer based on the parameter information, and associates the edge cutting result with the test plan; wherein the edge cutting result includes the edge result of the die to be tested and the complete result of whether each test structure on the die to be tested is cut; traverses the die to be tested in the test plan, determines whether the test structure of the die to be tested is testable based on the edge cutting result associated with the test plan, and automatically tests the die to be tested. In this method, in the process of the user making a test plan, the collaborative automatically obtains relevant information to calculate the edge cutting result including whether the edge bare chip and the test structure are complete, and associates it with the test plan (for example, includes it in the test plan). During the test, it is automatically judged based on the edge cutting result whether it is an edge bare chip and which test structures in the edge bare chip are testable. The entire process can be tested automatically without human intervention and participation. Compared with the existing technology, the existing method of determining whether it is testable by manually operating the test machine according to the test structure information of the test plan greatly improves the test efficiency and test accuracy. Therefore, this solution automatically calculates the testable range on the entire wafer and performs automated testing of the wafer. It does not need to rely on manual screening, can improve test efficiency, and will not cause errors.

[0017] Other features and advantages of the present disclosure will be set forth in the following description, or some features and advantages may be inferred or unambiguously determined from the description, or may be learned by practicing the above-mentioned technology of the present disclosure.

[0018] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 A flowchart of an automated wafer testing method provided by an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of determining an edge cutting result provided by an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of calculating the actual position of each Testkey provided by an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of an intelligent generation of a map image provided by an embodiment of the present invention;

[0024] Figure 5 A flowchart of another wafer automated testing method provided by an embodiment of the present invention;

[0025] Figure 6 A schematic diagram of an automated test provided by an embodiment of the present invention;

[0026] Figure 7 A schematic structural diagram of an automated wafer testing device provided by an embodiment of the present invention;

[0027] Figure 8 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0029] At present, in order to fully utilize wafer resources in existing wafer testing methods, testers often have to manually screen the dies near the edge during testing. Manual screening requires testers to manually jump to the corresponding position of each testkey through the machine according to the coordinates, and visually judge whether the testable part is complete. This screening method has high requirements for operators and is often time-consuming and labor-intensive because there are too many testkeys to screen. It is also possible that the selected part is not testable due to operator misjudgment, resulting in abnormal test data and some security issues. In addition, it is also possible that the testkey that can be tested may not be fully selected due to omissions, which will also lead to waste of resources. Therefore, in the actual operation process, if it is necessary to manually screen the actual testable part of the die near the edge, it will often greatly increase the difficulty of testing.

[0030] Based on this, an embodiment of the present invention provides a method, device, and electronic device for automated wafer testing, which specifically provides a method for autonomously determining whether there are test keys in the die at the edge of the wafer that can be tested during the test plan generation process, autonomously screening these testable parts, avoiding incomplete parts, and performing automated testing. The testable range on the entire wafer can be automatically calculated and automated testing of the wafer can be performed without relying on manual screening, which can improve test efficiency and prevent errors.

[0031] To facilitate understanding of this embodiment, an automated wafer testing method disclosed in an embodiment of the present invention is first introduced in detail.

[0032] Example 1:

[0033] The embodiment of the present invention provides an automated testing method for wafers. Figure 1 The flowchart of a wafer automated testing method shown in FIG. 1 includes the following steps:

[0034] Step S102, generate a test plan, and automatically obtain the parameter information of the wafer filled in by the user to generate the test plan, automatically determine the edge cutting result of the wafer based on the parameter information, and associate the edge cutting result with the test plan; wherein, the edge cutting result includes the edge result of the die to be tested and the complete result of whether each test structure on the die to be tested is cut.

[0035] Step S104 , obtaining a test plan, traversing the die to be tested in the test plan, determining whether the die to be tested is an edge die and whether the test structure of the edge die is testable based on the edge cutting result, and automatically testing the die to be tested.

[0036] In the process of users generating test plans, relevant parameter information (such as related parameters among wafer parameters, bare die parameters, test structure parameters, etc.) can be automatically obtained, and the edge bare die situation and the complete situation of the test structure located in the edge bare die can be calculated. The edge bare die situation and the complete situation are associated and bound with the test plan as test information (for example, included in the test plan). Combined with the judgment mechanism of the test link, the automated test of the testable test organization is completed. No human intervention is required for test judgment throughout the process, which can improve test efficiency and prevent errors.

[0037] The edge cutting results can be associated with the test plan through the die ID. In the subsequent test phase, the die ID is traversed to determine whether the edge cutting result is operated. If it exists, it is obtained and the judgment of whether it is an edge die and whether the test structure is complete (testable) is judged in turn.

[0038] The existing technology requires manual screening when testing edge dies. The method provided in this embodiment can solve the problems of inefficiency caused by manual screening and high requirements for operators. It is easy for improper operation to lead to unreliable results, waste of resources, and poor flexibility.

[0039] The method provided in this embodiment can automatically screen for testable testkeys in edge dies, automatically test, and integrate data during automated testing. This eliminates the need for manual screening of testkeys, significantly reducing manual intervention, saving significant time, and improving screening accuracy. Furthermore, the requirements for testers can be reduced, improving testing efficiency.

[0040] In some embodiments, the position information of each test structure in the die to be tested on the wafer is automatically determined based on the parameter information of the wafer; the edge cutting result of the wafer is automatically determined and / or a wafer map of the test structure is generated based on the parameter information of the wafer and the position information of each test structure on the wafer, so that the user can select a testable test structure according to the visually displayed wafer map of the test structure and complete the test plan generation.

[0041] In some embodiments, the position coordinates within the die may be automatically converted into position information relative to the wafer based on the wafer parameters and die parameters included in the parameter information.

[0042] In some embodiments, the parameter information includes: the radius of the wafer, the offset between the center of the wafer and the center of the test structure, the position coordinates of each test structure, and the size and position coordinates of the die.

[0043] See Figure 2 A schematic diagram of determining edge cutting results is shown in FIG. Figure 2 As shown, in this embodiment, the parameter information of the wafer input by the user can be first obtained, and the position of each test structure in the bare die of the wafer can be determined based on the parameter information.

[0044] In this embodiment, the user can input the parameter information of the wafer, including: the radius of the wafer, the offset value between the center of the wafer and the center of the Testkey, the position coordinates of each Testkey, the size and position coordinates of the Die, etc. These contents are the basis for the judgment of this solution.

[0045] like Figure 2 As shown, after obtaining the parameter information of the wafer, this embodiment can perform calculations in the built-in program based on the parameter information of the wafer input by the user, calculate the position of each Testkey on each Die on the wafer, and record the position of each Testkey on the wafer.

[0046] The position coordinates of the Testkey can be relative coordinates, representing the relative coordinates of the Testkey in the Die relative to a reference point. This embodiment can calculate the absolute coordinates of the Testkey relative to the center of the wafer, and can be used to determine whether the Testkey will be circularly cut at the edge. The calculation can be based on parameters such as the radius of the wafer, the size of each Die, the length and width of the Testkey, and whether there is an offset.

[0047] See also Figure 3 The diagram below shows how to calculate the actual position of each test key. This allows you to determine the radius and center of the wafer, the size of each die, and the position of the reference test key. The relative positions of other test keys to the reference test key are then determined, and the actual position of each test key is calculated.

[0048] like Figure 2As shown, when recording the position of each Testkey, this embodiment calculates the arrangement of all Testkeys on the entire wafer and outputs a wafer map of the test structure. The wafer map of the test structure can be an intelligent visual schematic diagram (Map image), so that the user can view the Map image externally and obtain the position of the Testkey on the wafer.

[0049] See also Figure 4 The schematic diagram of intelligently generating a map image is shown, which can obtain the position of each device on the wafer, draw an image of the wafer, and draw a schematic image of each testkey on the wafer, thereby generating a map image.

[0050] In this embodiment, all data can be integrated to intelligently generate a map image, so that users can view the position of the Testkey on the wafer externally, which can help users intuitively observe the status of each Testkey on the wafer and perform functions such as zooming in and out.

[0051] When creating a test plan, the user can use the Map image to select which TestKeys can be used in the test based on the completeness of the TestKeys. Of course, during the test, even if the user does not select, this embodiment can automatically avoid the content that cannot be tested. This image can assist the user in specifying the test plan in the early stage, and can also provide an intuitive and reliable visualization solution for the user to check and use the data later, making it easier for the user to check and use.

[0052] The embodiment of the present invention provides a visualization solution, which allows the user to visually observe the position of the Testkey through a Map image without operating the probe station.

[0053] This embodiment can determine the edge cutting result indicating whether each edge test structure of the wafer is cut based on the parameter information of the wafer and the position of each test structure, that is, measure and obtain whether the Die and Testkey at the edge of the wafer are cut.

[0054] In some embodiments, an edge die located at the edge of the wafer among the die to be tested can be determined based on the parameter information of the wafer; whether the test structure is cut can be determined based on the position information of the test structure on the edge die and the parameter information of the wafer, and the complete test structure can be determined; and the edge cutting result of the wafer can be obtained based on the edge die and the complete test structure.

[0055] like Figure 2As shown, this embodiment can calculate whether each die is an edge die and whether each testkey in the edge die has been cut (i.e., whether it is complete and measurable) based on the position of the die and testkey on the wafer. For example, edge die information can be obtained using information such as the wafer radius, the wafer center, and the position coordinates of the die. By determining the length, width, and height of the testkey and the absolute position of the center, the integrity of the testkey can be determined, and the edge cutting result can be recorded as data. At this point, the user can choose whether to export the edge cutting result externally. This embodiment can design an export button to facilitate the user to export the edge cutting result with one click.

[0056] In some embodiments, before performing automated testing on a wafer, it may be determined whether the user has selected a testable test structure; if so, each test structure is automatically tested; if not, the step of traversing the bare die to be tested in the test plan is executed.

[0057] This embodiment can also first determine whether the user has selected a testable test structure. If a testable test structure is selected, each test structure can be automatically tested; if a testable test structure is not selected, the step of traversing the test die to be tested in the test plan can be executed, thereby automatically testing the wafer.

[0058] An embodiment of the present invention provides an automated wafer testing method. The method generates a test plan and automatically obtains wafer parameter information entered by a user when generating the test plan. Based on the parameter information, the method automatically determines wafer edge cutting results and associates the edge cutting results with the test plan. The edge cutting results include edge results of a die to be tested and complete results of each test structure on the die to be tested. The method then obtains the test plan, iterates through the die to be tested in the test plan, and determines whether the test structures on the die to be tested are testable based on the edge cutting results associated with the test plan. The die to be tested is then automatically tested. In this method, during the user's test plan creation process, relevant information is automatically obtained to calculate edge cutting results, including whether the die and test structures are complete. The edge cutting results are then associated with the test plan (e.g., included in the test plan). During testing, the method automatically determines whether the die is an edge die and which test structures on the edge die are testable based on the edge cutting results. This entire process is automated, eliminating the need for human intervention. This significantly improves testing efficiency and accuracy compared to existing methods that determine testability based on test structure information in the test plan by manually operating a tester.

[0059] Example 2:

[0060] This embodiment provides another automated testing method for wafers. This method is implemented based on the above embodiment and focuses on the specific steps of automated testing of wafers based on edge cutting results. Figure 5 The flowchart of another wafer automated testing method is shown, and the wafer automated testing method includes the following steps:

[0061] Step S502, generate a test plan, and automatically obtain the parameter information of the wafer filled in by the user to generate the test plan, automatically determine the edge cutting result of the wafer based on the parameter information, and associate the edge cutting result with the test plan; wherein, the edge cutting result includes the edge result of the die to be tested and the complete result of whether each test structure on the die to be tested is cut.

[0062] Step S504, obtaining a test plan, traversing the die to be tested in the test plan, and determining whether the die to be tested is an edge die based on the edge cutting result; if the die to be tested is not an edge die, automatically testing all structures to be tested on the die to be tested; if the die to be tested is an edge die, determining whether the structures to be tested on the edge die are complete, and automatically testing the complete structures to be tested.

[0063] See also Figure 6 The schematic diagram of an automated test is shown. During the test, this embodiment will traverse the die to be tested. At this time, this embodiment will check whether the die to be tested is an edge die, that is, whether it is at the edge of the wafer. If the die is not an edge die, normal testing will be carried out without checking whether the test key is complete.

[0064] like Figure 6 As shown, if the die is an edge die, all test keys on this die will be compared with the built-in edge cutting results to check whether the test key to be tested is cut, that is, to check whether the test key to be tested is complete. If the test key is not cut, it is complete and the test is processed normally. If the test key is cut, it is incomplete and all test items on it are automatically skipped and marked in the results.

[0065] In some embodiments, after the test is complete, the automated test results and wafer maps of the test structures can be obtained to check for test data anomalies. For example, if a complete test structure calculated based on the edge cutting results is tested, an abnormal test result does not rule out a problem with the test process. The entire process is a black box process, and the user cannot verify the authenticity of the data. However, the wafer map of the test structure can be used to determine which test structures are complete. By comparing the test results, the data authenticity can be confirmed and the test accuracy can be checked.

[0066] In some embodiments, a test report of the automated test may be generated, in which the test structure that has not been tested is marked; wherein the test structure that has not been tested is an incomplete test structure.

[0067] like Figure 6 As shown, the above normal and abnormal data will be integrated and output to the test report. The user can obtain all test results and marks of skipped test items in this report.

[0068] In addition to the above-mentioned automated testing method, this embodiment can also generate a map image. The user can select a test key from the map image and complete the automatic testing of the testable test key based on the conventional testing process.

[0069] The above method provided in this embodiment can determine the position of each Testkey and whether it has been cut based on the input parameter information of the wafer; it can integrate all data and intelligently generate a Map image for the user to visually observe the position of the Testkey; it can also determine whether it is a testable Testkey during the test process and automatically avoid it.

[0070] This embodiment aims to solve the problems of low efficiency, waste of test resources, and unreliable test results due to improper human operation during the test process of wafer edge die.

[0071] This embodiment uses a built-in, fully automated measurement algorithm to autonomously calculate the testable range across the entire wafer and conduct autonomous testing. While existing technologies rely on complex manual screening to establish a test plan, this embodiment enables fully autonomous testing and provides a visualization solution before testing. This allows for intuitive display of the testable content across the entire wafer, facilitating inspection and observation by the tester.

[0072] Example 3:

[0073] Corresponding to the above method embodiment, the embodiment of the present invention provides an automated testing device for wafers, see Figure 7The structure diagram of a wafer automated testing device shown in FIG. 1 includes:

[0074] The test generation module 71 is configured to generate a test plan, automatically obtain the wafer parameter information entered by the user when generating the test plan, automatically determine the wafer edge cutting results based on the parameter information, and associate the edge cutting results with the test plan; the edge cutting results include the edge results of the die to be tested and the complete results of whether each test structure on the die to be tested has been cut;

[0075] The automatic testing module 72 is used to obtain a test plan, traverse the die to be tested in the test plan, and determine whether the die to be tested is an edge die based on the edge cutting result; if the die to be tested is not an edge die, all the structures to be tested on the die to be tested are automatically tested; if the die to be tested is an edge die, whether the structures to be tested on the edge die are complete, and automatically test the complete structures to be tested.

[0076] An embodiment of the present invention provides an automated testing device for wafers, which generates a test plan and automatically obtains parameter information of the wafer filled in by the user when generating the test plan, automatically determines the edge cutting result of the wafer based on the parameter information, and associates the edge cutting result with the test plan; wherein the edge cutting result includes the edge result of the die to be tested and the complete result of whether each test structure on the die to be tested is cut; traverses the die to be tested in the test plan, determines whether the test structure of the die to be tested is testable based on the edge cutting result associated with the test plan, and automatically tests the die to be tested. In this method, in the process of the user making a test plan, the collaborative automatically obtains relevant information to calculate the edge cutting result including whether the edge bare chip and the test structure are complete, and associates it with the test plan (for example, includes it in the test plan). During the test, it is automatically judged based on the edge cutting result whether it is an edge bare chip and which test structures in the edge bare chip are testable. The entire process can be tested automatically without human intervention and participation. Compared with the existing technology, the existing method of determining whether it is testable by manually operating the test machine according to the test structure information of the test plan greatly improves the test efficiency and test accuracy. Therefore, this solution automatically calculates the testable range on the entire wafer and performs automated testing of the wafer. It does not need to rely on manual screening, can improve test efficiency, and will not cause errors.

[0077] The above-mentioned test generation module is used to automatically determine the position information of each test structure in the bare die to be tested on the wafer based on the parameter information of the wafer; automatically determine the edge cutting result of the wafer and / or generate a wafer map of the test structure based on the parameter information of the wafer and the position information of each test structure on the wafer, so that the user can select a testable test structure according to the visually displayed wafer map of the test structure and complete the test plan generation.

[0078] The test generation module is further configured to determine whether the user has selected a testable test structure; if so, automatically test each test structure; if not, execute the step of traversing the bare chips to be tested in the test plan.

[0079] The test generation module is also used to obtain the test results of the automatic test and the wafer map of the test structure, and to check for abnormalities in the test data.

[0080] The test generation module is used to automatically convert the position coordinates within the die into position information relative to the wafer based on the wafer parameters and die parameters included in the parameter information.

[0081] The above-mentioned test generation module is used to determine the edge bare die located at the edge of the wafer among the bare die to be tested based on the parameter information of the wafer; determine whether the test structure is cut based on the position information of the test structure on the edge bare die and the parameter information of the wafer, and determine the complete test structure; and obtain the edge cutting result of the wafer based on the edge bare die and the complete test structure.

[0082] The above-mentioned automatic test module is used to traverse the die to be tested and determine whether the die to be tested is an edge die; if the die to be tested is not an edge die, all test structures on the die to be tested are automatically tested; if the die to be tested is an edge die, whether the test structure on the edge die is complete is determined and the complete test structure is automatically tested.

[0083] The automatic test module is further configured to generate a test report for the automated test, and mark the test structures that have not been tested in the test report; wherein the test structures that have not been tested are incomplete test structures.

[0084] The parameter information includes: the radius of the wafer, the offset value between the center of the wafer and the center of the test structure, the position coordinates of each test structure, and the size and position coordinates of the die.

[0085] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described automated wafer testing device can refer to the corresponding process in the aforementioned embodiment of the automated wafer testing method, and will not be repeated here.

[0086] Example 4:

[0087] The embodiment of the present invention also provides an electronic device for running the above-mentioned wafer automated testing method; see Figure 8A structural diagram of an electronic device is shown, which includes a memory 100 and a processor 101, wherein the memory 100 is used to store one or more computer instructions, and the one or more computer instructions are executed by the processor 101 to implement the above-mentioned automated testing method for wafers.

[0088] Further, Figure 8 The electronic device shown further includes a bus 102 and a communication interface 103 , and the processor 101 , the communication interface 103 and the memory 100 are connected via the bus 102 .

[0089] The memory 100 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage. The communication connection between the system network element and at least one other network element is achieved through at least one communication interface 103 (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used. The bus 102 may be an ISA bus, a PCI bus, or an EISA bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0090] The processor 101 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in the processor 101 or software instructions. The above processor 101 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in conjunction with the embodiments of the present invention can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium well-known in the art, such as a random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or register. The storage medium is located in the memory 100, and the processor 101 reads the information in the memory 100 and, in conjunction with its hardware, completes the steps of the method of the aforementioned embodiment.

[0091] An embodiment of the present invention also provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the above-mentioned wafer automated testing method. For specific implementation, please refer to the method embodiment, which will not be repeated here.

[0092] The computer program product of the wafer automated testing method, device and electronic device provided in the embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the method in the previous method embodiment. The specific implementation can be found in the method embodiment and will not be repeated here.

[0093] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working process of the system and / or device described above can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.

[0094] In addition, in the description of the embodiments of the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0095] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the method of the present invention. The aforementioned storage medium includes various media that can store program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0096] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0097] Finally, it should be noted that the above embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A wafer automated testing method, characterized in that: The method comprises: Generate a test plan, automatically obtain parameter information of the wafer entered by the user when generating the test plan, automatically determine the edge cutting result of the wafer based on the parameter information, and associate the edge cutting result with the test plan; wherein the edge cutting result includes the edge result of the die to be tested and the complete result of whether each test structure on the die to be tested has been cut; Obtain a test plan, traverse the die to be tested in the test plan, and determine whether the die to be tested is an edge die based on the edge cutting result; if the die to be tested is not an edge die, automatically test all structures to be tested on the die to be tested; if the die to be tested is an edge die, determine whether the structures to be tested on the edge die are complete, and automatically test the complete structures to be tested.

2. The method according to claim 1, characterized in that The automatically determining the edge cutting result of the wafer based on the parameter information includes: Automatically determining position information of each test structure in the die to be tested on the wafer based on parameter information of the wafer; Based on the parameter information of the wafer and the position information of each test structure on the wafer, the edge cutting result of the wafer is automatically determined and / or a wafer map of the test structure is generated, so that the user can select a testable test structure according to the visually displayed wafer map of the test structure and complete the test plan generation.

3. The method according to claim 2, characterized in that Before traversing the bare chips to be tested in the test plan, the method further includes: Determine whether the user selects a testable test structure; If yes, then each test structure is automatically tested; If not, the step of traversing the bare dies to be tested in the test plan is performed.

4. The method according to claim 2, characterized in that The method further comprises: Obtain test results from automated testing and wafer maps of test structures to check for test data anomalies.

5. The method according to claim 2, characterized in that The automatically determining position information of each test structure in the die to be tested on the wafer based on the parameter information of the wafer includes: Based on the wafer parameters and die parameters included in the parameter information, the position coordinates within the die are automatically converted into position information relative to the wafer.

6. The method according to claim 1, characterized in that The automatically determining the edge cutting result of the wafer based on the parameter information includes: Determining edge dies located at an edge of the wafer among the dies to be tested based on parameter information of the wafer; determining whether the test structure is cut based on the position information of the test structure on the edge die and the parameter information of the wafer, and determining a complete test structure; The wafer edge saw results are obtained based on the edge die and the complete test structure.

7. The method according to claim 6, characterized in that The method further comprises: A test report of the automated test is generated, and the test structure that has not been tested is marked in the test report; wherein the test structure that has not been tested is an incomplete test structure.

8. The method according to claim 1, characterized in that The parameter information includes: the radius of the wafer, the offset value between the center of the wafer and the center of the test structure, the position coordinates of each test structure, and the size and position coordinates of the die.

9. An automated wafer testing device, characterized in that: The device comprises: A test generation module is configured to generate a test plan, automatically obtain wafer parameter information entered by the user when generating the test plan, automatically determine wafer edge cutting results based on the parameter information, and associate the edge cutting results with the test plan; wherein the edge cutting results include edge results of the die to be tested and complete results of whether each test structure on the die to be tested has been cut; The automatic testing module is used to obtain a test plan, traverse the die to be tested in the test plan, and determine whether the die to be tested is an edge die based on the edge cutting result; if the die to be tested is not an edge die, automatically test all the structures to be tested on the die to be tested; if the die to be tested is an edge die, determine whether the structures to be tested on the edge die are complete, and automatically test the complete structures to be tested.

10. An electronic device, characterized in that: The invention comprises a processor and a memory, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the automated wafer testing method according to any one of claims 1 to 8.

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