Apparatus and method for reducing standby power consumption in isolated power conversion system

Abstract

The invention relates to a device and a method for reducing standby power consumption in an isolated power conversion system. In one embodiment, an apparatus includes: a secondary controller coupled to a secondary circuit of a power conversion system; and a primary controller coupled to a primary circuit of the power conversion system, the primary controller coupled to the secondary controller through an isolated interface, where the secondary controller is configured to: detect whether a load is coupled to the power conversion system; in response to the load being disconnected from the power conversion system, communicating with the primary controller by pulling down a secondary feedback node in the secondary circuit and a primary feedback node in the primary circuit for a first predetermined time; providing a high impedance at the secondary feedback node to reduce power consumption; and in response to the load reconnecting to the power conversion system, communicating with the primary controller by pulling down the secondary feedback node in the secondary circuit for a second predetermined time.

Description

Technical Field

[0001] The present invention relates to a feedback control apparatus and method, and in a specific embodiment, to a feedback control apparatus and method for reducing power consumption in an isolated power conversion system. Background Art

[0002] A power conversion system (e.g., an adapter) is used to convert an alternating current (ac) voltage from a utility company into a direct current (dc) voltage suitable for an electronic device. The power conversion system typically includes an ac / dc stage (e.g., a rectifier) ​​and an isolated dc / dc stage (e.g., an isolated dc / dc converter). The ac / dc stage converts power from the ac utility line and establishes a dc bus for the isolated dc / dc stage. The ac / dc stage may include various electromagnetic interference (EMI) filters and a bridge rectifier formed by four diodes. The EMI filter is used to attenuate both differential mode noise and common mode noise. The bridge rectifier converts the ac voltage into a full-wave rectified dc voltage. This full-wave rectified dc voltage provides a stable dc input voltage for the isolated dc / dc stage by coupling a plurality of smoothing capacitors to the output of the bridge rectifier.

[0003] The isolated dc / dc stage converts the voltage of the dc bus to a voltage suitable for the electronic load, such as a tablet, printer, mobile phone, personal computer, any combination thereof, etc. The isolated dc / dc stage can be implemented by using different power topologies such as a flyback converter, a forward converter, a half-bridge converter, a full-bridge converter, etc.

[0004] In some applications (e.g., adapters for powering personal computers), flyback converters are used to regulate the output voltage of a power conversion system. A flyback converter includes a transformer that provides galvanic isolation to meet various safety requirements. A flyback converter may include three controllers, namely: a primary side controller located at the primary side for driving the main switch (primary switch) of the flyback converter; a synchronous rectifier controller located at the secondary side for controlling the turning on and off of the synchronous switch to reduce secondary side conduction losses; and a secondary side controller located at the secondary side for sensing the output voltage and communicating with the primary side controller to implement various system functions, such as closed-loop regulation, Universal Serial Bus (USB) power delivery protocol, and the like.

[0005] A flyback converter provides a regulated output voltage to many devices that utilize a regulated output voltage. A primary controller and a secondary controller control the power conversion. The controller has an active mode to actively control the flyback converter when the power conversion system provides power to the load. To save energy, the primary controller and the secondary controller may have a standby mode. During the standby mode, the primary controller and the secondary controller enter a low power consumption state because the power required by the load connected to the power conversion system does not require the primary controller and the secondary controller to control the flyback converter.

[0006] In standby mode, in order to maintain regulation of the output voltage, the feedback circuits of the flyback converter (e.g., reference voltage, error amplifier, and optocoupler) must remain operational when the load is disconnected from the power conversion system. This means that the power consumption of the feedback circuits cannot be saved. Therefore, these feedback circuits always consume power even when the load device is disconnected. It is desirable to have a simple and reliable control method to reduce the power consumption of the feedback circuits, thereby achieving better power conversion efficiency. Summary of the invention

[0007] These and other problems are generally solved or avoided, and technical advantages are generally achieved, by preferred embodiments of the present disclosure, which provide a feedback control apparatus and method for reducing power consumption in an isolated power conversion system.

[0008] According to one embodiment, a device includes: a secondary controller coupled to a secondary circuit of a power conversion system; and a primary controller coupled to the primary circuit of the power conversion system, the primary controller coupled to the secondary controller through an isolation interface, wherein the secondary controller is configured to: detect whether a load is coupled to the power conversion system; in response to the load being disconnected from the power conversion system, communicate with the primary controller to enter a sleep mode by pulling down a secondary feedback node in the secondary circuit and a primary feedback node in the primary circuit for a first predetermined time, wherein in the sleep mode, both the primary feedback circuit and the secondary feedback circuit are disabled to reduce power consumption; provide a high impedance at the secondary feedback node to reduce power consumption; and in response to the load being reconnected to the power conversion system, communicate with the primary controller to exit the sleep mode by pulling down the secondary feedback node in the secondary circuit for a second predetermined time, wherein after exiting the sleep mode, the primary feedback circuit and the secondary feedback circuit are enabled to resume feedback loop control to regulate the output voltage of the power conversion system.

[0009] According to another embodiment, a method includes: detecting, by a secondary controller, whether a load is coupled to a power conversion system including a primary circuit and a secondary circuit; in response to the load being disconnected from the power conversion system, communicating with the primary controller by pulling down a secondary feedback node in the secondary circuit and a primary feedback node in the primary circuit for a first predetermined time; configuring the secondary feedback node to act as a high impedance node to reduce power consumption; and in response to the load being reconnected to the power conversion system, communicating with the primary controller by pulling down the secondary feedback node in the secondary circuit for a second predetermined time.

[0010] According to yet another embodiment, a system includes: an isolated power converter configured to be coupled between a power source and a load; a secondary controller coupled to a secondary circuit of the system; and a primary controller coupled to the primary circuit of the system, the primary controller being coupled to the secondary controller via an isolation interface, wherein the secondary controller is configured to: detect whether a load is coupled to the isolated power converter; notify the primary controller in response to the load being disconnected from the isolated power converter; and reduce power consumption of the secondary circuit by configuring a secondary feedback node as a high impedance node, and the primary controller is configured to: disable a feedback control loop of the isolated power converter once the load is disconnected from the isolated power converter.

[0011] The features and technical advantages of the present disclosure have been summarized quite broadly above so that the subsequent detailed description of the present disclosure can be better understood. Additional features and advantages of the present disclosure will be described below, which form the objects of the claims of the present disclosure. It should be understood by those skilled in the art that the disclosed concepts and specific embodiments can be easily used as the basis for modifying or designing other structures or processes for the same purpose of implementing the present disclosure. It should also be recognized by those skilled in the art that such equivalent structures do not depart from the spirit and scope of the present disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0013] Figure 1 illustrates a block diagram of a power conversion system according to various embodiments of the present disclosure;

[0014] Figure 2 The present invention illustrates various embodiments of the present invention. Figure 1 Schematic diagram of an isolated power converter shown in FIG.

[0015] Figure 3 The present invention illustrates various embodiments of the present invention. Figure 1 Schematic diagram of a first implementation of the primary feedback circuit, isolation interface and secondary feedback circuit shown in ;

[0016] Figure 4 The present invention illustrates various embodiments of the present invention. Figure 1 Schematic diagram of a second embodiment of the primary feedback circuit, isolation interface and secondary feedback circuit shown in ;

[0017] Figure 5 The present invention illustrates various embodiments of the present invention. Figures 3 to 4 Various waveforms associated with the circuit shown in;

[0018] Figure 6 illustrates a state machine for controlling mode transitions of a secondary controller according to various embodiments of the present disclosure;

[0019] Figure 7 illustrates a state machine for controlling mode transitions of a primary controller according to various embodiments of the present disclosure; and

[0020] Figure 8 Illustrate the control of various embodiments according to the present disclosure Figure 1 Flowchart of the power conversion system shown in FIG.

[0021] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0022] The making and using of the currently preferred embodiments are discussed in detail below. However, it should be understood that the present disclosure provides many applicable inventive concepts that can be embodied in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the present disclosure and do not limit the scope of the present disclosure.

[0023] The present disclosure will be described with respect to a preferred embodiment in a specific context, namely a feedback control device and method for reducing power consumption in an isolated power conversion system. However, the present disclosure may also be applied to various power conversion systems. In the following, various embodiments will be explained in detail with reference to the accompanying drawings.

[0024] Figure 1The block diagram of the power conversion system according to various embodiments of the present disclosure is illustrated. The power conversion system includes an isolated power converter 100 configured to be coupled between a power source VIN and a load 130. The isolated power converter 100 is used to convert a DC voltage from one level (e.g., VIN) to another level (e.g., Vo) suitable for the load 130. In some embodiments, the isolated power converter 100 is a flyback converter. In alternative embodiments, the isolated power converter 100 can be other suitable power converters, such as a full-bridge power converter, a half-bridge power converter, an LLC resonant converter, a forward converter, and the like.

[0025] like Figure 1 , the power conversion system further includes a primary controller 110, a secondary controller 120, a primary feedback circuit 115, a secondary feedback circuit 125, and an isolation interface 140. In some embodiments, the primary controller 110 is a PWM controller configured to receive a feedback signal Vcomp from a feedback node COMP and generate a PWM signal applied to a primary switch of the isolated power converter 100. The secondary controller 120 is a universal serial bus (USB) power delivery (PD) controller configured to provide flexible power delivery and data over a single cable. Both PWM controllers and USB PD controllers are well known and therefore are not discussed in detail herein.

[0026] It should be noted that Figure 1 The block diagrams shown in are merely examples, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the power conversion system may include a synchronous rectifier controller. In some embodiments, the synchronous rectifier controller is a separate integrated chip. In an alternative embodiment, the synchronous rectifier controller is part of the secondary controller 120.

[0027] like Figure 1 , secondary controller 120 is coupled to secondary feedback circuit 125 and the output of isolated power converter 100. Primary controller 110 is coupled to primary feedback circuit 115. Primary controller 110 is coupled to secondary controller 120 through primary feedback circuit 115, isolation interface 140, and secondary feedback circuit 125.

[0028] In some embodiments, the isolation interface 140 is implemented as an optocoupler. In alternative embodiments, the isolation interface 140 may be other suitable semiconductor devices, such as a digital isolator or the like.

[0029] The secondary feedback circuit 125 includes a resistor divider, a compensation network, and a feedback control integrated circuit (e.g., an operational amplifier or a shunt voltage regulator). The primary feedback circuit 115 includes a pull-up resistor and a capacitor. Figures 3 to 4 The detailed structures of the secondary feedback circuit 125 and the primary feedback circuit 115 are discussed in detail. Alternatively, the secondary feedback circuit 125 may be referred to as a secondary circuit throughout the description. The primary feedback circuit 115 may also be referred to as a primary circuit.

[0030] In operation, the secondary controller 120 is configured to detect whether the load 130 is coupled to the isolated power converter 100. In response to the load 130 being disconnected from the isolated power converter 100, the secondary controller 120 is configured to: Figures 3 to 4 ) to notify the primary controller 110; and by setting the secondary feedback node (eg, Figures 3 to 4 The OCDRV shown in FIG. 1 is configured as a high impedance node to reduce the power consumption of the primary feedback circuit 115 and the secondary feedback circuit 125. The primary controller 110 is configured to disable the feedback control loop of the isolated power converter 100 once the load 130 is disconnected from the isolated power converter 100. As a result, the isolated power converter enters the sleep mode. In the sleep mode, the secondary controller 120 shuts down the function of the feedback circuit (e.g., reference voltage, error amplifier) ​​and cuts off the current flowing through the isolation interface 140 (e.g., optocoupler). Correspondingly, the primary controller 110 interrupts the feedback loop and shuts down most functions to reduce power consumption. The following will focus on Figures 3 to 7 The detailed operation principles of the primary controller 110 and the secondary controller 120 are described.

[0031] One advantageous feature of having the sleep mode described above is that the standby power of the power conversion system is reduced from about 25 milliwatts to about 3 milliwatts.

[0032] It should be noted that Figure 1 Only relevant elements of the power conversion system are illustrated, and the power conversion system may include many other elements. The elements of the power conversion system illustrated herein are limited only for the purpose of clearly illustrating the inventive aspects of various embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, depending on different applications and design requirements, a switch may be coupled between the output of the isolated power converter and the load. The switching on and off of the switch is controlled by the secondary controller 120.

[0033] Figure 2 The present invention illustrates various embodiments of the present invention. Figure 1Schematic diagram of an isolated power converter shown in FIG. The isolated power converter is implemented as a flyback converter, such as Figure 2 The flyback converter includes an input capacitor CIN, a primary switch Q1, a transformer, a secondary rectifier, and an output capacitor Co. The secondary rectifier is formed by a synchronous switch Q2.

[0034] The voltage of the power supply VIN is coupled to the primary switch Q1 through the primary winding NP of the transformer. The primary switch Q1 is connected to ground. In some embodiments, a current sensing resistor (not shown) may be connected between the primary switch Q1 and ground. In addition, a reset device (not shown) may be connected in parallel with the primary winding NP. The reset device is used to reset the magnetizing current of the flyback converter. The reset device is formed by a diode, a resistor, and a clamping capacitor. The reset device is also called an RCD reset device.

[0035] Return to reference Figure 1 , the primary controller 110 may receive a plurality of signals, such as a feedback signal Vcomp, a current sensing signal detected from a current sensing resistor, and an input voltage signal. Based on the received signals, the primary controller 110 generates a gate drive signal PWM for driving the primary switch Q1. According to the operating principle of the flyback converter, the amount of time that the primary switch Q1 conducts current during a switching period T is determined by a duty cycle D. The duty cycle D may have a value from 0 to 1.

[0036] like Figure 2 As shown in FIG. 1 , the secondary rectifier is implemented as a synchronous switch. The synchronous switch may be an n-type MOSFET device. It should be further noted that although Figure 2 The diagram illustrates a single switching element for a synchronous switch, but those skilled in the art will recognize many variations, substitutions, and modifications. For example, the synchronous switch may include multiple MOSFET devices connected in parallel. In addition, depending on different applications and design requirements, the synchronous switch may be replaced by a diode.

[0037] According to the operating principle of the flyback converter, when the input voltage source VIN is applied to the primary side winding NP of the transformer by turning on the primary switch Q1, the polarity of the secondary side winding NS of the transformer is configured so that the synchronous switch (Q2) is turned off, and the load (not shown) connected to the flyback converter is supplied by the energy stored in the output capacitor Co. On the other hand, when the primary side switch Q1 is turned off and the synchronous switch (Q2) is turned on, the energy stored in the transformer is transferred to the load through the turned-on synchronous switch. The detailed operation of the secondary side of the flyback converter is well known in the art and is therefore not discussed in detail herein.

[0038] According to one embodiment, Figure 2The switching elements (e.g., switches Q1 and Q2) may be metal oxide semiconductor field effect transistor (MOSFET) devices. Alternatively, the switching elements may be any controllable switch, such as insulated gate bipolar transistor (IGBT) devices, integrated gate commutated thyristor (IGCT) devices, gate turn-off thyristor (GTO) devices, silicon controlled rectifier (SCR) devices, junction gate field effect transistor (JFET) devices, MOS controlled thyristor (MCT) devices, gallium nitride (GaN)-based power devices, silicon carbide (SiC)-based power devices, and the like.

[0039] It should be noted that although Figure 2 Switches Q1 and Q2 are shown implemented as single n-type transistors, but those skilled in the art will recognize that there may be many variations, modifications, and alternatives. For example, the switches may be implemented as p-type transistors depending on different applications and design requirements. In addition, Figure 2 Each switch shown in can be implemented as a plurality of switches connected in parallel. Also, a capacitor can be connected in parallel with one switch to achieve zero voltage switching (ZVS) / zero current switching (ZCS).

[0040] Figure 3 The present invention illustrates various embodiments of the present invention. Figure 1 Schematic diagram of a first implementation of the primary feedback circuit, isolation interface, and secondary feedback circuit shown in FIG. The isolation interface 140 is implemented as an optocoupler U1 including a light emitting diode and a phototransistor. The secondary circuit 125 includes a resistor divider, a compensation network, a three-terminal adjustable precision shunt voltage regulator integrated circuit TL431, a current limiting resistor Ra, and a bias resistor Rb.

[0041] The resistor divider includes a first resistor R1 and a second resistor R2 connected in series between Vo and ground. A compensation network is formed by R3, C1 and C2. Figure 3 As shown in FIG. 1 , R3 and C2 are connected in series between the common node of bias resistor Rb and the three-terminal adjustable precision shunt voltage regulator integrated circuit TL431 and the common node of R1 and R2. C1 is connected in parallel with the series R3 and C2. This is a type 2 compensator that provides phase boost to achieve a stable feedback loop.

[0042] like Figure 3 As shown in FIG. 1 , the cathode of the three-terminal adjustable precision shunt voltage regulator integrated circuit TL431 is connected to the cathode of the light emitting diode. The reference terminal of the three-terminal adjustable precision shunt voltage regulator integrated circuit TL431 is connected to the compensation network and the resistor divider. The anode of the three-terminal adjustable precision shunt voltage regulator integrated circuit TL431 is connected to ground. The cathode of the light emitting diode is the secondary feedback node in the secondary circuit. Figure 3As shown in FIG. 1 , the secondary feedback node is denoted as OCDRV.

[0043] The primary circuit 115 includes a pull-up resistor RP and a capacitor Ccomp connected in series between a bias voltage VCC and ground. A first terminal of the phototransistor is connected to a common node of the pull-up resistor RP and the capacitor Ccomp. A second terminal of the phototransistor is connected to ground. The common node of the pull-up resistor RP and the capacitor Ccomp is a primary feedback node. The primary feedback node is denoted as COMP.

[0044] In normal operation, when the load 130 is connected to the isolated power converter 100, the secondary circuit 125 detects the output voltage and sends a feedback signal to the primary circuit 115 through the optocoupler. Based on the feedback signal, the primary controller 110 generates a PWM signal to control the on and off of the primary switch Q1, so that the output voltage of the flyback converter is regulated to achieve the set output voltage. In normal operation, the secondary bias current is about 5 mA. The primary bias current is about 5 mA.

[0045] In operation, when the load 130 is disconnected from the isolated power converter 100, the secondary controller 120 configures the secondary feedback node OCDRV as a high impedance node to reduce the secondary bias current, and the primary controller 110 disables the feedback loop of the isolated power converter 100 to reduce the primary bias current. Once the secondary feedback node OCDRV is configured as a high impedance node, the secondary circuit enters a secondary sleep mode. The secondary bias current is reduced from about 5 mA to about 30 microamperes. Similarly, once the feedback loop of the isolated power converter 100 is disabled, the primary bias current is reduced from about 5 mA to about 70 microamperes.

[0046] In operation, the secondary controller 120 is configured to detect whether the load 130 is coupled to the power conversion system. In response to the load 130 being disconnected from the power conversion system, the secondary controller 120 communicates with the primary controller 110 by pulling down the secondary feedback node OCDRV in the secondary circuit and the primary feedback node COMP in the primary circuit for a first predetermined time (e.g., 240 milliseconds). Then, the secondary controller 120 configures the secondary feedback node OCDRV as a high impedance node to reduce power consumption in the secondary circuit. In addition, in response to the load 130 being reconnected to the power conversion system, the secondary controller 120 communicates with the primary controller 110 by pulling down the secondary feedback node in the secondary circuit for a second predetermined time (e.g., 1 millisecond). Once the secondary controller 120 wakes up the primary controller 110, the primary controller 110 exits the sleep mode and restarts the flyback converter.

[0047] In operation, the primary controller 110 is configured to detect whether the voltage on the primary feedback node COMP in the primary circuit is lower than a predetermined voltage (e.g., 600 millivolts) for a third predetermined time (e.g., 200 milliseconds). In response to the voltage on the primary feedback node COMP being lower than the predetermined voltage for the third predetermined time, the primary controller 110 enters a first sleep mode by disabling the feedback loop of the power conversion system. Then, once the voltage on the primary feedback node COMP increases to a level greater than the predetermined voltage (e.g., 600 millivolts), the primary controller 110 enters a second sleep mode. In addition, in response to the voltage on the primary feedback node COMP being lower than the predetermined voltage again, the primary controller 110 exits the sleep mode and enables the feedback loop to restart the power conversion system.

[0048] Figure 4 The present invention illustrates various embodiments of the present invention. Figure 1 Schematic diagram of a second implementation of the primary feedback circuit, isolation interface, and secondary feedback circuit shown in . Figure 4 The second embodiment shown in Figure 3 The first embodiment is shown in FIG. 1 , except that the three-terminal adjustable precision shunt voltage regulator integrated circuit TL431 is replaced by operational amplifier A1.

[0049] like Figure 4 , the secondary circuit 125 includes a resistor divider, a compensation network, and an operational amplifier A1. The compensation network is connected between the output of the operational amplifier A1 and the inverting input of the operational amplifier A1. The inverting input of the operational amplifier A1 is connected to the common node of R1 and R2. The non-inverting input of the operational amplifier A1 is connected to a predetermined reference Vref. The operating principle of the second embodiment is similar to that of the first embodiment, and therefore is not discussed herein to avoid unnecessary repetition.

[0050] Figure 5 The present invention illustrates various embodiments of the present invention. Figures 3 to 4 Various waveforms associated with the circuit shown in . Figure 5 The horizontal axis represents the time interval. Figure 5There are eight rows in . The first row represents a load plug signal indicating the state of the load 130. When the load 130 is connected to the isolated power converter 100, the load plug signal has a logic high state. On the other hand, when the load 130 is disconnected from the isolated power converter, the load plug signal has a logic low state. The second row represents the secondary bias current Icc_s. The third row represents the secondary side bias voltage Vcc_s. The fourth row represents the voltage on the secondary feedback node OCDRV. The fifth row represents the voltage on the primary feedback node COMP. The sixth row represents the primary bias current Icc_p. The seventh row represents the primary bias voltage Vcc_p. The eighth row represents the PWM signal generated by the primary controller 110.

[0051] Prior to t1, the load 130 is connected to the isolated power converter 100. The load plug signal has a logic high state. The secondary bias current Icc_s is about 5 mA. The secondary bias voltage Vcc_s is about 5 volts. The voltage on the secondary feedback node OCDRV is about 3 volts. The voltage on the primary feedback node COMP is greater than 600 mV. The primary bias current Icc_p is about 5 mA. The primary bias voltage Vcc_p is about 16 volts. The primary controller 110 operates in PWM mode, as indicated by Figure 5 As indicated by the PWM signal shown in .

[0052] At t1, the secondary controller 120 detects that the load 130 has been disconnected from the isolated power converter 100. In response to this change, the load plug signal changes from a logic high state to a logic low state, such as Figure 5 From t1 to t2, both the voltage on the secondary feedback node OCDRV and the voltage on the primary feedback node COMP decrease in response to the load change.

[0053] It should be noted that in normal operation, the voltage on the primary feedback node COMP is related to the load. The voltage on the primary feedback node COMP is kept high to deliver high power under heavy loads. When the load decreases, the voltage on the primary feedback node COMP will decrease with the load.

[0054] From t2 to t3, primary controller 110 enters burst mode to regulate output voltage and reduce switching losses. The primary bias current and secondary bias current remain the same.

[0055] From t3 to t6, the voltage on the secondary feedback node OCDRV will be pulled low by the secondary controller 120. Specifically, Figure 3 The shunt voltage regulator integrated circuit TL431 and Figure 4The operational amplifier A1 shown in both has an open drain structure. In other words, a transistor (e.g., an n-type MOS transistor) is connected between the secondary feedback node OCDRV and ground. The gate of this transistor is connected to the output of the error amplifier. The secondary controller 120 can pull the secondary feedback node OCDRV to a low by fully turning on this transistor.

[0056] In some embodiments, the duration from t3 to t6 is denoted as T1. Figure 5 . In some embodiments, T1 is about 240 milliseconds. At t3, the secondary bias current changes from about 5 mA to about 0.6 mA. From t3 to t6, in response to the low voltage on the secondary feedback node OCDRV, the voltage on the primary feedback node COMP drops to a voltage level below a predetermined voltage (e.g., 600 mV).

[0057] The duration from t3 to t5 is denoted as T2, as Figure 5 . In some embodiments, T2 is about 200 milliseconds. At t5, the primary controller 110 detects that the voltage on the primary feedback node COMP remains below a predetermined voltage (e.g., 600 millivolts) for more than T2 (e.g., 200 milliseconds). This indicates that the load 130 has been disconnected from the isolated power converter 100. At t5, the primary controller 110 enters a first sleep mode in which the primary controller 110 disables the feedback control loop of the isolated power converter 100. After the feedback control loop of the isolated power converter is disabled, the primary controller 110 stops regulating the output voltage, and its bias current is reduced from about 5 milliamperes to about 70 microamperes.

[0058] At t6, in order to reduce the power consumption of the feedback circuit including the primary feedback circuit 115, the secondary feedback circuit 125 and the isolation interface 140, the secondary controller 120 configures the secondary feedback node OCDRV as a high impedance node. As a result, the voltage on the secondary feedback node OCDRV increases to a level approximately equal to Vo. The secondary controller 120 enters a sleep mode in which the secondary feedback circuit (e.g., the secondary feedback circuit 125) has been disabled. The secondary bias current is reduced from approximately 600 microamperes to approximately 30 microamperes. In response to the voltage change on the secondary feedback node OCDRV, the voltage on the primary feedback node COMP increases from a low voltage (e.g., less than 600 millivolts) to a high voltage (e.g., 5V) approximately equal to VCC.

[0059] From t6 to t7, the secondary controller 120 stays in the sleep mode. The primary controller 110 operates in a second sleep mode, where the primary bias current remains the same. From t6 to t7, the primary controller 110 occasionally turns on the primary switch Q1 to maintain the primary bias voltage and the secondary bias voltage, such as Figure 5 As shown in .

[0060] At t7, the load plug signal changes from a logic low state to a logic high state. The secondary controller 120 detects that the load 130 is reconnected to the isolated power converter 100. From t7 to t8, the secondary controller 120 pulls down the secondary feedback node OCDRV to a low voltage level for about a predetermined time (e.g., 1 millisecond). In response to the voltage change on the secondary feedback node OCDRV, the voltage on the primary feedback node COMP drops below a predetermined voltage threshold (e.g., a low voltage less than 600 millivolts). The voltage change on the node COMP wakes up the primary controller 110. From t8 to t9, the isolated power converter 100 returns to normal operation. The feedback loop is enabled to regulate the output voltage of the isolated power converter 100.

[0061] It should be noted that from t6 to t7, the waveforms of Vocdrv and Vcomp are different from those in the conventional sleep mode. In the conventional sleep mode, Vocdrv and Vcomp are pulled down to a low voltage to prevent the primary switch Q1 from switching. However, such a low voltage causes bias current to flow through the optocoupler, thereby increasing power consumption. Figure 5 In the embodiment, from t6 to t7, Vocdrv and Vcomp are pulled up to a high voltage. As a result, the current flowing through the optocoupler is cut off, thereby reducing power consumption.

[0062] Figure 6 The diagram illustrates a state machine for controlling mode transition of a secondary controller according to various embodiments of the present disclosure. The state machine includes four states, namely, a normal state S0, an entry state S1, a sleep state S2, and an exit state S3. Return to reference Figure 5 , the normal state S0 of the secondary controller 120 corresponds to the time before t3. The entry state S1 of the secondary controller 120 corresponds to the time between t3 and t6. The sleep state S2 of the secondary controller 120 corresponds to the time between t6 and t7. The exit state S3 of the secondary controller 120 corresponds to the time between t7 and t8.

[0063] As used herein, the name state machine is applied to a machine that can be in one of several states (e.g., states S0, S1, S2, and S3), in one state at a time, and capable of changing from one state to another (e.g., transitioning) based on a conditional triggering event. Thus, such a state machine can be defined by its states and the triggering conditions for transitioning between two states.

[0064] according to Figure 6In the state machine shown in FIG. 6 , an event that fails to cause a transition can be represented by a line looping over the old state, as shown by lines 602 and 604. An event that causes a transition from one state to another is represented by an arrow starting from the old state and pointing to the new state, as shown by lines 602 and 604. Figure 6 as shown in .

[0065] The state machine allows state transitions between the normal state S0 and the entering state S1 , a state transition from the entering state S1 to the sleeping state S2 , a state transition from the sleeping state S2 to the exiting state S3 , and a state transition from the exiting state S3 to the normal state S0 .

[0066] Depending on whether load 130 is connected to isolated power converter 100, secondary controller 120 may determine different states of secondary controller 120. Figure 6 As shown in FIG. 1 , in the mode transition from the normal state S0 to the state S1, the transition from state S0 to state S1 is triggered if the following conditions can be met: the load plug signal has a logic low state. Specifically, once the load plug signal changes from a logic high state to a logic low state, the transition from state S0 to state S1 occurs. Figure 6 As shown in , in the mode transition from entering state S1 to normal state S0, the transition from state S1 to state S0 is triggered if the following conditions can be met: the load plug signal has a logic high state. In particular, once the load plug signal changes from a logic low state to a logic high state, the transition from state S1 to state S0 occurs. In normal state S0, the secondary bias current is about 5 mA. The voltage on the secondary feedback node OCDRV is at its normal value, at which the output voltage of the isolated power converter is regulated. In entering state S1, the secondary bias current is about 0.6 mA. The voltage on the secondary feedback node OCDRV is pulled down to a low voltage (e.g., a voltage approximately equal to zero volts). The duration for which the voltage on the secondary feedback node OCDRV remains at a low voltage is represented as T.

[0067] like Figure 6 As shown in FIG. 1 , in the mode transition from entering state S1 to sleeping state S2, the transition from state S1 to state S2 is triggered if the following conditions can be met: the load plug signal has a logic low state, and T is greater than T1. T1 is a predetermined time threshold. In some embodiments, T1 is equal to 240 milliseconds. In sleeping state S2, the secondary bias current is about 30 microamperes. The secondary controller 120 configures the secondary feedback node OCDRV as a high impedance node.

[0068] like Figure 6As shown in FIG. 1 , in a mode transition from sleep state S2 to exit state S3, a transition from state S2 to state S3 is triggered if the following conditions can be met: the load plug signal has a logic high state. In exit state S3, the secondary bias current is approximately 0.6 mA. The voltage on the secondary feedback node OCDRV is pulled down to a low voltage (e.g., a voltage approximately equal to zero volts).

[0069] like Figure 6 As shown in FIG. 1 , in the mode transition from the exit state S3 to the normal state S0, the transition from state S3 to state S0 is triggered if the following conditions can be met: the voltage on the secondary feedback node OCDRV remains at a low voltage for a time greater than a predetermined time T2. In some embodiments, T2 is equal to 1 millisecond.

[0070] Figure 7 The diagram illustrates a state machine for controlling mode transition of a primary controller according to various embodiments of the present disclosure. The state machine includes five states, namely, a normal state S0, an entry state S1, a first sleep state S2, a second sleep state S3, and an exit state S4. Return to reference Figure 5 , the normal state S0 of the primary controller 110 corresponds to the time before t3. The entry state S1 of the primary controller 110 corresponds to the time between t3 and t5. The first sleep state S2 of the primary controller 110 corresponds to the time between t5 and t6. The second sleep state S3 of the primary controller 110 corresponds to the time between t6 and t7. The exit state S4 of the primary controller 110 corresponds to the time between t7 and t8.

[0071] As used herein, the name state machine is applied to a machine that can be in one of several states (e.g., states S0, S1, S2, S3, and S4), the machine being in one state at a time, and being able to change from one state to another state (e.g., transition) according to a triggering event of a condition. Thus, such a state machine can be defined by its states and the triggering conditions of the transition between two states.

[0072] according to Figure 7 In the state machine shown in FIG. 1 , an event that fails to cause a transition can be represented by a line looping over the old state, as shown by lines 702 and 704. An event that causes a transition from one state to another is represented by an arrow starting from the old state and pointing to the new state, as shown by lines 702 and 704. Figure 7 as shown in .

[0073] The state machine allows state transitions between the normal state S0 and the entering state S1, a state transition from the entering state S1 to the first sleeping state S2, a state transition from the first sleeping state S2 to the second sleeping state S3, a state transition from the second sleeping state S3 to the exit state S4, and a state transition from the exit state S4 to the normal state S0.

[0074] Depending on whether load 130 is connected to isolated power converter 100, primary controller 110 may determine different states of the primary controller. Figure 7 As shown in FIG. 1 , in the mode transition from the normal state S0 to the state S1 , the transition from the state S0 to the state S1 is triggered if the following conditions can be met: the voltage on the primary feedback node COMP drops below the low voltage V1 . In some embodiments, V1 is equal to 600 millivolts.

[0075] like Figure 7 As shown in , in the mode transition from the entry state S1 to the normal state S0 , the transition from the state S1 to the state S0 is triggered if the following conditions can be satisfied: the voltage on the primary feedback node COMP increases to a level greater than V1 .

[0076] In the normal state S0, the primary bias current is about 5 mA. The voltage on the primary feedback node COMP is at its normal value, at which the output voltage of the isolated power converter 100 is regulated. In entering state S1, the primary bias current remains the same. The voltage on the primary feedback node COMP remains at a low voltage. The duration that the voltage on the primary feedback node COMP remains at a low voltage is denoted as T.

[0077] like Figure 7 , in the mode transition from entering state S1 to the first sleep state S2, the transition from state S1 to state S2 is triggered if the following conditions can be met: the voltage on the primary feedback node COMP is less than V1, and T is greater than T1. T1 is a predetermined voltage threshold. In some embodiments, T1 is equal to 200 milliseconds. In the first sleep state S2, the primary bias current is about 70 microamperes. The primary controller 110 disables the feedback control loop (e.g., disables the oscillator of the isolated power converter).

[0078] like Figure 7 As shown in FIG. 1 , in the mode transition from the first sleep state S2 to the second sleep state S3 , the transition from state S2 to state S3 is triggered if the following conditions can be met: the voltage on the primary feedback node COMP is greater than V1 . In the second sleep state S3 , the primary bias current remains the same.

[0079] like Figure 7, in the mode transition from the second sleep state S3 to the exit state S4, if the following conditions can be met, then the transition from state S3 to state S4 is triggered: the voltage on the primary feedback node COMP is less than V1. In the exit state S4, the primary bias current is about 5 mA. The isolated power converter 100 enters a soft start process, in which the output voltage is established. The voltage on the primary feedback node COMP returns to its normal value, at which the output voltage is regulated.

[0080] like Figure 7 As shown in FIG. 1 , in the mode transition from the exit state S4 to the normal state S0 , once the soft start process is completed, the transition from the state S4 to the state S0 is triggered.

[0081] Figure 8 Illustrate the control of various embodiments according to the present disclosure Figure 1 Flowchart of the power conversion system shown in FIG. Figure 8 The flowcharts shown in are merely examples, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, Figure 8 The various steps illustrated in the drawings may be added, removed, substituted, rearranged, and repeated.

[0082] Return to reference Figure 1 , the power conversion system includes an isolated power converter 100 coupled between a power source VIN and a load 130. The primary controller 110 is configured to control the operation of the primary switch of the isolated power converter 100. The secondary controller 120 is configured to detect whether the load 130 is connected to the isolated power converter 100. The secondary feedback circuit 125 is configured to detect the output voltage of the isolated power converter 100 and generate a feedback signal fed into the primary feedback circuit 115 through the isolation interface 140. Based on the received feedback signal, the primary feedback circuit 115 generates a primary side feedback signal Vcomp fed into the primary controller 110. Based on Vcomp, the primary controller 110 generates a PWM signal for regulating the output voltage of the isolated power converter 100.

[0083] In operation, load 130 may be disconnected from isolated power converter 100. To further reduce power consumption, secondary controller 120 and primary controller 110 perform the following steps.

[0084] At step 802 , the secondary controller detects whether a load is coupled to a power conversion system including a primary circuit and a secondary circuit.

[0085] At step 804 , in response to the load being disconnected from the power conversion system, the secondary controller communicates with the primary controller by pulling down a secondary feedback node in the secondary circuit and a primary feedback node in the primary circuit for a first predetermined time.

[0086] At step 806 , the secondary controller configures the secondary feedback node to function as a high impedance node to reduce power consumption.

[0087] At step 808 , in response to the load being reconnected to the power conversion system, the secondary controller communicates with the primary controller by pulling down a secondary feedback node in the secondary circuit for a second predetermined time.

[0088] The method further includes: detecting, by the primary controller, whether a voltage on a primary feedback node in the primary circuit is lower than a predetermined voltage for a third predetermined time; in response to the voltage on the primary feedback node being lower than the predetermined voltage for the third predetermined time, entering a first sleep mode by disabling a feedback loop of the power conversion system; once the voltage on the primary feedback node increases to a level greater than the predetermined voltage, entering a second sleep mode; and in response to the voltage on the primary feedback node being lower than the predetermined voltage again, enabling the feedback loop to restart the power conversion system.

[0089] The method further includes configuring the primary controller to operate in a primary entry mode once a voltage on the primary feedback node drops below a predetermined voltage, and entering the first sleep mode once the primary controller stays in the primary entry mode for more than a third predetermined time.

[0090] The method further includes configuring the primary controller to operate in a second sleep mode once the voltage on the primary feedback node increases to a level greater than a predetermined voltage, and configuring the primary controller to enter a primary exit mode once the voltage on the primary feedback node drops below the predetermined voltage again.

[0091] The method further includes configuring the secondary controller to operate in a secondary entry mode once the secondary controller detects that the load is disconnected from the power conversion system and pulling down a secondary feedback node in the secondary circuit for a first predetermined time unless the load is reconnected to the power conversion system.

[0092] The method further includes configuring the secondary controller to enter a sleep mode once the secondary controller stays in the secondary entry mode for more than a first predetermined time; and in the sleep mode, configuring the secondary feedback node to act as a high impedance node.

[0093] The method further includes configuring the secondary controller to enter a secondary exit mode once the secondary controller detects that the load is reconnected to the power conversion system; and in the secondary exit mode, pulling down a secondary feedback node in the secondary circuit for a second predetermined time.

[0094] The primary controller is coupled to the secondary controller through an optocoupler including a light emitting diode and a phototransistor. The secondary circuit includes a resistor divider, a compensation network, and a three-terminal adjustable precision shunt voltage regulating integrated circuit, and wherein a cathode of the three-terminal adjustable precision shunt voltage regulating integrated circuit is connected to a cathode of the light emitting diode, a reference terminal of the three-terminal adjustable precision shunt voltage regulating integrated circuit is connected to the compensation network and the resistor divider, and an anode of the three-terminal adjustable precision shunt voltage regulating integrated circuit is connected to ground, and wherein a secondary feedback node in the secondary circuit is the cathode of the light emitting diode, and the primary circuit includes a pull-up resistor and a capacitor connected in series between a bias voltage and ground, and wherein a first terminal of the phototransistor is connected to a common node of the pull-up resistor and the capacitor, and a second terminal of the phototransistor is connected to ground, and wherein a primary feedback node in the primary circuit is a common node of the pull-up resistor and the capacitor.

[0095] The primary controller is coupled to the secondary controller via an optocoupler including a light emitting diode and a phototransistor. The secondary circuit includes a resistor divider, a compensation network, and an operational amplifier, wherein the compensation network is connected between an output of the operational amplifier and an inverting input of the operational amplifier, the inverting input of the operational amplifier is connected to a midpoint of the resistor divider, and the non-inverting input of the operational amplifier is connected to a predetermined reference, and the primary circuit includes a pull-up resistor and a capacitor connected in series between a bias voltage and ground, and wherein a first terminal of the phototransistor is connected to a common node of the pull-up resistor and the capacitor, and a second terminal of the phototransistor is connected to ground.

[0096] Although the embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

[0097] Moreover, the scope of the present application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, components, methods, and steps described in the specification. As those skilled in the art will readily appreciate from the disclosure of the present disclosure, according to the present disclosure, existing or later developed processes, machines, manufactures, compositions of matter, components, methods, or steps that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein may be utilized. Therefore, the appended claims are intended to include such processes, machines, articles, compositions of matter, components, methods, or steps within their scope.

Claims

1. A device comprising: a secondary controller coupled to a secondary circuit of the power conversion system; and a primary controller coupled to a primary circuit of the power conversion system, the primary controller coupled to the secondary controller via an isolation interface, wherein the secondary controller is configured to: detecting whether a load is coupled to the power conversion system; in response to the load being disconnected from the power conversion system, communicating with the primary controller to enter a sleep mode by pulling down a secondary feedback node in the secondary circuit and a primary feedback node in the primary circuit for a first predetermined time, wherein in the sleep mode, both the primary feedback circuit and the secondary feedback circuit are disabled to reduce power consumption; providing a high impedance at the secondary feedback node to reduce power consumption; and In response to the load being reconnected to the power conversion system, the sleep mode is exited by communicating with the primary controller by pulling down the secondary feedback node in the secondary circuit for a second predetermined time, wherein after exiting the sleep mode, the primary feedback circuit and the secondary feedback circuit are enabled to resume feedback loop control to regulate the output voltage of the power conversion system.

2. The apparatus according to claim 1, wherein: The primary controller is configured to: detect whether the voltage on the primary feedback node in the primary circuit is lower than a predetermined voltage for a third predetermined time; in response to the voltage on the primary feedback node being lower than the predetermined voltage for the third predetermined time, enter the sleep mode by disabling the feedback loop of the power conversion system; and in response to the voltage on the primary feedback node being lower than the predetermined voltage again, enable the feedback loop to restart the power conversion system.

3. The apparatus according to claim 1, wherein: The isolation interface is an optical coupler including a light emitting diode and a phototransistor; The secondary circuit includes a resistor divider, a compensation network, and a voltage regulating circuit, and wherein an output of the voltage regulating circuit is coupled to a cathode of the light emitting diode; and The primary circuit includes a pull-up resistor and a capacitor connected in series between a bias voltage and ground, and wherein: A first terminal of the phototransistor is connected to a common node of the pull-up resistor and the capacitor; and A second terminal of the phototransistor is connected to ground.

4. The apparatus according to claim 3, wherein: The voltage regulator circuit is a three-terminal adjustable precision shunt voltage regulator integrated circuit, wherein: a cathode of the three-terminal adjustable precision shunt voltage regulator integrated circuit coupled to the cathode of the light emitting diode; A reference terminal of the three-terminal adjustable precision shunt voltage regulator integrated circuit is connected to the compensation network and the resistor divider; and The anode of the three-terminal adjustable precision shunt voltage regulator integrated circuit is connected to ground.

5. The apparatus according to claim 3, wherein: The secondary feedback node in the secondary circuit is the cathode of the light emitting diode; and The primary feedback node in the primary circuit is the common node of the pull-up resistor and the capacitor.

6. The apparatus of claim 3, wherein: The voltage regulation circuit is an operational amplifier, wherein: The compensation network is connected between the output of the operational amplifier and the inverting input of the operational amplifier; The inverting input of the operational amplifier is connected to the midpoint of the resistor divider; and The non-inverting input of the operational amplifier is connected to a predetermined reference.

7. The apparatus of claim 1, wherein: The power conversion system includes a flyback power converter.

8. A method comprising: detecting, by a secondary controller, whether a load is coupled to a power conversion system including a primary circuit and a secondary circuit; in response to the load being disconnected from the power conversion system, communicating with a primary controller by pulling down a secondary feedback node in the secondary circuit and a primary feedback node in the primary circuit for a first predetermined time; configuring the secondary feedback node to act as a high impedance node to reduce power consumption; and In response to the load being reconnected to the power conversion system, communicating with the primary controller by pulling down the secondary feedback node in the secondary circuit for a second predetermined time.

9. The method according to claim 8, further comprising: detecting, by the primary controller, whether the voltage on the primary feedback node in the primary circuit is lower than a predetermined voltage for a third predetermined time; responsive to the voltage on the primary feedback node being below the predetermined voltage for the third predetermined time, entering a first sleep mode by disabling a feedback loop of the power conversion system; Once the voltage on the primary feedback node increases to a level greater than the predetermined voltage, entering a second sleep mode; and In response to the voltage on the primary feedback node being lower than the predetermined voltage again, the feedback loop is enabled to restart the power conversion system.

10. The method according to claim 9, further comprising: configuring the primary controller to operate in a primary entry mode once the voltage on the primary feedback node drops below the predetermined voltage; and Once the primary controller stays in the primary entry mode for more than the third predetermined time, it enters the first sleep mode.

11. The method according to claim 9, further comprising: configuring the primary controller to operate in the second sleep mode once the voltage on the primary feedback node increases to the level greater than the predetermined voltage; and Once the voltage on the primary feedback node drops below the predetermined voltage again, the primary controller is configured to enter a primary exit mode.

12. The method according to claim 8, further comprising: configuring the secondary controller to operate in a secondary entry mode upon the secondary controller detecting that the load is disconnected from the power conversion system; and The secondary feedback node in the secondary circuit is pulled down for the first predetermined time unless the load is reconnected to the power conversion system.

13. The method according to claim 12, further comprising: configuring the secondary controller to enter a sleep mode once the secondary controller remains in the secondary entry mode for more than the first predetermined time; and In the sleep mode, the secondary feedback node is configured to act as a high impedance node.

14. The method according to claim 13, further comprising: configuring the secondary controller to enter a secondary exit mode upon the secondary controller detecting that the load is reconnected to the power conversion system; and In the secondary exit mode, the secondary feedback node in the secondary circuit is pulled down for the second predetermined time.

15. The method of claim 8, wherein: The primary controller is coupled to the secondary controller via an optical coupler including a light emitting diode and a phototransistor; The secondary circuit includes a resistor divider, a compensation network and a three-terminal adjustable precision shunt voltage regulator integrated circuit, wherein: The cathode of the three-terminal adjustable precision shunt voltage regulator integrated circuit is connected to the cathode of the light emitting diode; A reference terminal of the three-terminal adjustable precision shunt voltage regulator integrated circuit is connected to the compensation network and the resistor divider; and An anode of the three-terminal adjustable precision shunt voltage regulator integrated circuit is connected to ground, and wherein the secondary feedback node in the secondary circuit is the cathode of the light emitting diode; and The primary circuit includes a pull-up resistor and a capacitor connected in series between a bias voltage and ground, and wherein: A first terminal of the phototransistor is connected to a common node of the pull-up resistor and the capacitor; and A second terminal of the phototransistor is connected to ground, and wherein the primary feedback node in the primary circuit is the common node of the pull-up resistor and the capacitor.

16. The method of claim 8, wherein: The primary controller is coupled to the secondary controller via an optical coupler including a light emitting diode and a phototransistor; The secondary circuit includes a resistor divider, a compensation network and an operational amplifier, and wherein: The compensation network is connected between the output of the operational amplifier and the inverting input of the operational amplifier; The inverting input of the operational amplifier is connected to the midpoint of the resistor divider; and The non-inverting input of the operational amplifier is connected to a predetermined reference; and The primary circuit includes a pull-up resistor and a capacitor connected in series between a bias voltage and ground, and wherein: A first terminal of the phototransistor is connected to a common node of the pull-up resistor and the capacitor; and A second terminal of the phototransistor is connected to ground.

17. A system comprising: an isolated power converter configured to be coupled between a power source and a load; a secondary controller coupled to a secondary circuit of the system; and a primary controller coupled to a primary circuit of the system, the primary controller coupled to the secondary controller via an isolation interface, wherein: The secondary controller is configured to: detect whether a load is coupled to the isolated power converter; in response to the load being disconnected from the isolated power converter, notifying the primary controller; and reducing power consumption of the secondary circuit by configuring a secondary feedback node as a high impedance node; and The primary controller is configured to disable a feedback control loop of the isolated power converter once the load is disconnected from the isolated power converter.

18. The system of claim 17, wherein: The secondary controller is configured to: detect whether a load is coupled to a power conversion system; in response to the load being disconnected from the power conversion system, communicate with the primary controller by pulling down a secondary feedback node in the secondary circuit and a primary feedback node in the primary circuit for a first predetermined time; provide a high impedance at the secondary feedback node to reduce power consumption; and in response to the load being reconnected to the power conversion system, communicate with the primary controller by pulling down the secondary feedback node in the secondary circuit for a second predetermined time; and The primary controller is configured to: detect whether the voltage on the primary feedback node in the primary circuit is lower than a predetermined voltage for a third predetermined time; in response to the voltage on the primary feedback node being lower than the predetermined voltage for the third predetermined time, enter a first sleep mode by disabling a feedback loop of the power conversion system; Once the voltage on the primary feedback node increases to a level greater than the predetermined voltage, a second sleep mode is entered; and in response to the voltage on the primary feedback node being lower than the predetermined voltage again, the feedback loop is enabled to restart the power conversion system.

19. The system of claim 17, further comprising: The primary controller is coupled to the secondary controller via an optical coupler including a light emitting diode and a phototransistor; The secondary circuit includes a resistor divider, a compensation network and a three-terminal adjustable precision shunt voltage regulator integrated circuit, wherein: The cathode of the three-terminal adjustable precision shunt voltage regulator integrated circuit is connected to the cathode of the light emitting diode; A reference terminal of the three-terminal adjustable precision shunt voltage regulator integrated circuit is connected to the compensation network and the resistor divider; and An anode of the three-terminal adjustable precision shunt voltage regulator integrated circuit is connected to ground, and wherein the secondary feedback node in the secondary circuit is the cathode of the light emitting diode; and The primary circuit includes a pull-up resistor and a capacitor connected in series between a bias voltage and ground, wherein: A first terminal of the phototransistor is connected to a common node of the pull-up resistor and the capacitor; and A second terminal of the phototransistor is connected to ground, and wherein the primary feedback node in the primary circuit is the common node of the pull-up resistor and the capacitor.

20. The system of claim 17, further comprising: The primary controller is coupled to the secondary controller via an optical coupler including a light emitting diode and a phototransistor; The secondary circuit includes a resistor divider, a compensation network and an operational amplifier, and wherein: The compensation network is connected between the output of the operational amplifier and the inverting input of the operational amplifier; The inverting input of the operational amplifier is connected to the midpoint of the resistor divider; and The non-inverting input of the operational amplifier is connected to a predetermined reference; and The primary circuit includes a pull-up resistor and a capacitor connected in series between a bias voltage and ground, wherein: A first terminal of the phototransistor is connected to a common node of the pull-up resistor and the capacitor; and A second terminal of the phototransistor is connected to ground.

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