Radio frequency power amplifier chip, radio frequency front-end module and electronic device

Abstract

The application provides a radio frequency power amplifier chip, a radio frequency front-end module and an electronic device. Through reasonable layout of a transistor array (a first transistor array, a second transistor array, a third transistor array and a fourth transistor array) and a corresponding power synthesis unit (a first power synthesis unit and a second power synthesis unit), the integration of the radio frequency power amplifier chip is improved.

Description

Technical Field

[0001] This application relates to the field of radio frequency technology, and in particular to a radio frequency power amplifier chip, a radio frequency front-end module, and an electronic device. Background Technology

[0002] The rapid development of communication technology is constantly driving the progress of the electronic equipment industry. For mobile devices, portability and ease of use are crucial user requirements, demanding higher performance and smaller size from electronic devices. Consequently, the integration requirements for various modules within mobile devices are becoming increasingly stringent. Taking the radio frequency (RF) front-end module as an example, with the gradual popularization of 5G mobile communication technology, the number of frequency bands that communication devices need to support has increased significantly, posing a greater challenge to RF front-end design. To meet this challenge, the integration requirements for various modules are extremely important. Summary of the Invention

[0003] This application provides an RF power amplifier chip, an RF front-end module, and an electronic device that can improve overall integration.

[0004] In a first aspect, this application provides a radio frequency power amplifier chip, comprising:

[0005] A first transistor array is disposed on a first side in a first direction;

[0006] A second transistor array is disposed on a first side in a second direction, wherein the first direction and the second direction intersect;

[0007] A first power combining unit is disposed on a second side in the first direction and a second side in the second direction, and is configured to perform power combining on the output signals of the first transistor array and the second transistor array;

[0008] A third transistor array is disposed on the second side in the first direction;

[0009] A fourth transistor array is disposed on the second side in the second direction;

[0010] The second power combining unit, disposed on the first side in the second direction and the first side in the first direction, is configured to perform power combining on the output signals of the third transistor array and the fourth transistor array.

[0011] Furthermore, the portion of the first transistor array disposed on the first side in the first direction relative to the second power combining unit is closer to the second side in the first direction, and the portion of the second transistor array disposed on the first side in the second direction relative to the second power combining unit is closer to the second side in the second direction.

[0012] And / or,

[0013] The portion of the third transistor array disposed on the second side of the first power combining unit in the first direction is closer to the first side in the first direction, and the portion of the fourth transistor array disposed on the second side of the first power combining unit in the second direction is closer to the first side in the second direction.

[0014] Furthermore, the first direction is perpendicular to the second direction.

[0015] Furthermore, the first power combining unit and the second power combining unit are disposed on the outside of the radio frequency power amplifier chip.

[0016] Furthermore, the portion of the second power combining unit disposed on the first side in the first direction is closer to the second side in the first direction relative to the first transistor array; the portion of the second power combining unit disposed on the first side in the second direction is closer to the second side in the second direction relative to the second transistor array; the portion of the third transistor array is closer to the first side in the first direction relative to the portion of the first power combining unit disposed on the second side in the first direction; and the portion of the fourth transistor array is closer to the first side in the second direction relative to the portion of the first power combining unit disposed on the second side in the second direction.

[0017] or,

[0018] The portion of the first power combining unit disposed on the second side in the first direction is closer to the first side in the first direction relative to the third transistor array. The portion of the first power combining unit disposed on the second side in the second direction is closer to the first side in the second direction relative to the fourth transistor array. The first transistor array is closer to the second side in the first direction relative to the portion of the second power combining unit disposed on the first side in the first direction. The second transistor array is closer to the second side in the second direction relative to the portion of the second power combining unit disposed on the first side in the second direction.

[0019] Furthermore, the first power combining unit includes a first primary coil and a first secondary coil coupled to each other. The first primary coil includes a first primary sub-coil and a second primary sub-coil. The first secondary coil includes a first secondary sub-coil and a second secondary sub-coil. The first primary sub-coil and the first secondary sub-coil are coupled to each other and are disposed on a second side in the first direction. The second primary sub-coil and the second secondary sub-coil are coupled to each other and are disposed on a second side in the second direction.

[0020] The second power combining unit includes a second primary coil and a second secondary coil coupled to each other. The second primary coil includes a third primary sub-coil and a fourth primary sub-coil. The second secondary coil includes a third secondary sub-coil and a fourth secondary sub-coil. The third primary sub-coil and the third secondary sub-coil are coupled to each other and are disposed on a first side in the first direction. The fourth primary sub-coil and the fourth secondary sub-coil are coupled to each other and are disposed on a first side in the second direction.

[0021] Furthermore, the first primary sub-coil is closer to the first side in the first direction relative to the first primary sub-coil, the second primary sub-coil is closer to the first side in the second direction relative to the second primary sub-coil, the third primary sub-coil is closer to the second side in the first direction relative to the third primary sub-coil, and the fourth primary sub-coil is closer to the second side in the second direction relative to the fourth secondary sub-coil.

[0022] or,

[0023] The first primary sub-coil is closer to the first side in the first direction than the first primary sub-coil, the second primary sub-coil is closer to the first side in the second direction than the second primary sub-coil, the third primary sub-coil is closer to the second side in the first direction than the third primary sub-coil, and the fourth secondary sub-coil is closer to the second side in the second direction than the fourth primary sub-coil.

[0024] Furthermore, the first power combining unit includes a first primary coil and a first secondary coil coupled to each other. The first primary coil includes a first outer primary coil and a first inner primary coil. The second power combining unit includes a second primary coil and a second secondary coil coupled to each other. The second primary coil includes a second outer primary coil and a second inner primary coil. The first secondary coil includes a first portion of secondary coil disposed between the first outer primary coil and the first inner primary coil, and a second portion of secondary coil disposed between the second outer primary coil and the second inner primary coil. The first portion of secondary coil and the second portion of secondary coil are connected in series.

[0025] Furthermore, the first primary coil also includes a third secondary coil disposed inside the first primary coil, and the second secondary coil also includes a fourth secondary coil disposed inside the second primary coil. The first secondary coil, the third secondary coil, the second secondary coil and the fourth secondary coil are connected in series in sequence.

[0026] Furthermore, the first power combining unit includes a first primary coil and a second secondary coil coupled to each other, and the second power combining unit includes a second primary coil and a second secondary coil coupled to each other;

[0027] The first secondary coil includes a first part of the secondary coil disposed on the first metal layer of the RF power amplifier chip and a second part of the secondary coil disposed on the second metal layer of the RF power amplifier chip. The second secondary coil includes a third part of the secondary coil disposed on the first metal layer of the RF power amplifier chip and a fourth part of the secondary coil disposed on the second metal layer of the RF power amplifier chip.

[0028] One end of the first secondary coil is configured to be connected to the signal output terminal, and one end of the third secondary coil is configured to be grounded. The first secondary coil and the third secondary coil are connected in series. One end of the second secondary coil is configured to be connected to the signal output terminal, and one end of the fourth secondary coil is configured to be grounded. The second secondary coil and the fourth secondary coil are connected in series.

[0029] The coil from the end of the first secondary coil connected to the signal output terminal to the end of the third secondary coil configured to be grounded is wound in a first manner from the outer layer to the inner layer; the coil from the end of the second secondary coil connected to the signal output terminal to the end of the fourth secondary coil configured to be grounded is wound in a first manner from the inner layer to the outer layer; or, the coil from the end of the first secondary coil connected to the signal output terminal to the end of the third secondary coil configured to be grounded is wound in a first manner from the inner layer to the outer layer; the coil from the end of the second secondary coil connected to the signal output terminal to the end of the fourth secondary coil configured to be grounded is wound in a first manner from the outer layer to the inner layer, wherein the first manner is clockwise or counterclockwise.

[0030] Furthermore, the first power combining unit includes a first primary coil and a second secondary coil coupled to each other, and the second power combining unit includes a second primary coil and a second secondary coil coupled to each other;

[0031] The first primary coil includes a first portion of the primary coil disposed on a first metal layer of the RF power amplifier chip and a second portion of the primary coil disposed on a second metal layer of the RF power amplifier chip, wherein the first portion of the primary coil and the second portion of the primary coil are longitudinally coupled.

[0032] The second primary coil includes a third primary coil disposed on the first metal layer of the RF power amplifier chip and a fourth primary coil disposed on the second metal layer of the RF power amplifier chip, wherein the third primary coil and the fourth primary coil are longitudinally coupled.

[0033] Furthermore, it also includes a pre-stage driving circuit, which is disposed in the area surrounded by the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array.

[0034] Furthermore, it also includes a passive element network disposed in the area surrounded by the first power combining unit and the second power combining unit.

[0035] Furthermore, the passive component network includes a first passive component unit and a second passive component unit. The first passive component unit is disposed in the region between the first transistor array, the second transistor array, and the second power combining unit. The second passive component unit is disposed in the region between the third transistor array, the fourth transistor array, and the first power combining unit.

[0036] Furthermore, the first power combining unit includes a first primary coil and a second secondary coil coupled to each other, a first end of the first primary coil being connected to the first transistor array, and a second end of the first primary coil being connected to the second transistor array;

[0037] The second power combining unit includes a second primary coil and a second secondary coil coupled to each other. The first end of the second primary coil is connected to the third transistor array, and the second end of the second primary coil is connected to the fourth transistor array.

[0038] Furthermore, the first end of the first-stage coil is configured to be connected to the signal output terminal, the second end of the first-stage coil is connected to the first end of the second-stage coil, and the second end of the second-stage coil is configured to be grounded;

[0039] or,

[0040] The first end of the first-stage coil and the second end of the second-stage coil are configured to be connected to the signal output terminal, and the second end of the first-stage coil and the first end of the second-stage coil are configured to be grounded.

[0041] Furthermore, the first transistor array, the second transistor array, and the first power combining unit are configured to amplify the power of the differential radio frequency signal, and the third transistor array, the fourth transistor array, and the second power combining unit are configured to amplify the power of the differential radio frequency signal.

[0042] Furthermore, the first power combining unit and the second power combining unit are at least partially disposed in the contact metal layer of the chip, the contact metal layer being disposed adjacent to the substrate of the chip.

[0043] A second aspect of this application provides a radio frequency power amplifier chip, comprising:

[0044] The first transistor array, the second transistor array, the third transistor array, and the fourth transistor array are distributed in four regions: a first side in the first direction, a second side in the first direction, a first side in the second direction, and a second side in the second direction, wherein the first direction and the second direction intersect.

[0045] A first power combining unit is disposed on a second side in the first direction and a second side in the second direction, and is configured to perform power combining on two transistor arrays among the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array;

[0046] The second power combining unit, disposed on the first side in the second direction and the first side in the first direction, is disposed on the outside of the chip and is configured to perform power combining on two other transistor arrays among the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array.

[0047] Furthermore, the first power combining unit is configured to perform power combining on the output signals of the first transistor array and the second transistor array, and the second power combining unit is configured to perform power combining on the output signals of the third transistor array and the fourth transistor array; the first transistor array, the second transistor array and the first power combining unit are configured to amplify the radio frequency signal of the first frequency band, and the third transistor array, the fourth transistor array and the second power combining unit are configured to amplify the radio frequency signal of the second frequency band.

[0048] A third aspect of this application provides a radio frequency power amplifier chip, comprising:

[0049] A first transistor array is disposed on a first side of a first virtual rectangular region in a first direction;

[0050] A second transistor array is disposed on a first side of the first virtual rectangular region in a second direction, wherein the first direction and the second direction intersect.

[0051] A first transformer structure is disposed on the second side of the first virtual rectangular region in the first direction and the second side of the first virtual rectangular region in the second direction, including a first primary coil and a second secondary coil coupled to each other, the first end of the first primary coil being connected to the first transistor array, and the second end of the first primary coil being connected to the second transistor array.

[0052] Furthermore, it also includes:

[0053] A third transistor array is disposed on the second side in the first direction;

[0054] A fourth transistor array is disposed on the second side of the first virtual rectangular region in the second direction;

[0055] The second transformer structure is disposed on the first side of the first virtual rectangular region in the second direction and the first side of the first virtual rectangular region in the first direction, including a second primary coil and a second secondary coil coupled to each other. The first end of the second primary coil is connected to the third transistor array, and the second end of the second primary coil is connected to the fourth transistor array.

[0056] In a fourth aspect, this application provides a radio frequency front-end module, including the aforementioned radio frequency power amplifier chip.

[0057] In a fifth aspect, this application provides an electronic device including the aforementioned radio frequency front-end module.

[0058] In the RF power amplifier chip, RF front-end module, and electronic device provided in this application embodiment, the integration level of the RF power amplifier chip is improved by the reasonable layout of the transistor array (first transistor array, second transistor array, third transistor array, and fourth transistor array) and the corresponding power combining unit (first power combining unit and second power combining unit). Attached Figure Description

[0059] Figure 1 This is a schematic diagram of a radio frequency power amplifier chip provided in an embodiment of this application;

[0060] Figure 2 This is another schematic diagram of a radio frequency power amplifier chip provided in one embodiment of this application;

[0061] Figure 3 This is another schematic diagram of a radio frequency power amplifier chip provided in one embodiment of this application;

[0062] Figure 4 This is another schematic diagram of a radio frequency power amplifier chip provided in one embodiment of this application;

[0063] Figure 5 This is another schematic diagram of a radio frequency power amplifier chip provided in an embodiment of this application;

[0064] Figure 6 This is another schematic diagram of a radio frequency power amplifier chip provided in one embodiment of this application;

[0065] Figure 7 This is another schematic diagram of a radio frequency power amplifier chip provided in one embodiment of this application;

[0066] Figure 8 This is another schematic diagram of a radio frequency power amplifier chip provided in one embodiment of this application;

[0067] Figure 9 This is another schematic diagram of a radio frequency power amplifier chip provided in one embodiment of this application;

[0068] Figure 10 This is another schematic diagram of a radio frequency power amplifier chip provided in one embodiment of this application;

[0069] Figure 11 This is another schematic diagram of a radio frequency power amplifier chip provided in one embodiment of this application;

[0070] Figure 12 This is another schematic diagram of a radio frequency power amplifier chip provided in one embodiment of this application;

[0071] Figure 13 This is another schematic diagram of a radio frequency power amplifier chip provided in one embodiment of this application;

[0072] Figure 14 This is another schematic diagram of a radio frequency power amplifier chip provided in one embodiment of this application;

[0073] Figure 15 This is another schematic diagram of a radio frequency power amplifier chip provided in one embodiment of this application;

[0074] Figure 16 This is another schematic diagram of a radio frequency power amplifier chip provided in an embodiment of this application. Detailed Implementation

[0075] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0076] It should be understood that this application can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions of layers and regions, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0077] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," "linked to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0078] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0079] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “ / the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “compose” and / or “comprising,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0080] To fully understand this application, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0081] At least one embodiment of this application provides a radio frequency power amplifier chip, comprising:

[0082] A first transistor array is disposed on a first side in a first direction;

[0083] A second transistor array is disposed on a first side in a second direction, wherein the first direction and the second direction intersect;

[0084] A first power combining unit is disposed on a second side in the first direction and a second side in the second direction, and is configured to perform power combining on the output signals of the first transistor array and the second transistor array;

[0085] A third transistor array is disposed on the second side in the second direction;

[0086] A fourth transistor array is disposed on the second side in the first direction;

[0087] The second power combining unit, disposed on the first side in the second direction and the first side in the first direction, is configured to perform power combining on the output signals of the third transistor array and the fourth transistor array.

[0088] The RF power amplifier chip provided in this embodiment includes a first transistor array and a second transistor array. For example, as shown... Figure 1 As shown, a first transistor array 11 is disposed on a first side in a first direction. A second transistor array 12 is disposed on a first side in a second direction. A third transistor array 21 is disposed on a second side in the first direction. A fourth transistor array 22 is disposed on a second side in the second direction. The first direction and the second direction intersect. It can be understood that... Figure 1The first and second directions in the example are nearly perpendicular to each other, but this should not be construed as a limitation of this embodiment. In this embodiment, it is sufficient for the first and second directions to intersect (i.e., two non-parallel directions).

[0089] The transistor arrays (first transistor array, second transistor array, third transistor array, and fourth transistor array) can be formed by connecting two or more transistors in series or in parallel, or by other conventional implementation methods in the art, which are not limited herein. In at least one embodiment, the transistors constituting any of the above transistor arrays can be bipolar junction transistors (BJTs) or field-effect transistors (FETs), etc. In at least one embodiment, the transistors are heterojunction transistors (HBTs). For example, the transistors are heterojunction transistors implemented using GaAs technology. In at least one implementation, the transistors are NPN transistors, that is, the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array are all NPN transistors. It is understood that in some embodiments, different transistor arrays can be different types of transistors. For example, the first transistor array is a PNP transistor, the second transistor array is an NPN transistor, the third transistor array is a PNP transistor, and the fourth transistor array is an NPN transistor. The arrangement of each transistor array can be set in one column, two or more columns, or multiple columns interleaved, etc., which are not specifically limited herein.

[0090] In at least one embodiment, the RF power amplifier chip is implemented using a BJT process, or the RF power amplifier chip is implemented using a CMOS process, or the RF power amplifier chip is implemented using a gallium arsenide process.

[0091] like Figure 1 As shown, the first transistor array 11 is disposed on the first side in the first direction, and the third transistor array 21 is disposed on the second side in the first direction. The second transistor array 12 is disposed on the first side in the second direction, and the fourth transistor array 22 is disposed on the second side in the second direction.

[0092] Understandably, the first side and the second side in this embodiment are only limitations on their relative positions. Figure 1 For example, the first transistor array and the third transistor array are distributed in the first direction. The first transistor array is positioned closer to the lower side than the third transistor array, while the third transistor array is positioned closer to the upper side than the first transistor array. The second transistor array and the fourth transistor array are distributed in the second direction. The second transistor array is positioned closer to the right side than the fourth transistor array, while the fourth transistor array is positioned closer to the left side than the second transistor array.

[0093] A first power combining unit is disposed on a second side in the first direction and a second side in the second direction, and is configured to perform power combining on the output signals of the first transistor array and the second transistor array. For example... Figure 1 As shown, the first power combining unit 30 is disposed on a second side in the first direction and a second side in the second direction. Specifically, the first power combining unit 30 can be divided into two parts, one part disposed on the second side in the first direction and the other part disposed on the second side in the second direction. In at least one embodiment, the first power combining unit is a transformer structure, including a first primary coil and a first secondary coil, with the two ends of the first primary coil connected to the first transistor array and the second transistor array, respectively. Optionally, one end of the first secondary coil is connected to an output signal terminal, and the other end is configured to be grounded or connected to a second power combining unit. In at least one embodiment, the first primary coil and the first secondary coil can achieve co-layer coupling in the same metal layer in the chip, or the first primary coil and the first secondary coil can achieve longitudinal (stacked) coupling in different metal layers in the chip, or the first primary coil and the first secondary coil can achieve both co-layer coupling and longitudinal coupling.

[0094] The second power combining unit is disposed on the first side in the second direction and the first side in the first direction, and is configured to perform power combining on the output signals of the third transistor array and the fourth transistor array. For example... Figure 1 As shown, the second power combining unit 40 is disposed on a first side in the second direction and a first side in the first direction. Specifically, the second power combining unit 40 can be divided into two parts, one part disposed on the first side in the second direction and the other part disposed on the first side in the first direction. In at least one embodiment, the second power combining unit is a transformer structure, including a second primary coil and a second secondary coil, with the two ends of the second primary coil connected to the third transistor array and the fourth transistor array, respectively. One end of the second secondary coil is connected to the output signal terminal, and the other end is configured to be grounded; or, one end of the second secondary coil is configured to be grounded, and the other end is connected to the first power combining unit. In at least one embodiment, the second primary coil and the second secondary coil can achieve co-layer coupling in the same metal layer in the chip, or the second primary coil and the second secondary coil can achieve longitudinal (stacked) coupling in different metal layers in the chip, or the second primary coil and the second secondary coil can achieve both co-layer coupling and longitudinal coupling.

[0095] In at least one embodiment, the first primary coil and the second primary coil can be longitudinally (stacked) coupled in different metal layers of the chip, and the second primary coil and the second primary coil can also be longitudinally (stacked) coupled in different metal layers of the chip. Specifically, the first primary coil and the second primary coil are disposed in the first metal layer of the chip, and the first primary coil and the second primary coil are disposed in the second metal layer of the chip, with the first primary coil and the first primary coil being longitudinally coupled, and the second primary coil and the second primary coil being longitudinally coupled.

[0096] In at least one embodiment, such as Figure 1 As shown, the first power combining unit and the second power combining unit are arranged together around the first transistor array, the second transistor array, the third transistor array and the fourth transistor array.

[0097] In at least one embodiment, the first transistor array, the second transistor array, and the corresponding first power combining unit can constitute a first power amplification unit, while the third transistor array, the fourth transistor array, and the corresponding second power combining unit can constitute a second power amplification unit. The first and second power amplification units can amplify different radio frequency (RF) signals, for example, RF signals from different frequency bands. These different frequency bands can be different bands under the same communication standard (e.g., N41, N77, N79, etc.), or different frequency bands under different communication standards (e.g., 3G band, 4G band, 5G band, etc.). Alternatively, the first and second power amplification units can each support amplification of RF signals in different power modes.

[0098] Understandably, the relative positions in this embodiment can be defined by projections in the chip thickness direction. In other words, different devices / components can be placed in different layers of the chip.

[0099] In this embodiment, a first transistor array is disposed on a first side in a first direction; a second transistor array is disposed on a first side in a second direction, the first and second directions intersecting; a first power combining unit is disposed on a second side in both the first and second directions, configured to perform power combining on the output signals of the first and second transistor arrays; a third transistor array is disposed on a second side in the first direction; a fourth transistor array is disposed on a second side in the second direction; and a second power combining unit is disposed on a first side in both the second and first directions, configured to perform power combining on the output signals of the third and fourth transistor arrays. Through the rational layout of the transistor arrays and corresponding power combining units, the integration density of the RF power amplifier chip is significantly improved. Furthermore, while achieving high power, the overall thermal resistance of the chip is reduced, ensuring chip reliability.

[0100] In at least one embodiment, the portion of the first transistor array disposed on the first side in the first direction relative to the second power combining unit is closer to the second side in the first direction, and the portion of the second transistor array disposed on the first side in the second direction relative to the second power combining unit is closer to the second side in the second direction.

[0101] And / or,

[0102] The portion of the third transistor array disposed on the second side of the first power combining unit in the first direction is closer to the first side in the first direction, and the portion of the fourth transistor array disposed on the second side of the first power combining unit in the second direction is closer to the first side in the second direction.

[0103] For example, in Figure 1 In this configuration, the first transistor array 11 is closer to the second side in the first direction than the second power combining unit 40. Specifically, the first transistor array 11 is closer to the second side in the first direction than the portion of the second power combining unit 40 disposed on the first side in the first direction.

[0104] The second transistor array 12 is closer to the second side in the second direction than the second power combining unit 40 which is disposed on the first side in the second direction. Specifically, the second transistor array 12 is closer to the second side in the second direction than the portion of the second power combining unit 40 disposed on the first side in the second direction.

[0105] The third transistor array 21 is closer to the first side in the first direction than the first power combining unit 30. Specifically, the third transistor array 21 is closer to the first side in the first direction than the portion of the first power combining unit 30 disposed on the second side in the first direction.

[0106] The fourth transistor array 22 is closer to the first side in the second direction than the first power combining unit 30. Specifically, the fourth transistor array 22 is closer to the first side in the second direction than the portion of the first power combining unit 30 disposed on the second side in the second direction.

[0107] In this embodiment, by setting the transistor array to be positioned further inside the chip relative to the power combining unit, it is easier to set up the wiring, avoids too many cross-line crossings, further ensures the chip's integration, and also avoids the performance degradation caused by too many cross-line crossings.

[0108] In at least one embodiment, the first direction is perpendicular to the second direction. By setting the first and second directions to be perpendicular, the overall layout can be made more square, conforming to the chip's appearance and making the overall layout more compact. It is understood that the perpendicularity in this embodiment is not limited to an absolute 90 degrees. As long as the first and second directions deviate from each other by a certain angle within the range of 90 degrees (for example, ±5 degrees or ±10 degrees, etc.), it should be considered to conform to this embodiment.

[0109] In at least one embodiment, the first power combining unit and the second power combining unit are disposed outside the RF power amplifier chip. For example... Figure 1 As shown, by setting the first power combining unit 30 and the second power combining unit 40 on the outside of the RF power amplifier chip, the internal space of the chip is well utilized, and the circuit routing is also facilitated, taking into account both integration and chip performance.

[0110] Furthermore, the first power combining unit and the second power combining unit are disposed on the outside of the RF power amplifier chip, which can serve as at least part of the sealing ring of the RF power amplifier chip, thereby reducing the additional space consumption of the chip (otherwise, an additional sealing ring needs to be set on the outside of the chip), and also improving the overall integration of the chip.

[0111] In at least one embodiment, the first power combining unit and the second power combining unit are at least partially disposed in the contact metal layer of the chip, the contact metal layer being disposed adjacent to the substrate of the chip.

[0112] Understandably, the first power combining unit and the second power combining unit may be partially disposed in the first metal layer of the chip and partially disposed in the contact metal layer. Alternatively, the first power combining unit and the second power combining unit may be partially disposed in the first metal layer and the second metal layer of the chip and partially disposed in the contact metal layer.

[0113] In at least one embodiment, such as Figure 16 As shown, a contact metal layer 202 is disposed on the substrate 201, and a first metal layer 204 is disposed above the contact metal layer 202. The first metal layer 204 and the contact metal layer 202 can be connected through a first via 203. A second metal layer 206 is disposed above the first metal layer 204, and the second metal layer 206 and the first metal layer 204 can be connected through a second via 204.

[0114] In at least one embodiment, the first power combining unit and the second power combining unit are disposed in the first metal layer 204 and the contact metal layer 202, and the pattern disposed in the first metal layer and the pattern disposed in the contact metal layer 202 are connected by a first via 203.

[0115] In at least one embodiment, the first power combining unit and the second power combining unit are disposed in the second metal layer 206, the first metal layer 204 and the contact metal layer 202, and the pattern disposed in the first metal layer and the pattern disposed in the contact metal layer 202 are connected by a first via 203, and the pattern disposed in the first metal layer and the pattern disposed in the second metal layer 206 are connected by a second via 205.

[0116] This embodiment achieves the function of a chip sealing ring by at least partially disposing the first power combining unit and the second power combining unit in the contact metal layer of the chip, thereby improving the chip's integration density.

[0117] In at least one embodiment, the portion of the second power combining unit 40 disposed on the first side in the first direction is closer to the second side in the first direction than the first transistor array.

[0118] In at least one embodiment, the portion of the second power combining unit 40 disposed on the first side in the second direction is closer to the second side in the second direction than the second transistor array 12.

[0119] In at least one embodiment, the portion of the first power combining unit 30 disposed on the second side in the first direction is closer to the first side in the first direction than the third transistor array 21.

[0120] In at least one embodiment, the portion of the first power combining unit 30 disposed on the second side in the second direction is closer to the first side in the second direction than the fourth transistor array 22.

[0121] In at least one embodiment, the RF power amplifier chip meets at least one of the following criteria:

[0122] The portion of the second power combining unit 40 disposed on the first side in the first direction is closer to the second side in the first direction relative to the first transistor array;

[0123] The portion of the second power combining unit 40 disposed on the first side in the second direction is closer to the second side in the second direction than the second transistor array 12;

[0124] The portion of the first power combining unit 30 disposed on the second side in the first direction is closer to the first side in the first direction than the third transistor array 21;

[0125] The portion of the first power combining unit 30 disposed on the second side in the second direction is closer to the first side in the second direction than the fourth transistor array 22.

[0126] In at least one embodiment, the portion of the second power combining unit 40 disposed on the first side in the first direction is closer to the second side in the first direction relative to the first transistor array, and the portion of the second power combining unit 40 disposed on the first side in the second direction is closer to the second side in the second direction relative to the second transistor array 12.

[0127] And / or,

[0128] The portion of the first power combining unit 30 disposed on the second side in the first direction is closer to the first side in the first direction than the third transistor array 21, and the portion of the first power combining unit 30 disposed on the second side in the second direction is closer to the first side in the second direction than the fourth transistor array 22.

[0129] In this embodiment, by flexibly configuring the power combining unit and the corresponding transistor array, it is possible to better ensure the adaptation to different application scenarios (different frequency modes, different power modes, or reconfigurable modes, etc.), and to ensure good functionality and performance in different scenarios.

[0130] In at least one embodiment, the portion of the second power combining unit 40 disposed on the first side in the first direction is closer to the second side in the first direction relative to the first transistor array, and the portion of the second power combining unit 40 disposed on the first side in the second direction is closer to the second side in the second direction relative to the second transistor array 12.

[0131] The portion of the third transistor array disposed on the second side of the first power combining unit in the first direction is closer to the first side in the first direction, and the portion of the fourth transistor array disposed on the second side of the first power combining unit in the second direction is closer to the first side in the second direction.

[0132] In this embodiment, the layout can be made more flexible by flexibly adjusting the relative positions of the transistor array and the corresponding power combining unit.

[0133] In at least one embodiment, the portion of the first power combining unit 30 disposed on the second side in the first direction is closer to the first side in the first direction relative to the third transistor array 21, and the portion of the first power combining unit 30 disposed on the second side in the second direction is closer to the first side in the second direction relative to the fourth transistor array 22.

[0134] The portion of the first transistor array disposed on the first side in the first direction relative to the second power combining unit is closer to the second side in the first direction, and the portion of the second transistor array disposed on the first side in the second direction relative to the second power combining unit is closer to the second side in the second direction.

[0135] In this embodiment, the layout can be made more flexible by flexibly adjusting the relative positions of the transistor array and the corresponding power combining unit.

[0136] In at least one embodiment, the first primary sub-coil is closer to the first side in the first direction than the first primary sub-coil, the second primary sub-coil is closer to the first side in the second direction than the second primary sub-coil, the third primary sub-coil is closer to the second side in the first direction than the third primary sub-coil, and the fourth primary sub-coil is closer to the second side in the second direction than the fourth secondary sub-coil.

[0137] or,

[0138] The first primary sub-coil is closer to the first side in the first direction than the first primary sub-coil, the second primary sub-coil is closer to the first side in the second direction than the second primary sub-coil, the third primary sub-coil is closer to the second side in the first direction than the third primary sub-coil, and the fourth secondary sub-coil is closer to the second side in the second direction than the fourth primary sub-coil.

[0139] In at least one embodiment, such as Figure 1 As shown, the first primary sub-coil 33 is closer to the first side in the first direction than the first primary sub-coil 31, the second primary sub-coil 34 is closer to the first side in the second direction than the second primary sub-coil 32, the third primary sub-coil 41 is closer to the second side in the first direction than the third primary sub-coil 43, and the fourth primary sub-coil 42 is closer to the second side in the second direction than the fourth secondary sub-coil 44.

[0140] In at least one embodiment, such as Figure 3 As shown, the first primary sub-coil 31 is closer to the first side in the first direction than the first primary sub-coil 33, the second primary sub-coil 32 is closer to the first side in the second direction than the second primary sub-coil 34, the third primary sub-coil 43 is closer to the second side in the first direction than the third primary sub-coil 41, and the fourth secondary sub-coil 44 is closer to the second side in the second direction than the fourth primary sub-coil 42.

[0141] In at least one embodiment, one end of the first primary sub-coil 31 is connected to the output terminal of the second transistor array 12, the other end of the first primary sub-coil 31 is connected to one end of the second primary sub-coil 32, and the other end of the second primary sub-coil 32 is connected to the output terminal of the first transistor array 11. In at least one embodiment, the other end of the first primary sub-coil 31 and one end of the second primary sub-coil 32 are configured to be connected to a first power supply terminal.

[0142] In at least one embodiment, one end of the third primary sub-coil 41 is connected to the output terminal of the fourth transistor array 22, the other end of the third primary sub-coil 41 is connected to one end of the fourth primary sub-coil 42, and the other end of the fourth primary sub-coil 42 is connected to the output terminal of the third transistor array 21. In at least one embodiment, the other end of the third primary sub-coil 41 and one end of the fourth primary sub-coil 42 are configured to be connected to a second power supply terminal.

[0143] Understandably, the first power supply terminal and the second power supply terminal can be configured to receive the same power supply voltage, or they can be configured to receive different power supply voltages.

[0144] In at least one embodiment, the first power combining unit includes a first primary coil and a first secondary coil coupled to each other. The first primary coil includes a first primary sub-coil 31 and a second primary sub-coil 32. The first secondary coil includes a first secondary sub-coil 33 and a second secondary sub-coil 34. The first primary sub-coil 31 and the first secondary sub-coil 33 are coupled to each other and disposed on a second side in the first direction. The second primary sub-coil 32 and the second secondary sub-coil 34 are coupled to each other and disposed on a second side in the second direction.

[0145] The second power combining unit includes a second primary coil and a second secondary coil coupled to each other. The second primary coil includes a third primary sub-coil 41 and a fourth primary sub-coil 42. The second secondary coil includes a third secondary sub-coil 43 and a fourth secondary sub-coil 44. The third primary sub-coil 41 and the third secondary sub-coil 43 are coupled to each other and are disposed on a first side in the first direction. The fourth primary sub-coil 42 and the fourth secondary sub-coil 44 are coupled to each other and are disposed on a first side in the second direction.

[0146] The primary sub-coil 31 can be at least one, the second primary sub-coil 32 can be at least one, the first primary sub-coil 33 can be at least one, and the second primary sub-coil 34 can be at least one. Optionally, the first primary sub-coil 31 can be two; for example, two first primary sub-coils 31 are connected in parallel on the second side in the first direction. The second primary sub-coil 32 can be two; for example, two second primary sub-coils 32 are connected in parallel on the second side in the second direction. Optionally, the first primary sub-coil 34 can be two; for example, two first primary sub-coils 34 are connected in parallel on the second side in the first direction. The second primary sub-coil 34 can be two; for example, two second primary sub-coils 34 are connected in parallel on the second side in the second direction. Further, the number of primary sub-coils (first primary sub-coil 31 and second primary sub-coil 32) and secondary sub-coils (first primary sub-coil 33 and second primary sub-coil 34) can be the same or different, and this is not limited here.

[0147] The number of the third primary sub-coil 41, the number of the fourth primary sub-coil 42, the number of the third secondary sub-coil 41, and the number of the fourth secondary sub-coil 44 can be at least one. Optionally, the number of the third primary sub-coil 41 can be two; for example, two third primary sub-coils 41 are connected in parallel on the second side in the first direction. The number of the fourth primary sub-coil 42 can be two; for example, two fourth primary sub-coils 42 are connected in parallel on the second side in the second direction. Optionally, the number of the third secondary sub-coil 41 can be two; for example, two third secondary sub-coils 41 are connected in parallel on the second side in the first direction. The number of the fourth secondary sub-coil 44 can be two; for example, two fourth secondary sub-coils 44 are connected in parallel on the second side in the second direction. Further, the number of primary sub-coils (third primary sub-coil 41 and fourth primary sub-coil 42) and secondary sub-coils (third secondary sub-coil 41 and fourth secondary sub-coil 44) can be the same or different, and there is no limitation here.

[0148] In at least one embodiment, the first primary sub-coil is closer to the first side in the first direction than the first primary sub-coil, the second primary sub-coil is closer to the first side in the second direction than the second primary sub-coil, the third primary sub-coil is closer to the second side in the first direction than the third primary sub-coil, and the fourth primary sub-coil is closer to the second side in the second direction than the fourth secondary sub-coil.

[0149] or,

[0150] The first primary sub-coil is closer to the first side in the first direction than the first primary sub-coil, the second primary sub-coil is closer to the first side in the second direction than the second primary sub-coil, the third primary sub-coil is closer to the second side in the first direction than the third primary sub-coil, and the fourth secondary sub-coil is closer to the second side in the second direction than the fourth primary sub-coil.

[0151] like Figure 1 As shown, in at least one embodiment, the first primary sub-coil 33 is closer to the first side in the first direction than the first primary sub-coil 31, the second primary sub-coil 34 is closer to the first side in the second direction than the second primary sub-coil 32, the third primary sub-coil 41 is closer to the second side in the first direction than the third primary sub-coil 43, and the fourth primary sub-coil 42 is closer to the second side in the second direction than the fourth secondary sub-coil 44.

[0152] like Figure 3 As shown, in at least one embodiment, the first primary sub-coil 31 is closer to the first side in the first direction than the first primary sub-coil 33, the second primary sub-coil 32 is closer to the first side in the second direction than the second primary sub-coil 34, the third primary sub-coil 43 is closer to the second side in the first direction than the third primary sub-coil 41, and the fourth secondary sub-coil 44 is closer to the second side in the second direction than the fourth primary sub-coil 42.

[0153] In at least one embodiment, the first power combining unit includes a first primary coil and a first secondary coil coupled to each other, the first primary coil including a first outer primary coil and a first inner primary coil; the second power combining unit includes a second primary coil and a second secondary coil coupled to each other, the second primary coil including a second outer primary coil and a second inner primary coil; the first secondary coil includes a first portion of a secondary coil disposed between the first outer primary coil and the first inner primary coil, and a second portion of a secondary coil disposed between the second outer primary coil and the second inner primary coil; the first portion of the secondary coil and the second portion of the secondary coil are connected in series.

[0154] like Figure 4 As shown, the first power combining unit 30 includes a first primary coil and a first secondary coil coupled to each other. The first primary coil includes a first outer primary coil 35 and a first inner primary coil 36. The second power combining unit includes a second primary coil and a second secondary coil coupled to each other. The second primary coil includes a second outer primary coil 45 and a second inner primary coil 46. The first secondary coil includes a first portion of secondary coil 37 disposed between the first outer primary coil 35 and the first inner primary coil 36, and a second portion of secondary coil 47 disposed between the second outer primary coil 45 and the second inner primary coil 46. The first portion of secondary coil 37 and the second portion of secondary coil 47 are connected in series.

[0155] In at least one embodiment, one end of the first portion of the secondary coil 37 is configured to be connected to a signal output terminal, and the other end of the first portion of the secondary coil 37 is connected to one end of the second portion of the secondary coil 47, the other end of the second portion of the secondary coil 47 being configured to be grounded. In at least one embodiment, one end of the first portion of the secondary coil 37 is configured to be grounded, and the other end of the first portion of the secondary coil 37 is connected to one end of the second portion of the secondary coil 47, the other end of the second portion of the secondary coil 47 being configured to be connected to a signal output terminal.

[0156] In this embodiment, the first primary coil includes a first outer primary coil 35 and a first inner primary coil 36, and a corresponding first portion of the secondary coil 37 is disposed between the first outer primary coil 35 and the first inner primary coil 36. The second primary coil includes a second outer primary coil 45 and a second inner primary coil 46, and a corresponding first portion of the secondary coil 37 is disposed between the first outer primary coil 35 and the first inner primary coil 36, ensuring better coupling and further improving the performance of the power amplifier.

[0157] In at least one embodiment, the first primary coil further includes a third secondary coil disposed inside the first primary coil, and the second secondary coil further includes a fourth secondary coil disposed inside the second primary coil, wherein the first secondary coil, the third secondary coil, the second secondary coil and the fourth secondary coil are connected in series in sequence.

[0158] like Figure 5 As shown, the first primary coil further includes a third secondary coil 38 disposed inside the first primary coil, and the second primary coil further includes a fourth secondary coil 48 disposed inside the second primary coil. Figure 5 In this configuration, the third secondary coil 38 is disposed inside the first primary coil; specifically, the third secondary coil 38 is disposed inside both the first outer primary coil 35 and the first inner primary coil 36. The fourth secondary coil 48 is disposed inside the second primary coil; specifically, the fourth secondary coil 48 is disposed inside both the second outer primary coil 45 and the second inner primary coil 46. The first secondary coil 37, the third secondary coil 47, the second secondary coil 38, and the fourth secondary coil 48 are connected in series sequentially. Specifically, one end of the first secondary coil 37 is configured to be connected to a signal output terminal; the other end of the first secondary coil 37 is connected to one end of the second secondary coil 47; the other end of the second secondary coil 47 is connected to one end of the third secondary coil 38; the other end of the third secondary coil 38 is connected to one end of the fourth secondary coil 48; and the other end of the fourth secondary coil 48 is configured to be grounded. Alternatively, one end of the first secondary coil 37 is configured to be grounded, the other end of the first secondary coil 37 is connected to one end of the second secondary coil 47, the other end of the second secondary coil 47 is connected to one end of the third secondary coil 38, the other end of the third secondary coil 38 is connected to one end of the fourth secondary coil 48, and the other end of the fourth secondary coil 48 is configured to be connected to a signal output terminal.

[0159] In this embodiment, by winding the secondary coil in multiple layers, a lower impedance matching can be achieved for the power amplifier in conjunction with the primary coil.

[0160] In at least one embodiment, the first power combining unit includes a first primary coil and a second secondary coil coupled to each other, and the second power combining unit includes a second primary coil and a second secondary coil coupled to each other.

[0161] The first secondary coil includes a first part of the secondary coil disposed on the first metal layer of the RF power amplifier chip and a second part of the secondary coil disposed on the second metal layer of the RF power amplifier chip. The second secondary coil includes a third part of the secondary coil disposed on the first metal layer of the RF power amplifier chip and a fourth part of the secondary coil disposed on the second metal layer of the RF power amplifier chip.

[0162] One end of the first secondary coil is configured to be connected to the signal output terminal, and one end of the third secondary coil is configured to be grounded. The first secondary coil and the third secondary coil are connected in series. One end of the second secondary coil is configured to be connected to the signal output terminal, and one end of the fourth secondary coil is configured to be grounded. The second secondary coil and the fourth secondary coil are connected in series.

[0163] The coil from the end of the first secondary coil connected to the signal output terminal to the end of the third secondary coil configured to be grounded is wound in a first manner from the outer layer to the inner layer; the coil from the end of the second secondary coil connected to the signal output terminal to the end of the fourth secondary coil configured to be grounded is wound in a first manner from the inner layer to the outer layer; or, the coil from the end of the first secondary coil connected to the signal output terminal to the end of the third secondary coil configured to be grounded is wound in a first manner from the inner layer to the outer layer; the coil from the end of the second secondary coil connected to the signal output terminal to the end of the fourth secondary coil configured to be grounded is wound in a first manner from the outer layer to the inner layer, wherein the first manner is clockwise or counterclockwise.

[0164] like Figure 6 As shown, the first secondary coil includes a first portion of secondary coil 391 disposed on the first metal layer of the RF power amplifier chip and a second portion of secondary coil 392 disposed on the second metal layer of the RF power amplifier chip. The second secondary coil includes a third portion of secondary coil 491 disposed on the first metal layer of the RF power amplifier chip and a fourth portion of secondary coil 492 disposed on the second metal layer of the RF power amplifier chip. It can be understood that... Figure 6The first part of the secondary coil 391, the second part of the secondary coil 392, the third part of the secondary coil 491 and the fourth part of the secondary coil 492 each include two parts (an L-shaped coil segment arranged on the outer side and an L-shaped coil segment arranged on the inner side), but this should not be interpreted as a limitation on the number and shape of any of the above secondary coils, and is only used as an example.

[0165] Understandably, Figure 6 The side-by-side arrangement of the first portion of the secondary coil 391 and the third portion of the secondary coil 491 in the first metal layer, and the second portion of the secondary coil 392 and the fourth portion of the secondary coil 492 in the second metal layer, is merely for visual clarity; in reality, the first metal layer and the second metal layer are different layers along the chip thickness direction. In at least one embodiment, the first metal layer is located above the second metal layer. In at least one embodiment, the first metal layer is located below the second metal layer. In at least one embodiment, the first metal layer and the second metal layer are adjacent metal layers.

[0166] In at least one embodiment, the first metal layer and the second metal layer are two non-adjacent metal layers. Exemplarily, the RF power amplifier chip further includes a third metal layer, on which the first primary coil and the second primary coil may be disposed, and the third metal layer is disposed between the first metal layer and the second metal layer.

[0167] One end of the first secondary coil 391 is configured to be connected to the signal output terminal, and one end of the third secondary coil 491 is configured to be grounded. The first secondary coil 391 and the third secondary coil 491 are connected in series. One end of the second secondary coil 392 is configured to be connected to the signal output terminal, and one end of the fourth secondary coil 492 is configured to be grounded. The second secondary coil 392 and the fourth secondary coil 492 are connected in series.

[0168] by Figure 6 For example, the first secondary coil 391 includes a first outer coil and a first inner coil, and the third secondary coil 491 includes a third outer coil and a third inner coil. The first end of the first outer coil is configured to be connected to a signal output terminal, the other end of the first outer coil is connected to the first end of the third outer coil, the other end of the third outer coil is connected to the first end of the first inner coil, the other end of the first inner coil is connected to the first end of the third inner coil, and the other end of the third inner coil is configured to be grounded.

[0169] The second secondary coil 392 includes a second outer coil and a second inner coil, and the fourth secondary coil 492 includes a fourth outer coil and a fourth inner coil. A first end of the second inner coil is configured to be connected to a signal output terminal, the other end of the second inner coil is connected to the first end of the fourth inner coil, the other end of the fourth inner coil is connected to the first end of the second outer coil, the other end of the second outer coil is connected to the first end of the fourth outer coil, and the other end of the fourth outer coil is configured to be grounded.

[0170] In at least one embodiment, the coil from the end of the first portion of the secondary coil connected to the signal output terminal to the end of the third portion of the secondary coil configured to be grounded is wound in a first manner from the outer layer to the inner layer, and the coil from the end of the second portion of the secondary coil connected to the signal output terminal to the end of the fourth portion of the secondary coil configured to be grounded is wound in a first manner from the inner layer to the outer layer, wherein the first manner is a clockwise manner or a counterclockwise manner.

[0171] by Figure 6 For example, the first secondary coil 391 includes a first outer coil and a first inner coil, and the third secondary coil 491 includes a third outer coil and a third inner coil. The first end of the first outer coil is configured to be connected to a signal output terminal, the other end of the first outer coil is connected to the first end of the third outer coil, the other end of the third outer coil is connected to the first end of the first inner coil, the other end of the first inner coil is connected to the first end of the third inner coil, and the other end of the third inner coil is configured to be grounded.

[0172] The second secondary coil 392 includes a second outer coil and a second inner coil, and the fourth secondary coil 492 includes a fourth outer coil and a fourth inner coil. A first end of the second inner coil is configured to be connected to a signal output terminal, the other end of the second inner coil is connected to the first end of the fourth inner coil, the other end of the fourth inner coil is connected to the first end of the second outer coil, the other end of the second outer coil is connected to the first end of the fourth outer coil, and the other end of the fourth outer coil is configured to be grounded.

[0173] In at least one embodiment, the coil from the end of the first portion of the secondary coil connected to the signal output terminal to the end of the third portion of the secondary coil configured to be grounded is wound in a manner from the inner layer to the outer layer, and the coil from the end of the second portion of the secondary coil connected to the signal output terminal to the end of the fourth portion of the secondary coil configured to be grounded is wound in a manner from the outer layer to the inner layer.

[0174] The first secondary coil includes a first outer coil and a first inner coil, and the third secondary coil includes a third outer coil and a third inner coil. A first end of the first inner coil is configured to be connected to a signal output terminal, the other end of the first inner coil is connected to a first end of the third inner coil, the other end of the third inner coil is connected to a first end of the second outer coil, the other end of the first outer coil is connected to a first end of the third outer coil, and the other end of the third outer coil is configured to be grounded.

[0175] The second secondary coil includes a second outer coil and a second inner coil, and the fourth secondary coil includes a fourth outer coil and a fourth inner coil. A first end of the second outer coil is configured to be connected to a signal output terminal, the other end of the second outer coil is connected to the first end of the fourth outer coil, the other end of the fourth outer coil is connected to the first end of the second inner coil, the other end of the second inner coil is connected to the first end of the fourth inner coil, and the other end of the fourth inner coil is configured to be grounded.

[0176] In this embodiment, in at least one implementation, the first primary coil and the second primary coil may be disposed only on the first metal layer.

[0177] In at least one embodiment, a first primary coil portion is disposed on a first metal layer, and another portion is disposed on a second metal layer; a second primary coil portion is disposed on the first metal layer, and another portion is disposed on the second metal layer. Exemplarily, the first and second primary coils on the first metal layer can be referenced in the appendix. Figure 5 The configuration is as shown in the appendix. The first primary coil and the second primary coil can also be mounted on the second metal layer, as also described. Figure 5 The method is set in [the context].

[0178] In this embodiment, the complementary arrangement of the first-stage coil and the second-stage coil in different metal layers better ensures the balance of the RF power amplifier.

[0179] In at least one embodiment, the first power combining unit includes a first primary coil and a second secondary coil coupled to each other, and the second power combining unit includes a second primary coil and a second secondary coil coupled to each other.

[0180] The first primary coil includes a first portion of the primary coil disposed on a first metal layer of the RF power amplifier chip and a second portion of the primary coil disposed on a second metal layer of the RF power amplifier chip, wherein the first portion of the primary coil and the second portion of the primary coil are longitudinally coupled.

[0181] The second primary coil includes a third primary coil disposed on the first metal layer of the RF power amplifier chip and a fourth primary coil disposed on the second metal layer of the RF power amplifier chip, wherein the third primary coil and the fourth primary coil are longitudinally coupled.

[0182] In this embodiment, the first primary coil includes a first portion of the primary coil disposed on the first metal layer and a second portion of the primary coil disposed on the second metal layer, and the first portion of the primary coil and the second portion of the primary coil are longitudinally coupled. The second primary coil includes a third portion of the primary coil disposed on the first metal layer of the RF power amplifier chip and a fourth portion of the primary coil disposed on the second metal layer of the RF power amplifier chip, and the third portion of the primary coil and the fourth portion of the primary coil are longitudinally coupled. In at least one embodiment, it is possible to achieve mutual cooperation with the secondary coil disposed on the two metal layers, thereby better ensuring the performance of the power amplifier.

[0183] In at least one embodiment, the RF power amplifier chip further includes a pre-stage driving circuit disposed in the region surrounded by the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array.

[0184] like Figure 7 As shown, the pre-stage driver circuit 90 is disposed within the area surrounded by the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array. The pre-stage driver circuit 90 is a radio frequency signal conversion circuit, for example, converting an unbalanced radio frequency signal into a balanced radio frequency signal, or a single-ended signal into a differential signal. Alternatively, the pre-stage driver circuit can be at least one stage of amplifier circuit.

[0185] Figure 8 The circuit diagram shown corresponds to Figure 1 The structure is such that one end of the first-stage coil is connected to the output signal terminal, and the other end is connected to one end of the second-stage coil, the other end of which is configured to be grounded.

[0186] Figure 9 The circuit diagram shown corresponds to Figure 2 The structure is such that one end of the first-stage coil is configured to be grounded, and the other end is connected to one end of the second-stage coil and configured to be connected to the output signal terminal, while the other end of the second-stage coil is configured to be grounded.

[0187] In at least one implementation, such as Figure 10As shown, the pre-stage drive circuit includes a first input transformer 50 and a second input transformer 60. The first end of the secondary coil of the first input transformer 50 is connected to the first transistor array 11, and the second end of the secondary coil of the first input transformer 50 is connected to the second transistor array 12. The first end of the secondary coil of the second input transformer 60 is connected to the third transistor array 21, and the second end of the secondary coil of the second input transformer 60 is connected to the fourth transistor array 22. Taking an NPN transistor array as an example, the first end of the secondary coil of the first input transformer 50 is connected to the base of the first transistor array 11, and the second end of the secondary coil of the first input transformer 50 is connected to the base of the second transistor array 12. The first end of the secondary coil of the second input transformer 60 is connected to the base of the third transistor array 21, and the second end of the secondary coil of the second input transformer 60 is connected to the base of the fourth transistor array 22. The emitters of the first transistor array 11, the second transistor array 12, the third transistor array 21, and the fourth transistor array 21 are all configured to be grounded. The collectors of the first transistor array 11 and the second transistor array 12 are respectively connected to the two ends of the first primary coil of the first power combining unit. The collectors of the third transistor array 21 and the fourth transistor array 22 are respectively connected to the two ends of the second primary coil of the second power combining unit.

[0188] In at least one embodiment, a first terminal of the primary coil of the first input transformer 50 receives an input radio frequency signal, a second terminal of the primary coil of the first input transformer 50 is connected to a first terminal of the second input transformer 60, and the second terminal of the second input transformer 60 is configured to be grounded. Optionally, a preamplifier circuit is further included, the input terminal of which is configured to receive the input radio frequency signal, and the output terminal is connected to the first terminal of the primary coil of the first input transformer 50.

[0189] In at least one implementation, such as Figure 11 As shown, the first terminal of the primary coil of the first input transformer 50 is configured to be grounded, the second terminal of the primary coil of the first input transformer 50 receives the input radio frequency signal, the first terminal of the second input transformer 60 receives the input radio frequency signal, and the second terminal of the second input transformer 60 is configured to be grounded. Optionally, a preamplifier circuit is also included, the input terminal of which is configured to receive the input radio frequency signal, and the output terminal is connected to the second terminal of the primary coil of the first input transformer 50 and the first terminal of the second input transformer 60.

[0190] In at least one implementation, such as Figure 12As shown, the first terminal of the primary coil of the first input transformer 50 is configured to be grounded, and the second terminal of the primary coil of the first input transformer 50 is connected to the output terminal of a preamplifier circuit. The first terminal of the second input transformer 60 is connected to the output terminal of another preamplifier circuit, and the second terminal of the second input transformer 60 is configured to be grounded.

[0191] In at least one implementation, such as Figure 13 As shown, the two ends of the secondary coil of the first input transformer 50 are connected to the fifth transistor array 71 and the sixth transistor array 72, respectively. The two ends of the secondary coil of the second input transformer 60 are connected to the seventh transistor array 81 and the eighth transistor array 82, respectively. It can be understood that the composition of the fifth transistor array 71, the sixth transistor array 72, the seventh transistor array 81, and the eighth transistor array 82 can be the same as that of the first transistor array described above, and will not be repeated here.

[0192] It is understood that the above embodiments may also include other circuit modules such as bias circuits, matching circuits, and power supply circuits, which will not be described in detail here.

[0193] In at least one embodiment, the RF power amplifier chip further includes a passive element network disposed in the region surrounded by the first power combining unit and the second power combining unit.

[0194] The passive component network is a network composed of at least one passive component, exemplarily a network composed of at least one of a resistor, capacitor, or inductor. In at least one embodiment, the passive component network is a network composed of at least one capacitor and at least one inductor. The passive component network is disposed in the region surrounded by the first power combining unit and the second power combining unit.

[0195] Optionally, the passive component network can be disposed in the space between the power combining unit and the corresponding transistor array. For example, it can be disposed in the region between the first transistor array, the second transistor array, and the second power combining unit. Alternatively, it can be disposed in the region between the third transistor array, the fourth transistor array, and the first power combining unit.

[0196] Optionally, the passive component network can be disposed in the space between two transistor arrays. Exemplarily, it can be disposed between the first transistor array and the second transistor array, or between the third transistor array and the fourth transistor array. Alternatively, it can be disposed between the second transistor array and the third transistor array. Or, it can be disposed between the first transistor array and the fourth transistor array.

[0197] Alternatively, the passive element network can be located inside the transistor array.

[0198] In at least one embodiment, the passive component network includes a first passive component unit and a second passive component unit, wherein the first passive component unit is disposed in the region between the first transistor array, the second transistor array and the second power combining unit, and the second passive component unit is disposed in the region between the third transistor array, the fourth transistor array and the first power combining unit.

[0199] like Figure 14 As shown, the passive component network includes a first passive component unit 110 and a second passive component unit 120. The first passive component unit 110 is disposed in the region between the first transistor array, the second transistor array, and the second power combining unit. The second passive component unit 120 is disposed in the region between the third transistor array, the fourth transistor array, and the first power combining unit.

[0200] In at least one embodiment, the first passive element unit 110 includes a first capacitor, a second capacitor, and a first inductor. One end of the first capacitor is connected to the output terminal of the first transistor array, the second end of the first capacitor is connected to the first end of the second capacitor, the second end of the second capacitor is connected to the output terminal of the second transistor array, the first end of the first inductor is connected to the second end of the first capacitor and the first end of the second capacitor, and the second end of the first inductor is configured to be grounded.

[0201] In at least one embodiment, the second passive unit 120 includes a third capacitor, a fourth capacitor, and a second inductor. One end of the third capacitor is connected to the output terminal of the first transistor array, the second end of the third capacitor is connected to the first end of the second capacitor, the second end of the fourth capacitor is connected to the output terminal of the second transistor array, the first end of the second inductor is connected to both the second end of the first capacitor and the first end of the fourth capacitor, and the second end of the second inductor is configured to be grounded.

[0202] In at least one embodiment, the passive element network includes a third passive unit, a fourth passive unit, a fifth passive unit, and a sixth passive unit, wherein the third passive unit is disposed between the first transistor array and the second transistor array, the fourth passive unit is disposed between the second transistor array and the third transistor array, the fifth passive unit is disposed between the third transistor array and the fourth transistor array, and the sixth passive unit is disposed between the fourth transistor array and the first transistor array.

[0203] Each of the aforementioned passive units can be connected to one of the transistor arrays to achieve network matching. In at least one embodiment, the third passive unit is connected to the first transistor array, the fourth passive unit is connected to the second transistor array, the fifth passive unit is connected to the third transistor array, and the sixth passive unit is connected to the fourth transistor array.

[0204] Further, one end of the third passive unit is connected to the output terminal of the first transistor array, and the other end is configured to be grounded. One end of the fourth passive unit is connected to the output terminal of the second transistor array, and the other end is configured to be grounded. One end of the fifth passive unit is connected to the output terminal of the third transistor array, and the other end is configured to be grounded. One end of the sixth passive unit is connected to the output terminal of the fourth transistor array, and the other end is configured to be grounded. In at least one embodiment, the third, fourth, fifth, and sixth passive units each include an inductor and a capacitor connected in series. In at least one embodiment, the third, fourth, fifth, and sixth passive units each include an inductor and a capacitor connected in series. One end of the capacitor is connected to the corresponding transistor array, and the second end of the capacitor is connected to the ground terminal via a bonding wire.

[0205] In at least one embodiment, the first power combining unit includes a first primary coil and a second secondary coil coupled to each other, a first end of the first primary coil being connected to the first transistor array, and a second end of the first primary coil being connected to the second transistor array.

[0206] The second power combining unit includes a second primary coil and a second secondary coil coupled to each other. The first end of the second primary coil is connected to the third transistor array, and the second end of the second primary coil is connected to the fourth transistor array.

[0207] In at least one embodiment, a first end of the first-stage coil is configured to be connected to a signal output terminal, a second end of the first-stage coil is connected to the first end of the second-stage coil, and a second end of the second-stage coil is configured to be grounded.

[0208] or,

[0209] The first end of the first-stage coil and the second end of the second-stage coil are configured to be connected to the signal output terminal, and the second end of the first-stage coil and the first end of the second-stage coil are configured to be grounded.

[0210] In at least one embodiment, the first transistor array, the second transistor array, and the first power combining unit are configured to amplify the power of the differential radio frequency signal, and the third transistor array, the fourth transistor array, and the second power combining unit are configured to amplify the power of the differential radio frequency signal.

[0211] At least one embodiment of the present invention provides an RF power amplifier chip, comprising:

[0212] The first power combining amplifier circuit includes a first amplification branch and a second amplification branch;

[0213] The second power combining amplifier circuit includes a third amplification branch and a fourth amplification branch;

[0214] The output transformer network is configured to receive the radio frequency signals output from the first amplification branch, the second amplification branch, the third amplification branch, and the fourth amplification branch, and then combine them before outputting them. The output transformer network is disposed on the outside of the chip and surrounds the first power combining amplifier circuit and the second power combining amplifier circuit.

[0215] The amplification branch may include a first transistor array, the second amplification branch may include a second transistor array, the third amplification branch may include a third transistor array, and the fourth amplification branch may include a fourth transistor array. The output transformer network includes a first output transformer and a second output transformer. One end of the primary coil of the first output transformer is connected to the output terminal of the first transistor array, and the other end of the primary coil of the first output transformer is connected to the output terminal of the second transistor array. One end of the primary coil of the second output transformer is connected to the output terminal of the third transistor array, and the other end of the primary coil of the second output transformer is connected to the output terminal of the fourth transistor array. Optionally, one end of the secondary coil of the first output transformer is configured to be connected to the output signal terminal, and the other end of the secondary coil of the first output transformer is connected to one end of the secondary coil of the second output transformer, and the other end of the secondary coil of the second output transformer is configured to be grounded. Optionally, one end of the secondary coil of the first output transformer is configured to be grounded, and the other end of the secondary coil of the first output transformer is connected to one end of the secondary coil of the second output transformer and configured to be connected to the output signal terminal, and the other end of the secondary coil of the second output transformer is configured to be grounded.

[0216] Understandably, the above-described output transformer network can be implemented using the first power combining unit and the second power combining unit in any of the above embodiments, and will not be described in detail here.

[0217] At least one embodiment of the present invention provides an RF power amplifier chip, comprising:

[0218] The first transistor array, the second transistor array, the third transistor array, and the fourth transistor array are distributed in four regions: a first side in the first direction, a second side in the first direction, a first side in the second direction, and a second side in the second direction, wherein the first direction and the second direction intersect.

[0219] A first power combining unit is disposed on a second side in the first direction and a second side in the second direction, and is configured to perform power combining on two transistor arrays among the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array;

[0220] The second power combining unit, disposed on the first side in the second direction and the first side in the first direction, is disposed on the outside of the chip and is configured to perform power combining on two other transistor arrays among the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array.

[0221] The first transistor array, the second transistor array, the third transistor array, and the fourth transistor array each select one region from four regions (the first side in the first direction, the second side in the first direction, the first side in the second direction, and the second side in the second direction).

[0222] For example, a first transistor array is disposed on a first side in a first direction, a second transistor array is disposed on a first side in a second direction, a third transistor array is disposed on a second side in the first direction, and a fourth transistor array is disposed on a second side in the second direction. Alternatively, the first transistor array is disposed on a first side in the first direction, the second transistor array is disposed on a second side in the first direction, the third transistor array is disposed on a first side in the second direction, and the fourth transistor array is disposed on a second side in the second direction. Or, the first transistor array is disposed on a second side in the first direction, the second transistor array is disposed on a second side in the second direction, the third transistor array is disposed on a first side in the first direction, and the fourth transistor array is disposed on a first side in the second direction.

[0223] A first power combining unit, disposed on a second side in the first direction and on a second side in the second direction, is configured to perform power combining on two transistor arrays among the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array; a second power combining unit, disposed on a first side in the second direction and on a first side in the first direction, is disposed on the outside of the chip, and is configured to perform power combining on the other two transistor arrays among the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array.

[0224] For example, if the first power combining unit is configured to perform power combining on the first transistor array and the second transistor array, then the second power combining unit is configured to perform power combining on the third transistor array and the fourth transistor array. If the first power combining unit is configured to perform power combining on the first transistor array and the third transistor array, then the second power combining unit is configured to perform power combining on the second transistor array and the fourth transistor array. If the first power combining unit is configured to perform power combining on the second transistor array and the third transistor array, then the second power combining unit is configured to perform power combining on the first transistor array and the fourth transistor array.

[0225] It is understood that the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array described above can be implemented using the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array in any of the above embodiments / implementations, and will not be described in detail here. Similarly, the first power combining unit and the second power combining unit described above can be implemented using the first power combining unit and the second power combining unit in any of the above embodiments / implementations, and will not be described in detail here.

[0226] In this embodiment, by rationally arranging the transistor array and the corresponding power combining unit, and distributing the four transistor arrays, the overall thermal resistance of the chip is reduced, thus ensuring the reliability of the chip.

[0227] In at least one embodiment, a first transistor array is disposed on a first side in a first direction, a second transistor array is disposed on a second side in the first direction, a first power combining unit is configured to perform power combining on the output signals of the first transistor array and the second transistor array; a third transistor array is disposed on a first side in the second direction, a fourth transistor array is disposed on a second side in the second direction, and a second power combining unit is configured to perform power combining on the output signals of the third transistor array and the fourth transistor array.

[0228] Optionally, the first power combining unit may be disposed in at least one of the four regions (the first side in the first direction, the second side in the first direction, the first side in the second direction, and the second side in the second direction), and the second power combining unit may be disposed in at least one of the four regions (the first side in the first direction, the second side in the first direction, the first side in the second direction, and the second side in the second direction).

[0229] In at least one embodiment, the first power combining unit may be disposed in two of the four regions, and the second power combining unit may be disposed in the other two regions of the four regions.

[0230] In at least one embodiment, the first power combining unit is configured to perform power combining on the output signals of the first transistor array and the second transistor array, and the second power combining unit is configured to perform power combining on the output signals of the third transistor array and the fourth transistor array.

[0231] The first transistor array, the second transistor array, and the first power combining unit are configured to amplify radio frequency signals in a first frequency band, and the third transistor array, the fourth transistor array, and the second power combining unit are configured to amplify radio frequency signals in a second frequency band.

[0232] The first frequency band and the second frequency band can be different frequency bands under the same communication standard (e.g., N41, N77, N79, etc.), or they can be different frequency bands under different communication standards (e.g., 3G, 4G, 5G, etc.).

[0233] In at least one embodiment, the first transistor array, the second transistor array, the third transistor array, the fourth transistor array, the first power combining unit, and the second power combining unit are configured to operate in a first operating mode, and the first transistor array, the second transistor array, and the first power combining unit are configured to operate in a second operating mode. The first operating mode can be a higher power operating mode than the second operating mode.

[0234] At least one embodiment of the present invention provides an RF power amplifier chip, comprising:

[0235] A first transistor array is disposed on a first side of a first virtual rectangular region in a first direction;

[0236] A second transistor array is disposed on a first side of the first virtual rectangular region in a second direction, wherein the first direction and the second direction intersect.

[0237] A first transformer structure is disposed on the second side of the first virtual rectangular region in the first direction and the second side of the first virtual rectangular region in the second direction, including a first primary coil and a second secondary coil coupled to each other, the first end of the first primary coil being connected to the first transistor array, and the second end of the first primary coil being connected to the second transistor array.

[0238] like Figure 15As shown, a first transistor array 11 is disposed on a first side of a first virtual rectangular region 100 in a first direction. A second transistor array 12 is disposed on a first side of the first virtual rectangular region 100 in a second direction, the first direction and the second direction intersecting.

[0239] A first transformer structure is disposed on the second side of the first virtual rectangular region in the first direction and on the second side of the first virtual rectangular region in the second direction. It includes a first primary coil and a second secondary coil coupled to each other. A first end of the first primary coil is connected to the first transistor array, and a second end of the first primary coil is connected to the second transistor array. Understandably, the first transformer structure can be implemented using the first power combining unit 30 in any of the above embodiments, and will not be elaborated further here. The first virtual rectangular region 100 can be any approximately rectangular region in the chip.

[0240] In this embodiment, by rationally setting and arranging the first transistor array 11, the second transistor array 12 and the first transformer structure, the chip space is well utilized. In scenarios where the transistor arrays are close together and the transformer structure requires a large inductance value, the additional space required for the transformer structure to be wound separately can be avoided, thereby improving the overall integration of the chip.

[0241] In at least one embodiment, the RF power amplifier chip further includes a third transistor array disposed on a second side in the first direction;

[0242] A fourth transistor array is disposed on the second side of the first virtual rectangular region in the second direction;

[0243] The second transformer structure is disposed on the first side of the first virtual rectangular region in the second direction and the first side of the first virtual rectangular region in the first direction, including a second primary coil and a second secondary coil coupled to each other. The first end of the second primary coil is connected to the third transistor array, and the second end of the second primary coil is connected to the fourth transistor array.

[0244] Understandably, the second transformer structure can be implemented by the second power combining unit 40 in any of the above embodiments, and will not be described in detail here.

[0245] At least one embodiment of the present invention provides a radio frequency front-end module, including a radio frequency power amplifier chip as described in any of the above embodiments / implementations.

[0246] At least one embodiment of the present invention provides a radio frequency front-end module, including a substrate and a radio frequency power amplifier chip disposed on the substrate. The radio frequency power amplifier chip includes a first transistor array, a second transistor array, a third transistor array, and a fourth transistor array, which are distributed in four regions: a first side of the radio frequency power amplifier chip in a first direction, a second side of the radio frequency power amplifier chip in a first direction, a first side of the radio frequency power amplifier chip in a second direction, and a second side of the radio frequency power amplifier chip in a second direction. The first direction and the second direction intersect.

[0247] The radio frequency front-end module also includes a first transformer structure and a second transformer structure disposed on a substrate, the first transformer structure and the second transformer structure being arranged around the first transistor array, the second transistor array, the third transistor array and the fourth transistor array.

[0248] Understandably, the specific configuration of the first transformer structure in this embodiment can be implemented by the first synthesis unit in any of the above embodiments / implementations, the difference being that the first transformer structure is disposed on the substrate. Similarly, the specific configuration of the second transformer structure in this embodiment can be implemented by the second synthesis unit in any of the above embodiments / implementations, the difference being that the second transformer structure is disposed on the substrate.

[0249] At least one embodiment of the present invention provides an electronic device including a radio frequency front-end module as described in any of the above embodiments / implementations.

[0250] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of this application, and these improvements and substitutions should also be considered within the scope of protection of this application.

Claims

1. A radio frequency power amplifier chip, characterized in that, include: A first transistor array is disposed on a first side in a first direction; A second transistor array is disposed on a first side in a second direction, wherein the first direction and the second direction intersect; A first power combining unit is disposed on a second side in the first direction and a second side in the second direction, and is configured to perform power combining on the output signals of the first transistor array and the second transistor array. The first power combining unit includes a first primary coil and a second secondary coil coupled to each other. A first end of the first primary coil is connected to the first transistor array, and a second end of the first primary coil is connected to the second transistor array. A third transistor array is disposed on the second side in the first direction; A fourth transistor array is disposed on the second side in the second direction; The second power combining unit, disposed on the first side in the second direction and the first side in the first direction, is configured to perform power combining on the output signals of the third transistor array and the fourth transistor array. The second power combining unit includes a second primary coil and a second secondary coil coupled to each other. The first end of the second primary coil is connected to the third transistor array, and the second end of the second primary coil is connected to the fourth transistor array.

2. The RF power amplifier chip according to claim 1, characterized in that, The portion of the first transistor array disposed on the first side in the first direction relative to the second power combining unit is closer to the second side in the first direction, and the portion of the second transistor array disposed on the first side in the second direction relative to the second power combining unit is closer to the second side in the second direction. And / or, The portion of the third transistor array disposed on the second side of the first power combining unit in the first direction is closer to the first side in the first direction, and the portion of the fourth transistor array disposed on the second side of the first power combining unit in the second direction is closer to the first side in the second direction.

3. The RF power amplifier chip according to claim 1, characterized in that, The first direction is perpendicular to the second direction.

4. The RF power amplifier chip according to claim 1, characterized in that, The first power combining unit and the second power combining unit are disposed on the outside of the radio frequency power amplifier chip.

5. The RF power amplifier chip according to claim 1, characterized in that, The portion of the second power combining unit disposed on the first side in the first direction is closer to the second side in the first direction relative to the first transistor array; the portion of the second power combining unit disposed on the first side in the second direction is closer to the second side in the second direction relative to the second transistor array; the portion of the third transistor array is closer to the first side in the first direction relative to the portion of the first power combining unit disposed on the second side in the first direction; and the portion of the fourth transistor array is closer to the first side in the second direction relative to the portion of the first power combining unit disposed on the second side in the second direction. or, The portion of the first power combining unit disposed on the second side in the first direction is closer to the first side in the first direction relative to the third transistor array. The portion of the first power combining unit disposed on the second side in the second direction is closer to the first side in the second direction relative to the fourth transistor array. The first transistor array is closer to the second side in the first direction relative to the portion of the second power combining unit disposed on the first side in the first direction. The second transistor array is closer to the second side in the second direction relative to the portion of the second power combining unit disposed on the first side in the second direction.

6. The RF power amplifier chip according to claim 1, characterized in that, The first primary coil includes a first primary sub-coil and a second primary sub-coil, and the first primary coil includes a first secondary sub-coil and a second secondary sub-coil; the first primary sub-coil and the first secondary sub-coil are coupled to each other and disposed on a second side in the first direction; the second primary sub-coil and the second secondary sub-coil are coupled to each other and disposed on a second side in the second direction. The second primary coil includes a third primary sub-coil and a fourth primary sub-coil, and the second secondary coil includes a third secondary sub-coil and a fourth secondary sub-coil; the third primary sub-coil and the third secondary sub-coil are coupled to each other and are disposed on a first side in the first direction; the fourth primary sub-coil and the fourth secondary sub-coil are coupled to each other and are disposed on a first side in the second direction.

7. The RF power amplifier chip according to claim 6, characterized in that, The first primary sub-coil is closer to the first side in the first direction than the first primary sub-coil; the second primary sub-coil is closer to the first side in the second direction than the second primary sub-coil; the third primary sub-coil is closer to the second side in the first direction than the third primary sub-coil; and the fourth primary sub-coil is closer to the second side in the second direction than the fourth secondary sub-coil. or, The first primary sub-coil is closer to the first side in the first direction than the first primary sub-coil, the second primary sub-coil is closer to the first side in the second direction than the second primary sub-coil, the third primary sub-coil is closer to the second side in the first direction than the third primary sub-coil, and the fourth secondary sub-coil is closer to the second side in the second direction than the fourth primary sub-coil.

8. The RF power amplifier chip according to claim 1, characterized in that, The first primary coil includes a first outer primary coil and a first inner primary coil, the second primary coil includes a second outer primary coil and a second inner primary coil, and the first secondary coil includes a first portion of secondary coil disposed between the first outer primary coil and the first inner primary coil, and a second portion of secondary coil disposed between the second outer primary coil and the second inner primary coil, wherein the first portion of secondary coil and the second portion of secondary coil are connected in series.

9. The RF power amplifier chip according to claim 8, characterized in that, The first primary coil also includes a third secondary coil disposed inside the first primary coil, and the second secondary coil also includes a fourth secondary coil disposed inside the second primary coil. The first secondary coil, the third secondary coil, the second secondary coil and the fourth secondary coil are connected in series in sequence.

10. The radio frequency power amplifier chip according to claim 1, characterized in that, The first secondary coil includes a first part of the secondary coil disposed on the first metal layer of the RF power amplifier chip and a second part of the secondary coil disposed on the second metal layer of the RF power amplifier chip. The second secondary coil includes a third part of the secondary coil disposed on the first metal layer of the RF power amplifier chip and a fourth part of the secondary coil disposed on the second metal layer of the RF power amplifier chip. One end of the first secondary coil is configured to be connected to the signal output terminal, and one end of the third secondary coil is configured to be grounded. The first secondary coil and the third secondary coil are connected in series. One end of the second secondary coil is configured to be connected to the signal output terminal, and one end of the fourth secondary coil is configured to be grounded. The second secondary coil and the fourth secondary coil are connected in series. The coil from the end of the first secondary coil connected to the signal output terminal to the end of the third secondary coil configured to be grounded is wound in a first manner from the outer layer to the inner layer; the coil from the end of the second secondary coil connected to the signal output terminal to the end of the fourth secondary coil configured to be grounded is wound in a first manner from the inner layer to the outer layer; or, the coil from the end of the first secondary coil connected to the signal output terminal to the end of the third secondary coil configured to be grounded is wound in a first manner from the inner layer to the outer layer; the coil from the end of the second secondary coil connected to the signal output terminal to the end of the fourth secondary coil configured to be grounded is wound in a first manner from the outer layer to the inner layer, wherein the first manner is clockwise or counterclockwise.

11. The RF power amplifier chip according to claim 1, characterized in that, The first primary coil includes a first portion of the primary coil disposed on a first metal layer of the RF power amplifier chip and a second portion of the primary coil disposed on a second metal layer of the RF power amplifier chip, wherein the first portion of the primary coil and the second portion of the primary coil are longitudinally coupled. The second primary coil includes a third primary coil disposed on the first metal layer of the RF power amplifier chip and a fourth primary coil disposed on the second metal layer of the RF power amplifier chip, wherein the third primary coil and the fourth primary coil are longitudinally coupled.

12. The RF power amplifier chip according to claim 1, characterized in that, It also includes a pre-stage driving circuit, which is disposed in the area surrounded by the first transistor array, the second transistor array, the third transistor array and the fourth transistor array.

13. The RF power amplifier chip according to claim 1, characterized in that, It also includes a passive component network disposed in the area surrounded by the first power combining unit and the second power combining unit.

14. The RF power amplifier chip according to claim 13, characterized in that, The passive component network includes a first passive component unit and a second passive component unit. The first passive component unit is disposed in the region between the first transistor array, the second transistor array, and the second power combining unit. The second passive component unit is disposed in the region between the third transistor array, the fourth transistor array, and the first power combining unit.

15. The RF power amplifier chip according to claim 1, characterized in that, The first end of the first-stage coil is configured to be connected to the signal output terminal, the second end of the first-stage coil is connected to the first end of the second-stage coil, and the second end of the second-stage coil is configured to be grounded; or, The first end of the first-stage coil and the second end of the second-stage coil are configured to be connected to the signal output terminal, and the second end of the first-stage coil and the first end of the second-stage coil are configured to be grounded.

16. The RF power amplifier chip according to claim 1, characterized in that, The first transistor array, the second transistor array, and the first power combining unit are configured to amplify the power of the differential radio frequency signal, and the third transistor array, the fourth transistor array, and the second power combining unit are configured to amplify the power of the differential radio frequency signal.

17. The RF power amplifier chip according to claim 4, characterized in that, The first power combining unit and the second power combining unit are at least partially disposed in the contact metal layer of the chip, the contact metal layer being disposed adjacent to the substrate of the chip.

18. A radio frequency power amplifier chip, characterized in that, include: A first transistor array is disposed on a first side of a first virtual rectangular region in a first direction; A second transistor array is disposed on a first side of the first virtual rectangular region in a second direction, wherein the first direction and the second direction intersect. A first transformer structure is disposed on the second side of the first virtual rectangular region in the first direction and the second side of the first virtual rectangular region in the second direction, including a first primary coil and a second secondary coil coupled to each other, the first end of the first primary coil being connected to the first transistor array, and the second end of the first primary coil being connected to the second transistor array.

19. The RF power amplifier chip according to claim 18, characterized in that, Also includes: A third transistor array is disposed on the second side in the first direction; A fourth transistor array is disposed on the second side of the first virtual rectangular region in the second direction; The second transformer structure is disposed on the first side of the first virtual rectangular region in the second direction and the first side of the first virtual rectangular region in the first direction, including a second primary coil and a second secondary coil coupled to each other. The first end of the second primary coil is connected to the third transistor array, and the second end of the second primary coil is connected to the fourth transistor array.

20. A radio frequency front-end module, characterized in that, Includes the radio frequency power amplifier chip as described in any one of claims 1-19.

21. An electronic device, characterized in that, Includes the radio frequency front-end module as described in claim 20.

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