Low additional phase shift amplitude control circuit
By combining a variable gain amplifier and a bridge differential passive attenuator and setting a symmetric inductor therebetween, the problem of the traditional amplitude phase control module being too large for large attenuation is solved, achieving the effect of low additional phase shift and compact area.
Patent Information
- Application Number
- CN202411975037.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-05-09
AI Technical Summary
The traditional amplitude phase control module has the problem of excessive additional phase shift when achieving large attenuation, and conventional attenuators require cascaded multiple attenuation units, which increases area and through-through losses.
A low additional phase shift amplitude control circuit is adopted, combined with a variable gain amplifier and a bridge differential passive attenuator, and a symmetric inductor is set between them to achieve low additional phase shift and impedance matching, while controlling the attenuation amount through a CNC signal.
Maintaining low additional phase shift in the large attenuation state reduces circuit area, reduces through-through losses, and simplifies circuit structure and reduces complexity.
Smart Images
Figure CN119966378A_ABST
Abstract
Description
Technical Field
[0001] The present specification relates to the technical field of amplitude control circuits, and in particular to a low additional phase shift amplitude control circuit. Background Art
[0002] With the increasing development of millimeter wave technology and the continuous increase in operating frequency, phased array technology is increasingly being used in military radar, autonomous driving, wireless communications and other fields. By adjusting the amplitude and phase of each antenna element in the array, electronic scanning can be achieved and the signal strength can be enhanced in a specific direction, improving the flexibility and directivity of the detection signal.
[0003] The amplitude control module is an essential component of phased array technology. Usually, the amplitude control is mainly achieved through a variable gain amplifier (VGA) and an attenuator (ATT). Among them, the variable gain amplifier can achieve amplitude control while having gain. Its working principle is to control the conduction and shutdown of the common-gate tube to control whether the current flows through the load, thereby changing the gain. Compared with the variable gain amplifier, the attenuator has the advantages of low power consumption and high linearity. Its working principle is to use transistor switches to construct low-loss signal paths and high-loss signal paths, and use control signals to switch the attenuation gear.
[0004] However, the additional phase shift of the variable gain amplifier when achieving large attenuation is too large, thus limiting its application under large attenuation. In addition, the conventional attenuator requires cascading multiple attenuation units, which increases the area and direct loss. Summary of the invention
[0005] The purpose of this specification is to provide a low additional phase shift amplitude control circuit, which can solve the problem of excessive additional phase shift when a traditional amplitude-phase control module achieves large attenuation.
[0006] The embodiments of this specification are implemented as follows:
[0007] A low additional phase shift amplitude control circuit includes a variable gain amplifier and a bridge differential passive attenuator;
[0008] The output end of the variable gain amplifier is connected to the bridge-type differential passive attenuator, and a first symmetrical inductor is arranged in parallel between the output end of the variable gain amplifier and the bridge-type differential passive attenuator;
[0009] A second symmetrical inductor is arranged in parallel between the output ends of the bridge differential passive attenuator, and the center taps of the first symmetrical inductor and the second symmetrical inductor are both connected to the power supply voltage;
[0010] The attenuation amounts of the variable gain amplifier and the bridge differential passive attenuator are respectively configured according to an attenuation control signal so that an additional phase shift during attenuation of the variable gain amplifier can be offset by an additional phase shift during attenuation of the bridge differential passive attenuator.
[0011] The embodiments of this specification have at least the following advantages or beneficial effects:
[0012] Compared with the prior art, the low additional phase shift amplitude control circuit can still have the advantage of low additional phase shift in a large attenuation state by combining a variable gain amplifier and a bridge differential passive attenuator. Moreover, by setting a first symmetrical inductor between the variable gain amplifier and the bridge differential passive attenuator, DC power supply and impedance matching can be achieved. By setting a second symmetrical inductor in parallel at the output end of the bridge differential passive attenuator to provide a power supply voltage bias, and then setting a DC blocking capacitor in series to block the DC, impedance matching with the subsequent circuit can be achieved at the same time. In addition, the amplitude control circuit can be made compact by combining a variable gain amplifier and a bridge differential passive attenuator, thereby achieving the effect of reducing the circuit area, that is, there is no need to cascade multiple attenuation units, and the direct-through loss can also be effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present specification and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.
[0014] Figure 1 A schematic diagram of the structure of the low additional phase shift amplitude control circuit provided in this specification;
[0015] Figure 2 This is a schematic diagram of the structure of the variable gain amplifier provided in this specification. DETAILED DESCRIPTION
[0016] In order to make the purpose, technical solutions and advantages of the embodiments of this specification more clear, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are part of the embodiments of this specification, not all of the embodiments. Generally, the components of the embodiments of this specification described and shown in the drawings here can be arranged and designed in various different configurations.
[0017] Therefore, the following detailed description of the embodiments of the present specification provided in the accompanying drawings is not intended to limit the scope of the present specification claimed for protection, but merely represents selected embodiments of the present specification. Based on the embodiments in the present specification, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present specification.
[0018] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.
[0019] In the description of the embodiments of this specification, it should be noted that if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, or the orientation or position relationship in which the product of this specification is usually placed when used. It is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this specification. In addition, if the terms "first", "second", "third", etc. appear, they are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0020] In addition, the use of terms such as "horizontal", "vertical", and "overhanging" does not mean that the components must be absolutely horizontal or overhanging, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0021] In the description of the embodiments of this specification, it is also necessary to explain that, unless otherwise clearly specified and limited, the words "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be fixedly connected, detachably connected, or integrally connected; it can be mechanically connected or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or it can be internal communication between two components. For ordinary technicians in this field, the specific meanings of the above terms in this specification can be understood according to specific circumstances.
[0022] Please refer to Figure 1 and Figure 2 , a low additional phase shift amplitude control circuit provided by an embodiment of the present specification mainly includes a variable gain amplifier and a bridge differential passive attenuator;
[0023] The output end of the variable gain amplifier is connected to the bridge-type differential passive attenuator, and a first symmetrical inductor is arranged in parallel between the output end of the variable gain amplifier and the bridge-type differential passive attenuator;
[0024] A second symmetrical inductor is arranged in parallel between the output ends of the bridge differential passive attenuator, and the center taps of the first symmetrical inductor and the second symmetrical inductor are both connected to the power supply voltage;
[0025] The attenuation amounts of the variable gain amplifier and the bridge differential passive attenuator are respectively configured according to an attenuation control signal so that an additional phase shift during attenuation of the variable gain amplifier can be offset by an additional phase shift during attenuation of the bridge differential passive attenuator.
[0026] In this embodiment, a DC blocking capacitor is connected in series to the output end of the bridge differential passive attenuator.
[0027] In this embodiment, the attenuation control signal is a digital control signal, so that the amplitude control circuit does not need an additional analog control voltage generating circuit, thereby effectively reducing the complexity of the circuit.
[0028] In this embodiment, the attenuation of the variable gain amplifier and the bridge differential passive attenuator can be controlled respectively through the control action of the attenuation control signal, so that the negative additional phase shift that increases continuously during attenuation of the variable gain amplifier can offset the positive additional phase shift that increases continuously during attenuation of the bridge differential passive attenuator, thereby making the additional phase shift of the amplitude control circuit lower.
[0029] It can be seen that the amplitude control circuit can still have the advantage of low additional phase shift in a large attenuation state by combining a variable gain amplifier and a bridge differential passive attenuator. Moreover, by setting a first symmetrical inductor between the variable gain amplifier and the bridge differential passive attenuator, DC power supply and impedance matching can be achieved. By setting a second symmetrical inductor in parallel at the output end of the bridge differential passive attenuator to provide a power supply voltage bias, and then setting a DC blocking capacitor in series to block the DC, impedance matching with the subsequent circuit can be achieved at the same time. In addition, the amplitude control circuit can be made compact in area by combining a variable gain amplifier and a bridge differential passive attenuator, thereby achieving the effect of reducing the circuit area, that is, there is no need to cascade multiple attenuation units, and the direct-through loss can be effectively reduced. In this embodiment, the variable gain amplifier includes a common source tube M1, a common source tube M2, a common gate tube M3 group, a common gate tube M4 group, a common gate tube M5 group and a common gate tube M6 group;
[0030] The source of the common source transistor M1 and the source of the common source transistor M2 are grounded, and the gate of the common source transistor M1 and the gate of the common source transistor M2 can input signals respectively;
[0031] The source of the common-gate transistor M3 group and the source of the common-gate transistor M4 group are connected to the drain of the common-source transistor M1, and the source of the common-gate transistor M5 group and the source of the common-gate transistor M6 group are connected to the drain of the common-source transistor M2;
[0032] The gate of the common-gate transistor M3 group and the gate of the common-gate transistor M6 group are connected to the power supply voltage, and the gate of the common-gate transistor M4 group and the gate of the common-gate transistor M5 group can input the first attenuation control signal;
[0033] The drain of the common-gate tube M3 group is connected to the drain of the common-gate tube M5 group, and the common connection end of the drain of the common-gate tube M3 group and the drain of the common-gate tube M5 group is the positive output end of the variable gain amplifier. The drain of the common-gate tube M4 group is connected to the drain of the common-gate tube M6 group, and the common connection end of the drain of the common-gate tube M4 group and the drain of the common-gate tube M6 group is the negative output end of the variable gain amplifier.
[0034] In this embodiment, when the first attenuation control signal VC1 is at a low level, all the currents generated by the common source tubes M1 and M2 flow outward through the load through the common gate tube group M3 and the common gate tube group M6. At this time, the gain of the variable gain amplifier is the highest and there is no signal attenuation. The number of common gate tubes in the common gate tube group M4 and the common gate tube group M5 that are turned on is increased by controlling the first attenuation control signal VC1, and the current that originally flows through the load is continuously diverted to the ground, and the gain is continuously reduced. When the first attenuation control signal VC1 is all at a high level, the attenuation of the variable gain amplifier is the largest.
[0035] In this embodiment, a first inductor Ind1 is provided between the common end connecting the source of the common gate transistor M3 group and the source of the common source transistor M4 group and the drain of the common source transistor M1, and a second inductor Ind2 is provided between the common end connecting the source of the common gate transistor M5 group and the source of the common source transistor M6 group and the drain of the common source transistor M2. The gain can be improved by the above-mentioned arrangement.
[0036] In this embodiment, the gate of the common source transistor M1 and the gate of the common source transistor M2 are respectively provided with bias resistors, that is, a DC bias voltage VB can be provided through the bias resistor RB.
[0037] In this embodiment, the common-gate transistor M3 group includes a plurality of common-gate transistors M3 arranged in parallel, the common-gate transistor M4 group includes a plurality of common-gate transistors M4 arranged in parallel, the common-gate transistor M5 group includes a plurality of common-gate transistors M5 arranged in parallel, and the common-gate transistor M6 group includes a plurality of common-gate transistors M6 arranged in parallel;
[0038] The number of the common-gate tubes M3, the number of the common-gate tubes M4, the number of the common-gate tubes M5 and the number of the common-gate tubes M6 are consistent;
[0039] At least two of the common-gate transistors M3 in the common-gate transistor group M3 have different sizes, and the common-gate transistor group M3, the common-gate transistor group M4, the common-gate transistor group M5 and the common-gate transistor group M6 have the same sizes.
[0040] In this embodiment, the common-gate transistor M3 group is represented by common-gate transistor M3<3:0>, that is, it includes M3 <0> 、M3 <1> 、M3 <2> and M3 <4> Four common-gate tubes, and M3 <0> :M3 <1> :M3 <2> :M3 <4> The size ratio is 1:1:2:4, which can increase the conduction form of the common-gate tube, facilitate flexible adjustment of the attenuation, and also make the adjustment range of the attenuation larger and the adjustment accuracy higher.
[0041] In other embodiments, the size of each common-grid tube may be specifically set according to the setting accuracy and range of the attenuation amount.
[0042] In this embodiment, the common-gate transistor M4 group is represented by the common-gate transistor M4<3:0>, the common-gate transistor M5 group is represented by the common-gate transistor M5<3:0>, and the common-gate transistor M6 group is represented by the common-gate transistor M6<3:0>, and the first attenuation control signal is VC1<3:0>. The first attenuation control signal controls each common-gate transistor, that is, the first attenuation control signal VC1<3:0>. <0> Corresponding control M3 <0> 、M4 <0> 、M5 <0> and M6 <0> The conduction state.
[0043] When in use, the first attenuation control signal VC1<3:0> corresponds to controlling the number of common-gate transistors M4<3:0> and M5<3:0> to be turned on, and the current originally flowing through the load is continuously diverted to the ground, and the gain is continuously reduced. When the first attenuation control signal VC1<3:0> is all high level, the attenuation of the variable gain amplifier is the largest. When the first attenuation control signal VC1<3:0> is all low level, the current generated by the common-source transistors M1 and M2 all flows outward through the load through the common-gate transistors M3<3:0> and M6<3:0>. At this time, the gain of the variable gain amplifier is the highest, and there is no signal attenuation.
[0044] It can be seen that by arranging multiple common-gate tubes in parallel, the area of the amplitude and phase control circuit can be further made compact, the attenuation range and attenuation accuracy can be effectively increased, and the circuit complexity is relatively low.
[0045] In this embodiment, the variable gain amplifier has a positive output port and a negative output port, and the bridge differential passive attenuator includes a PMOS transistor M7 group, a PMOS transistor M8 group, a PMOS transistor M9 group and a PMOS transistor M10 group;
[0046] The gate of the PMOS transistor M7 group and the gate of the PMOS transistor M10 group are connected to the ground respectively, and the gate of the PMOS transistor M8 group and the gate of the PMOS transistor M9 group can input the second attenuation control signal respectively;
[0047] The PMOS transistor M7 group is arranged between the positive output port and the differential output positive terminal of the bridge differential passive attenuator, the PMOS transistor M8 group is connected between the positive output port and the differential negative terminal of the bridge differential passive attenuator, the PMOS transistor M9 group is arranged between the negative output port and the differential output positive terminal of the bridge differential passive attenuator, and the PMOS transistor M10 group is connected between the negative output port and the differential negative terminal of the bridge differential passive attenuator.
[0048] In this embodiment, the positive output port is VGA_OUTP, the negative output port is VGA_OUTN, the positive differential output terminal is Voutp, and the negative differential output terminal is Voutn. The input terminals of the variable gain amplifier are Vinp and Vinn respectively.
[0049] In this embodiment, the PMOS transistor M7 group includes a plurality of P-type transistors M7 connected in parallel, the PMOS transistor M8 group includes a plurality of P-type transistors M8 connected in parallel, the PMOS transistor M9 group includes a plurality of P-type transistors M9 connected in parallel, and the PMOS transistor M10 group includes a plurality of P-type transistors M10 connected in parallel;
[0050] The number of the P-type tube M7, the P-type tube M8, the P-type tube M9 and the P-type tube M10 is the same;
[0051] At least two of the P-type transistors M7 in the PMOS transistor M7 group have different sizes, and the sizes of the PMOS transistor M7 group, the PMOS transistor M8 group, the PMOS transistor M9 group, and the PMOS transistor M10 group are consistent.
[0052] In this embodiment, the PMOS transistor M7 group can be represented as a P-type transistor M7<3:0>, including M7 <0> 、M7 <1> 、M7<2>、M7 <3> The PMOS transistor M8 group can be represented as a P-type transistor M8<3:0>, the PMOS transistor M9 group can be represented as a P-type transistor M9<3:0>, and the PMOS transistor M10 group can be represented as a P-type transistor M10<3:0>.
[0053] In this embodiment, the second attenuation control signal is VC2<3:0>, and the second attenuation control signal VC2<3:0> corresponds to controlling M7<3:0>, M8<3:0>, M9<3:0> and M10<3:0>.
[0054] The second attenuation control signal VC2 <0> For example, it can control M7 <0> 、M8 <0> 、M9 <0> and M10 <0> The conduction state.
[0055] In this embodiment, the P-type transistor M7<3:0> and the P-type transistor M10<3:0> are in a constant conduction state.
[0056] In this embodiment, the sizes of the P-type tube M7<3:0>, the P-type tube M8<3:0>, the P-type tube M9<3:0> and the P-type tube M10<3:0> are consistent, and M7<3:0> <0> 、M7 <1> 、M7 <2> 、M7 <3> The size ratio can be preferably 1: 1: 2: 4. The above setting can facilitate the flexible adjustment of the attenuation, and at the same time, the adjustment range of the attenuation can be larger and the adjustment accuracy can be higher.
[0057] In other embodiments, the size of each P-type tube may be specifically set according to the setting accuracy and range of the attenuation amount.
[0058] In detail, each of the above-mentioned PMOS transistor groups is arranged in an array form (i.e., is arranged in parallel) to avoid the use of an analog second attenuation control signal, so that the above-mentioned second attenuation control signal can adopt a digital control signal without the need for an additional analog control voltage generating circuit, thereby achieving the effect of effectively reducing the complexity of the above-mentioned amplitude and phase control circuit.
[0059] In this embodiment, the first symmetrical inductor Ind3 is connected between the above-mentioned positive output port (VGA_OUTP) and the above-mentioned negative output port (VGA_OUTN), and the center tap of the first symmetrical inductor Ind3 is connected to the power supply voltage VDD, which can not only power the above-mentioned variable gain amplifier, but also provide good switching characteristics for the P-type tube of the above-mentioned bridge differential passive attenuator, and can also be used for impedance matching.
[0060] In this embodiment, the second symmetrical inductor Ind4 is connected between the above-mentioned differential output positive terminal (Voutp) and the above-mentioned differential output negative terminal (Voutn), and the center tap of the second symmetrical inductor Ind4 is connected to the power supply voltage VDD, which can further provide good switching characteristics for the P-type tube of the above-mentioned bridge differential passive attenuator.
[0061] In this embodiment, the DC blocking capacitors are a DC blocking capacitor C1 and a DC blocking capacitor C2, which are respectively connected in series to the differential output positive terminal (Voutp) and the differential output negative terminal (Voutn), and cooperate with the second symmetrical inductor to achieve impedance matching with the subsequent circuit.
[0062] Specifically, when the signal is attenuated by 0 dB, the second attenuation control signal VC2<3:0> is all connected to a high level, and the P-type tubes M8<3:0> and M9<3:0> are all turned off. Since the P-type tubes M7<3:0> and M10<3:0> are always turned on, the attenuation is the smallest at this time. The attenuation can be increased by appropriately increasing the number of P-type tubes M8<3:0> and M9<3:0> that are turned on. When the number of P-type tubes M8<3:0> and M9<3:0> that are turned on is the same as that of P-type tubes M7<3:0> and M10<3:0>, the attenuation is the largest.
[0063] In this embodiment, the gate of the PMOS transistor M7 group and the gate of the PMOS transistor M10 group are connected to the ground through the first resistor group and the fourth resistor group, respectively, and the gate of the PMOS transistor M8 group and the gate of the PMOS transistor M9 group can be connected to the input port of the second attenuation control signal through the second resistor group and the third resistor group, respectively.
[0064] In this embodiment, the first resistor group includes multiple parallel resistors R1, the second resistor group includes multiple parallel resistors R2, the third resistor group includes multiple parallel resistors R3, and the fourth resistor group includes multiple parallel resistors R4. The number of resistors in the first resistor group, the second resistor group, the third resistor group, and the fourth resistor group is consistent with the number of P-type tubes M8.
[0065] In this embodiment, the first resistor group is R1<3:0>, including R1 <0> 、R1 <1> 、R1 <2> and R1 <3> The second resistor group is R2<3:0>, the third resistor group is R3<3:0>, and the fourth resistor group is R4<3:0>.
[0066] In summary, the first attenuation control signal VC1<3:0> can control the attenuation of the variable gain amplifier, the second attenuation controller VC2<3:0> controls the attenuation of the bridge differential passive attenuator, the variable gain amplifier adds a negative phase shift while attenuating, and the bridge differential passive attenuator adds a positive phase shift while attenuating. By reasonably configuring the first attenuation control signal VCl<3:0> and the second attenuation controller VC2<3:0>, not only can the additional phase shift be offset, but also the attenuation range can be effectively expanded and the attenuation accuracy can be improved. The configuration of the first attenuation control signal VC1<3:0> and the second attenuation controller VC2<3:0> can be illustrated by an example: the first attenuation control signal VC1<3:0> controls the attenuation of the variable gain amplifier to be a first preset attenuation, and the second attenuation controller VC2<3:0> can control the attenuation of the bridge differential passive attenuator to be a second preset attenuation, and the sum of the first preset attenuation and the second preset attenuation is the total preset attenuation, and by setting the first preset attenuation and the second preset attenuation, the additional phase shift can be offset, so that the attenuation meets the expected requirements while the additional phase shift is minimized.
[0067] The above are only preferred embodiments of this specification and are not intended to limit this specification. For those skilled in the art, this specification may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this specification shall be included in the protection scope of this specification.
Claims
1. A low additional phase shift amplitude control circuit, characterized in that: Includes a variable gain amplifier and a bridge differential passive attenuator; The output end of the variable gain amplifier is connected to the bridge-type differential passive attenuator, and a first symmetrical inductor is arranged in parallel between the output end of the variable gain amplifier and the bridge-type differential passive attenuator; A second symmetrical inductor is arranged in parallel between the output ends of the bridge differential passive attenuator, and the center taps of the first symmetrical inductor and the second symmetrical inductor are both connected to the power supply voltage; The attenuation amounts of the variable gain amplifier and the bridge differential passive attenuator are respectively configured according to an attenuation control signal so that an additional phase shift during attenuation of the variable gain amplifier can be offset by an additional phase shift during attenuation of the bridge differential passive attenuator.
2. The low additional phase shift amplitude control circuit according to claim 1, characterized in that: The output end of the bridge type differential passive attenuator is provided with a DC blocking capacitor in series.
3. The low additional phase shift amplitude control circuit according to claim 1, characterized in that: The variable gain amplifier includes a common source tube M1, a common source tube M2, a common gate tube M3 group, a common gate tube M4 group, a common gate tube M5 group and a common gate tube M6 group; The source of the common source transistor M1 and the source of the common source transistor M2 are grounded, and the gate of the common source transistor M1 and the gate of the common source transistor M2 can input signals respectively; The source of the common-gate transistor M3 group and the source of the common-gate transistor M4 group are connected to the drain of the common-source transistor M1, and the source of the common-gate transistor M5 group and the source of the common-gate transistor M6 group are connected to the drain of the common-source transistor M2; The gate of the common-gate transistor M3 group and the gate of the common-gate transistor M6 group are connected to the power supply voltage, and the gate of the common-gate transistor M4 group and the gate of the common-gate transistor M5 group can input the first attenuation control signal; The drain of the common-gate tube M3 group is connected to the drain of the common-gate tube M5 group, and the common connection end of the drain of the common-gate tube M3 group and the drain of the common-gate tube M5 group is the positive output end of the variable gain amplifier. The drain of the common-gate tube M4 group is connected to the drain of the common-gate tube M6 group, and the common connection end of the drain of the common-gate tube M4 group and the drain of the common-gate tube M6 group is the negative output end of the variable gain amplifier.
4. The low additional phase shift amplitude control circuit according to claim 3, characterized in that: A first inductor is provided between a common end connecting the source of the common-gate transistor M3 group and the source of the common-source transistor M4 group and the drain of the common-source transistor M1, and a second inductor is provided between a common end connecting the source of the common-gate transistor M5 group and the source of the common-source transistor M6 group and the drain of the common-source transistor M2.
5. The low additional phase shift amplitude control circuit according to claim 3, characterized in that: The gate of the common source transistor M1 and the gate of the common source transistor M2 are respectively provided with bias resistors.
6. The low additional phase shift amplitude control circuit according to claim 3, characterized in that: The common-gate tube M3 group includes a plurality of common-gate tubes M3 arranged in parallel, the common-gate tube M4 group includes a plurality of common-gate tubes M4 arranged in parallel, the common-gate tube M5 group includes a plurality of common-gate tubes M5 arranged in parallel, and the common-gate tube M6 group includes a plurality of common-gate tubes M6 arranged in parallel; The number of the common-gate tubes M3, the number of the common-gate tubes M4, the number of the common-gate tubes M5 and the number of the common-gate tubes M6 are consistent; At least two of the common-gate transistors M3 in the common-gate transistor group M3 have different sizes, and the common-gate transistor group M3, the common-gate transistor group M4, the common-gate transistor group M5 and the common-gate transistor group M6 have the same sizes.
7. The low additional phase shift amplitude control circuit according to claim 1, characterized in that: The variable gain amplifier has a positive output port and a negative output port, and the bridge differential passive attenuator includes a PMOS transistor M7 group, a PMOS transistor M8 group, a PMOS transistor M9 group and a PMOS transistor M10 group; The gate of the PMOS transistor M7 group and the gate of the PMOS transistor M10 group are connected to the ground respectively, and the gate of the PMOS transistor M8 group and the gate of the PMOS transistor M9 group can input the second attenuation control signal respectively; The PMOS transistor M7 group is arranged between the positive output port and the differential output positive terminal of the bridge differential passive attenuator, the PMOS transistor M8 group is connected between the positive output port and the differential negative terminal of the bridge differential passive attenuator, the PMOS transistor M9 group is arranged between the negative output port and the differential output positive terminal of the bridge differential passive attenuator, and the PMOS transistor M10 group is connected between the negative output port and the differential negative terminal of the bridge differential passive attenuator.
8. The low additional phase shift amplitude control circuit according to claim 7, characterized in that: The PMOS transistor M7 group includes a plurality of P-type transistors M7 connected in parallel, the PMOS transistor M8 group includes a plurality of P-type transistors M8 connected in parallel, the PMOS transistor M9 group includes a plurality of P-type transistors M9 connected in parallel, and the PMOS transistor M10 group includes a plurality of P-type transistors M10 connected in parallel; The number of the P-type tube M7, the P-type tube M8, the P-type tube M9 and the P-type tube M10 is the same; At least two of the P-type transistors M7 in the PMOS transistor M7 group have different sizes, and the sizes of the PMOS transistor M7 group, the PMOS transistor M8 group, the PMOS transistor M9 group, and the PMOS transistor M10 group are consistent.
9. The low additional phase shift amplitude control circuit according to claim 8, characterized in that: The gate of the PMOS transistor M7 group and the gate of the PMOS transistor M10 group are connected to the ground through the first resistor group and the fourth resistor group, respectively, and the gate of the PMOS transistor M8 group and the gate of the PMOS transistor M9 group can be connected to the input port of the second attenuation control signal through the second resistor group and the third resistor group, respectively.
10. The low additional phase shift amplitude control circuit according to claim 9, characterized in that: The first resistor group includes multiple parallel resistors R1, the second resistor group includes multiple parallel resistors R2, the third resistor group includes multiple parallel resistors R3, and the fourth resistor group includes multiple parallel resistors R4. The number of resistors in the first resistor group, the second resistor group, the third resistor group and the fourth resistor group is consistent with the number of P-type tubes M8.