Comparator

Abstract

The invention discloses a comparator, which comprises a pre-amplification and input unit, a tail current tube unit, a load unit, a latch unit and a reset unit, the pre-amplification and input unit is used for receiving a differential input signal, comparing and amplifying the differential input signal to obtain a differential amplification signal, and transmitting the differential amplification signal and bias current output by the tail current tube unit to the latch unit in a latch stage; the tail current tube unit is used for providing required bias current for the pre-amplification unit; the latch unit is used for latching the differential amplification signal to obtain a differential output signal; and the reset unit is used for resetting the latch unit in a pre-amplification stage. According to the invention, by increasing the tail current in the latching stage, the latching speed can be ensured, and the size of a latching unit transistor can be increased, so that the equivalent input imbalance of the input end of the comparator is reduced; and the working speed of the comparator is improved, and the limitation on the traditional comparator is not increased.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to a comparator. Background Art

[0002] Digital systems dominate modern information technology due to their powerful computing, storage, processing and transmission capabilities. Modern communication systems are usually designed to perform most of the processing in the digital domain. This trend, coupled with the need for systems that can handle high bit rates, makes the development of fast, energy-efficient mixed-signal building blocks a critical research topic. Comparators are an important component of most mixed-signal applications, such as analog-to-digital converters and digital-to-analog converters. The performance of comparators, such as speed, offset and noise, directly affects the performance of mixed-signal processing systems. Therefore, improving these comparators is crucial to improving the performance of the systems to which they belong.

[0003] In order to reduce the input offset voltage and improve the comparison speed of the comparator, the traditional comparator is usually composed of two stages: a dynamic latch and a pre-amplifier. Although the traditional two-stage structure can reduce the input offset and input noise and improve the comparison speed of the comparator to a certain extent, there are still many areas for improvement. Therefore, it is necessary to propose a comparator that can inherit the advantages of the traditional comparator, further reduce the non-ideal characteristics of the comparator and improve the comparison speed. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a comparator.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0006] A comparator, comprising:

[0007] The pre-amplification and input unit is used to receive the differential input signal and perform comparative amplification to obtain the differential amplified signal, and in the latching stage, send the differential amplified signal and the bias current output by the tail current tube unit to the latching unit;

[0008] The tail current tube unit is used to provide the required bias current for the pre-amplification unit;

[0009] A load unit, used for providing a corresponding load according to the gain required for amplification;

[0010] a latch unit, used for latching the differential amplified signal to obtain a differential output signal; and

[0011] A reset unit is used to reset the latch unit in the pre-amplification stage.

[0012] Furthermore, the pre-amplification and input unit includes a pre-amplification circuit and a latch input circuit. The pre-amplification circuit is used to receive a differential input signal and perform comparative amplification to obtain a differential amplified signal; the latch input circuit is used to send the differential amplified signal and the bias current output by the tail current tube unit to the latch unit during the latching stage.

[0013] Furthermore, the pre-amplifier circuit includes a first NMOS tube MN1, a first PMOS tube MP1, a second NMOS tube MN2 and a second PMOS tube MP2, the source of the first NMOS tube MN1 and the source of the second NMOS tube MN2 are both electrically connected to the tail current tube unit, the drain of the first NMOS tube MN1 is electrically connected to the drain of the first PMOS tube MP1 and the non-inverting input terminal of the latch unit, and the gate of the first NMOS tube MN1 is used to connect the input signal non-inverting terminal VIP; the drain of the second NMOS tube MN2 is electrically connected to the drain of the second PMOS tube MP2 and the inverting input terminal of the latch unit, and the gate of the second NMOS tube MN2 is used to connect the input signal inverting terminal VIN; the source of the first PMOS tube MP1 and the source of the second PMOS tube MP2 are electrically connected to the load unit, and the gate of the first PMOS tube MP1 and the gate of the second PMOS tube MP2 are both connected to the clock signal CLK.

[0014] Furthermore, the load unit includes a first load resistor R1 and a second load resistor R2; the first end of the first load resistor R1 is electrically connected to the source of the first PMOS tube MP1, the first end of the second load resistor R2 is electrically connected to the source of the second PMOS tube MP2, and the second end of the first load resistor R1 and the second end of the second load resistor R2 are both connected to the power supply VDD.

[0015] Furthermore, the latch input circuit includes a third NMOS tube MN3, a drain of the third NMOS tube MN3 is electrically connected to the source of the first NMOS tube MN1 and the source of the second NMOS tube MN2, a source of the third NMOS tube MN3 is grounded, and a gate of the third NMOS tube MN3 is connected to the clock signal CLK.

[0016] Furthermore, when the clock signal CLK is at a low level, the third NMOS tube MN3 is turned off, and the first NMOS tube MN1 and the second NMOS tube MN2 act as a differential amplifier pair to amplify the input signal; when the clock signal CLK is at a high level, the third NMOS tube MN3 is turned on, and the first NMOS tube MN1 and the second NMOS tube MN2 act as a differential input pair to send the differential amplified signal to the latch unit.

[0017] Furthermore, the tail current tube unit is defined as a current source IB1, an anode of the current source IB1 is electrically connected to a source of the first NMOS tube MN1 and a source of the second NMOS tube MN2; and a cathode of the current source IB1 is grounded.

[0018] Further, the latch unit includes a third PMOS tube MP3, a fourth NMOS tube MN4, a fourth PMOS tube MP4 and a fifth NMOS tube MN5; the source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4 are both connected to the power supply VDD; the gate of the third PMOS tube MP3 is electrically connected to the drain of the fourth PMOS tube MP4, the drain of the fifth NMOS tube MN5 and the gate of the fourth NMOS tube MN4, thereby forming an output signal in-phase terminal VOP; the gate of the fourth PMOS tube MP4 is electrically connected to the drain of the third PMOS tube MP3, the drain of the fourth NMOS tube MN4 and the gate of the fifth NMOS tube MN5, thereby forming an output signal inverting terminal VON; the source of the fourth NMOS tube MN4 is electrically connected to the drain of the first NMOS tube MN1 as the in-phase input terminal of the latch unit, and the source of the fifth NMOS tube MN5 is electrically connected to the drain of the second NMOS tube MN2 as the inverting input terminal of the latch unit.

[0019] Further, the reset unit includes a fifth PMOS tube MP5, a sixth PMOS tube MP6 and a seventh PMOS tube MP7; the source of the fifth PMOS tube MP5 and the source of the sixth PMOS tube MP6 are both connected to the power supply VDD, the drain of the fifth PMOS tube MP5 and the source of the seventh PMOS tube MP7 are both electrically connected to the output signal inverting terminal VON, the drain of the sixth PMOS tube MP6 and the drain of the seventh PMOS tube MP7 are both electrically connected to the output signal non-inverting terminal VOP; the gate of the fifth PMOS tube MP5, the gate of the sixth PMOS tube MP6 and the gate of the seventh PMOS tube MP7 are all connected to the clock CLK.

[0020] Further, when the clock signal CLK is at a low level, the fifth PMOS tube MP5, the sixth PMOS tube MP6 and the seventh PMOS tube MP7 are all turned on to reset the latch unit; when the clock signal CLK is at a high level, the fifth PMOS tube MP5, the sixth PMOS tube MP6 and the seventh PMOS tube MP7 are all turned off, and the latch unit latches the differential amplification signal.

[0021] In the present invention, the two-stage input differential pair of the pre-amplifier circuit and the latch input circuit are reused, the circuit structure is simplified, and the tail current in the latch stage is increased, so that the size of the latch unit transistor can be increased while ensuring the latch speed, thereby reducing the equivalent input offset of the comparator input terminal. The working speed of the comparator is also improved, and the path from the power supply to the ground is turned off when the latch is completed, so that no additional static power consumption is increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0023] Figure 1 The circuit diagram of a commonly used comparator in the prior art is shown in FIG.

[0024] Figure 2 FIG. 4 is a structural block diagram of a comparator according to an embodiment of the present invention.

[0025] Figure 3 FIG. 4 is a circuit diagram of a comparator according to an embodiment of the present invention.

[0026] The accompanying drawings in the specification are as follows:

[0027] Pre-amplification and input unit-100; tail current tube unit-200; load unit-300; latch unit-400; reset unit-500. DETAILED DESCRIPTION

[0028] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.

[0029] See also Figure 1 A commonly used comparator in the prior art includes a pre-amplification stage composed of NMOS tube MN11, NMOS tube MN12, load resistor R11, load resistor R12, and current source IB2, and a latch module composed of NMOS tube MN13, NMOS tube MN14, NMOS tube MN15, NMOS tube MN16, NMOS tube MN17, PMOS tube MP11, PMOS tube MP12, PMOS tube MP13, PMOS tube MP14, PMOS tube MP15, and PMOS tube MP16. Under the action of the clock signal CLK, the pre-amplification stage performs pre-amplification processing on the input signal, and the output differential amplification signal is latched in the latch module, and the comparator is periodically reset along with the clock CLK.

[0030] Specifically, when the clock signal CLK is at a low level, the pre-amplifier stage amplifies the input signal, and the output differential amplified signal generates a difference under the difference between the input signal in-phase end and the input signal inverting end, and is added to the latch input end; at the same time, the PMOS tube MP11, the PMOS tube MP12, the PMOS tube MP15 and the PMOS tube MP16 are turned on to reset the latch. When the clock signal CLK is at a high level, the PMOS tube MP11, the PMOS tube MP12, the PMOS tube MP15 and the PMOS tube MP16 are turned off, and the latch begins to latch the differential amplified signal and generates the final comparator output. Although the comparator circuit is relatively mature and has many advantages, its performance can be further improved.

[0031] See also Figure 2 , Figure 2 The structure block diagram of an embodiment of a comparator of the present invention. The comparator of this embodiment includes a pre-amplification and input unit 100, a tail current tube unit 200, a load unit 300, a latch unit 400 and a reset unit 500. The pre-amplification and input unit 100 is used to receive a differential input signal and perform comparative amplification to obtain a differential amplified signal, and send the differential amplified signal and the bias current output by the tail current tube unit 200 to the latch unit 400 in the latching stage. The load unit 300 is used to provide a corresponding load according to the gain required for amplification. The pre-amplification and input unit 100 includes a pre-amplification circuit and a latch input circuit, and the pre-amplification circuit is used to receive a differential input signal from the input signal in-phase terminal VIP and the input signal inverting terminal VIN and perform comparative amplification to obtain a differential amplified signal. The latch input circuit is used to send the differential amplified signal and the bias current output by the tail current tube unit 200 to the latch unit 400 in the latching stage.

[0032] See also Figure 3The pre-amplifier circuit includes a first NMOS transistor MN1, a first PMOS transistor MP1, a second NMOS transistor MN2, and a second PMOS transistor MP2, and the load unit 300 includes a first load resistor R1 and a second load resistor R2. The source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are both electrically connected to the tail current tube unit 200, the drain of the first NMOS transistor MN1 is electrically connected to the drain of the first PMOS transistor MP1 and the non-inverting input terminal of the latch unit 400, and the gate of the first NMOS transistor MN1 is used to connect the input signal non-inverting terminal VIP. The drain of the second NMOS transistor MN2 is electrically connected to the drain of the second PMOS transistor MP2 and the inverting input terminal of the latch unit 400, and the gate of the second NMOS transistor MN2 is used to connect the input signal inverting terminal VIN. The source of the first PMOS transistor MP1 is connected to the power supply VDD through the first load resistor R1, the source of the second PMOS transistor MP2 is connected to the power supply VDD through the second load resistor R2, and the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the clock signal CLK.

[0033] Please continue reading Figure 3 In this embodiment, the pre-amplifier circuit and the latch input circuit are deeply integrated, and the two-stage input differential pair tubes of the pre-amplifier circuit and the latch input circuit are reused to simplify the circuit structure; the latch input circuit only includes the third NMOS tube MN3, so as to simplify the circuit structure. Figure 1 The structure in the embodiment omits the NMOS transistor MN13 and the NMOS transistor MN14. The drain of the third NMOS transistor MN3 is electrically connected to the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2, the source of the third NMOS transistor MN3 is grounded, and the gate of the third NMOS transistor MN3 is connected to the clock signal CLK. When the clock signal CLK is at a low level, the third NMOS transistor MN3 is turned off, and the first NMOS transistor MN1 and the second NMOS transistor MN2 act as a differential amplifier pair to amplify the input signal. When the clock signal CLK is at a high level, the third NMOS transistor MN3 is turned on, and the first NMOS transistor MN1 and the second NMOS transistor MN2 act as a differential input pair to send the differential amplified signal to the latch unit 400.

[0034] The tail current tube unit 200 is used to provide the pre-amplification unit with the bias current required for pre-amplification. Figure 3In this embodiment, the tail current tube unit 200 is defined as a current source IB1, the anode of the current source IB1 is electrically connected to the source of the first NMOS tube MN1 and the source of the second NMOS tube MN2; the cathode of the current source IB1 is grounded. With the above structure, the working state of the first NMOS tube MN1 and the second NMOS tube MN2 is determined according to the input signal in the latching stage. Since the signals of the input signal in-phase terminal VIP and the input signal inverting terminal VIN cannot be 0 at the same time, at least one of the first NMOS tube MN1 and the second NMOS tube MN2 can always be turned on in the latching stage, so as to provide the tail current (i.e., the bias current output by the tail current tube unit 200) to the latch unit 400, thereby increasing the latching speed of the latch unit 400 and reducing the size limit of the transistor of the latch unit 400.

[0035] Please continue reading Figure 3 , the latch unit 400 is used to latch the differential amplified signal to obtain a differential output signal. The latch unit 400 may include a third PMOS tube MP3, a fourth NMOS tube MN4, a fourth PMOS tube MP4 and a fifth NMOS tube MN5. The source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4 are both connected to the power supply VDD; the gate of the third PMOS tube MP3 is electrically connected to the drain of the fourth PMOS tube MP4, the drain of the fifth NMOS tube MN5 and the gate of the fourth NMOS tube MN4, thereby forming an output signal in-phase terminal VOP. The gate of the fourth PMOS tube MP4 is electrically connected to the drain of the third PMOS tube MP3, the drain of the fourth NMOS tube MN4 and the gate of the fifth NMOS tube MN5, thereby forming an output signal inverting terminal VON. The source of the fourth NMOS transistor MN4 is electrically connected to the drain of the first NMOS transistor MN1 as the non-inverting input terminal of the latch unit 400 , and the source of the fifth NMOS transistor MN5 is electrically connected to the drain of the second NMOS transistor MN2 as the inverting input terminal of the latch unit 400 .

[0036] The reset unit 500 is used to reset the latch unit 400 in the pre-amplification stage. Figure 3The reset unit 500 may include a fifth PMOS tube MP5, a sixth PMOS tube MP6, and a seventh PMOS tube MP7. The source of the fifth PMOS tube MP5 and the source of the sixth PMOS tube MP6 are both connected to the power supply VDD, the drain of the fifth PMOS tube MP5 and the source of the seventh PMOS tube MP7 are both electrically connected to the output signal inverting terminal VON, and the drain of the sixth PMOS tube MP6 and the drain of the seventh PMOS tube MP7 are both electrically connected to the output signal non-inverting terminal VOP. The gate of the fifth PMOS tube MP5, the gate of the sixth PMOS tube MP6, and the gate of the seventh PMOS tube MP7 are all connected to the clock CLK.

[0037] When the clock signal CLK is at a low level, the fifth PMOS tube MP5, the sixth PMOS tube MP6 and the seventh PMOS tube MP7 are all turned on, and the latch unit 400 is reset; when the clock signal CLK is at a high level, the fifth PMOS tube MP5, the sixth PMOS tube MP6 and the seventh PMOS tube MP7 are all turned off, and the latch unit 400 latches the differential amplification signal.

[0038] The working principle of this embodiment is as follows:

[0039] See also Figure 2 and Figure 3 When the clock signal CLK is at a low level, the third NMOS tube MN3 is turned off, and the first PMOS tube MP1, the second PMOS tube MP2, the fifth PMOS tube MP5, the sixth PMOS tube MP6 and the seventh PMOS tube MP7 are turned on. Under the action of the input differential signal, the drains of the first NMOS tube MN1 and the second NMOS tube MN2 generate differential amplified signals. Due to the addition of the first PMOS tube MP1 and the second PMOS tube MP2, Figure 1 Compared with the conventional comparator, this embodiment can improve the pre-amplifier gain, improve the equivalent input offset and equivalent input noise. At the same time, since the fifth PMOS tube MP5, the sixth PMOS tube MP6 and the seventh PMOS tube MP7 are turned on, the latch unit 400 is reset.

[0040] When the clock signal CLK is at a high level, the third NMOS transistor MN3 is turned on, the first PMOS transistor MP1, the second PMOS transistor MP2, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are turned off, and the latch unit 400 starts to latch the generated differential amplification signal, and generates a comparator output at the source and drain of the seventh PMOS transistor MP7. Since there is no DC path from the power supply VDD to the ground after the latching is completed in the latching stage, and no static power consumption is generated, the current source IB1 does not need to be turned off. In addition, IB1 can also provide additional tail current for the latch unit 400 in the latching stage, thereby increasing the latching speed of the latch unit 400, thereby relaxing the constraints on the size of the latch unit 400 transistors (i.e., the third PMOS transistor MP3, the fourth NMOS transistor MN4, the fourth PMOS transistor MP4 and the fifth NMOS transistor MN5), and then a larger size transistor can be used to further reduce the equivalent input offset and equivalent input noise.

[0041] In this embodiment, by multiplexing the two-stage input differential pair of the pre-amplifier circuit and the latch input circuit, the circuit structure is simplified and the transistor cost is reduced. In addition, the tail current can still be used in the latching stage, which increases the tail current when the latching stage is working, improves the latching speed of the latch unit 400, and the VDD to GND path is turned off when the latching is completed, so the newly added tail current will not increase the static power consumption of the comparator. In addition, the increase in tail current in the latching stage also allows the transistor of the latch unit 400 to be selected in a larger size, thereby reducing the equivalent offset of the input end.

[0042] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A comparator, characterized in that: include: The pre-amplification and input unit is used to receive the differential input signal and perform comparative amplification to obtain the differential amplified signal, and in the latching stage, send the differential amplified signal and the bias current output by the tail current tube unit to the latching unit; The tail current tube unit is used to provide the required bias current for the pre-amplification unit; A load unit, used for providing a corresponding load according to the gain required for amplification; A latch unit, used for latching the differential amplified signal to obtain a differential output signal; as well as A reset unit is used to reset the latch unit in the pre-amplification stage.

2. The comparator according to claim 1, wherein: The pre-amplification and input unit includes a pre-amplification circuit and a latch input circuit. The pre-amplification circuit is used to receive a differential input signal and perform comparative amplification to obtain a differential amplified signal; the latch input circuit is used to send the differential amplified signal and the bias current output by the tail current tube unit to the latch unit during the latching stage.

3. The comparator according to claim 2, wherein: The pre-amplifier circuit includes a first NMOS tube MN1, a first PMOS tube MP1, a second NMOS tube MN2 and a second PMOS tube MP2. The source of the first NMOS tube MN1 and the source of the second NMOS tube MN2 are both electrically connected to the tail current tube unit, the drain of the first NMOS tube MN1 is electrically connected to the drain of the first PMOS tube MP1 and the non-inverting input end of the latch unit, and the gate of the first NMOS tube MN1 is used to connect the input signal non-inverting end VIP; the drain of the second NMOS tube MN2 is electrically connected to the drain of the second PMOS tube MP2 and the inverting input end of the latch unit, and the gate of the second NMOS tube MN2 is used to connect the input signal inverting end VIN; the source of the first PMOS tube MP1 and the source of the second PMOS tube MP2 are electrically connected to the load unit, and the gate of the first PMOS tube MP1 and the gate of the second PMOS tube MP2 are both connected to the clock signal CLK.

4. The comparator according to claim 3, wherein: The load unit includes a first load resistor R1 and a second load resistor R2; a first end of the first load resistor R1 is electrically connected to the source of the first PMOS tube MP1, a first end of the second load resistor R2 is electrically connected to the source of the second PMOS tube MP2, and a second end of the first load resistor R1 and a second end of the second load resistor R2 are both connected to a power supply VDD.

5. The comparator according to claim 4, wherein: The latch input circuit includes a third NMOS transistor MN3, a drain of the third NMOS transistor MN3 is electrically connected to the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2, a source of the third NMOS transistor MN3 is grounded, and a gate of the third NMOS transistor MN3 is connected to the clock signal CLK.

6. The comparator according to claim 5, wherein: When the clock signal CLK is at a low level, the third NMOS transistor MN3 is turned off, and the first NMOS transistor MN1 and the second NMOS transistor MN2 act as a differential amplifier pair to amplify the input signal; when the clock signal CLK is at a high level, the third NMOS transistor MN3 is turned on, and the first NMOS transistor MN1 and the second NMOS transistor MN2 act as a differential input pair to send the differential amplified signal to the latch unit.

7. The comparator according to claim 6, wherein: The tail current tube unit is defined as a current source IB1, an anode of the current source IB1 is electrically connected to the source of the first NMOS tube MN1 and the source of the second NMOS tube MN2; and a cathode of the current source IB1 is grounded.

8. The comparator according to any one of claims 1 to 7, characterized in that: The latch unit includes a third PMOS tube MP3, a fourth NMOS tube MN4, a fourth PMOS tube MP4 and a fifth NMOS tube MN5; the source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4 are both connected to the power supply VDD; the gate of the third PMOS tube MP3 is electrically connected to the drain of the fourth PMOS tube MP4, the drain of the fifth NMOS tube MN5 and the gate of the fourth NMOS tube MN4, thereby forming an output signal in-phase terminal VOP; the gate of the fourth PMOS tube MP4 is electrically connected to the drain of the third PMOS tube MP3, the drain of the fourth NMOS tube MN4 and the gate of the fifth NMOS tube MN5, thereby forming an output signal inverting terminal VON; the source of the fourth NMOS tube MN4 is electrically connected to the drain of the first NMOS tube MN1 as the in-phase input terminal of the latch unit, and the source of the fifth NMOS tube MN5 is electrically connected to the drain of the second NMOS tube MN2 as the inverting input terminal of the latch unit.

9. The comparator according to claim 8, wherein: The reset unit includes a fifth PMOS tube MP5, a sixth PMOS tube MP6 and a seventh PMOS tube MP7; the source of the fifth PMOS tube MP5 and the source of the sixth PMOS tube MP6 are both connected to the power supply VDD, the drain of the fifth PMOS tube MP5 and the source of the seventh PMOS tube MP7 are both electrically connected to the output signal inverting terminal VON, the drain of the sixth PMOS tube MP6 and the drain of the seventh PMOS tube MP7 are both electrically connected to the output signal non-inverting terminal VOP; the gate of the fifth PMOS tube MP5, the gate of the sixth PMOS tube MP6 and the gate of the seventh PMOS tube MP7 are all connected to the clock CLK.

10. The comparator according to claim 9, wherein: When the clock signal CLK is at a low level, the fifth PMOS tube MP5, the sixth PMOS tube MP6 and the seventh PMOS tube MP7 are all turned on to reset the latch unit; when the clock signal CLK is at a high level, the fifth PMOS tube MP5, the sixth PMOS tube MP6 and the seventh PMOS tube MP7 are all turned off, and the latch unit latches the differential amplification signal.

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