Power-on reset circuit

Abstract

The invention discloses a power-on reset circuit which comprises a starting sub-circuit, a reference sub-circuit connected to the starting sub-circuit and a comparison sub-circuit connected to the reference sub-circuit. The reference sub-circuit comprises a band-gap reference core module, a sixth NMOS tube connected to the band-gap reference core module, and a ninth PMOS tube connected to the starting sub-circuit; the starting sub-circuit receives a starting signal to start the whole circuit, in the starting process, grid electrodes of the ninth PMOS tube and the sixth NMOS tube are pulled up by the starting sub-circuit to power supply voltage, a source electrode of the sixth NMOS tube outputs reference voltage to the comparison sub-circuit, the comparison sub-circuit compares the reference voltage with sampling voltage, and when the sampling voltage is larger than the reference voltage, the starting sub-circuit starts the whole circuit. And outputting the reset signal to a subsequent circuit. According to the technical scheme, the reference sub-circuit can approximately follow the power supply voltage all the time before loop starting is completed, the reference voltage is output after starting is completed, abnormal overturning is avoided in the starting process, and the situation that system work is affected due to error indication is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a power-on reset circuit. Background Art

[0002] The POR (power-on reset) circuit is generally at the highest priority in the system, so there is generally no available reference voltage source and current source. Therefore, the threshold voltage of the POR circuit generally has a large deviation (the error range of the common POR circuit is about +-20%) and is easily affected by temperature and process angle.

[0003] Generally, since the priority of the reference circuit is lower than that of the POR circuit, when the threshold voltage of the POR circuit is set low (taking 1.6V as an example), the circuit will have no stable reference voltage available; secondly, if the priority of the reference circuit is higher than that of the POR circuit, when the power supply voltage is lower than the minimum operating voltage of the reference source, the reference source outputs zero voltage, causing the POR circuit to give an erroneous indication and fail to protect the system.

[0004] like Figure 1 As shown, the current traditional scheme is to use a current source with a positive temperature coefficient as a reference voltage. Specifically, the bias current is mirrored to the P-type field effect tube M3 through the P-type field effect tube M1, and then added to the resistor R2' to generate a positive temperature coefficient voltage. The gate-source voltage VGS of the N-type field effect tube M5 is a negative temperature coefficient voltage, which is used to reduce the slope of the positive temperature coefficient voltage of the reference voltage VREF. The power supply voltage VIN minus the gate-source voltage VGS of the N-type field effect tube M5 (i.e., VIN-VGS) is used as the reference voltage VREF and the sampling voltage VSAM are compared. When the power supply voltage VIN rises, the sampling voltage VSAM gradually rises and exceeds the reference voltage VREF, and the POR circuit flips. Although this method approximately offsets the temperature coefficient, it cannot completely offset it; and it is easily affected by the process angle and process deviation. The temperature coefficient is also different at different process angles. The flip threshold of the POR circuit is often relatively fixed, and the flip of the POR circuit has high requirements for the rising and falling slopes of the power supply. Summary of the invention

[0005] The main purpose of the present invention is to provide a power-on reset circuit, aiming to make the power-on reset circuit indicate correctly within the threshold voltage of the reset circuit.

[0006] To achieve the above object, the present invention provides a power-on reset circuit, comprising a starter subcircuit, a reference subcircuit connected to the starter subcircuit, and a comparison subcircuit connected to the reference subcircuit; The reference subcircuit comprises a bandgap reference core module, a sixth NMOS transistor connected to the bandgap reference core module, and a ninth PMOS transistor connected to the starter subcircuit; the gate of the ninth PMOS transistor is connected to the starter subcircuit, the source is connected to the gate of the sixth NMOS transistor, and the drain is grounded; the sixth NMOS transistor is a native transistor, the gate of which is connected to the starter subcircuit, the source is connected to the bandgap reference core module and the comparison subcircuit, and the drain is connected to the power supply voltage; The startup subcircuit receives a startup signal to start the entire circuit. During the startup process, the gates of the ninth PMOS tube and the sixth NMOS tube are pulled up to the power supply voltage by the startup subcircuit, and the source of the sixth NMOS tube outputs a reference voltage to the comparison subcircuit. The comparison subcircuit compares the reference voltage and the input voltage sampling voltage. When the sampling voltage is greater than the reference voltage, a reset signal is output to the subsequent circuit.

[0007] Preferably, the start subcircuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a fifth PMOS tube, a first NMOS tube, a second NMOS tube and a first resistor; the gate of the first PMOS tube receives a start signal, the sources of the first PMOS tube, the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are connected to the power supply voltage, and the drain of the first PMOS tube is connected to the source of the second PMOS tube; the gate of the second PMOS tube is grounded, and the drain is connected to the drain and the gate of the first NMOS tube; the gate of the first NMOS tube is also connected to the gate of the second NMOS tube, and the source of the first NMOS tube is grounded; the source of the second NMOS tube is grounded through the first resistor; the drain of the second NMOS tube is connected to the gates of the fourth PMOS tube and the fifth PMOS tube and the drain of the third PMOS tube; the gate of the third PMOS tube is connected to the reference subcircuit; the drain of the fourth PMOS tube is connected to the gate of the ninth PMOS tube in the reference subcircuit; the drain of the fifth PMOS tube is connected to the gate of the sixth NMOS tube in the reference subcircuit.

[0008] Preferably, the reference subcircuit further includes a seventh NMOS tube, an eighth NMOS tube, an eighth PMOS tube, a tenth PMOS tube and a second resistor, the drain of the seventh NMOS tube is connected to the source of the sixth NMOS tube through the second resistor to generate a bias current; the gates of the seventh NMOS tube and the eighth NMOS tube are connected to each other, and the sources of both are grounded; the drain of the eighth NMOS tube is connected to the drain and gate of the tenth PMOS tube; the sources of the eighth PMOS tube and the tenth PMOS tube are connected to the power supply voltage, the gates are connected to each other and connected to the gate of the third PMOS tube in the startup subcircuit; the drain of the eighth PMOS tube is respectively connected to the gate of the sixth NMOS tube and the source of the ninth PMOS tube, so as to provide a current source for the sixth NMOS tube and the ninth PMOS tube after the circuit startup is completed.

[0009] Preferably, the reference sub-circuit further comprises an operational amplifier module, and the operational amplifier module is respectively connected to the seventh NMOS transistor, the ninth PMOS transistor and the bandgap reference core module.

[0010] Preferably, the operational amplifier module includes a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth PMOS tube and a seventh PMOS tube; the sources of the sixth PMOS tube and the seventh PMOS tube are connected to the power supply voltage, and the gates are connected to each other; the drain of the sixth PMOS tube is connected to the gate and also connected to the drain of the third NMOS tube; the drain of the seventh PMOS tube is connected to the gate of the ninth PMOS tube and the drain of the fourth NMOS tube; the source of the third NMOS tube and the source of the fourth NMOS tube are simultaneously connected to the drain of the fifth NMOS tube, and the gate of the third NMOS tube and the gate of the fourth NMOS tube are connected to the bandgap reference core module; the source of the fifth NMOS tube is grounded, and the gate is connected to the drain and gate of the seventh NMOS tube.

[0011] Preferably, the bandgap reference core module includes a first triode, a second triode, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor; the base and the collector of the first triode and the second triode are both grounded, the emitter of the first triode is connected to one end of the third resistor, the other end of the third resistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the source of the sixth NMOS; the emitter of the second triode is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to one end of the fourth resistor.

[0012] Preferably, the comparison subcircuit includes a comparator, a seventh resistor and an eighth resistor; one end of the seventh resistor is connected to the power supply voltage, the other end is connected to one end of the eighth resistor and the first input terminal of the comparator, the other end of the eighth resistor is grounded, the second input terminal of the comparator is connected to the source of the sixth NMOS tube, and the output terminal is used to output a reset signal.

[0013] The reference subcircuit in the technical solution of the present invention can always approximately follow the power supply voltage before the loop startup is completed, and output the reference voltage after the startup is completed. There is no abnormal flipping during the startup process, and no error indication will occur to affect the system operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of a reset circuit in the prior art; Figure 2 is a schematic diagram of a power-on reset circuit according to an embodiment of the present invention; Figure 3 a is a schematic diagram showing the relationship between the power supply voltage, the reference voltage and the reset voltage during the startup and operation of the reset circuit in the prior art; Figure 3 b is a schematic diagram of the relationship between the power supply voltage, the reference voltage and the reset voltage during the startup and operation of the power-on reset circuit of an embodiment of the present invention.

[0015] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0016] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0017] The present invention is further described below in conjunction with the accompanying drawings.

[0018] The present invention designs a power-on reset circuit with a built-in low-voltage started bandgap reference core module. When the power supply voltage VIN is low, the reference subcircuit can be approximately equal to the power supply voltage VIN, so that the power-on reset circuit indicates correctly within a threshold voltage.

[0019] The power-on reset circuit of the embodiment of the present invention includes a start subcircuit, a reference subcircuit connected to the start subcircuit, and a comparison subcircuit connected to the reference subcircuit. The start subcircuit receives a start signal ST to start the entire circuit, the reference subcircuit is used to generate and output a reference voltage VREF, and the comparison subcircuit is used to compare the reference voltage VREF with an input voltage sampling voltage VSAM. When the sampling voltage VSAM is greater than the reference voltage VREF, a reset signal RSTN is output to the subsequent circuit.

[0020] Specifically, Figure 2As shown, the reference subcircuit includes a bandgap reference core module, a sixth NMOS tube MN6 connected to the bandgap reference core module, and a ninth PMOS tube MP9 connected to the start-up subcircuit; the gate of the ninth PMOS tube MP9 is connected to the start-up subcircuit, the source is connected to the gate of the sixth NMOS tube MN6, and the drain is grounded GND; the sixth NMOS tube MN6 is a native tube, the gate of which is connected to the start-up subcircuit, the source is connected to the bandgap reference core module and the comparison subcircuit, and the drain is connected to the power supply voltage VIN; during the circuit startup process, the power supply voltage VIN gradually rises from 0, and the gates of the ninth PMOS tube MP9 and the sixth NMOS tube MN6 are pulled up to the power supply voltage VIN by the start-up subcircuit. Since the sixth NMOS tube MN6 is a native tube and the conduction threshold is 0, the reference voltage VREF output by the source of the sixth NMOS tube MN6 is approximately equal to the power supply voltage VIN, so that the reference subcircuit can always approximately follow the power supply voltage VIN before the entire circuit is started. There is no abnormal flipping during the startup process, and no error indication will occur to affect the system operation.

[0021] like Figure 2 As shown, the starter circuit includes a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4 and a fifth PMOS tube MP5, a first NMOS tube MN1, a second NMOS tube MN2 and a first resistor R1; the gate of the first PMOS tube MP1 is connected to the start signal sending end to receive the start signal ST, the sources of the first PMOS tube MP1, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are connected to the power supply voltage VIN, the drain of the first PMOS tube MP1 is connected to the source of the second PMOS tube MP2; the gate of the second PMOS tube MP2 is grounded GND, and the drain is connected to the drain and gate of the first NMOS tube MN1; the first NMOS tube MP1 is connected to the start signal sending end to receive the start signal ST, the sources of the first PMOS tube MP1, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are connected to the power supply voltage VIN, and the drain of the first PMOS tube MP1 is connected to the source of the second PMOS tube MP2; the gate of the second PMOS tube MP2 is grounded GND, and the drain is connected to the drain and gate of the first NMOS tube MN1; The gate of the MOS tube MN1 is also connected to the gate of the second NMOS tube MN2, and the source of the first NMOS tube MN1 is grounded GND; the source of the second NMOS tube MN2 is grounded GND through the first resistor R1, one end of the first resistor R1 is connected to the source of the second NMOS tube MN2, and the other end is grounded GND; the drain of the second NMOS tube MN2 is connected to the gates of the fourth PMOS tube MP4 and the fifth PMOS tube MP5 and the drain of the third PMOS tube MP3; the gate of the third PMOS tube MP3 is connected to the reference sub-circuit; the drain of the fourth PMOS tube MP4 is connected to the gate of the ninth PMOS tube MP9 in the reference sub-circuit; the drain of the fifth PMOS tube MP5 is connected to the gate of the sixth NMOS tube MN6 in the reference sub-circuit.

[0022] Specifically, the first PMOS transistor MP1 in the startup subcircuit receives the startup signal ST. In the initial state, the first PMOS transistor MP1 is a switch transistor at a low level; the second PMOS transistor MP2 is an inverse ratio transistor, whose channel length is greater than the channel width, and is used as a large resistor to generate a startup current I of the startup subcircuit. START , the starting current is calculated by the equation I START= (VGS MN1 -VGS MN2 ) / R1, where VGS MN1 is the gate-source voltage of the first NMOS tube MN1, VGS MN2 is the gate-source voltage of the second NMOS transistor MN2, and R1 is the resistance value of the first resistor R1. When the circuit is not fully started, the current of the third PMOS transistor MP3 is 0, the gate voltages of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are pulled down to 0, and enter the fully turned-on state, so the gates of the ninth PMOS transistor MP9 and the sixth NMOS transistor MN6 are pulled up to the power supply voltage VIN.

[0023] like Figure 2 As shown, the reference subcircuit includes a bandgap reference core module and a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8 and a second resistor R2; Among them, the sixth PMOS tube MP6, the seventh PMOS tube MP7, the third NMOS tube MN3, the fourth NMOS tube MN4 and the fifth NMOS tube MN5 constitute an operational amplifier module: the sources of the sixth PMOS tube MP6 and the seventh PMOS tube MP7 are connected to the power supply voltage VIN, the gates are connected to each other and connected to the drain of the sixth PMOS tube MP6, the drain of the sixth PMOS tube MP6 is also connected to the drain of the third NMOS tube MN3, the drain of the seventh PMOS tube MP7 is connected to the drain of the fourth PMOS tube MP4 in the starter circuit, the gate of the ninth PMOS tube MP9 and the drain of the fourth NMOS tube MN4; the sources of the third NMOS tube MN3 and the fourth NMOS tube MN4 are connected to each other and connected to the drain of the fifth NMOS tube MN5; the gate of the fifth NMOS tube MN5 is connected to the gates of the seventh NMOS tube MN7 and the eighth NMOS tube MN8, and the source is grounded GND. In other embodiments, the operational amplifier module in the embodiment of the present invention can also use other operational amplifier circuits in the prior art. The operational amplifier module used in the embodiment of the present invention has low power consumption and a small area, and can meet the low power consumption requirement of the embodiment.

[0024] The drain of the seventh NMOS transistor MN7 is connected to the source of the sixth NMOS transistor MN6 through the second resistor R2 to generate a bias current to power the reference sub-circuit. Specifically, the source of the sixth NMOS transistor MN6 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the gate and drain of the seventh NMOS transistor MN7; the gates of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are connected to each other, and the sources of both are grounded GND; the drain of the eighth NMOS transistor MN8 is connected to the drain and gate of the tenth PMOS transistor MP10; the sources of the eighth PMOS transistor MP8 and the tenth PMOS transistor MP10 are connected to the power supply voltage VIN, and the gates are connected to each other and to the gate of the third PMOS transistor MP3 in the startup sub-circuit; the drain of the eighth PMOS transistor MP8 is respectively connected to the gate of the sixth NMOS transistor MN6 and the source of the ninth PMOS transistor MP9 to provide a current source for the sixth NMOS transistor MN6 and the ninth PMOS transistor MP9 after the circuit startup is completed. At the same time, the drain of the tenth PMOS transistor MP10 serves as a VPN output terminal, which can provide a bias current / bias voltage for subsequent circuits and generate a PTAT current.

[0025] Specifically, during the circuit startup process, as the power supply voltage VIN increases, when the reference voltage VREFVREF output by the source of the sixth NMOS tube MN6 exceeds the threshold voltage VTH of the seventh NMOS tube MN7, a self-bias current source is generated on the seventh NMOS tube MN7, and the current value is (VREF-VBN) / R2, and this current provides a bias current for the reference sub-circuit.

[0026] In a specific embodiment, VBN has a negative temperature coefficient, and after the reference voltage VREF generated at the source of the sixth NMOS tube MN6 passes through the second resistor R2 with a zero temperature coefficient, the bias current source generated on the seventh NMOS tube MN7 has a positive temperature coefficient, that is, the currents at the eighth NMOS tube MN8, the tenth NMOS tube and the eighth PMOS tube MP8 are all positive temperature coefficients, so that the circuit can reduce the impact of leakage under high temperature conditions.

[0027] like Figure 2As shown, the bandgap reference core module includes a first transistor BJT1, a second transistor BJT2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6; the base and collector of the first transistor BJT1 and the second transistor BJT2 are both grounded GND, the emitter of the first transistor BJT1 is connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the source of the sixth NMOS; the emitter of the second transistor BJT2 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is connected to one end of the fourth resistor R4. In other embodiments, the bandgap reference core module can use other bandgap reference circuits in the prior art according to the needs of designers. The bandgap reference core module of the embodiment of the present invention has high precision and low required power supply voltage.

[0028] like Figure 2 As shown, the comparison sub-circuit includes a comparator COMP, a seventh resistor R7 and an eighth resistor R8; one end of the seventh resistor R7 is connected to the power supply voltage VIN, the other end is connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is grounded GND; a first input end of the comparator COMP is connected to the other end of the seventh resistor R7 and one end of the eighth resistor R8, for receiving a sampling voltage VSAM; a second input end of the comparator COMP is connected to the source of the sixth NMOS transistor MN6, for receiving a reference voltage VREF; the comparator COMP compares the reference voltage VREF with the sampling voltage VSAM, and when the sampling voltage VSAM is greater than the reference voltage VREF, the output end is used to output a reset signal RSTN.

[0029] In a specific embodiment, the designer may also adjust the voltage division coefficient of the voltage division resistors (ie, the seventh resistor R7 and the eighth resistor R8) according to actual needs, so that the threshold range of the power-on reset circuit may be adjusted.

[0030] The principles of the embodiments of the present invention are: The startup sub-circuit receives the startup signal ST, and the circuit starts to start.

[0031] In the initial state, the circuit is not fully started. At this time: The first PMOS tube MP1 is used as a switch tube, and its initial state is low level; the second PMOS tube MP2 is an inverse ratio tube, which is used to generate a starting current I START ; The current of the third PMOS transistor MP3 is 0, and the gate voltages of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are pulled down to 0, entering a fully on state; therefore, the gates of the ninth PMOS transistor MP9 and the sixth NMOS transistor MN6 in the reference subcircuit are pulled up to the power supply voltage VIN. Since the conduction threshold of the sixth NMOS transistor MN6 is approximately 0, its source output reference voltage VREF is approximately equal to the power supply voltage VIN, that is, when the startup current is established but the bandgap reference loop has not yet been fully established, the output reference voltage VREF is approximately equal to the power supply voltage VIN; As the power supply voltage VIN increases, when the output reference voltage VREF is greater than the threshold voltage VTH of the seventh NMOS transistor MN7, a self-bias current source is generated on the seventh NMOS transistor MN7 to provide a bias current for the reference loop.

[0032] When the circuit startup is complete and the loop is established: The reference voltage VREF no longer needs to be pulled up by the startup circuit, so the bias current is mirrored to the eighth NMOS tube MN8 and then mirrored to the third PMOS tube MP3 by the tenth PMOS tube MP10, and then compared with the startup current at the second NMOS tube MN2. When the reference voltage VREF is high enough, the current of the third PMOS tube MP3 is greater than the startup current of the second NMOS tube MN2, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are turned off, and the startup circuit is turned off, thereby reducing the power consumption of the startup circuit.

[0033] The reference subcircuit in the embodiment of the present invention can always approximately follow the power supply voltage VIN before the loop startup is completed, and output the reference voltage VREF after the startup is completed. There is no abnormal flip during the startup process, and no error indication will occur to affect the system operation.

[0034] At the same time, the comparison sub-circuit compares the reference voltage VREF with the sampled voltage VSAM of the power supply voltage VIN, and when the sampled voltage VSAM is greater than the reference voltage VREF, a reset signal RSTN is output to the subsequent circuit.

[0035] The embodiment of the present invention generates a high-precision reference voltage VREF by designing a bandgap reference subcircuit of a low power supply voltage VIN to compare with the sampling voltage VSAM. When the sampling voltage VSAM exceeds the reference voltage VREF, the comparison is flipped to generate a reset signal RSTN. Since the reset circuit in the prior art usually has the highest priority and no reference source, the embodiment of the present invention designs a bandgap reference subcircuit started by a low power supply voltage VIN, so that the reference subcircuit has the highest priority in the system. The power-on reset circuit of this embodiment has a high-precision reference source, and its flip threshold is not easily affected by factors such as process angle and temperature.

[0036] Furthermore, when the power supply voltage VIN of the bandgap reference is lower than the minimum operating voltage, the output voltage of the reset circuit structure in the prior art will directly drop to zero or be at a lower voltage value, which will cause the reset circuit to flip erroneously, thereby losing the protection effect on the subsequent circuit. Figure 3 (a) shows the working state of the reset circuit using a traditional bandgap reference: the reference voltage VREF is generally high enough to meet the minimum working voltage point, and when it is lower than the minimum working voltage, the output of the reference is generally 0 or a lower voltage (such as 0.2-0.3V). When the power supply voltage VIN rises to a certain stage but does not reach the threshold voltage of the reset circuit (i.e., the working voltage), an erroneous flip will occur (see reset signal RSTN); then, the power supply voltage VIN continues to rise, the reset circuit returns to normal, and flips normally when the threshold voltage of the reset circuit is reached.

[0037] The bandgap reference source circuit designed in the embodiment of the present invention can always approximately follow the power supply voltage VIN before the startup completion stage, that is, when the reference is lower than the minimum operating voltage, it is the output power supply voltage VIN; after the startup is completed, the reference voltage VREF is output, that is, when it is at the normal operating voltage, the output is the reference voltage VREF; Figure 3 (b) shows the situation when the circuit of the present invention is started, and there is no abnormal flipping during the startup process.

[0038] It should be understood that the above are only preferred embodiments of the present invention, and the patent scope of the present invention cannot be limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A power-on reset circuit, comprising a starter subcircuit, a reference subcircuit connected to the starter subcircuit, and a comparison subcircuit connected to the reference subcircuit, characterized in that: The reference subcircuit comprises a bandgap reference core module, a sixth NMOS transistor connected to the bandgap reference core module, and a ninth PMOS transistor connected to the starter subcircuit; the gate of the ninth PMOS transistor is connected to the starter subcircuit, the source is connected to the gate of the sixth NMOS transistor, and the drain is grounded; the sixth NMOS transistor is a native transistor, the gate of which is connected to the starter subcircuit, the source is connected to the bandgap reference core module and the comparison subcircuit, and the drain is connected to the power supply voltage; The startup subcircuit receives a startup signal to start the entire circuit. During the startup process, the gates of the ninth PMOS tube and the sixth NMOS tube are pulled up to the power supply voltage by the startup subcircuit, and the source of the sixth NMOS tube outputs a reference voltage to the comparison subcircuit. The comparison subcircuit compares the reference voltage and the input voltage sampling voltage. When the sampling voltage is greater than the reference voltage, a reset signal is output to the subsequent circuit.

2. The power-on reset circuit according to claim 1, characterized in that: The start subcircuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a fifth PMOS tube, a first NMOS tube, a second NMOS tube and a first resistor; the gate of the first PMOS tube receives a start signal, the sources of the first PMOS tube, the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are connected to a power supply voltage, and the drain of the first PMOS tube is connected to the source of the second PMOS tube; the gate of the second PMOS tube is grounded, and the drain is connected to the drain and the gate of the first NMOS tube; the gate of the first NMOS tube is also connected to the gate of the second NMOS tube, and the source of the first NMOS tube is grounded; the source of the second NMOS tube is grounded through the first resistor; the drain of the second NMOS tube is connected to the gates of the fourth PMOS tube and the fifth PMOS tube and the drain of the third PMOS tube; the gate of the third PMOS tube is connected to the reference subcircuit; the drain of the fourth PMOS tube is connected to the gate of the ninth PMOS tube in the reference subcircuit; and the drain of the fifth PMOS tube is connected to the gate of the sixth NMOS tube in the reference subcircuit.

3. The power-on reset circuit according to claim 2, characterized in that: The reference subcircuit also includes a seventh NMOS tube, an eighth NMOS tube, an eighth PMOS tube, a tenth PMOS tube and a second resistor, the drain of the seventh NMOS tube is connected to the source of the sixth NMOS tube through the second resistor to generate a bias current; the gates of the seventh NMOS tube and the eighth NMOS tube are connected to each other, and the sources of both are grounded; the drain of the eighth NMOS tube is connected to the drain and gate of the tenth PMOS tube; the sources of the eighth PMOS tube and the tenth PMOS tube are connected to the power supply voltage, the gates are connected to each other and connected to the gate of the third PMOS tube in the startup subcircuit; the drain of the eighth PMOS tube is respectively connected to the gate of the sixth NMOS tube and the source of the ninth PMOS tube, so as to provide a current source for the sixth NMOS tube and the ninth PMOS tube after the circuit startup is completed.

4. The power-on reset circuit according to claim 3, characterized in that: The reference sub-circuit also includes an operational amplifier module, which is respectively connected to the seventh NMOS transistor, the ninth PMOS transistor and the bandgap reference core module.

5. The power-on reset circuit according to claim 4, characterized in that: The operational amplifier module includes a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth PMOS tube and a seventh PMOS tube; the sources of the sixth PMOS tube and the seventh PMOS tube are connected to the power supply voltage, and the gates are connected to each other; the drain of the sixth PMOS tube is connected to the gate and also connected to the drain of the third NMOS tube; the drain of the seventh PMOS tube is connected to the gate of the ninth PMOS tube and the drain of the fourth NMOS tube; the source of the third NMOS tube and the source of the fourth NMOS tube are simultaneously connected to the drain of the fifth NMOS tube, and the gate of the third NMOS tube and the gate of the fourth NMOS tube are connected to the bandgap reference core module; the source of the fifth NMOS tube is grounded, and the gate is connected to the drain and the gate of the seventh NMOS tube.

6. The power-on reset circuit according to claim 1, characterized in that: The bandgap reference core module includes a first triode, a second triode, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor; the base and collector of the first triode and the second triode are both grounded, the emitter of the first triode is connected to one end of the third resistor, the other end of the third resistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the source of the sixth NMOS; The emitter of the second transistor is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to one end of the fourth resistor.

7. The power-on reset circuit according to claim 1, characterized in that: The comparison subcircuit includes a comparator, a seventh resistor and an eighth resistor; one end of the seventh resistor is connected to the power supply voltage, the other end is connected to one end of the eighth resistor and the first input end of the comparator, the other end of the eighth resistor is grounded, the second input end of the comparator is connected to the source of the sixth NMOS tube, and the output end is used to output a reset signal.

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