PHY chip access control method, apparatus and device, readable storage medium and program product

Abstract

The invention relates to a PHY chip access control method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: packaging an SDK calling function of the FPGA, wherein the SDK calling function comprises a PHY read-write function; the SDK calling function is added to the virtual file node attribute of each PHY chip; creating an independent virtual file node of each PHY chip according to the attribute of the virtual file node; and controlling PHY chip access based on the virtual file node. By adopting the method, the access flexibility of the PHY chip can be improved, the concurrent access of each PHY chip is realized, and the access efficiency of the PHY chip is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a PHY chip access control method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Art

[0002] The physical layer (PHY) chip is responsible for processing the physical layer data transmission between devices and is an important part of Ethernet switches. With the continuous expansion of network scale and the rapid growth of device connection requirements, the port density of switches is constantly increasing, and the number of PHY chips used in switches is also increasing accordingly.

[0003] In actual applications, when multiple PHY chips are used on a switch, concurrent access to the PHY chips is required in many scenarios, such as PHY firmware loading, etc. These scenarios require flexible reading and writing of PHY registers to shorten the time for initialization and reading and writing of PHY chips, allowing the system to start faster and respond to upper-layer calls.

[0004] However, the traditional way of reading and writing PHY registers requires calling PHY read and write functions from a software development kit (Software Development Kit, SDK), which has the problems of poor flexibility and difficulty in concurrent access. Summary of the invention

[0005] Based on this, it is necessary to provide a PHY chip access control method, apparatus, computer device, computer-readable storage medium and computer program product that can improve the flexibility of PHY chip access and support concurrent access in response to the above technical problems.

[0006] In a first aspect, the present application provides a PHY chip access control method, comprising:

[0007] Encapsulate the SDK calling function of FPGA, which includes PHY read and write functions;

[0008] Add SDK call functions to the virtual file node properties of each PHY chip;

[0009] Create independent virtual file nodes for each PHY chip based on the virtual file node attributes;

[0010] Control access to the PHY chip based on virtual file nodes.

[0011] In one embodiment, the SDK calling function of the packaged FPGA includes:

[0012] Get the parameters of the SDK calling function, which include PHY attribute parameters;

[0013] Extract PHY read and write functions from SDK;

[0014] The parameters of the SDK calling function and the PHY read and write functions are encapsulated together to obtain the SDK calling function.

[0015] In one embodiment, the above-mentioned creation of independent virtual file nodes for each PHY chip according to the virtual file node attributes includes:

[0016] The virtual file creation function is called to parse the virtual file node attributes and generate a virtual file directory and a virtual file node for each PHY chip.

[0017] In one embodiment, the virtual file creation function includes an object creation and addition function and an attribute group creation function;

[0018] The above-mentioned calling of the virtual file creation function parses the virtual file node attributes and generates the virtual file directory and virtual file node of each PHY chip, including:

[0019] Calling object creation and adding functions, creating object files of each PHY chip in the virtual file system, and adding parent objects to the object files of each PHY chip;

[0020] Calling an attribute group creation function to parse the virtual file node attributes and create an attribute group in the virtual file system;

[0021] An association relationship is established between the object file of the added parent object of each PHY chip and the attribute group, so as to obtain the virtual file directory and virtual file node of each PHY chip.

[0022] In one embodiment, the control of access to the PHY chip based on the virtual file node includes:

[0023] receiving an access instruction of a target PHY chip, wherein the access instruction carries an identifier of the target PHY chip;

[0024] The virtual file node of the target PHY chip is accessed according to the access instruction.

[0025] In one of the embodiments, the virtual file system architecture of the virtual file node includes any one of sysfs, procfs, devfs and tempfs architectures.

[0026] In a second aspect, the present application further provides a PHY chip access control device, including:

[0027] The encapsulation module is used to encapsulate the SDK calling function of the FPGA, and the SDK calling function includes the PHY read and write function;

[0028] Node attribute configuration module, used to add SDK call functions to the virtual file node attributes of each PHY chip;

[0029] A virtual file node creation module is used to create independent virtual file nodes for each PHY chip according to the virtual file node attributes;

[0030] The access control module is used to control the access to the PHY chip based on the virtual file node.

[0031] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the PHY chip access control method in any of the above embodiments when executing the computer program.

[0032] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the PHY chip access control method in any of the above embodiments.

[0033] In a fifth aspect, the present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the PHY chip access control method in any of the above embodiments.

[0034] The above-mentioned PHY chip access control method, device, computer equipment, computer-readable storage medium and computer program product encapsulate the SDK call function of FPGA, which includes PHY read and write functions; add the SDK call function to the virtual file node attributes of each PHY chip, create independent virtual file nodes for each PHY chip according to the virtual file node attributes; and control the access to the PHY chip based on the virtual file node. By encapsulating the SDK call function and creating independent virtual file nodes for each PHY chip, the PHY read and write functions can be mapped from the underlying SDK to the virtual file system. When the access to the PHY chip is controlled based on the virtual file node, the upper-layer application can directly interact with the virtual file node in the virtual file system without having to care about the underlying logic, thereby improving the flexibility of PHY chip access; and a corresponding virtual file node is independently created for each PHY chip, and the access process of each virtual file node is independent of each other, and the PHY chips are decoupled, so that concurrent access to each PHY chip can be achieved, thereby improving the access efficiency of the PHY chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 A schematic diagram of a flow chart of a PHY chip access control method in one embodiment;

[0037] Figure 2 A schematic diagram of a flow chart of the steps of calling a function of an SDK encapsulating an FPGA in an embodiment;

[0038] Figure 3 A flowchart of steps for creating independent virtual file nodes for each PHY chip according to virtual file node attributes in one embodiment;

[0039] Figure 4 A flowchart of steps for calling a virtual file creation function to parse the virtual file node attributes and generate virtual file directories and virtual file nodes for each PHY chip in one embodiment;

[0040] Figure 5 It is a flowchart of the steps of controlling access to a PHY chip based on a virtual file node in one embodiment;

[0041] Figure 6 A structural block diagram of a PHY chip access control device in an embodiment;

[0042] Figure 7 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0044] The PHY chip access control method provided in the embodiment of the present application can be applied to electronic devices. Among them, the electronic device has a built-in PHY chip. The types of electronic devices include but are not limited to various terminals, servers, network devices, etc. Among them, the terminal can be but is not limited to various personal computers, laptops, smart phones, tablets, Internet of Things devices and portable wearable devices, and the Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart car devices, projection devices, game devices, industrial Internet of Things devices, smart medical devices, etc. Portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc. The head-mounted device can be a virtual reality (VR) device, an augmented reality (AR) device, smart glasses, etc. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides cloud computing services. The network device can be but is not limited to various switches, gateway devices, etc.

[0045] In an exemplary embodiment, Figure 1 As shown, a PHY chip access control method is provided, comprising the following steps S202 to S208. Among them:

[0046] S202, encapsulate the SDK calling function of the FPGA, where the SDK calling function includes a PHY read and write function.

[0047] In this embodiment, a Field Programmable Gate Array (FPGA) chip is used to connect to the PHY chip, and the FPGA chip is used to control the physical layer data transmission. The FPGA chip can communicate with external devices through various physical media to realize the transmission and reception of Ethernet data. The programmable characteristics of FPGA enable it to flexibly customize the control and data processing of the PHY chip according to specific communication protocols and application requirements. Compared with dedicated communication chips such as ASIC, FPGA chips can quickly adapt to changes in protocols or realize some special communication functions. At the same time, the PHY chip focuses on the processing of physical layer signals, such as signal modulation and demodulation, digital-to-analog conversion, etc. The combination of the two can achieve efficient communication.

[0048] A software development kit (SDK) is a collection of development tools used by developers to create application software for specific software packages, software frameworks, hardware platforms, operating systems, etc. It mainly includes development tools (such as compilers, debuggers, linkers, etc.), library functions (functions and interfaces required for development), documentation (overall introduction of the SDK, functional features, how to use each tool and library function, API reference manual, etc.) and sample code, etc. SDK can help developers develop software on a specific platform, system or framework more efficiently.

[0049] In this embodiment, the FPGA SDK is a set of software tools for developing FPGA-related applications, which can help developers efficiently program and configure the FPGA, thereby realizing various customized digital circuit functions. When the FPGA chip is connected to the PHY chip, it is necessary to read and write the registers of the PHY chip to complete the configuration of these registers, so there needs to be a read and write function for the PHY chip in the FPGA SDK.

[0050] However, the PHY read and write functions in the SDK are low-level functions. Low-level functions generally lack abstraction and encapsulation and interact directly with hardware resources. If upper-level applications call low-level functions directly from the SDK, they need to have a deep understanding of the physical structure and working principle of the hardware. This knowledge is often complex and highly professional, so it is very difficult for upper-level users to call them. In addition, as low-level functions, PHY read and write functions usually lack built-in concurrency control mechanisms and are difficult to support concurrent access to PHY chips.

[0051] Therefore, in this embodiment, an SDK call function of an FPGA is first encapsulated, and the call function includes a PHY read and write function, that is, the underlying PHY read and write function is also packaged into the SDK call function, so as to prepare for mapping the PHY read and write function to the virtual file system. The virtual file system can present the kernel objects in the form of files and directories in the user space, which is equivalent to the interface connecting the kernel and the user space. Through the virtual file system, the user state program can easily access and control the object information in the kernel. Exemplary virtual file systems include but are not limited to sysfs, procfs, devfs, and tempfs.

[0052] S204, adding the SDK calling function to the virtual file node attributes of each PHY chip.

[0053] In this step, the above SDK calling function is added to the virtual file node attributes corresponding to each PHY chip respectively.

[0054] In one example, the virtual file node attributes corresponding to each PHY chip also include a node identifier, for example, PHY1, PHY2, PHY3...PHYn; further optionally, the virtual file node attributes also include a read function, a write function, a node read and write attributes (for example, users, groups, and others can read, but only the owner can write), a node index, etc.

[0055] S206: Create independent virtual file nodes for each PHY chip according to the virtual file node attributes.

[0056] Exemplarily, a virtual file creation function may be preset in the system kernel. After the virtual file node attributes of each PHY chip are prepared, the virtual file creation function may be called to parse the virtual file node attributes, thereby generating a virtual file directory and a virtual file node of each PHY chip. The virtual file nodes of each PHY chip may belong to the same virtual file directory.

[0057] Since each PHY chip has its own corresponding virtual file node, and the virtual file nodes are independent of each other, the access to the virtual file nodes is also independent of each other, achieving the purpose of decoupling between PHY chips.

[0058] S208, controlling access to the PHY chip based on the virtual file node.

[0059] The PHY chip access control method of this embodiment can map the PHY read and write functions from the underlying SDK to the virtual file system by encapsulating the SDK call function and creating independent virtual file nodes for each PHY chip. When the PHY chip access is controlled based on the virtual file node, the upper-layer application can directly interact with the virtual file node in the virtual file system without caring about the underlying logic, thereby improving the flexibility of PHY chip access; and a corresponding virtual file node is independently created for each PHY chip, and the access processes of each virtual file node are independent of each other, and the PHY chips are decoupled, so that concurrent access to each PHY chip can be achieved, thereby improving the access efficiency of the PHY chip.

[0060] In some embodiments, Figure 2 As shown, S202 includes S302 to S306. Among them:

[0061] S302, obtaining parameters of the SDK calling function, where the parameters of the SDK calling function include PHY attribute parameters.

[0062] The SDK call function is used to call underlying functions such as PHY read and write functions from the SDK. Therefore, the parameter type of the SDK call function must be consistent with the parameter type expected by the underlying function.

[0063] In this embodiment, the parameters of the SDK calling function obtained can be consistent with the parameter types expected by the PHY read and write functions. Exemplarily, the parameters of the SDK calling function at least partially include PHY attribute parameters, such as: device object parameters, which can represent the virtual file directory to which the PHY virtual file node belongs; device attribute parameters, which can include the name of the attribute, a function pointer for reading the attribute value, and a function pointer for writing the attribute value, and the target PHY can be found through the device attribute parameters; attribute value parameters, which are used to obtain the value passed in by the user for setting the attribute; data size parameters, such as the string length of the attribute value entered by the user, or can also represent the number of PHY registers that need to be written.

[0064] S304, extracting PHY read and write functions from the SDK.

[0065] It should be noted that the PHY read and write functions may include a PHY read function and a PHY write function. Extracting the PHY read and write functions from the SDK includes extracting the PHY read function and the PHY write function therefrom.

[0066] S306, encapsulate the parameters of the SDK calling function and the PHY read and write function together to obtain the SDK calling function.

[0067] The encapsulated SDK calling function has strict interface specifications, including parameter type, quantity, order and return value type, etc. Developers can implement it based on known programming techniques, which will not be elaborated here.

[0068] Taking the sysfs system architecture as an example, the following shows a coded example of an SDK calling function:

[0069] Static ssize_t bsp_phy_custom_set_attr(struct device*kobj,structdevice_attribute*da,const char*buf,size_t count)

[0070] {

[0071] Parse the parameters and call the FPGA SDK PHY write function

[0072] return count;

[0073] }

[0074] static ssize_t bsp_phy_custom_get_attr(struct device*kobj,structdevice_attribute*da,char*buf)

[0075] {

[0076] Parse the parameters and call the FPGA SDK PHY read function

[0077] return len;

[0078] }

[0079] In this embodiment, the SDK calling function is obtained by obtaining the parameters of the SDK calling function, the parameters of the SDK calling function include PHY attribute parameters, extracting the PHY read and write function from the SDK, and encapsulating the parameters of the SDK calling function and the PHY read and write function together. The SDK calling function can be adapted to the PHY read and write function, laying a foundation for the subsequent creation of virtual file nodes and access control of the PHY chip based on the virtual file node, ensuring that the PHY chip can be correctly accessed through the virtual file node.

[0080] For example, based on the above SDK calling function code, the coding example of step S204 is as follows:

[0081] static SENSOR_DEVICE_ATTR(phy1,(S_IRUGO|S_IWUSR),bsp_phy_custom_get_attr,bsp_phy_custom_set_attr,PHY1);

[0082] static SENSOR_DEVICE_ATTR(phy2,(S_IRUGO|S_IWUSR),bsp_phy_custom_get_attr,bsp_phy_custom_set_attr,PHY2);

[0083] static SENSOR_DEVICE_ATTR(phy3,(S_IRUGO|S_IWUSR),bsp_phy_custom_get_attr,bsp_phy_custom_set_attr,PHY3);

[0084] static SENSOR_DEVICE_ATTR(phy4,(S_IRUGO|S_IWUSR),bsp_phy_custom_get_attr,bsp_phy_custom_set_attr,PHY4);

[0085] static SENSOR_DEVICE_ATTR(phy5,(S_IRUGO|S_IWUSR),bsp_phy_custom_get_attr,bsp_phy_custom_set_attr,PHY5);

[0086] static SENSOR_DEVICE_ATTR(phy6,(S_IRUGO|S_IWUSR),bsp_phy_custom_get_attr,bsp_phy_custom_set_attr,PHY6);

[0087] static SENSOR_DEVICE_ATTR(phy7,(S_IRUGO|S_IWUSR),bsp_phy_custom_get_attr,bsp_phy_custom_set_attr,PHY7);

[0088] static SENSOR_DEVICE_ATTR(phy8,(S_IRUGO|S_IWUSR),bsp_phy_custom_get_attr,bsp_phy_custom_set_attr,PHY8);

[0089] …

[0090] static struct attribute*phy_custom_attributes[]=

[0091] {

[0092] &sensor_dev_attr_phy1.dev_attr.attr,

[0093] &sensor_dev_attr_phy2.dev_attr.attr,

[0094] &sensor_dev_attr_phy3.dev_attr.attr,

[0095] &sensor_dev_attr_phy4.dev_attr.attr,

[0096] &sensor_dev_attr_phy5.dev_attr.attr,

[0097] &sensor_dev_attr_phy6.dev_attr.attr,

[0098] &sensor_dev_attr_phy7.dev_attr.attr,

[0099] &sensor_dev_attr_phy8.dev_attr.attr,

[0100] …

[0101] NULL

[0102] };

[0103] static const struct attribute_group phy_custom_attr_group=

[0104] {

[0105] .attrs=phy_custom_attributes,

[0106] }

[0107] The above example shows that when there are at least 8 PHY chips, the SDK call function is added to the virtual file node attributes of at least 8 PHY chips. Of course, the number of PHY chips can be more or less than 8, and the code can be adjusted accordingly.

[0108] In an exemplary embodiment, Figure 3 As shown, step S206 includes:

[0109] S402, calling a virtual file creation function to parse the virtual file node attributes, and generating a virtual file directory and a virtual file node for each PHY chip.

[0110] Exemplarily, the virtual file creation function may be a nested function, including an external function and an internal function, wherein the external function is used to call the internal function, and the internal function performs more specific operations.

[0111] In one example, the internal functions or virtual file creation functions may include object creation and addition functions and attribute group creation functions. Figure 4 As shown, step S402 includes steps S502 to S506.

[0112] in:

[0113] S502, calling an object creation and addition function, creating an object file of each PHY chip in the virtual file system, and adding a parent object to the object file of each PHY chip.

[0114] The object creation and addition functions described in this step are used to create object files for each PHY chip in the virtual file system, and add parent objects to the object files of each PHY chip, so that they can be mapped to the form of directories and file nodes in the virtual file system. The parent object has an inheritance relationship with the object file, and the parent object here can be understood as the directory to which each file node in the virtual file system belongs. The object files of each PHY chip can have a common parent object, that is, these object files can exist in the same directory.

[0115] S504, calling an attribute group creation function, parsing the virtual file node attributes, and creating an attribute group in the virtual file system.

[0116] By using the attribute group creation function, the virtual file node attributes with the SDK call function added in the above embodiment can be parsed, and the parsed attributes can be integrated to form an attribute set, that is, an attribute group can be obtained. The attribute group can include detailed attribute contents such as node identification, read function, write function, node read and write attributes, node index, etc.

[0117] S506 , establishing an association relationship between the object file of each PHY chip to which the parent object has been added and the attribute group, and obtaining a virtual file directory and a virtual file node of each PHY chip.

[0118] Exemplarily, the virtual file system architecture of the virtual file node includes any one of sysfs, procfs, devfs and tempfs architectures. Taking the sysfs system architecture as an example, the virtual file directory and virtual file node of the PHY chip can be in the form of root@sonic: / sys / phy / phy1, / sys / phy / phy2... / sys / phy / phyn, where phy1, phy2,...phyn represent the identifiers of n PHY chips, and these virtual file nodes all belong to the file directory / sys / phy. For other types of virtual file system architectures, the corresponding virtual file directories and file nodes can be constructed according to the format requirements of the system architecture of that type.

[0119] Following the code examples provided in the above embodiments, a code example for creating independent virtual file nodes for each PHY chip is also shown here:

[0120] int create_phy_kobjs(void)

[0121] {

[0122] int ret = ERROR_SUCCESS;

[0123] kobj_phy=kobject_create_and_add("phy",kernel_kobj->parent);

[0124] CHECK_IF_ERROR(-ENOMEM,ret,kobj_phy,"kobj_switch create falled!\n");

[0125] ret=sysfs_create_group(kobj_phy,&phy_custom_attr_group);

[0126] CHECK_IF_ERROR(ret,"create phy group failed");

[0127] return ret;

[0128] }

[0129] In this embodiment, the creation of virtual file directories and virtual file nodes of each PHY chip is completed by calling object creation and addition functions and attribute group creation functions. The cooperation of the two functions makes the creation process more efficient. In addition, the virtual file nodes are independent of each other, which realizes the decoupling between PHY chips and can meet the concurrent access requirements of each PHY chip.

[0130] In an exemplary embodiment, Figure 5 As shown, S208 includes S602 to S604. Among them:

[0131] S602: Receive an access instruction for a target PHY chip, where the access instruction carries an identifier of the target PHY chip.

[0132] Specifically, the access instruction for the target PHY chip may be an access instruction from an upper layer application or a user mode program, such as a read and write instruction for the PHY chip. The access instruction carries an identifier of the target PHY chip.

[0133] S604: Access the virtual file node of the target PHY chip according to the access instruction.

[0134] Since the access instruction carries the identifier of the target PHY chip, the system can find the corresponding virtual file node and read or write the attributes of the virtual file node according to the data in the access instruction, thereby realizing access control to the PHY chip.

[0135] In this embodiment, an access instruction for a target PHY chip is received, and the corresponding virtual file node is located and the reading and writing of the virtual file node attributes are completed according to the data carried in the access instruction. The upper-layer application directly interacts with the virtual file node in the virtual file system without caring about the underlying logic, thereby improving the flexibility of PHY chip access; since each virtual file node is independent of each other, concurrent access to each PHY chip can be achieved, thereby improving the access efficiency of the PHY chip.

[0136] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0137] Based on the same inventive concept, an embodiment of the present application also provides a PHY chip access control device. The implementation solution for solving the problem provided by the device is similar to the implementation solution recorded in the above method. Therefore, the specific limitations in one or more PHY chip access control device embodiments provided below can refer to the limitations on the PHY chip access control method above, and will not be repeated here.

[0138] In an exemplary embodiment, Figure 6 As shown, a PHY chip access control device 700 is provided, comprising: an encapsulation module 701, a node attribute configuration module 702, a virtual file node creation module 703 and an access control module 704, wherein:

[0139] The encapsulation module 701 is used to encapsulate the SDK calling function of the FPGA, wherein the SDK calling function includes a PHY read and write function;

[0140] The node attribute configuration module 702 is used to add the SDK call function to the virtual file node attribute of each PHY chip;

[0141] A virtual file node creation module 703, used to create an independent virtual file node for each PHY chip according to the virtual file node attributes;

[0142] The access control module 704 is used to control the access to the PHY chip based on the virtual file node.

[0143] In an exemplary embodiment, the encapsulation module 701 is also used to obtain parameters of the SDK calling function, the parameters of the SDK calling function include PHY attribute parameters; extract the PHY read and write function from the SDK; and encapsulate the parameters of the SDK calling function and the PHY read and write function together to obtain the SDK calling function.

[0144] In an exemplary embodiment, the virtual file node creation module 703 is further configured to call a virtual file creation function to parse the virtual file node attributes and generate a virtual file directory and a virtual file node for each PHY chip.

[0145] In one embodiment, the virtual file creation function may include an object creation and addition function and an attribute group creation function. The virtual file node creation module 703 is also used to call the object creation and addition function, create object files for each PHY chip in the virtual file system, and add parent objects to the object files of each PHY chip; call the attribute group creation function, parse the virtual file node attributes, and create an attribute group in the virtual file system; establish an association relationship between the object file of each PHY chip with the added parent object and the attribute group, and obtain the virtual file directory and virtual file node of each PHY chip.

[0146] In an exemplary embodiment, the access control module 704 is further configured to receive an access instruction for a target PHY chip, wherein the access instruction carries an identifier of the target PHY chip; and access the virtual file node of the target PHY chip according to the access instruction.

[0147] Each module in the above-mentioned PHY chip access control device can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0148] In an exemplary embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 7As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store operating system data, upper-layer application data, network data and / or hardware device related data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a PHY chip access control method is implemented.

[0149] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0150] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the steps of the PHY chip access control method in any of the above embodiments are implemented.

[0151] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the PHY chip access control method in any of the above embodiments are implemented.

[0152] In one embodiment, a computer program product is provided, including a computer program, which implements the steps of the PHY chip access control method in any of the above embodiments when executed by a processor.

[0153] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0154] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0156] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0157] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A PHY chip access control method, characterized in that: The method comprises: Encapsulate the SDK calling function of the FPGA, wherein the SDK calling function includes a PHY read and write function; Add the SDK calling function to the virtual file node attributes of each PHY chip; Creating independent virtual file nodes for each PHY chip according to the virtual file node attributes; Access to the PHY chip is controlled based on the virtual file node.

2. The method according to claim 1, characterized in that The SDK calling function of the packaged FPGA includes: Obtaining parameters of the SDK calling function, where the parameters of the SDK calling function include PHY attribute parameters; Extract PHY read and write functions from SDK; The parameters of the SDK calling function and the PHY read and write function are encapsulated together to obtain the SDK calling function.

3. The method according to claim 1, characterized in that The step of creating independent virtual file nodes for each PHY chip according to the virtual file node attributes includes: The virtual file creation function is called to parse the virtual file node attributes and generate the virtual file directory and virtual file node of each PHY chip.

4. The method according to claim 3, characterized in that: The virtual file creation function includes an object creation and addition function and an attribute group creation function; The calling of the virtual file creation function to parse the virtual file node attributes and generate the virtual file directory and virtual file node of each PHY chip includes: Calling the object creation and addition function to create an object file for each PHY chip in the virtual file system and adding a parent object to the object file for each PHY chip; Calling the attribute group creation function, parsing the virtual file node attributes, and creating an attribute group in the virtual file system; An association relationship is established between the object file of each PHY chip to which the parent object has been added and the attribute group, so as to obtain a virtual file directory and a virtual file node of each PHY chip.

5. The method according to claim 1, characterized in that The controlling the access to the PHY chip based on the virtual file node includes: receiving an access instruction of a target PHY chip, wherein the access instruction carries an identifier of the target PHY chip; The virtual file node of the target PHY chip is accessed according to the access instruction.

6. The method according to any one of claims 1 to 5, characterized in that: The virtual file system architecture of the virtual file node includes any one of sysfs, procfs, devfs and tempfs architectures.

7. A PHY chip access control device, characterized in that: The device comprises: A packaging module, used to package the SDK calling function of the FPGA, wherein the SDK calling function includes a PHY read and write function; A node attribute configuration module, used to add the SDK call function to the virtual file node attributes of each PHY chip; A virtual file node creation module, used to create independent virtual file nodes for each PHY chip according to the virtual file node attributes; An access control module is used to control access to the PHY chip based on the virtual file node.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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