LDMOS device and manufacturing method thereof
In the manufacturing method of LDMOS devices, using a photocoat to pattern the side wall material layer and form a composite field plate, the problem of the impact of silicon nitride thin film accumulation and LDMOS process steps on the CMOS devices is solved, and the process window optimization and yield improvement are achieved.
Patent Information
- Application Number
- CN202510077208.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-17
- Publication Date
- 2025-05-09
AI Technical Summary
In the 55nm BCD process, the silicon nitride film will accumulate between the polysilicon during the deposition process, resulting in unclear subsequent etching, increasing process difficulty, and adding LDMOS process steps alone will pose a challenge to the gate oxygen growth control of CMOS devices.
In the manufacturing method of the LDMOS device, a photocoat is added after the side wall material layer is formed, and the side wall material layer is patterned to obtain the first gate side wall, the second gate side wall, the first field plate and the second field plate, and a thinner silicide barrier layer is formed in the SAB stage to form a composite field plate to optimize the SAB process window.
This method effectively expands the SAB process window, reduces the number of etching and cleaning of oxides, prevents the occurrence of Divot defects or reduces its degree, and is compatible with the CMOS device process in the core area, reduces the difficulty of controlling gate oxygen growth of CMOS devices, and improves yield.
Smart Images
Figure CN119967838A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductors and relates to an LDMOS device and a manufacturing method thereof. Background Art
[0002] Field plate technology is a method for regulating planar electric fields to increase the breakdown voltage of devices. BCD process (Bipolar-CMOS-DMOS) is an integrated process technology that integrates three different semiconductor manufacturing technologies: bipolar transistors (Bipolar), complementary metal oxide semiconductors (CMOS) and double diffused metal oxide semiconductors (DMOS) on the same chip. The design goal of this process is to achieve the functional integration of digital circuits, analog circuits and power drive circuits to meet the requirements of high speed, low power consumption, high precision and high power drive. Among them, Bipolar (bipolar transistor) is mainly used in analog circuits, has high mobility and low noise characteristics, and performs well in high-speed and high-precision applications. CMOS (complementary metal oxide semiconductor) is a low-power digital circuit manufacturing technology, composed of PMOS (positive metal oxide semiconductor field effect transistor) and NMOS (negative metal oxide semiconductor field effect transistor). It is widely used in digital logic circuits due to its low power consumption, low noise and radiation resistance. DMOS (double diffused metal oxide semiconductor) is mainly used in the design of power amplifier and drive circuits, and has high power drive capability and low switching loss characteristics.
[0003] In the 0.18μm BCD process, the deposition thickness is about The silicon nitride film is used as a salicide block (SAB) to form the SAB region, and as a field plate to increase the device's insulation breakdown voltage (Breakdown, Voltage). When the process node is reduced to 55nm, the silicon nitride film of this thickness will accumulate between the polysilicon (poly) of the small-sized device during the deposition process, making the subsequent etching unable to etch cleanly. Therefore, in the 55nm BCD process, a mask is added during the gate oxide growth stage to obtain a thick oxide layer as a field plate. However, adding a process step to the laterally diffused metal oxide semiconductor (LDMOS) in the front-end process will increase the process difficulty of controlling the gate oxide growth of the CMOS device in the core area.
[0004] Therefore, how to provide an LDMOS device and a manufacturing method thereof to optimize the SAB process window and be compatible with the CMOS device process in the core area to improve the yield has become an important technical problem that needs to be solved urgently by those skilled in the art.
[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an LDMOS device and a manufacturing method thereof, so as to solve the problem that the manufacturing method of the prior LDMOS device has a small process window and a high process difficulty.
[0007] To achieve the above object and other related objects, the present invention provides a method for manufacturing an LDMOS device, comprising the following steps:
[0008] Providing a substrate, the substrate comprising a drift layer and a body region located in the drift layer;
[0009] forming a first gate structure and a second gate structure spaced apart from each other on the substrate, wherein the first gate structure is located on the drift layer at one side of the body region and extends to the body region, and the second gate structure is located on the drift layer at the other side of the body region and extends to the body region;
[0010] Forming a spacer material layer on the substrate, wherein the spacer material layer covers the first gate structure and the second gate structure;
[0011] Providing a photomask, and patterning the spacer material layer based on the photomask to obtain a first gate spacer, a second gate spacer, a first field plate, and a second field plate, wherein the first gate spacer is located on both side walls of the first gate structure, the second gate spacer is located on both side walls of the second gate structure, the first field plate is located on the drift layer on a side of the first gate structure away from the second gate structure and connected to the bottom of the first gate spacer, and the second field plate is located on the drift layer on a side of the second gate structure away from the first gate structure and connected to the bottom of the second gate spacer;
[0012] forming a source region, a first drain region and a second drain region, wherein the source region is located on the upper surface layer of the body region between the first gate sidewall and the second gate sidewall, the first drain region is located on the upper surface layer of the drift layer on one side of the first field plate, and the second drain region is located on the upper surface layer of the drift layer on one side of the second field plate;
[0013] forming a first silicide barrier layer and a second silicide barrier layer, wherein the first silicide barrier layer is located on the first field plate, and the second silicide barrier layer is located on the second field plate;
[0014] A first conductive column and a second conductive column are formed, wherein the first conductive column is located on the first silicide blocking layer, and the second conductive column is located on the second silicide blocking layer.
[0015] Optionally, the first silicide blocking layer further extends to a sidewall of the first gate spacer, and the second silicide blocking layer further extends to a sidewall of the second gate spacer.
[0016] Optionally, both the first conductive pillar and the second conductive pillar are electrically connected to the source region.
[0017] Optionally, the sidewall material layer includes a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer stacked in sequence, the first silicon oxide layer has a thickness range of 20 to 100 angstroms, the silicon nitride layer has a thickness range of 100 to 300 angstroms, and the second silicon oxide layer has a thickness range of 220 to 420 angstroms.
[0018] Optionally, both the first silicide barrier layer and the second silicide barrier layer include silicon nitride layers, the first silicide barrier layer has a thickness ranging from 150 to 300 angstroms, and the second silicide barrier layer has a thickness ranging from 150 to 300 angstroms.
[0019] Optionally, the total thickness of the first silicide barrier layer and the first field plate is in the range of 600 to 100 angstroms, and the total thickness of the second silicide barrier layer and the second field plate is in the range of 600 to 100 angstroms.
[0020] Optionally, the substrate includes an LDMOS device region, a core device region, and an input-output device region divided according to a preset rule, and the first gate structure and the second gate structure are both located in the LDMOS device region.
[0021] Optionally, the first gate structure includes a first gate dielectric layer and a first polysilicon layer located on the first gate dielectric layer, and the second gate structure includes a second gate dielectric layer and a second polysilicon layer located on the second gate dielectric layer.
[0022] The present invention also provides an LDMOS device, comprising:
[0023] A substrate, comprising a drift layer and a body region located in the drift layer;
[0024] A first gate structure and a second gate structure are arranged on the substrate at intervals, the first gate structure is located on the drift layer on one side of the body region and extends to the body region, and the second gate structure is located on the drift layer on the other side of the body region and extends to the body region;
[0025] A first gate sidewall, located on two side walls of the first gate structure;
[0026] A second gate sidewall, located on two side walls of the second gate structure;
[0027] A first field plate is located on the drift layer at a side of the first gate structure away from the second gate structure and is integrally connected to a bottom of the first gate sidewall;
[0028] A second field plate is located on the drift layer at a side of the second gate structure away from the first gate structure and is integrally connected to a bottom of the second gate sidewall;
[0029] A source region located at an upper surface layer of the body region between the first gate spacer and the second gate spacer;
[0030] A first drain region, located on an upper surface layer of the drift layer at one side of the first field plate;
[0031] A second drain region, located on an upper surface layer of the drift layer at one side of the second field plate;
[0032] A first silicide blocking layer, located on the first field plate;
[0033] A second silicide blocking layer, located on the second field plate;
[0034] A first conductive pillar, located on the first silicide barrier layer;
[0035] The second conductive column is located on the second silicide barrier layer.
[0036] Optionally, the first silicide blocking layer further extends to a sidewall of the first gate spacer, and the second silicide blocking layer further extends to a sidewall of the second gate spacer.
[0037] Optionally, both the first conductive pillar and the second conductive pillar are electrically connected to the source region.
[0038] Optionally, the sidewall material layer includes a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer stacked in sequence, the first silicon oxide layer has a thickness range of 20 to 100 angstroms, the silicon nitride layer has a thickness range of 100 to 300 angstroms, and the second silicon oxide layer has a thickness range of 220 to 420 angstroms.
[0039] Optionally, both the first silicide barrier layer and the second silicide barrier layer include silicon nitride layers, the first silicide barrier layer has a thickness ranging from 150 to 300 angstroms, and the second silicide barrier layer has a thickness ranging from 150 to 300 angstroms.
[0040] Optionally, the total thickness of the first silicide barrier layer and the first field plate is in the range of 600 to 100 angstroms, and the total thickness of the second silicide barrier layer and the second field plate is in the range of 600 to 100 angstroms.
[0041] Optionally, the substrate includes an LDMOS device region, a core device region, and an input-output device region divided according to a preset rule, and the first gate structure and the second gate structure are both located in the LDMOS device region.
[0042] Optionally, the first gate structure includes a first gate dielectric layer and a first polysilicon layer located on the first gate dielectric layer, and the second gate structure includes a second gate dielectric layer and a second polysilicon layer located on the second gate dielectric layer.
[0043] As described above, in the manufacturing method of the LDMOS device of the present invention, a photomask is added after forming the sidewall material layer, and the sidewall material layer is patterned based on the photomask to obtain the first gate sidewall and the second gate sidewall, and a part of the sidewall material layer is retained as the first field plate and the second field plate, and then the first silicide barrier layer and the second silicide barrier layer are formed in the SAB stage, wherein the first silicide barrier layer is located on the first field plate to form a first composite field plate together with the first field plate, and the second silicide barrier layer is located on the second field plate to form a second composite field plate together with the second field plate. Since the thickness of the silicide barrier layer required in the composite field plate is relatively small, the SAB process window is optimized, and the present invention adopts the sidewall material layer as the first field plate and the second field plate to reduce at least one etching and cleaning of the oxide, which helps to ensure the step height of the STI, prevent the generation of divots or prevent the increase of the divot degree, so that it can be compatible with the CMOS device process in the core device area, reduce the difficulty of controlling the gate oxide growth of the CMOS device in the core device area, and help improve the yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] Figure 1 The process flow chart of the manufacturing method of the LDMOS device of the present invention is shown.
[0045] Figure 2 A schematic structural diagram showing a substrate provided for the method for manufacturing an LDMOS device of the present invention.
[0046] Figure 3 The schematic diagram shows a structure obtained after forming a first gate structure and a second gate structure according to the manufacturing method of the LDMOS device of the present invention.
[0047] Figure 4 It is a schematic diagram showing the structure obtained after forming a spacer material layer in the manufacturing method of the LDMOS device of the present invention.
[0048] Figure 5 It is a schematic diagram showing the structure obtained after patterning the spacer material layer in the manufacturing method of the LDMOS device of the present invention.
[0049] Figure 6 It is a schematic diagram showing the structure obtained after forming the source and drain regions according to the manufacturing method of the LDMOS device of the present invention.
[0050] Figure 7 The schematic diagram shows the structure obtained after forming the first silicide barrier layer and the second silicide barrier layer in the manufacturing method of the LDMOS device of the present invention.
[0051] Figure 8 It is a schematic diagram showing a structure obtained after forming a first conductive pillar and a second conductive pillar according to the manufacturing method of the LDMOS device of the present invention.
[0052] Fig. 9 FIG. 1 is a schematic structural diagram of an LDMOS device according to an embodiment of the present invention.
[0053] Description of Reference Numerals
[0054] S1~S7 Step 101 Drift layer 102 Body region
[0055] 103 N-type layer 104 P-type inversion layer 105 First gate structure 1051 First gate dielectric layer 1052 First polysilicon layer 106 Second gate structure 1061 Second gate dielectric layer 1062 Second polysilicon layer 107 Spacer material layer 1071 First silicon oxide layer 1072 Silicon nitride layer 1073 Second silicon oxide layer 107a First gate spacer 107b Second gate spacer 107c First field plate 107d Second field plate 108 Source region
[0056] 109 first drain region 110 second drain region 111 first silicide blocking layer 112 second silicide blocking layer 113 first conductive pillar 114 second conductive pillar
[0057] 115, 116 Trench isolation structure A LDMOS device area B Core device area C Input and output device area DETAILED DESCRIPTION
[0058] In a device structure using a BCD process, LDMOS uses a SAB field plate, and the SAB field plate has a thickness of about A silicon nitride film of such thickness will accumulate between the polysilicon of a small-sized device during the deposition process, and cannot be etched cleanly during the subsequent etching process. In another device structure using the BCD process, the LDMOS uses a thick oxide field plate, wherein, in the gate oxide growth stage of the LDMOS, a thick oxide layer is first grown and exposed, developed and etched, and the remaining thick oxide portion is used as the thick oxide field plate, and then a thin oxide layer is grown and exposed, developed and etched, and the remaining thin oxide portion is used as the gate oxide of the LDMOS. These two etching and cleaning of the oxide will reduce the step height of the shallow trench isolation structure (STI) in the core area and the input / output (IO) area, and will easily cause Divot (depression) defects or increase the degree of Divot defects, which will increase the process difficulty of controlling the gate oxide growth of the CMOS device in the core area.
[0059] Specifically, the Divot defect mainly refers to a concave area formed by excessive corrosion of the oxide layer filled at the corner edge of the STI interface due to local stress concentration during the STI process. The step high height of STI refers to the height difference between the STI area and the active area. The Divot phenomenon may cause the polysilicon constituting the gate to fill the Divot area when the transistor gate crosses the STI and the active area, generating a parasitic device. The turn-on voltage of this parasitic transistor is much lower than that of the normal transistor originally designed, thereby generating additional leakage during normal transistor operation. In addition, the Divot phenomenon may also cause problems such as residue defects to occur more easily when the transistor gate is corroded.
[0060] The inventors of the present application have improved the manufacturing method of LDMOS devices through a lot of analysis and research, wherein the process flow before the sidewall (spacer) can be unchanged or adjusted as needed, but a photomask is added in the sidewall etching stage to retain the sidewall (SiO2) in the position (field plate) where the thick oxide layer was originally made. 2 / Si 3 N 4 / SiO 2 Structure), on this basis, a thinner SAB layer is grown, and finally connected to the source through a tungsten (W) through-hole. Among them, the thinner SAB layer helps to expand the SAB process window, and the composite field plate structure of the sidewall material + SAB can not only maintain the BV of the device, but also be compatible with the CMOS device process in the core area, which is conducive to improving the yield.
[0061] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0062] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.
[0063] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.
[0064] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.
[0065] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
[0066] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0067] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0068] The present invention provides a method for manufacturing an LDMOS device. Figure 1 , shown as a process flow chart of the method, comprising the following steps:
[0069] S1: providing a substrate, wherein the substrate comprises a drift layer and a body region located in the drift layer;
[0070] S2: forming a first gate structure and a second gate structure spaced apart from each other on the substrate, wherein the first gate structure is located on the drift layer on one side of the body region and extends to the body region, and the second gate structure is located on the drift layer on the other side of the body region and extends to the body region;
[0071] S3: forming a spacer material layer on the substrate, wherein the spacer material layer covers the first gate structure and the second gate structure;
[0072] S4: providing a photomask, and patterning the spacer material layer based on the photomask to obtain a first gate spacer, a second gate spacer, a first field plate, and a second field plate, wherein the first gate spacer is located on both side walls of the first gate structure, the second gate spacer is located on both side walls of the second gate structure, the first field plate is located on the drift layer on a side of the first gate structure away from the second gate structure and connected to the bottom of the first gate spacer, and the second field plate is located on the drift layer on a side of the second gate structure away from the first gate structure and connected to the bottom of the second gate spacer;
[0073] S5: forming a source region, a first drain region and a second drain region, wherein the source region is located on the upper surface layer of the body region between the first gate sidewall spacer and the second gate sidewall spacer, the first drain region is located on the upper surface layer of the drift layer on one side of the first field plate, and the second drain region is located on the upper surface layer of the drift layer on one side of the second field plate;
[0074] S6: forming a first silicide barrier layer and a second silicide barrier layer, wherein the first silicide barrier layer is located on the first field plate, and the second silicide barrier layer is located on the second field plate;
[0075] S7: forming a first conductive column and a second conductive column, wherein the first conductive column is located on the first silicide blocking layer, and the second conductive column is located on the second silicide blocking layer.
[0076] The above steps are described in detail below with reference to the structure diagram.
[0077] First see Figure 2 , perform the step S1: provide a substrate, the substrate comprising a drift layer 101 and a body region 102 located in the drift layer 101 .
[0078] As an example, the drift layer 101 may be of N-type or P-type, and the body region 102 has a conductivity type opposite to that of the drift layer 101 .
[0079] In some embodiments, the drift layer 101 is N-type, the body region 102 is P-type, and the substrate further includes an N-type layer 103 and a P-type inversion layer 104 , the P-type inversion layer 104 is located on the N-type layer 103 , and the drift layer 101 is located on the P-type inversion layer 104 .
[0080] As an example, the N-type layer 103 may be formed by a deep N-well (DNW) or an N-type buried layer (NBL) in a P-type substrate.
[0081] Please see again Figure 3 , perform the step S2: form a first gate structure 105 and a second gate structure 106 that are spaced apart on the substrate, wherein the first gate structure 105 is located on the drift layer 101 on one side of the body region 102 and extends to the body region 102, and the second gate structure 106 is located on the drift layer 101 on the other side of the body region 102 and extends to the body region 102.
[0082] As an example, the first gate structure 105 includes a first gate dielectric layer 1051 and a first polysilicon layer 1052 located on the first gate dielectric layer 1051 , and the second gate structure 106 includes a second gate dielectric layer 1061 and a second polysilicon layer 1062 located on the second gate dielectric layer 1061 .
[0083] As an example, both the first gate dielectric layer 1051 and the second gate dielectric layer 1061 are made of silicon oxide layers.
[0084] As an example, forming the first gate structure 105 and the second gate structure 106 includes the following steps:
[0085] (1) forming a gate dielectric material layer by thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods;
[0086] (2) forming a polysilicon layer on the gate dielectric material layer by chemical vapor deposition, physical vapor deposition or other suitable methods;
[0087] (3) forming a mask layer on the polysilicon layer;
[0088] (4) patterning the mask layer;
[0089] (5) etching the polysilicon layer based on the patterned mask layer to obtain the first gate structure 105 and the second gate structure 106;
[0090] (6) Removing the mask layer.
[0091] Please see again Figure 4, perform the step S3: use chemical vapor deposition, physical vapor deposition or other suitable methods to form a spacer material layer 107 on the substrate, and the spacer material layer 107 covers the first gate structure 105 and the second gate structure 106.
[0092] As an example, the spacer material layer 107 includes a first silicon oxide layer 1071 , a silicon nitride layer 1072 and a second silicon oxide layer 1073 stacked in sequence.
[0093] As an example, the thickness range of the first silicon oxide layer 1071 is The thickness of the silicon nitride layer 1072 ranges from 100 to 300 angstroms, and the thickness of the second silicon oxide layer 1073 ranges from 220 to 420 angstroms. For example, in one embodiment, the thickness of the first silicon oxide layer 1071 is 60 angstroms, the thickness of the silicon nitride layer 1072 is 200 angstroms, and the thickness of the second silicon oxide layer 1073 is 320 angstroms.
[0094] Please see again Figure 5 , performing the step S4: providing a photomask, and patterning the spacer material layer 107 based on the photomask to obtain a first gate spacer 107a, a second gate spacer 107b, a first field plate 107c and a second field plate 107d.
[0095] As an example, patterning the spacer material layer 107 based on the photomask includes the following steps:
[0096] (1) coating a photoresist layer on the sidewall material layer 107;
[0097] (2) exposing the photoresist layer based on the photomask;
[0098] (3) developing the exposed photoresist layer to obtain a patterned photoresist layer;
[0099] (4) etching the spacer material layer 107 using the patterned photoresist layer as a mask to obtain the first gate spacer 107a, the second gate spacer 107b, the first field plate 107c and the second field plate 107d;
[0100] (5) Removing the photoresist layer.
[0101] Specifically, the first gate side wall 107a is located on the two side walls of the first gate structure 105, the second gate side wall 107b is located on the two side walls of the second gate structure 106, the first field plate 107c is located on the drift layer 101 on the side of the first gate structure 105 away from the second gate structure 106 and is connected to the bottom of the first gate side wall 107a, and the second field plate 107d is located on the drift layer 101 on the side of the second gate structure 106 away from the first gate structure 105 and is connected to the bottom of the second gate side wall 107b.
[0102] It should be noted that in the conventional sidewall etching stage, no mask is used, but etching is directly performed to form the sidewall. The present invention improves the manufacturing method of the LDMOS device, keeps the process flow before the sidewall consistent, adds a mask in the sidewall etching stage, and retains the sidewall material layer (e.g., SiO 2 / Si 3 N 4 / SiO 2 structure) as the first field plate 107c and the second field plate 107d.
[0103] Please see again Figure 6 , perform the step S5: use ion implantation or other suitable methods to form a source region 108, a first drain region 109 and a second drain region 110, the source region 108 is located on the upper surface layer of the body region 102 between the first gate sidewall 107a and the second gate sidewall 107b, the first drain region 109 is located on the upper surface layer of the drift layer 101 on the side of the first field plate 107c, and the second drain region 110 is located on the upper surface layer of the drift layer 101 on the side of the second field plate 107d.
[0104] Specifically, the conductivity type of the source region 108, the first drain region 109 and the second drain region 110 is the same and opposite to the conductivity type of the body region 102. For example, in some embodiments, the drift layer 101 is N-type, the body region 102 is P-type, and the source region 108, the first drain region 109 and the second drain region 110 are all N-type.
[0105] Specifically, one end of the first field plate 107c away from the first gate structure 105 defines an ion injection boundary on one side of the first drain region 109, one end of the second field plate 107d away from the second gate structure 106 defines an ion injection boundary on one side of the second drain region 110, the opposite sides of the first gate sidewall 107a and the second gate sidewall 107b define an ion injection boundary of the source region 108, the overlapping area of the first gate structure 105 and the body region 102 defines a first channel region, and the overlapping area of the second gate structure 106 and the body region 102 defines a second channel region.
[0106] Please see again Figure 7 , performing the step S6: forming a first silicide barrier layer 111 and a second silicide barrier layer 112, wherein the first silicide barrier layer 111 is located on the first field plate 107c, and the second silicide barrier layer 112 is located on the second field plate 107d.
[0107] As an example, forming the first silicide barrier layer 111 and the second silicide barrier layer 112 includes the following steps:
[0108] (1) depositing a silicide barrier material layer of a certain thickness;
[0109] (2) coating a photoresist layer on the silicide blocking material layer;
[0110] (3) performing photolithography processes such as exposure and development to obtain a patterned photoresist layer;
[0111] (4) etching the silicide blocking material layer using the patterned photoresist layer as a mask to obtain the first silicide blocking layer 111 and the second silicide blocking layer 112;
[0112] (5) Removing the photoresist layer.
[0113] Specifically, the silicide blocking layer (SAB) is located in the area where metal silicide (Salicide) does not need to be formed, and is used to block the growth of metal silicide. Usually, metal silicide is formed on the gate surface, source surface and drain surface of the CMOS device to reduce the contact resistance between the contact plug. In the present invention, the silicide blocking layer in the SAB process is used to form the first silicide blocking layer 111 and the second silicide blocking layer 112 in the LDMOS device area, wherein the first silicide blocking layer 111 is located on the first field plate 107c to form a first composite field plate together with the first field plate 107c, and the second silicide blocking layer 112 is located on the second field plate 107d to form a second composite field plate together with the second field plate 107d.
[0114] Specifically, compared with a simple silicide barrier layer field plate, the thickness of the silicide barrier layer required in the composite field plate of the present invention is relatively small, which helps to expand the SAB process window.
[0115] As an example, the first silicide barrier layer 111 and the second silicide barrier layer 112 both include silicon nitride layers, the thickness of the first silicide barrier layer 111 is in the range of 150 to 300 angstroms, and the thickness of the second silicide barrier layer 112 is in the range of 150 to 300 angstroms.
[0116] In one embodiment, the thickness of the first silicide barrier layer 111 and the second silicide barrier layer 112 are both 220 angstroms, which are obtained by depositing a 220 angstrom thick silicon nitride layer and then patterning it.
[0117] As an example, the total thickness of the first silicide barrier layer 111 and the first field plate 107 c is in the range of 600 to 100 angstroms, and the total thickness of the second silicide barrier layer 112 and the second field plate 107 d is in the range of 600 to 100 angstroms.
[0118] In one embodiment, the total thickness of the first composite field plate composed of the first silicide barrier layer 111 and the first field plate 107 c is 800 angstroms, and the total thickness of the second composite field plate composed of the second silicide barrier layer 112 and the second field plate 107 d is 800 angstroms.
[0119] As an example, the first silicide blocking layer 111 may be located only on the upper surface of the first field plate 107c, or may extend to the side wall of the first gate spacer 107a, and the second silicide blocking layer 112 may be located only on the upper surface of the second field plate 107d, or may extend to the side wall of the second gate spacer 107b.
[0120] Please see again Figure 8 , performing the step S7: forming a first conductive column 113 and a second conductive column 114 , wherein the first conductive column 113 is located on the first silicide blocking layer 111 , and the second conductive column 114 is located on the second silicide blocking layer 112 .
[0121] As an example, an interlayer dielectric layer may be deposited first, a through hole may be etched in the interlayer dielectric layer, and a conductive material may be filled in the through hole to obtain the first conductive pillar 113 and the second conductive pillar 114 .
[0122] As an example, the first conductive pillar 113 and the second conductive pillar 114 may be made of tungsten (W) pillars or other suitable conductive materials.
[0123] As an example, the first conductive pillar 113 and the second conductive pillar 114 are both electrically connected to the source region 108 through wiring.
[0124] Thus, an LDMOS device is manufactured, which has a composite field plate structure of sidewall + SAB, which can maintain the withstand voltage (BV) of the device, and because the thickness of the silicide barrier layer required in the composite field plate is relatively small, it helps to expand the SAB process window.
[0125] In some embodiments, the substrate includes an LDMOS device area, a core device area, and an input-output device area divided according to a preset rule, and the first gate structure 105 and the second gate structure 106 are both located in the LDMOS device area. Since the manufacturing method of the LDMOS device of the present invention uses a sidewall material layer as the first field plate and the second field plate, there is no need to grow a thick oxide layer and perform thick oxide layer etching, thereby reducing at least one etching and cleaning of the oxide, which helps to ensure the height of the step height of the STI, prevent the generation of Divot defects or prevent the increase of the Divot degree. In other words, the present invention can be compatible with the CMOS device process in the core device area on the basis of ensuring the device withstand voltage level and expanding the SAB process window, reducing the difficulty of controlling the gate oxide growth of the CMOS device in the core device area, and is conducive to improving the yield.
[0126] In some embodiments of the present invention, there is further provided an LDMOS device, comprising a substrate, a first gate structure, a second gate structure, a first gate sidewall, a second gate sidewall, a first field plate, a second field plate, a source region, a first drain region, a second drain region, a first silicide barrier layer, a second silicide barrier layer, a first conductive column, and a second conductive column, wherein the substrate comprises a drift layer and a body region in the drift layer, the first gate structure and the second gate structure are spaced apart and arranged on the substrate, the first gate structure is located on the drift layer on one side of the body region and extends to the body region, the second gate structure is located on the drift layer on the other side of the body region and extends to the body region, the first gate sidewall is located on both side walls of the first gate structure, the second gate sidewall is located on both side walls of the second gate structure, and the The first field plate is located on the drift layer on the side of the first gate structure away from the second gate structure and is integrally connected to the bottom of the first gate sidewall. The second field plate is located on the drift layer on the side of the second gate structure away from the first gate structure and is integrally connected to the bottom of the second gate sidewall. The source region is located on the upper surface layer of the body region between the first gate sidewall and the second gate sidewall. The first drain region is located on the upper surface layer of the drift layer on one side of the first field plate. The second drain region is located on the upper surface layer of the drift layer on one side of the second field plate. The first silicide barrier layer is located on the first field plate. The second silicide barrier layer is located on the second field plate. The first conductive column is located on the first silicide barrier layer. The second conductive column is located on the second silicide barrier layer.
[0127] It should be pointed out that in the present invention, the first field plate and the bottom of the first gate side wall are "integrally connected", which means that the first field plate and the first gate side wall are formed in the same deposition process, and the second field plate and the bottom of the second gate side wall are "integrally connected", which means that the second field plate and the second gate side wall are formed in the same deposition process.
[0128] Specifically, the first silicide barrier layer and the first field plate together form a first composite field plate, and the second silicide barrier layer and the second field plate together form a second composite field plate, so as to ensure the withstand voltage level of the device.
[0129] In some embodiments, the first silicide blocking layer further extends to the sidewall of the first gate spacer, and the second silicide blocking layer further extends to the sidewall of the second gate spacer.
[0130] In some embodiments, both the first conductive pillar and the second conductive pillar are electrically connected to the source region.
[0131] In some embodiments, the sidewall material layer includes a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer stacked in sequence, the first silicon oxide layer has a thickness range of 20 to 100 angstroms, the silicon nitride layer has a thickness range of 100 to 300 angstroms, and the second silicon oxide layer has a thickness range of 220 to 420 angstroms.
[0132] In some embodiments, the first silicide barrier layer and the second silicide barrier layer both include silicon nitride layers, the first silicide barrier layer has a thickness ranging from 150 to 300 angstroms, and the second silicide barrier layer has a thickness ranging from 150 to 300 angstroms.
[0133] In some embodiments, the total thickness of the first silicide barrier layer and the first field plate is in the range of 600 to 100 angstroms, and the total thickness of the second silicide barrier layer and the second field plate is in the range of 600 to 100 angstroms.
[0134] In some embodiments, the first gate structure includes a first gate dielectric layer and a first polysilicon layer located on the first gate dielectric layer, and the second gate structure includes a second gate dielectric layer and a second polysilicon layer located on the second gate dielectric layer.
[0135] In some embodiments, the substrate includes an LDMOS device region, a core device region, and an input-output device region divided according to a preset rule, and the first gate structure and the second gate structure are both located in the LDMOS device region.
[0136] As an example, see Fig. 9 , which is a schematic diagram of the structure of the LDMOS device of the present invention in an embodiment, wherein the substrate includes an LDMOS device area A, a core device area B and an input-output device area C, the LDMOS device area A and the core device area B are isolated from each other by a shallow trench isolation structure 115, and the core device area B and the input-output device area C are isolated from each other by a shallow trench isolation structure 116. Since the first field plate and the first gate sidewall are formed in the same deposition process, and the second field plate and the second gate sidewall are formed in the same deposition process, there is no need to add thick oxide growth and etching process steps to the LDMOS in the front-end process, so that it is easier to control the gate oxide growth of the CMOS device in the core area and improve the device quality.
[0137] It should be noted that the device structures in the core device area B and the input / output device area C can be designed and manufactured according to actual needs. Fig. 9 Only those shown are limited.
[0138] In summary, in the manufacturing method of the LDMOS device of the present invention, a photomask is added after forming the sidewall material layer, and the sidewall material layer is patterned based on the photomask to obtain the first gate sidewall and the second gate sidewall, and a part of the sidewall material layer is retained as the first field plate and the second field plate, and then the first silicide barrier layer and the second silicide barrier layer are formed in the SAB stage, wherein the first silicide barrier layer is located on the first field plate to form a first composite field plate together with the first field plate, and the second silicide barrier layer is located on the second field plate to form a second composite field plate together with the second field plate. Since the thickness of the silicide barrier layer required in the composite field plate is relatively small, the SAB process window can be expanded, and the method of using the sidewall material layer as the first field plate and the second field plate of the present invention can reduce at least one etching and cleaning of the oxide, which helps to ensure the step height of the STI, prevent the generation of Divot defects or prevent the increase of the Divot degree, so that it can be compatible with the CMOS device process in the core device area, reduce the difficulty of controlling the gate oxide growth of the CMOS device in the core device area, and is conducive to improving the yield. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
[0139] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing an LDMOS device, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a drift layer and a body region located in the drift layer; forming a first gate structure and a second gate structure spaced apart from each other on the substrate, wherein the first gate structure is located on the drift layer at one side of the body region and extends to the body region, and the second gate structure is located on the drift layer at the other side of the body region and extends to the body region; Forming a spacer material layer on the substrate, wherein the spacer material layer covers the first gate structure and the second gate structure; Providing a photomask, and patterning the spacer material layer based on the photomask to obtain a first gate spacer, a second gate spacer, a first field plate, and a second field plate, wherein the first gate spacer is located on both side walls of the first gate structure, the second gate spacer is located on both side walls of the second gate structure, the first field plate is located on the drift layer on a side of the first gate structure away from the second gate structure and connected to the bottom of the first gate spacer, and the second field plate is located on the drift layer on a side of the second gate structure away from the first gate structure and connected to the bottom of the second gate spacer; forming a source region, a first drain region and a second drain region, wherein the source region is located on the upper surface layer of the body region between the first gate sidewall and the second gate sidewall, the first drain region is located on the upper surface layer of the drift layer on one side of the first field plate, and the second drain region is located on the upper surface layer of the drift layer on one side of the second field plate; forming a first silicide barrier layer and a second silicide barrier layer, wherein the first silicide barrier layer is located on the first field plate, and the second silicide barrier layer is located on the second field plate; A first conductive column and a second conductive column are formed, wherein the first conductive column is located on the first silicide blocking layer, and the second conductive column is located on the second silicide blocking layer.
2. The method for manufacturing an LDMOS device according to claim 1, wherein: The first silicide blocking layer further extends to the sidewall of the first gate spacer, and the second silicide blocking layer further extends to the sidewall of the second gate spacer.
3. The method for manufacturing an LDMOS device according to claim 1, wherein: The first conductive pillar and the second conductive pillar are both electrically connected to the source region.
4. The method for manufacturing an LDMOS device according to claim 1, wherein: The sidewall material layer includes a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer stacked in sequence, the first silicon oxide layer has a thickness range of 20 to 100 angstroms, the silicon nitride layer has a thickness range of 100 to 300 angstroms, and the second silicon oxide layer has a thickness range of 220 to 420 angstroms.
5. The method for manufacturing an LDMOS device according to claim 1, wherein: The first silicide barrier layer and the second silicide barrier layer both include silicon nitride layers. The thickness of the first silicide barrier layer is in the range of 150 to 300 angstroms, and the thickness of the second silicide barrier layer is in the range of 150 to 300 angstroms.
6. The method for manufacturing an LDMOS device according to claim 1, characterized in that: The total thickness of the first silicide barrier layer and the first field plate is in the range of 600 to 100 angstroms, and the total thickness of the second silicide barrier layer and the second field plate is in the range of 600 to 100 angstroms.
7. The method for manufacturing an LDMOS device according to claim 1, characterized in that: The substrate includes an LDMOS device area, a core device area, and an input-output device area divided according to a preset rule, and the first gate structure and the second gate structure are both located in the LDMOS device area.
8. The method for manufacturing an LDMOS device according to claim 1, wherein: The first gate structure includes a first gate dielectric layer and a first polysilicon layer located on the first gate dielectric layer, and the second gate structure includes a second gate dielectric layer and a second polysilicon layer located on the second gate dielectric layer.
9. An LDMOS device, characterized in that: include: A substrate, comprising a drift layer and a body region located in the drift layer; A first gate structure and a second gate structure are arranged on the substrate at intervals, the first gate structure is located on the drift layer on one side of the body region and extends to the body region, and the second gate structure is located on the drift layer on the other side of the body region and extends to the body region; A first gate sidewall, located on two side walls of the first gate structure; A second gate sidewall, located on two side walls of the second gate structure; A first field plate is located on the drift layer at a side of the first gate structure away from the second gate structure and is integrally connected to a bottom of the first gate sidewall; A second field plate is located on the drift layer at a side of the second gate structure away from the first gate structure and is integrally connected to a bottom of the second gate sidewall; A source region located at an upper surface layer of the body region between the first gate spacer and the second gate spacer; A first drain region, located on an upper surface layer of the drift layer at one side of the first field plate; A second drain region, located on an upper surface layer of the drift layer at one side of the second field plate; A first silicide blocking layer, located on the first field plate; A second silicide blocking layer, located on the second field plate; A first conductive pillar, located on the first silicide barrier layer; The second conductive column is located on the second silicide barrier layer.
10. The LDMOS device according to claim 9, characterized in that: The first silicide blocking layer further extends to the sidewall of the first gate spacer, and the second silicide blocking layer further extends to the sidewall of the second gate spacer.
11. The LDMOS device according to claim 9, characterized in that: The first conductive pillar and the second conductive pillar are both electrically connected to the source region.
12. The LDMOS device according to claim 9, characterized in that: The sidewall material layer includes a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer stacked in sequence, the first silicon oxide layer has a thickness range of 20 to 100 angstroms, the silicon nitride layer has a thickness range of 100 to 300 angstroms, and the second silicon oxide layer has a thickness range of 220 to 420 angstroms.
13. The LDMOS device according to claim 9, characterized in that: The first silicide barrier layer and the second silicide barrier layer both include silicon nitride layers. The thickness of the first silicide barrier layer is in the range of 150 to 300 angstroms, and the thickness of the second silicide barrier layer is in the range of 150 to 300 angstroms.
14. The LDMOS device according to claim 9, characterized in that: The total thickness of the first silicide barrier layer and the first field plate is in the range of 600 to 100 angstroms, and the total thickness of the second silicide barrier layer and the second field plate is in the range of 600 to 100 angstroms.
15. The LDMOS device according to claim 9, characterized in that: The substrate includes an LDMOS device area, a core device area, and an input-output device area divided according to a preset rule, and the first gate structure and the second gate structure are both located in the LDMOS device area.
16. The LDMOS device according to claim 9, characterized in that: The first gate structure includes a first gate dielectric layer and a first polysilicon layer located on the first gate dielectric layer, and the second gate structure includes a second gate dielectric layer and a second polysilicon layer located on the second gate dielectric layer.