Semiconductor Device and Method for Manufacturing the Same

Abstract

The present application relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes: a well region, a drift region, a drain region, and a source region are included in a substrate. The drift region is located within the well region, the drain region is located within the drift region, and the outer sidewall of the drain region includes two first sidewalls distributed in a second direction and two second sidewalls distributed in a first direction; the source region is located within the well region on one side of the first sidewall; the shallow trench isolation structure is partially located within the drift region and surrounds the first sidewall and the second sidewall of the drain region, and further extends along the second direction to the inner sidewall of the well region; the dimension in the first direction between the first sidewall of the drain region close to the source region and the outer sidewall of the shallow trench isolation structure close to the source region is a target width, and the dimension in the second direction between the second sidewall of the drain region and the inner sidewall of the drift region is a target length; the ratio of the target width to the target length is within a target range, and the target range is related to the target breakdown voltage of the semiconductor device. The present application improves the breakdown voltage of the semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] A DEMOS device (Drain Extension MOS) is a high-voltage device. Among DEMOS devices, a lateral double-diffused MOSFET (LDMOS) is relatively common. The DEMOS device has many advantages. For example, it has better thermal stability and frequency stability, higher gain and durability, lower feedback capacitance and thermal resistance, as well as a constant input impedance and a simpler biasing circuit.

[0003] In order to increase the breakdown voltage (BV) or the drain-to-source breakdown voltage (BVdss), a shallow trench isolation structure is usually provided in the DEMOS device. However, the breakdown voltage or the drain-to-source breakdown voltage of the existing DEMOS device with a shallow trench isolation structure still needs to be improved. Summary of the Invention

[0004] Based on this, the present application provides a semiconductor structure and a method for manufacturing the same to improve the breakdown voltage or the drain-to-source breakdown voltage of a semiconductor device, particularly a DEMOS device.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor device, including:

[0006] a substrate, a shallow trench isolation structure, and a gate structure; a well region, a drift region, a drain region, and a source region are included in the substrate. The drift region is located within the well region, the drain region is located within the drift region, and the outer sidewall of the drain region includes two first sidewalls distributed along a second direction and two second sidewalls distributed along a first direction. The first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects with the second direction;

[0007] The source region is located within the well region on one side of one of the first sidewalls;

[0008] The shallow trench isolation structure is partially located within the drift region and surrounds the first sidewall and the second sidewall of the drain region. Among them, the shallow trench isolation structure located outside the second sidewall also extends along the second direction to the inner sidewall of the well region;

[0009] The gate structure extends across and covers a part of the well region, the drift region, and the shallow trench isolation structure along the first direction;

[0010] Wherein, a dimension in the first direction between a first sidewall of the drain region close to the source region and an outer sidewall of the shallow trench isolation structure close to the source region is a target width, and a dimension in the second direction between a second sidewall of the drain region and an inner sidewall of the drift region is a target length; a ratio of the target width to the target length is within a target range, and the target range is related to a target breakdown voltage of the semiconductor device.

[0011] In some embodiments of the present application, the target range is 0.9 - 1.3.

[0012] In some embodiments of the present application, the target range related to the target breakdown voltage of the semiconductor device includes: when the ratio of the target width to the target length is within the target range, a position of the superimposed breakdown voltage moves from a first position of the drift region to a second position of the drift region, and a target breakdown voltage at the second position is greater than a target breakdown voltage at the first position; the superimposed breakdown voltage is a superposition of a lateral breakdown voltage in the first direction between the source region and the drain region and a longitudinal breakdown voltage in the second direction between the drain region and the substrate.

[0013] In some embodiments of the present application, the target breakdown voltage range of the semiconductor device is 30V - 60V, the target width range is 1.4 μm - 1.9 μm, and the target length range is 1.4 μm - 1.9 μm.

[0014] In some embodiments of the present application, an outer sidewall of the shallow trench isolation structure outside the first sidewall does not contact an inner sidewall of the drift region in the first direction.

[0015] In some embodiments of the present application, a depth of the shallow trench isolation structure is greater than a depth of the drain region and less than a depth of the drift region.

[0016] In some embodiments of the present application, the inner sidewall of the drift region includes four inner corners, and a cross-section of the inner corners in a direction parallel to the top surface of the substrate is arc-shaped.

[0017] In some embodiments of the present application, a doping type of the drift region is opposite to a doping type of the well region, a doping type of the drain region is the same as a doping type of the drift region, and a doping type of the source region is opposite to a doping type of the well region.

[0018] In some embodiments of the present application, the doping type of the well region is P-type, and doping types of the drift region, the drain region, and the source region are N-type; or, the doping type of the well region is N-type, and doping types of the drift region, the drain region, and the source region are P-type.

[0019] In a second aspect, an embodiment of the present application further provides a method for manufacturing a semiconductor device, including:

[0020] Providing a substrate, in which a well region is formed;

[0021] Forming a drift region in the well region, the doping type of the drift region being opposite to that of the well region;

[0022] Forming a drain region in the drift region, the doping type of the drain region being the same as that of the drift region. The outer sidewalls of the drain region include two first sidewalls distributed along a second direction and two second sidewalls distributed along a first direction. The first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects the second direction;

[0023] Forming a source region in the well region on one side of one of the first sidewalls of the drain region, the doping type of the source region being opposite to that of the well region;

[0024] Forming a shallow trench isolation structure surrounding the first sidewalls and the second sidewalls of the drain region in the drift region. The shallow trench isolation structure outside the second sidewall further extends along the second direction to the inner sidewall of the well region; wherein, the dimension along the first direction between the first sidewall of the drain region close to the source region and the outer sidewall of the shallow trench isolation structure close to the source region is a target width, and the dimension along the second direction between the second sidewall of the drain region and the inner sidewall of the drift region is a target length; the ratio of the target width to the target length is within a target range, and the target range is related to the target breakdown voltage of the semiconductor device;

[0025] Forming a gate structure extending across and covering a part of the well region, the drift region, and the shallow trench isolation structure along the first direction.

[0026] The embodiments of the present application may / at least have the following advantages:

[0027] In the embodiments of the present application, a semiconductor device and a method for forming the same are provided. The semiconductor device includes a substrate, which includes a well region, a drift region, a drain region, and a source region. The drift region is located within the well region, the drain region is located within the drift region, and the outer sidewall of the drain region includes two first sidewalls distributed along a second direction and two second sidewalls distributed along a first direction. The first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects the second direction. The source region is located within the well region on one side of one of the first sidewalls. A shallow trench isolation structure is provided, which is partially located within the drift region and surrounds the first sidewalls and the second sidewalls of the drain region. Among them, the shallow trench isolation structure located outside the second sidewall also extends along the second direction to the inner sidewall of the well region. A gate structure extends across and covers a part of the well region, the drift region, and the shallow trench isolation structure along the first direction. Among them, the dimension along the first direction between the first sidewall of the drain region close to the source region and the outer sidewall of the shallow trench isolation structure close to the source region is a target width, and the dimension along the second direction between the second sidewall of the drain region and the inner sidewall of the drift region is a target length. The ratio of the target width to the target length is within a target range, and the target range is related to the target breakdown voltage of the semiconductor device. By making the shallow trench isolation structure in the drift region satisfy the ratio of the target width to the target length, the semiconductor device of the present application not only optimizes the lateral breakdown voltage along the first direction between the source region and the drain region, but also optimizes the longitudinal breakdown voltage along the second direction between the drain region and the substrate, so that the position of the superimposed breakdown voltage of the lateral breakdown voltage and the longitudinal breakdown voltage moves from the easily breakdown inner corner of the drift region to the inner sidewall of the drift region that is not easily breakdown and is parallel to the second sidewall, thereby improving the target breakdown voltage (breakdown voltage (BV) or source-drain breakdown voltage (BVdss)) of the semiconductor device.

[0028] Details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0030] Figure 1 A schematic structural diagram of a semiconductor device provided by the prior art;

[0031] Figure 2A top view structural schematic diagram of a semiconductor device provided by some embodiments of the present application;

[0032] Figure 3 For Figure 2 a structural schematic diagram of the semiconductor device when it does not have a gate structure;

[0033] Figure 4 For Figure 2 a cross-sectional structural schematic diagram of the semiconductor device obtained along the cutting line AB direction in

[0034] Figure 5 For Figure 2 a cross-sectional structural schematic diagram of the semiconductor device obtained along the cutting line CD direction in

[0035] Figure 6 Simulated structural schematic diagrams of the semiconductor device provided by some embodiments of the present application at different target widths. Detailed implementation manners

[0036] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0038] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below may be referred to as the second element, component, region, layer or part.

[0039] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both upward and downward orientations. In addition, the device may also have additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0040] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprise / include" or "have" etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0041] The structure of the embodiments of the present invention should not be limited to the specific shapes shown in the accompanying drawings of the specification, but includes shape deviations caused by, for example, manufacturing techniques.

[0042] It can be understood that in the accompanying drawings of the specification of this application, adjacent film layers with the same processed film layer material are drawn as connected to make it closer to the actual structure.

[0043] The DEMOS device can increase the distance from the drain region to the source region by increasing or deepening the size of the shallow trench isolation structure (STI), thereby sharing more of the large voltage from the drain region, and thus improving the breakdown voltage (BV) or the drain-source breakdown voltage (BVdss). Figure 1FIG. 0 is a schematic structural diagram of an existing DEMOS device with a shallow trench isolation structure. The DEMOS device includes: a first substrate 101; a first well region 102 located in the first substrate 101, and the doping type of the first well region 102 can be P-type; a first drift region 103 located in the first well region 102, and the doping type of the first drift region 103 is N-type; a first shallow trench isolation structure 106 located in the first drift region 103; a first drain region 104 located in the first drift region 103 on one side of the first shallow trench isolation structure 106, and the doping type of the first drain region 104 is N-type; a first source region 105 located in the first well region 102 on the side of the first shallow trench isolation structure 106 away from the first drain region 104. The existing DEMOS device only considers the lateral breakdown voltage between the first drain region 104 and the first source region 105 (lateral direction is, for example, Figure 1 the X-axis direction in FIG. Figure 1 ), but in actual processes, it is found that the breakdown point of the DEMOS device is not only caused by the simple one-dimensional electric field from the first drain region 104 to the first source region 105 (such as Figure 1 the lateral breakdown voltage BVDS in the X-axis direction in FIG. Figure 1 ). Sometimes, only enhancing the lateral breakdown voltage between the first drain region 104 and the first source region 105 cannot improve the breakdown voltage (BV) or the source-drain breakdown voltage (BVdss) of the DEMOS device. At this time, the superposition effect of multi-dimensional fields needs to be considered. Specifically, referring to Figure 1 continuously, in the DEMOS device, there is actually a longitudinal breakdown voltage BVDB between the first drain region 104 and the first substrate 101 (longitudinal direction is, for example, Figure 1 the Y-axis direction in FIG. Figure 1 ). The superposition of the longitudinal breakdown voltage BVDB and the lateral breakdown voltage BVDS results in a superposition breakdown voltage VE, and this superposition breakdown voltage VE is close to the position of the first inner angle 10 of the first drift region 103, making the position of the first inner angle 10 of the first drift region 103 prone to becoming a breakdown point or being easily broken down, thus limiting the breakdown voltage (BV) or the source-drain breakdown voltage (BVdss) of the DEMOS device.

[0044] Therefore, an embodiment of the present application provides a semiconductor device and a manufacturing method thereof. By making the shallow trench isolation structure in the drift region satisfy the ratio of the target width to the target length, the semiconductor device not only optimizes the lateral breakdown voltage along the first direction between the source region and the drain region, but also optimizes the longitudinal breakdown voltage along the second direction between the drain region and the substrate, so that the position of the superposition breakdown voltage of the lateral breakdown voltage and the longitudinal breakdown voltage moves from the easily broken-down inner angle of the drift region to the inner sidewall of the drift region that is not easily broken down and is parallel to the first sidewall, thereby improving the target breakdown voltage value (breakdown voltage (BV) or source-drain breakdown voltage (BVdss)) of the semiconductor device.

[0045] Embodiments of the present application first provide a semiconductor device. Figure 2 It is a top view structural schematic diagram of a semiconductor device provided by some embodiments of the present application; Figure 3 is Figure 2 a structural schematic diagram of the semiconductor device without a gate structure in Figure 4 is Figure 2 a cross-sectional structural schematic diagram of the semiconductor device obtained along the cutting line AB direction in Figure 5 is Figure 2 a cross-sectional structural schematic diagram of the semiconductor device obtained along the cutting line CD direction in

[0046] Referring to Figures 2 - 5 , the semiconductor device includes:

[0047] a substrate 201, a shallow trench isolation structure 205, and a gate structure 207;

[0048] The substrate 201 includes a well region 202, a drift region 203, a drain region 204, and a source region 206. The drift region 203 is located in the well region 202, the drain region 204 is located in the drift region 203, and the outer sidewall of the drain region 204 includes two first sidewalls 11 distributed along a second direction (refer to Figure 3 ) and two second sidewalls 12 distributed along a first direction (refer to Figure 3 ). The first direction and the second direction are both parallel to the top surface of the substrate 201, and the first direction intersects with the second direction;

[0049] The source region 206 is located in the well region 202 on one side of one of the first sidewalls 11;

[0050] The shallow trench isolation structure 205 is partially located in the drift region 203 and surrounds the first sidewall 11 and the second sidewall 12 of the drain region 204. Among them, the shallow trench isolation structure 205 located outside the second sidewall 12 also extends along the second direction to the inner sidewall of the well region 202;

[0051] The gate structure 207 extends across and covers a part of the well region 202, the drift region 203, and the shallow trench isolation structure 205 along the first direction;

[0052] Among them, the dimension along the first direction between the first sidewall 11 of the drain region 204 close to the source region 206 and the outer sidewall of the shallow trench isolation structure 205 close to the source region 206 is a target width D1, and the dimension along the second direction between the second sidewall 12 of the drain region 204 and the inner sidewall of the drift region 203 is a target length D2; the ratio of the target width D1 to the target length D2 is within a target range, and the target range is related to the target breakdown voltage of the semiconductor device.

[0053] Specifically, the semiconductor device is a power device, the power device includes a DEMOS device, and the DEMOS device includes an LDMOS device.

[0054] The substrate 201 may include opposite top and back surfaces, and the material of the substrate 201 may include silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also include other materials, such as group III-V compounds such as gallium arsenide.

[0055] The substrate 201 has a well region 202, the well region 202 is doped with impurity ions, and the doping type of the well region 202 varies according to the type of the semiconductor device. In some embodiments, when the type of the semiconductor device is N-type, the doping type of the well region 202 is P-type, that is, the well region 202 is doped with P-type impurity ions, and the P-type impurity ions include one or more of boron ions, gallium ions, or indium ions. In other embodiments, when the type of the semiconductor device is P-type, the doping type of the well region 202 is N-type, that is, the well region 202 is doped with N-type impurity ions, and the N-type impurity ions include one or more of phosphorus ions, arsenic ions, or antimony ions. In some embodiments, the well region 202 may be formed by implanting P-type or N-type impurity ions into the substrate 201.

[0056] The drift region 203 is located within the well region 202, the depth of the drift region 203 may be less than, equal to, or greater than the depth of the well region 202, and the doping type of the drift region 203 is opposite to the doping type of the well region 202. In some embodiments, when the doping type of the well region 202 is P-type, the doping type of the drift region 203 is N-type. In other embodiments, when the doping type of the well region 202 is N-type, the doping type of the drift region 203 is P-type. In some embodiments, the drift region 203 may be formed by implanting P-type or N-type impurity ions into the substrate 201.

[0057] The leakage region 204 is located within the drift region 203. The depth of the leakage region 204 is less than the depth of the drift region 203. The doping type of the leakage region 204 is the same as that of the drift region 203, and the concentration of the doped impurity ions in the leakage region 204 is greater than the concentration of the doped impurity ions in the drift region 203. In some embodiments, when the doping type of the drift region 203 is N-type, the doping type of the leakage region 204 is N-type. In some other embodiments, when the doping type of the drift region 203 is P-type, the doping type of the leakage region 204 is P-type. In some embodiments, the leakage region 204 can be formed by implanting P-type impurity ions or N-type impurity ions into the substrate 201.

[0058] The leakage region 204 is in the shape of a cube. Specifically, the leakage region 204 may include an opposite top surface and bottom surface, and four outer sidewalls located between the top surface and the bottom surface. The four outer sidewalls include two first sidewalls 11 distributed along the second direction (refer to Figure 3 ), and two second sidewalls 12 distributed along the first direction (refer to Figure 3 ). Both the first direction and the second direction are parallel to the top surface of the substrate 201, and the first direction intersects with the second direction. In some embodiments, the two first sidewalls 11 may be parallel to each other, and the two second sidewalls 12 may also be parallel to each other. The first direction is perpendicular to the second direction. In a specific example, the first direction is the Figures 2 - 5 X-axis direction shown in Figures 2 - 5 , and the second direction is the

[0059] Y-axis direction shown in

[0060] The source region 206 is located within the well region 202 on one side of one of the first sidewalls 11. The doping type of the source region 206 is opposite to that of the well region 202 and the same as that of the leakage region 204. The depth of the source region 206 is less than the depth of the well region 202, and the concentration of the doped impurity ions in the source region 206 is greater than the concentration of the doped impurity ions in the well region 202. In some embodiments, when the doping type of the well region 202 is P-type, the doping type of the source region 206 is N-type. In some other embodiments, when the doping type of the well region 202 is N-type, the doping type of the source region 206 is P-type. In some embodiments, the source region 206 can be formed by implanting P-type impurity ions or N-type impurity ions into the substrate 201.

[0060] The shallow trench isolation structure 205 is partially located in the drift region 203 and partially located in the well region 202. The outer wall of the shallow trench isolation structure 205 outside the first side wall does not contact the inner wall of the drift region 203 in the first direction. The depth of the shallow trench isolation structure 205 is greater than the depth of the drain region 204 and less than the depth of the drift region 203. Specifically, the shallow trench isolation structure 205 is partially located in the drift region 203 and surrounds the first side wall 11 and the second side wall 12 of the drain region 204, and the shallow trench isolation structure 205 located outside the second side wall 12 also extends along the second direction to the inner wall of the well region 202; and the The ratio of the target width D1 to the target length D2 is within the target range, the target range is associated with the target withstand voltage value of the semiconductor device, the target width D1 is the dimension between the first side wall 11 of the drain region 204 close to the source region 206 and the outer side wall of the shallow trench isolation structure 205 close to the source region 206 along the first direction, the target length D2 is the dimension between the second side wall 12 of the drain region 204 and the inner side wall of the drift region 203 along the second direction, and the target range is associated with the target withstand voltage value of the semiconductor device including: when the ratio of the target width D1 to the target length D2 is within the target range, the position VE of the superimposed breakdown voltage (reference Figure 3 ) moves from a first position of the drift region 203 to a second position of the drift region 203, wherein the target withstand voltage value of the second position is greater than the target withstand voltage value of the first position; the superimposed breakdown voltage VE is a lateral breakdown voltage BVDS along a first direction between the source region 206 and the drain region 204 (reference Figure 3 ), and the longitudinal breakdown voltage BVDB between the drain region 204 and the substrate 201 along the second direction (reference Figure 3 In one example, the first position is an inner corner 13 (reference Figure 3 ), the second position is the inner sidewall of the drift region 203 which is not easily broken down and is parallel to the second sidewall 12, and the angle between the superimposed breakdown voltage VE and the longitudinal breakdown voltage BVDB at the second position is smaller than the angle between the superimposed breakdown voltage VE and the longitudinal breakdown voltage BVDB at the first position. The present application enables the shallow trench isolation structure 205 in the drift region 203 to meet the ratio of the target width D1 to the target length D2, which not only optimizes the lateral breakdown voltage BVDS along the first direction between the source region 206 and the drain region 204 (reference Figure 3 , Breakdown Voltage Drain to Source, BVDS), and optimizes the longitudinal breakdown voltage BVDB along the second direction between the drain region 204 and the substrate 201 (referenceFigure 3 , Breakdown Voltage Bulk to Drain, BVDB), so that the position of the superimposed breakdown voltage VE of the lateral breakdown voltage BVDS and the vertical breakdown voltage BVDB moves from the easily breakdown inner corner 13 of the drift region 203 to the inner side wall of the drift region 203 that is not easily breakdown and is parallel to the second side wall 12, thereby increasing the target breakdown voltage value (breakdown voltage (BV) or source-drain breakdown voltage (BVdss)) of the semiconductor device.

[0061] The target breakdown voltage value is greater than the breakdown voltage value of the existing semiconductor device. The target breakdown voltage value is greater than the breakdown voltage value of the existing semiconductor device (the existing semiconductor device can be, for example, a semiconductor device before the improvement of the shallow trench isolation structure). The breakdown voltage value of the existing semiconductor device is generally 5V - 10V. For example, when the breakdown voltage value of the existing semiconductor device is 45V, by adopting the improvement of the foregoing method of the present application, the breakdown voltage value of the semiconductor device can be increased by 5V - 10V, that is, the breakdown voltage value of the improved semiconductor device is 45V - 55V, so the target breakdown voltage value is 45V - 55V.

[0062] In some embodiments, the ratio of the target width D1 to the target length D2 is within a target range. The target range can be 0.9 - 1.3. Further, the target range can be 1. In a specific embodiment, the ratio of the target width D1 to the target length D2 can be 0.9, 1.0, 1.1, 1.2, 1.3. When the ratio of the target width D1 to the target length D2 is within the foregoing specific range, the lateral breakdown voltage BVDS (refer to Figure 3 , Breakdown Voltage Drain to Source, BVDS) along the first direction between the source region 206 and the drain region 204 is further optimized, and the vertical breakdown voltage BVDB (refer to Figure 3 , Breakdown VoltageBulk to Drain, BVDB) along the second direction between the drain region 204 and the substrate 201 is further optimized. Figure 6 , Figure 6The simulation diagram of the target breakdown voltage corresponding to the change of the target width D1 when the target length D2 is 1.5 microns. The abscissa represents the target width D1, and the ordinate represents the target breakdown voltage. From Figure 6 It can be seen that when the target width D1 is in the range of 1.4 microns - 1.9 microns, that is, when the ratio of the target width D1 to the target length D2 is in the target range of 0.9 - 1.3, the target breakdown voltage can maintain a relatively high value (47V - 51V). When the ratio of the target width D1 to the target length D2 is less than 0.9 (the target width D1 is less than 1.4 microns and the target length D2 is 1.5 microns) or greater than 1.3 (the target width D1 is greater than 1.9 microns and the target length D2 is 1.5 microns), the target breakdown voltage does not increase but decreases (will decrease).

[0063] In a specific embodiment, the target breakdown voltage range of the semiconductor device is 30V - 60V, for example, it can be 30V, 35V, 40V, 45V, 50V, 50V, 60V. The target width D1 range is 1.4 microns - 1.9 microns, for example, it can be 1.4 microns, 1.5 microns, 1.6 microns, 1.7 microns, 1.8 microns, 1.9 microns. The target length D2 range is 1.4 microns - 1.9 microns, for example, it can be 1.4 microns, 1.5 microns, 1.6 microns, 1.7 microns, 1.8 microns, 1.9 microns, and the ratio of the target width D1 to the target length D2 is within the target range of 0.9 - 1.3.

[0064] In some embodiments, the inner sidewall of the drift region 203 includes four inner corners 13 (refer to Figure 3 ) The cross-section of the inner corner 13 in the direction parallel to the top surface of the substrate 201 is arc-shaped. When the inner corner 13 is arc-shaped, it is beneficial to reduce the tip discharge, making the inner corner 13 less likely to be broken down. Through the cooperation with the shallow trench isolation structure 205 with the aforementioned specific structure and the specific ratio of the target width D1 to the target length D2, the target breakdown voltage (breakdown voltage (BV) or source-drain breakdown voltage (BVdss)) of the semiconductor device can be further improved.

[0065] The gate structure 207 extends across and covers a part of the well region 202, the drift region 203, and the shallow trench isolation structure 205 along the first direction. The source region 206 and the drain region 204 are respectively located on both sides of the gate structure 207 along the first direction.

[0066] In some embodiments, the gate structure 207 includes a gate dielectric layer and a gate electrode located on the upper dielectric layer. In a specific example, the material of the gate dielectric layer is silicon oxide, and the material of the gate electrode is polysilicon. In another specific example, the material of the gate dielectric layer is a high-K dielectric material, and the K dielectric material includes one or more of HfO2, Al2O3, ZrO2, HfSiO, HfSiON, HfTaO, and HfZrO. The material of the gate electrode includes a metal, and the metal includes one or more of W, Al, Cu, Ti, Ta, Co, TaN, NiSi, CoSi, TiN, TiAl, and TaSiN.

[0067] The embodiments of the present application also provide a method for manufacturing a semiconductor device, including:

[0068] Providing a substrate 201, in which a well region 202 is formed. In a specific example, the well region 202 is formed by performing a first ion implantation on the substrate 201. Before performing the first ion implantation, a mask layer may be correspondingly formed on the portion of the top surface of the substrate 201 that does not need to be implanted.

[0069] Forming a drift region 203 in the well region 202. The doping type of the drift region 203 is opposite to that of the well region 202. In a specific example, the drift region 203 is formed by performing a second ion implantation on the substrate 201. Before performing the second ion implantation, a mask layer may be correspondingly formed on the portion of the top surface of the substrate 201 that does not need to be implanted.

[0070] Forming a drain region 204 in the drift region 203. The doping type of the drain region 204 is the same as that of the drift region 203. The outer sidewall of the drain region 204 includes two first sidewalls distributed along a second direction and two second sidewalls distributed along a first direction. Both the first direction and the second direction are parallel to the top surface of the substrate 201, and the first direction intersects with the second direction.

[0071] Forming a source region 206 in the well region 202 on one side of one of the first sidewalls of the drain region 204. The doping type of the source region 206 is opposite to that of the well region 202. In a specific example, the source region 206 and the drain region 204 are formed by performing a third ion implantation on the substrate 201. Before performing the third ion implantation, a mask layer may be correspondingly formed on the portion of the top surface of the substrate 201 that does not need to be implanted.

[0072] A shallow trench isolation structure 205 is formed in the drift region 203 to surround the first sidewall and the second sidewall of the drain region 204, wherein the shallow trench isolation structure 205 outside the second sidewall also extends along the second direction to the inner sidewall of the well region 202; wherein, the dimension in the first direction between the first sidewall 11 of the drain region 204 close to the source region 206 and the outer sidewall of the shallow trench isolation structure 205 close to the source region 206 is a target width D1, and the dimension in the second direction between the second sidewall 12 of the drain region 204 and the inner sidewall of the drift region 203 is a target length D2; the ratio of the target width D1 to the target length D2 is within a target range, and the target range is related to the target breakdown voltage of the semiconductor device. In a specific example, the formation process of the shallow trench isolation structure 205 may include: forming a trench in the substrate 201; filling the trench with an isolation material and planarizing the filled isolation material to form the shallow trench isolation structure 205 in the trench;

[0073] Form a gate structure 207 that extends across and covers part of the well region 202, the drift region 203, and the shallow trench isolation structure 205 in the first direction.

[0074] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0075] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0076] The above embodiments only represent several implementation manners of the present application. The descriptions are relatively specific and detailed, but should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A semiconductor device, characterized in that: include: Substrate, shallow trench isolation structure and gate structure; The substrate includes a well region, a drift region, a drain region and a source region, the drift region is located in the well region, the drain region is located in the drift region, and the outer sidewall of the drain region includes two first sidewalls distributed along the second direction and two second sidewalls distributed along the first direction, the first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects with the second direction; The source region is located in a well region on one side of the first side wall; The shallow trench isolation structure is partially located in the drift region and surrounds the first side wall and the second side wall of the drain region, wherein the shallow trench isolation structure located outside the second side wall also extends along the second direction to the inner side wall of the well region; The gate structure crosses and covers a portion of the well region, the drift region and the shallow trench isolation structure along the first direction; Among them, the dimension along the first direction between the first side wall of the drain region close to the source region and the outer side wall of the shallow trench isolation structure close to the source region is a target width, and the dimension along the second direction between the second side wall of the drain region and the inner side wall of the drift region is a target length; the ratio of the target width to the target length is within a target range, and the target range is associated with a target withstand voltage value of the semiconductor device, and the target range is associated with the target withstand voltage value of the semiconductor device including: when the ratio of the target width to the target length is within the target range, the position of the superimposed breakdown voltage moves from the first position of the drift region to the second position of the drift region, and the target withstand voltage value of the second position is greater than the target withstand voltage value of the first position; the superimposed breakdown voltage is the superposition of the lateral breakdown voltage between the source region and the drain region along the first direction and the longitudinal breakdown voltage between the drain region and the substrate along the second direction.

2. The semiconductor device according to claim 1, wherein: The target range is 0.9-1.

3.

3. The semiconductor device according to claim 1, wherein: The target withstand voltage range of the semiconductor device is 30V-60V, the target width range is 1.4 microns-1.9 microns, and the target length range is 1.4 microns-1.9 microns.

4. The semiconductor device according to claim 1, wherein: An outer sidewall of the shallow trench isolation structure outside the first sidewall does not contact the inner sidewall of the drift region in the first direction.

5. The semiconductor device according to claim 1 or 4, characterized in that: The depth of the shallow trench isolation structure is greater than the depth of the drain region and less than the depth of the drift region.

6. The semiconductor device according to claim 1 or 2, characterized in that: The inner side wall of the drift region includes four inner corners, and the cross-section of the inner corners in a direction parallel to the top surface of the substrate is in an arc shape.

7. The semiconductor device according to claim 1, wherein: The doping type of the drift region is opposite to that of the well region, the doping type of the drain region is the same as that of the drift region, and the doping type of the source region is opposite to that of the well region.

8. The semiconductor device according to claim 7, characterized in that The doping type of the well region is P type, and the doping types of the drift region, the drain region and the source region are N type; or, the doping type of the well region is N type, and the doping types of the drift region, the drain region and the source region are P type.

9. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, wherein a well region is formed in the substrate; forming a drift region in the well region, wherein the doping type of the drift region is opposite to the doping type of the well region; forming a drain region in the drift region, wherein the doping type of the drain region is the same as the doping type of the drift region, and the outer sidewall of the drain region comprises two first sidewalls distributed along a second direction and two second sidewalls distributed along the first direction, wherein the first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects with the second direction; forming a source region in a well region on one side of the first sidewall of the drain region, wherein the doping type of the source region is opposite to the doping type of the well region; A shallow trench isolation structure is formed in the drift region, which surrounds the first sidewall and the second sidewall of the drain region, wherein the shallow trench isolation structure outside the second sidewall also extends to the inner sidewall of the well region along the second direction; wherein the dimension along the first direction between the first sidewall of the drain region close to the source region and the outer sidewall of the shallow trench isolation structure close to the source region is a target width, and the dimension along the second direction between the second sidewall of the drain region and the inner sidewall of the drift region is a target length; the ratio of the target width to the target length is within a target range, and the target range is associated with a target withstand voltage value of the semiconductor device, and the target range is associated with the target withstand voltage value of the semiconductor device, including: when the ratio of the target width to the target length is within the target range, the position of the superimposed breakdown voltage moves from the first position of the drift region to the second position of the drift region, and the target withstand voltage value of the second position is greater than the target withstand voltage value of the first position; the superimposed breakdown voltage is the superposition of the lateral breakdown voltage between the source region and the drain region along the first direction and the longitudinal breakdown voltage between the drain region and the substrate along the second direction; A gate structure is formed along the first direction, spanning and covering a portion of the well region, the drift region and the shallow trench isolation structure.

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