Semiconductor packaging structure and preparation method thereof

Abstract

The invention provides a semiconductor packaging structure and a preparation method thereof. The semiconductor packaging structure comprises a first semiconductor structure, a second semiconductor structure and a bonding pad lead-out layer which are sequentially stacked and arranged along a first direction, wherein the first semiconductor structure comprises a device layer; the second semiconductor structure comprises a semiconductor layer and at least one capacitor structure; the capacitor structure comprises a first polar plate, a second polar plate and a dielectric layer located between the first polar plate and the second polar plate; the first polar plate comprises a plurality of first parts penetrating through the semiconductor layer along the first direction and a second part positioned between the first parts and the bonding pad lead-out layer; one second part is connected with one first part; the second part and the first end of the device layer are coupled with a first bonding pad in the bonding pad lead-out layer; and the second polar plate and the second end of the device layer are coupled with a second bonding pad in the bonding pad lead-out layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure and a preparation method thereof. Background Art

[0002] With the development of advanced packaging technology, effective power distribution network (PDN) and high-frequency signal noise processing have become the main factors restricting chip packaging performance. At present, it has been proposed to use decoupling capacitors to achieve noise bypass. However, when using traditional capacitors as decoupling capacitors, due to the large thickness of the capacitors, the decoupling capacitors can only be placed on the periphery of the chip. The decoupling capacitors on the chip and the packaging substrate (or intermediate carrier) will occupy a large area, resulting in a larger size of the packaging substrate. In addition, since the setting position of the decoupling capacitor is far away from the chip pins, the filtering effect of the decoupling capacitor is poor. Therefore, how to achieve high-density integration of decoupling capacitors and chips has become a problem that needs to be solved urgently. Summary of the invention

[0003] In view of this, an embodiment of the present disclosure provides a semiconductor packaging structure and a method for manufacturing the same.

[0004] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a semiconductor package structure, comprising a first semiconductor structure, a second semiconductor structure and a pad lead-out layer stacked in sequence along a first direction; wherein:

[0006] The first semiconductor structure includes a device layer;

[0007] The second semiconductor structure includes a semiconductor layer and at least one capacitor structure; the capacitor structure includes a first electrode, a second electrode and a dielectric layer located between the first electrode and the second electrode; the first electrode includes a plurality of first parts that penetrate the semiconductor layer along the first direction and a second part that is located between the first part and the pad lead-out layer; one second part is connected to one first part; the first end of the second part and the device layer are both coupled to the first pad in the pad lead-out layer; the second electrode and the second end of the device layer are both coupled to the second pad in the pad lead-out layer.

[0008] In an optional implementation, the second semiconductor structure further includes:

[0009] A plurality of first conductive connection structures are located between the capacitor structure and the pad lead-out layer in the first direction; the first conductive connection structure extends along the first direction, and one end of the first conductive connection structure at two opposite ends along the first direction is coupled to the first pad, and the other end of the first conductive connection structure at two opposite ends along the first direction is connected to the second portion.

[0010] In an optional implementation, the second semiconductor structure further includes:

[0011] A plurality of second conductive connection structures are located between the capacitor structure and the first semiconductor structure in the first direction; the second conductive connection structure extends along the first direction, and one end of the second conductive connection structure at two opposite ends along the first direction is connected to the second electrode plate, and the other end of the second conductive connection structure at two opposite ends along the first direction is coupled to the second pad.

[0012] In an optional embodiment, the first electrode plate further includes:

[0013] A third part is located between the first part and the first semiconductor structure; one of the third parts is connected to two first parts adjacent to each other in the second direction; the second direction is perpendicular to the first direction; and the second conductive connection structure is located between the third part and the first semiconductor structure in the first direction.

[0014] In an optional embodiment, the semiconductor package structure further includes a bonding layer located between the first semiconductor structure and the second semiconductor structure; the bonding layer includes a dielectric layer and a plurality of bonding structures penetrating the dielectric layer along the first direction;

[0015] The first semiconductor structure further includes a first interconnect layer; the first interconnect layer is located between the device layer and the bonding layer;

[0016] The second semiconductor structure further includes a second interconnect layer; the second interconnect layer is located between the plurality of second conductive connection structures and the bonding layer.

[0017] In an optional implementation, the second semiconductor structure further includes:

[0018] A plurality of third conductive connection structures are located between the second interconnect layer and the pad lead-out layer; the third conductive connection structures penetrate the semiconductor layer along the first direction; and one of the two opposite ends of the third conductive connection structures along the first direction is connected to an interconnect line in the second interconnect layer.

[0019] In an optional implementation, the coupling path between the first end of the device layer and the first pad or the coupling path between the second end of the device layer and the second pad includes:

[0020] The interconnection line in the first interconnection layer, the bonding structure, the interconnection line in the second interconnection layer and the third conductive connection structure.

[0021] In an optional implementation, the coupling path between the second electrode plate and the second pad includes:

[0022] The second conductive connection structure, the interconnection line in the second interconnection layer and the third conductive connection structure.

[0023] In an optional implementation, the second semiconductor structure further includes:

[0024] An isolation layer is located between the semiconductor layer and the first electrode plate.

[0025] In an optional embodiment, the semiconductor packaging structure includes a plurality of the first semiconductor structures and a plurality of the second semiconductor structures; one of the plurality of the second semiconductor structures is located between two adjacent second semiconductor structures in the first direction; and another of the plurality of the second semiconductor structures is located between the pad lead-out layer and the first semiconductor structure.

[0026] In an optional implementation, the first end of the device layer includes an input / output end of the device layer or a power supply end of the device layer; and the second end of the device layer includes a ground end of the device layer.

[0027] In a second aspect, an embodiment of the present disclosure provides a method for preparing a semiconductor packaging structure, comprising:

[0028] forming a first semiconductor structure; the first semiconductor structure comprising a device layer;

[0029] forming a second semiconductor structure; the second semiconductor structure comprising a semiconductor layer and at least one capacitor structure; the capacitor structure comprising a first plate, a second plate and a dielectric layer located between the first plate and the second plate;

[0030] Stacking and arranging the first semiconductor structure and the second semiconductor structure along a first direction;

[0031] A pad lead-out layer is formed on one side of the second semiconductor structure that is away from the first semiconductor structure on two sides opposite to each other along the first direction; the first electrode includes a plurality of first parts that penetrate the semiconductor layer along the first direction and a second part that is located between the first part and the pad lead-out layer; one second part is connected to one first part; the first end of the second part and the device layer are both coupled to the first pad in the pad lead-out layer; the second electrode and the second end of the device layer are both coupled to the second pad in the pad lead-out layer.

[0032] In an optional implementation, the forming of the second semiconductor structure includes:

[0033] Providing an initial semiconductor layer and forming a plurality of grooves in the initial semiconductor layer; the grooves extend along the first direction;

[0034] forming an isolation layer covering inner walls of the plurality of trenches and the initial semiconductor layer;

[0035] The first electrode plate covering the isolation layer, the dielectric layer covering the first electrode plate, and the second electrode plate covering the dielectric layer are formed to form the capacitor structure.

[0036] In an optional implementation, the forming of the second semiconductor structure further includes:

[0037] A plurality of second conductive connection structures are formed on the capacitor structure; the second conductive connection structures extend along the first direction, and one of two opposite ends of the second conductive connection structures along the first direction is connected to the second electrode plate.

[0038] In an optional embodiment, the forming of the first semiconductor structure includes: forming a first interconnect layer on the device layer;

[0039] The forming of the second semiconductor structure further includes: forming a second interconnect layer on the plurality of second conductive connection structures;

[0040] The method for preparing the semiconductor package structure further includes: before stacking and arranging the first semiconductor structure and the second semiconductor structure along the first direction, forming a first bonding layer on the first interconnect layer, and forming a second bonding layer on the second interconnect layer;

[0041] The stacking and arranging of the first semiconductor structure and the second semiconductor structure along a first direction includes: bonding the first bonding layer and the second bonding layer to form a bonding layer located between the first semiconductor structure and the second semiconductor structure; the bonding layer includes a dielectric layer and a plurality of bonding structures penetrating the dielectric layer along the first direction; the first interconnection layer is located between the device layer and the bonding layer; and the second interconnection layer is located between the plurality of second conductive connection structures and the bonding layer.

[0042] In an optional implementation, the forming of the second semiconductor structure further includes:

[0043] removing a portion of the initial semiconductor layer from one side away from the first semiconductor structure among two sides of the initial semiconductor layer opposite to each other along the first direction to expose the isolation layer connected to the second portion, and the remaining initial semiconductor layer constitutes the semiconductor layer;

[0044] forming an insulating layer covering the exposed isolation layer and the semiconductor layer;

[0045] A plurality of first conductive connection structures are formed; the first conductive connection structures penetrate the insulating layer and the isolation layer along the first direction, and one of the two opposite ends of the first conductive connection structure along the first direction is connected to the second portion.

[0046] In an optional implementation, the forming of the second semiconductor structure further includes:

[0047] A plurality of third conductive connection structures are formed; the third conductive connection structures penetrate the semiconductor layer along the first direction; and one of two opposite ends of the third conductive connection structure along the first direction is connected to an interconnection line in the second interconnection layer.

[0048] In the technical solution provided in the present disclosure, the first semiconductor structure, the second semiconductor structure and the pad lead-out layer are stacked and arranged along the first direction, the first electrode plate of the capacitor structure in the second semiconductor structure includes a plurality of first parts extending along the first direction and a second part connected to the first part, the second part is located between the first part and the pad lead-out layer, and the second part is coupled to the first pad, and a shorter coupling path can be provided between the first electrode plate and the first pad, so that the capacitor structure can bypass the noise of the signal transmitted through the first pad in time, thereby improving the stability of the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic diagram of a semiconductor package structure provided by an embodiment of the present disclosure Figure 1 ;

[0050] Figure 2 for Figure 1 A magnified schematic diagram of the structure in the middle;

[0051] Figure 3 For a specific example Figure 2 A schematic cross-sectional view of the capacitor structure along line AA';

[0052] Figure 4 In another specific example Figure 2 A schematic cross-sectional view of the capacitor structure along line AA';

[0053] Figure 5 In another specific example Figure 2 A schematic cross-sectional view of the capacitor structure along line AA';

[0054] Figure 6 Schematic cross-sectional views of capacitor structures provided for other specific examples of the present disclosure;

[0055] Figure 7 A schematic diagram of a semiconductor package structure provided by an embodiment of the present disclosure Figure 2 ;

[0056] Figure 8 A schematic diagram of a process for preparing a semiconductor packaging structure provided by an embodiment of the present disclosure;

[0057] Fig. 9 A schematic diagram of a semiconductor packaging structure manufacturing process according to an embodiment of the present disclosure Figure 1 ;

[0058] Fig.10 A schematic diagram of a semiconductor packaging structure manufacturing process according to an embodiment of the present disclosure Figure 2 ;

[0059] Fig.11 A schematic diagram of a semiconductor packaging structure manufacturing process according to an embodiment of the present disclosure Figure 3 ;

[0060] Fig.12 A schematic diagram of a semiconductor packaging structure manufacturing process according to an embodiment of the present disclosure Figure 4 ;

[0061] Fig.13 for Fig.12 A magnified schematic diagram of the structure in the middle;

[0062] Fig.14 A schematic diagram of a semiconductor packaging structure manufacturing process according to an embodiment of the present disclosure Figure 5 ;

[0063] Fig.15 A schematic diagram of a semiconductor packaging structure manufacturing process according to an embodiment of the present disclosure Figure 6 ;

[0064] Fig.16 A schematic diagram of a semiconductor packaging structure manufacturing process according to an embodiment of the present disclosure Figure 7 ;

[0065] Fig.17 A schematic diagram of a semiconductor packaging structure manufacturing process according to an embodiment of the present disclosure Figure 8 ;

[0066] Fig.18 A schematic diagram of a semiconductor packaging structure manufacturing process according to an embodiment of the present disclosure Figure 9 ;

[0067] Fig.19 for Fig.18 A magnified schematic diagram of the structure in the middle;

[0068] Fig. 20 A schematic diagram of a semiconductor packaging structure manufacturing process according to an embodiment of the present disclosure Figure 10 . DETAILED DESCRIPTION

[0069] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0070] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0071] In the drawings, like reference numerals refer to like elements throughout.

[0072] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0073] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0074] With the development of advanced packaging technology, effective power distribution network (PDN) and high-frequency signal noise processing have become the main factors restricting chip packaging performance. At present, it has been proposed to use decoupling capacitors to achieve noise bypass. However, when using traditional capacitors as decoupling capacitors, due to the large thickness of the capacitors, the decoupling capacitors can only be placed on the periphery of the chip. The decoupling capacitors on the chip and the packaging substrate (or intermediate carrier) will occupy a large area, resulting in a larger size of the packaging substrate. In addition, since the setting position of the decoupling capacitor is far away from the chip pins, the filtering effect of the decoupling capacitor is poor. Therefore, how to achieve high-density integration of decoupling capacitors and chips has become a problem that needs to be solved urgently.

[0075] In this regard, the present disclosure proposes the following implementation modes.

[0076] The present disclosure provides a semiconductor packaging structure. Figure 1 A schematic diagram of a semiconductor packaging structure provided by an embodiment of the present disclosure, Figure 2 for Figure 1 The enlarged schematic diagram of the structure in the middle part, combined with reference Figure 1 and Figure 2The semiconductor packaging structure includes a first semiconductor structure 100, a second semiconductor structure 200 and a pad lead-out layer 300 stacked in sequence along a first direction; wherein the first semiconductor structure 100 includes a device layer 101; the second semiconductor structure 200 includes a semiconductor layer 210 and at least one capacitor structure 201; the capacitor structure 201 includes a first electrode 202, a second electrode 204 and a dielectric layer 203 located between the first electrode 202 and the second electrode 204; the first electrode 202 includes a plurality of first portions 2021 penetrating the semiconductor layer 210 along the first direction and a second portion 2022 located between the first portion 2021 and the pad lead-out layer 300; a second portion 2022 is connected to a first portion 2021; the first end of the second portion 2022 and the device layer 101 are both coupled to the first pad 301 in the pad lead-out layer 300; the second end of the second electrode 204 and the device layer 101 are both coupled to the second pad 302 in the pad lead-out layer 300. Here, the first direction may be a Z direction.

[0077] In some specific examples, the first electrode plate 202 and the second electrode plate 204 may include a conductive material, where the conductive material may be one or more of a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., copper, aluminum, tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0078] In some specific examples, the dielectric layer 203 may include a high dielectric constant (High-K) material, such as aluminum oxide, zirconium oxide, hafnium oxide, etc.

[0079] In some specific examples, the device layer 101 may include an integrated circuit, such as a central processing unit (CPU), a graphics processing unit (GPU), a memory, etc. The present disclosure does not specifically limit the type of the integrated circuit.

[0080] In some embodiments, the first end of the device layer 101 includes an input / output end of the device layer 101 or a power supply end of the device layer 101 ; the second end of the device layer 101 includes a ground end of the device layer 101 .

[0081] In some specific examples, if the first end of the device layer 101 is the input / output end of the device layer 101, the first pad 301 may be the input / output pad of the semiconductor package structure; if the first end of the device layer 101 is the power supply end of the device layer 101, the first pad 301 may be the power supply pad of the semiconductor package structure and may be coupled to an external power supply. The second pad 302 may be the ground pad of the semiconductor package structure.

[0082] In the embodiment of the present disclosure, the capacitor structure 201 in the second semiconductor structure 200 can be used as a decoupling capacitor to bypass the noise of the input / output signal to improve the stability of the high-frequency signal, or bypass the noise of the power supply signal to improve the power integrity. In addition, the first electrode 202 of the capacitor structure 201 includes a plurality of first parts 2021 extending along the first direction and a second part 2022 connected to the first part 2021, the second part 2022 is located between the first part 2021 and the pad lead-out layer 300, and the second part 2022 is coupled to the first pad 301. There can be a shorter coupling path between the first electrode 202 and the first pad 301, so that the capacitor structure 201 can bypass the noise of the signal transmitted through the first pad 301 in time, further improving the stability of the signal.

[0083] It should be noted that Figure 1 Three capacitor structures 201 in the first semiconductor structure 100 are shown, but the present disclosure is not limited thereto, and the present disclosure does not specifically limit the number of capacitor structures 201 in the first semiconductor structure 100. In addition, the first semiconductor structure 100 may include both a capacitor structure coupled to the input / output pad of the pad lead-out layer 300 and a capacitor structure coupled to the power pad in the pad lead-out layer 300. The multiple capacitor structures 201 in the first semiconductor structure 100 may have similar structures, and the present disclosure is mainly described by taking one capacitor structure 201 as an example in the embodiment of the present disclosure.

[0084] In some embodiments, in conjunction with reference Figure 1 and Figure 2 The first electrode plate 202 further includes: a third portion 2023 located between the first portion 2021 and the first semiconductor structure 100; one third portion 2023 is connected to two first portions 2021 adjacent to each other in the second direction; the second direction is perpendicular to the first direction. Here, the second direction may be the X direction.

[0085] Figure 3 , Figure 4 and Figure 5 Some specific examples of the present disclosure are provided Figure 2 A cross-sectional view of the capacitor structure 201 along line AA'. Figures 2 to 5 The first portion 2021 of the first electrode 202 surrounds the dielectric layer 203, and the portion of the dielectric layer 203 extending along the first direction surrounds the second electrode 204. The cross-sectional shapes of the plurality of first portions 2021 may be the same and may be circular (eg Figure 3 As shown), square (as Figure 4 As shown), rectangle (as Figure 5 as shown) or other shapes.

[0086] In some other specific examples, the cross-section of the capacitor structure may also include: Figure 6 The pattern shown can be composed of multiple Figure 5 The patterns shown are formed, and the extension directions of the single patterns in two adjacent patterns may intersect, for example, the single patterns in one pattern may extend along the X direction, and the single patterns in the other pattern may extend along the Y direction.

[0087] It should be noted that Figure 3 , Figure 4 , Figure 5 and Figure 6 The cross-sectional patterns of the capacitor structures shown in the figures are specific examples and are not intended to be specific limitations on the semiconductor package structure provided by the present disclosure.

[0088] In the embodiment of the present disclosure, the first electrode plate 202 of the capacitor structure 201 includes a plurality of first portions 2021 extending along the first direction, a second portion 2022 located between the first portion 2021 and the pad lead-out layer 300, and a third portion 2023 located between the first portion 2021 and the first semiconductor structure 100, and the dielectric layer 203 and the second electrode plate 204 are both conformal to the first electrode plate 202, thereby, the first electrode plate 202 and the second electrode plate 204 can have a larger facing area, which is beneficial to increase the capacitance value of the capacitor structure 201 when the projection area is limited. Here, the projection area refers to the area of ​​the projection of the capacitor structure 201 along the first direction on any plane perpendicular to the first direction.

[0089] In some embodiments, in conjunction with reference Figure 1 and Figure 2 The second semiconductor structure 200 also includes: a plurality of first conductive connection structures 205 located between the capacitor structure 201 and the pad lead-out layer 300 in the first direction; the first conductive connection structure 205 extends along the first direction, and one end of the first conductive connection structure 205 at two opposite ends along the first direction is coupled to the first pad 301, and the other end of the first conductive connection structure 205 at two opposite ends along the first direction is connected to the second portion 2022.

[0090] In some embodiments, in conjunction with reference Figure 1 and Figure 2 The second semiconductor structure 200 further includes: a plurality of second conductive connection structures 206 located between the capacitor structure 201 and the first semiconductor structure 100 in the first direction; the second conductive connection structures 206 extend along the first direction, and one end of the second conductive connection structures 206 opposite to each other along the first direction is connected to the second electrode plate 204, and the other end of the second conductive connection structures 206 opposite to each other along the first direction is coupled to the second pad 302. The second conductive connection structures 206 are located between the third portion 2023 and the first semiconductor structure 100 in the first direction.

[0091] In some specific examples, the first conductive connection structure 205 and the second conductive connection structure 206 include a conductive material, which may be one or more of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., copper, aluminum, tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0092] In the embodiment of the present disclosure, the first electrode plate 202 of the capacitor structure 201 can be led out through multiple first conductive connection structures 205, and the second electrode plate 204 can be led out through multiple second conductive connection structures 206, and the multiple first conductive connection structures 205 and the multiple second conductive connection structures 206 are respectively located on both sides of the capacitor structure 201 in the first direction, the second portion 2022 of the first electrode plate 202 is connected to the first conductive connection structure 205, and the portion where the second electrode plate 204 is connected to the second conductive connection structure 206 is located between the third portion 2023 of the first electrode plate 202 and the second conductive connection structure 206. Compared with the method in which the first electrode plate and the second electrode plate are both led out from the same side of the capacitor structure, the lead-out method of the capacitor structure 201 in the semiconductor packaging structure provided by the embodiment of the present disclosure can set as many first conductive connection structures 205 and second conductive connection structures 206 as possible without sacrificing the facing area between the first electrode plate 202 and the second electrode plate 204, which is conducive to reducing the equivalent series resistance (Equivalent Series Resistance, ESR) and equivalent series inductance (Equivalent Series Inductance, ESL), thereby accelerating the response speed of the capacitor structure 201 and enhancing the decoupling capability of the capacitor structure 201.

[0093] In some specific examples, refer to Figure 2 The second semiconductor structure 200 may further include: a plurality of insulating pillars 211 extending along the first direction, the insulating pillars 211 being connected to the second electrode plate 204 and surrounded by a portion of the second electrode plate 204 extending along the first direction. The insulating pillars 211 may include insulating materials, such as silicon oxide, silicon nitride, silicon carbonitride, and the like.

[0094] In some embodiments, reference Figure 2 The second semiconductor structure 200 further includes: an isolation layer 207 located between the semiconductor layer 210 and the first electrode plate 202 .

[0095] In some specific examples, the semiconductor layer 210 may be a P-type doped silicon substrate or an N-type doped silicon substrate, and the isolation layer 207 may include silicon oxide to achieve insulation isolation between the semiconductor layer 210 and the first electrode 202 .

[0096] In some embodiments, the semiconductor packaging structure further includes a bonding layer 400 located between the first semiconductor structure 100 and the second semiconductor structure 200; the bonding layer 400 includes a dielectric layer 401 and a plurality of bonding structures 402 penetrating the dielectric layer 401 along a first direction; the first semiconductor structure 100 further includes a first interconnection layer 110; the first interconnection layer 110 is located between the device layer 101 and the bonding layer 400; the second semiconductor structure 200 further includes a second interconnection layer 220; the second interconnection layer 220 is located between the plurality of second conductive connection structures 206 and the bonding layer 400.

[0097] In some specific examples, the bonding layer 400 is a hybrid bonding layer, the bonding structure 402 may include a copper-copper bonding structure, and the dielectric layer 401 may include one or more dielectric materials such as silicon oxide, silicon nitride, and silicon carbonitride.

[0098] In some specific examples, the first interconnection layer 110 and the second interconnection layer 220 are both redistribution layers (RDL), including multiple layers of interconnection lines arranged along a first direction.

[0099] In some embodiments, the second semiconductor structure 200 also includes: a plurality of third conductive connection structures 209 located between the second interconnect layer 220 and the pad lead-out layer 300; the third conductive connection structure 209 penetrates the semiconductor layer 210 along the first direction; and the third conductive connection structure 209 is connected to an interconnect line in the second interconnect layer 220 at one of the two opposite ends along the first direction.

[0100] In some embodiments, the coupling path between the first end of the device layer 101 and the first pad 301 or the coupling path between the second end of the device layer 101 and the second pad 302 includes: an interconnect line in the first interconnect layer 110, a bonding structure 402, an interconnect line in the second interconnect layer 220, and a third conductive connection structure 209.

[0101] In some embodiments, the coupling path between the second electrode plate 204 and the second pad 302 includes: the second conductive connection structure 206 , the interconnection line in the second interconnection layer 220 , and the third conductive connection structure 209 .

[0102] In the embodiment of the present disclosure, the first semiconductor structure 100 including the device layer 101 and the second semiconductor structure 200 including the capacitor structure 201 can be three-dimensionally integrated through the bonding layer 400. Specifically, the device layer 101 can be coupled to the pad lead-out layer 300 through the interconnection line in the first interconnection layer 110, the bonding structure 402 in the bonding layer 400, the interconnection line in the second interconnection layer 220, and the third conductive connection structure 209, and the first electrode 202 of the capacitor structure 201 can be coupled to the pad lead-out layer 300 through the plurality of first conductive connection structures 205. The pad lead-out layer 300, the second electrode 204 of the capacitor structure 201 can be coupled to the pad lead-out layer 300 through the second conductive connection structure 206, the interconnection line in the second interconnection layer 220 and the third conductive connection structure 209. As a result, the semiconductor packaging structure can have a smaller projected area, and the coupling path between the device layer 101 and the pad lead-out layer 300 and the coupling path between the capacitor structure 201 and the pad lead-out layer 300 can both be shorter, which is beneficial to reducing signal delay and improving signal integrity, thereby improving the reliability of the semiconductor packaging structure.

[0103] In some embodiments, the device layer 101 in the first semiconductor structure 100 may include a selection circuit, which can be coupled to multiple capacitor structures 201 through the first interconnect layer 110, the bonding layer 400, and the second interconnect layer 220, and can be configured to select the number of enabled capacitor structures 201, thereby achieving flexible setting of the capacitor structure 201, which is beneficial for the compatibility of the semiconductor packaging structure with different application scenarios.

[0104] In some embodiments, the semiconductor package structure may include a plurality of first semiconductor structures 100 and a plurality of second semiconductor structures 200 , and the plurality of first semiconductor structures 100 and the plurality of second semiconductor structures 200 are stacked and arranged in a first direction.

[0105] In a specific example, referring to Figure 7 , one of the plurality of second semiconductor structures 200 is located between two second semiconductor structures 200 adjacent to each other in the first direction; another second semiconductor structure 200 of the plurality of second semiconductor structures 200 is located between the pad lead-out layer 300 and the first semiconductor structure 100. Here, the number and stacking order of the first semiconductor structure 100 and the second semiconductor structure 200 are only examples and are not intended to be a specific limitation on the semiconductor package structure provided by the present disclosure.

[0106] In the embodiment of the present disclosure, the second semiconductor structure 200 including the capacitor structure 201 can also be arranged between two first semiconductor structures 100 including device layers. Thus, the capacitor structure 201 can not only decouple the power supply signal and input / output signal of the semiconductor packaging structure, but also decouple the signals transmitted between the first semiconductor structures 100 to optimize the signal integrity of the semiconductor packaging structure including multiple first semiconductor structures 100.

[0107] Based on the concept similar to the above-mentioned semiconductor packaging structure, the present disclosure also provides a method for preparing a semiconductor packaging structure. Figure 8 The present invention provides a schematic flow chart of a method for preparing a semiconductor package structure according to an embodiment of the present invention. The method for preparing a semiconductor package structure includes the following steps:

[0108] S10: forming a first semiconductor structure; the first semiconductor structure includes a device layer;

[0109] S20: forming a second semiconductor structure; the second semiconductor structure comprises a semiconductor layer and at least one capacitor structure; the capacitor structure comprises a first electrode plate, a second electrode plate and a dielectric layer located between the first electrode plate and the second electrode plate;

[0110] S30: stacking and arranging the first semiconductor structure and the second semiconductor structure along a first direction;

[0111] S40: A pad lead-out layer is formed on one side of the second semiconductor structure that is away from the first semiconductor structure on two sides opposite to each other along the first direction; the first electrode includes a plurality of first parts that penetrate the semiconductor layer along the first direction and a second part that is located between the first part and the pad lead-out layer; one second part is connected to one first part; the first end of the second part and the device layer are both coupled to the first pad in the pad lead-out layer; the second electrode and the second end of the device layer are both coupled to the second pad in the pad lead-out layer.

[0112] Figures 9 to 20 The structure diagram of the preparation process of the semiconductor packaging structure provided by the embodiment of the present disclosure is as follows. Figures 8 to 20 The preparation method of the semiconductor packaging structure provided by the present disclosure is described.

[0113] In some embodiments, reference Fig. 9 , executing step S10: forming a first semiconductor structure 100 , which may specifically include: forming a device layer 101 , and forming a first interconnect layer 110 on the device layer 101 .

[0114] In some embodiments, reference Fig.10The method for preparing the semiconductor package structure further includes: forming a first bonding layer 400a on the first interconnect layer 110, and the first bonding layer 400a may include a first dielectric layer 401a and a plurality of first bonding pads 402a located in the first dielectric layer 401a.

[0115] In some embodiments, in conjunction with reference Figures 11 to 13 ,in, Fig.13 for Fig.12 The enlarged schematic diagram of the structure in the middle part, executing step S20: forming a second semiconductor structure 200, specifically may include: providing an initial semiconductor layer 500 and forming a plurality of grooves 501 in the initial semiconductor layer 500; the grooves 501 extend along a first direction; forming an isolation layer 207 covering the inner walls of the plurality of grooves 501 and the initial semiconductor layer 500; forming a first electrode 202 covering the isolation layer 207, a dielectric layer 203 covering the first electrode 202 and a second electrode 204 covering the dielectric layer 203 to form a capacitor structure 201.

[0116] In some specific examples, multiple capacitor structures 201 can be formed simultaneously. Specifically, the first plates 202 of multiple capacitor structures 201, the dielectric layers 203 of multiple capacitor structures 201, and the second plates 204 of multiple capacitor structures 201 can be sequentially formed by a deposition process, and then two adjacent capacitor structures 201 can be separated by an etching process to form multiple independent capacitor structures 201. Thus, the efficiency of forming multiple capacitor structures 201 can be improved.

[0117] In some specific examples, refer to Fig.13 The specific process of executing step S20 also includes: forming an insulating material layer covering the second electrode plate 204 and completely filling the remaining space of the groove to form an insulating column 211.

[0118] In some embodiments, in conjunction with reference Fig.12 and Fig.13 The specific process of executing step S20 also includes: forming a plurality of second conductive connection structures 206 on the capacitor structure 201; the second conductive connection structures 206 extend along the first direction, and one of the two opposite ends of the second conductive connection structure 206 along the first direction is connected to the second electrode plate 204.

[0119] In some embodiments, reference Fig.12 The specific process of executing step S20 also includes: forming a second interconnection layer 220 on the plurality of second conductive connection structures 206; and coupling the other end of the second conductive connection structure 206 along the first direction with the interconnection line in the second interconnection layer 220.

[0120] In some embodiments, reference Fig.14The method for preparing the semiconductor package structure further includes: forming a second bonding layer 400b on the second interconnect layer 220, and the second bonding layer 400b may include a second dielectric layer 401b and a plurality of second bonding pads 402b located in the second dielectric layer 401b.

[0121] In some embodiments, in conjunction with reference Fig.10 , Fig.14 and Fig.15 , executing step S30, stacking the first semiconductor structure 100 and the second semiconductor structure 200 along the first direction, which may specifically include: bonding the first bonding layer 400a and the second bonding layer 400b to form a bonding layer 400 located between the first semiconductor structure 100 and the second semiconductor structure 200; the bonding layer 400 includes a dielectric layer 401 and a plurality of bonding structures 402 penetrating the dielectric layer 401 along the first direction; the first interconnection layer 110 is located between the device layer 101 and the bonding layer 400; the second interconnection layer 220 is located between the plurality of second conductive connection structures 206 and the bonding layer 400.

[0122] In some specific examples, the first bonding layer 400a and the second bonding layer 400b may be bonded by a hybrid bonding process. Specifically, in the hybrid bonding process, the first dielectric layer 401a and the second dielectric layer 401b are bonded, and the first bonding pad 402a and the second bonding pad 402b are bonded, and there may be no obvious dividing line in the formed dielectric layer 401 and the bonding structure 402.

[0123] In some embodiments, in conjunction with reference Figures 15 to 19 ,in, Fig.19 for Fig.18 The enlarged schematic diagram of the structure in the middle part, the specific process of executing step S20 also includes: removing part of the initial semiconductor layer 500 from the side away from the first semiconductor structure 100 on both sides of the initial semiconductor layer 500 opposite to each other along the first direction to expose the isolation layer 207 connected to the second part 2022, and the remaining initial semiconductor layer constitutes the semiconductor layer 210; forming an insulating layer 208 covering the exposed isolation layer 207 and the semiconductor layer 210; forming a plurality of first conductive connection structures 205; the first conductive connection structure 205 penetrates the insulating layer 208 and the isolation layer 207 along the first direction, and one of the two opposite ends of the first conductive connection structure 205 along the first direction is connected to the second part 2022.

[0124] In some embodiments, in conjunction with reference Fig.18 and Fig. 20The specific process of executing step S20 also includes: forming a plurality of third conductive connection structures 209; the third conductive connection structures 209 penetrate the semiconductor layer 210 along the first direction; and the third conductive connection structures 209 are connected to the interconnection line in the second interconnection layer 220 at one of the two opposite ends along the first direction.

[0125] In some embodiments, reference Fig. 20 , performing step S40: forming a pad lead-out layer 300 on one side of the second semiconductor structure 200 that is away from the first semiconductor structure 100 among the two sides that are opposite to each other along the first direction. Fig.19 and Fig. 20 The first electrode 202 includes a plurality of first parts 2021 penetrating the semiconductor layer 210 along the first direction and a second part 2022 located between the first part 2021 and the pad lead-out layer 300; a second part 2022 is connected to a first part 2021; the second part 2022 and the first end of the device layer 101 are both coupled to the first pad 301 in the pad lead-out layer 300; the second electrode 204 and the second end of the device layer 101 are both coupled to the second pad 302 in the pad lead-out layer 300.

[0126] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0127] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0128] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor packaging structure, characterized in that: It includes a first semiconductor structure, a second semiconductor structure and a pad lead-out layer which are sequentially stacked and arranged along a first direction; wherein, The first semiconductor structure includes a device layer; The second semiconductor structure includes a semiconductor layer and at least one capacitor structure; the capacitor structure includes a first electrode, a second electrode and a dielectric layer located between the first electrode and the second electrode; the first electrode includes a plurality of first parts that penetrate the semiconductor layer along the first direction and a second part that is located between the first part and the pad lead-out layer; one second part is connected to one first part; the first end of the second part and the device layer are both coupled to the first pad in the pad lead-out layer; the second electrode and the second end of the device layer are both coupled to the second pad in the pad lead-out layer.

2. The semiconductor package structure according to claim 1, wherein: The second semiconductor structure further includes: A plurality of first conductive connection structures are located between the capacitor structure and the pad lead-out layer in the first direction; the first conductive connection structure extends along the first direction, and one end of the first conductive connection structure at two opposite ends along the first direction is coupled to the first pad, and the other end of the first conductive connection structure at two opposite ends along the first direction is connected to the second portion.

3. The semiconductor package structure according to claim 1, wherein: The second semiconductor structure further includes: A plurality of second conductive connection structures are located between the capacitor structure and the first semiconductor structure in the first direction; the second conductive connection structure extends along the first direction, and one end of the second conductive connection structure at two opposite ends along the first direction is connected to the second electrode plate, and the other end of the second conductive connection structure at two opposite ends along the first direction is coupled to the second pad.

4. The semiconductor package structure according to claim 3, characterized in that: The first plate further comprises: A third part is located between the first part and the first semiconductor structure; one of the third parts is connected to two first parts adjacent to each other in the second direction; the second direction is perpendicular to the first direction; and the second conductive connection structure is located between the third part and the first semiconductor structure in the first direction.

5. The semiconductor package structure according to claim 3, characterized in that: The semiconductor package structure further includes a bonding layer located between the first semiconductor structure and the second semiconductor structure; the bonding layer includes a dielectric layer and a plurality of bonding structures penetrating the dielectric layer along the first direction; The first semiconductor structure further includes a first interconnect layer; the first interconnect layer is located between the device layer and the bonding layer; The second semiconductor structure further includes a second interconnect layer; the second interconnect layer is located between the plurality of second conductive connection structures and the bonding layer.

6. The semiconductor package structure according to claim 5, characterized in that: The second semiconductor structure further includes: A plurality of third conductive connection structures are located between the second interconnect layer and the pad lead-out layer; the third conductive connection structures penetrate the semiconductor layer along the first direction; and one of the two opposite ends of the third conductive connection structures along the first direction is connected to an interconnect line in the second interconnect layer.

7. The semiconductor package structure according to claim 6, characterized in that: A coupling path between the first end of the device layer and the first pad or a coupling path between the second end of the device layer and the second pad includes: The interconnection line in the first interconnection layer, the bonding structure, the interconnection line in the second interconnection layer and the third conductive connection structure.

8. The semiconductor package structure according to claim 6, wherein: The coupling path between the second electrode plate and the second pad includes: The second conductive connection structure, the interconnection line in the second interconnection layer and the third conductive connection structure.

9. The semiconductor package structure according to claim 1, wherein: The second semiconductor structure further includes: An isolation layer is located between the semiconductor layer and the first electrode plate.

10. The semiconductor package structure according to claim 1, wherein: The semiconductor packaging structure includes a plurality of the first semiconductor structures and a plurality of the second semiconductor structures; one of the plurality of the second semiconductor structures is located between two adjacent second semiconductor structures in the first direction; and another of the plurality of the second semiconductor structures is located between the pad lead-out layer and the first semiconductor structure.

11. The semiconductor package structure according to claim 1, wherein: The first end of the device layer includes an input / output end of the device layer or a power supply end of the device layer; the second end of the device layer includes a ground end of the device layer.

12. A method for preparing a semiconductor packaging structure, characterized in that: include: forming a first semiconductor structure; the first semiconductor structure comprising a device layer; forming a second semiconductor structure; The second semiconductor structure includes a semiconductor layer and at least one capacitor structure; the capacitor structure includes a first plate, a second plate, and a dielectric layer located between the first plate and the second plate; Stacking and arranging the first semiconductor structure and the second semiconductor structure along a first direction; A pad lead-out layer is formed on one side of the second semiconductor structure that is away from the first semiconductor structure on two sides opposite to each other along the first direction; the first electrode includes a plurality of first parts that penetrate the semiconductor layer along the first direction and a second part that is located between the first part and the pad lead-out layer; one second part is connected to one first part; the first end of the second part and the device layer are both coupled to the first pad in the pad lead-out layer; the second electrode and the second end of the device layer are both coupled to the second pad in the pad lead-out layer.

13. The method for preparing a semiconductor packaging structure according to claim 12, characterized in that: The forming of the second semiconductor structure comprises: Providing an initial semiconductor layer and forming a plurality of grooves in the initial semiconductor layer; the grooves extend along the first direction; forming an isolation layer covering inner walls of the plurality of trenches and the initial semiconductor layer; The first electrode plate covering the isolation layer, the dielectric layer covering the first electrode plate, and the second electrode plate covering the dielectric layer are formed to form the capacitor structure.

14. The method for preparing a semiconductor packaging structure according to claim 13, characterized in that: The forming of the second semiconductor structure further includes: A plurality of second conductive connection structures are formed on the capacitor structure; the second conductive connection structures extend along the first direction, and one of two opposite ends of the second conductive connection structures along the first direction is connected to the second electrode plate.

15. The method for preparing a semiconductor packaging structure according to claim 14, characterized in that: The forming of the first semiconductor structure comprises: forming a first interconnect layer on the device layer; The forming of the second semiconductor structure further includes: forming a second interconnect layer on the plurality of second conductive connection structures; The method for preparing the semiconductor package structure further includes: before stacking and arranging the first semiconductor structure and the second semiconductor structure along the first direction, forming a first bonding layer on the first interconnect layer, and forming a second bonding layer on the second interconnect layer; The stacking and arranging of the first semiconductor structure and the second semiconductor structure along a first direction includes: bonding the first bonding layer and the second bonding layer to form a bonding layer located between the first semiconductor structure and the second semiconductor structure; the bonding layer includes a dielectric layer and a plurality of bonding structures penetrating the dielectric layer along the first direction; the first interconnection layer is located between the device layer and the bonding layer; and the second interconnection layer is located between the plurality of second conductive connection structures and the bonding layer.

16. The method for preparing a semiconductor packaging structure according to claim 15, characterized in that: The forming of the second semiconductor structure further includes: removing a portion of the initial semiconductor layer from one side away from the first semiconductor structure among two sides of the initial semiconductor layer opposite to each other along the first direction to expose the isolation layer connected to the second portion, and the remaining initial semiconductor layer constitutes the semiconductor layer; forming an insulating layer covering the exposed isolation layer and the semiconductor layer; A plurality of first conductive connection structures are formed; the first conductive connection structures penetrate the insulating layer and the isolation layer along the first direction, and one of the two opposite ends of the first conductive connection structure along the first direction is connected to the second portion.

17. The method for preparing a semiconductor packaging structure according to claim 16, characterized in that: The forming of the second semiconductor structure further includes: A plurality of third conductive connection structures are formed; the third conductive connection structures penetrate the semiconductor layer along the first direction; and one of two opposite ends of the third conductive connection structure along the first direction is connected to an interconnection line in the second interconnection layer.

Images