Radio frequency power amplifier structure and radio frequency power amplifier circuit

Abstract

The invention provides a radio frequency power amplifier structure and a radio frequency power amplifier circuit. The radio frequency power amplifier structure comprises a substrate; the trench isolation structure comprises active regions and shallow trench isolation structures, and the adjacent active regions are isolated through the shallow trench isolation structures; the first amplification module at least comprises an MOS (Metal Oxide Semiconductor) tube which is positioned in a first active region of the substrate; the second amplification module comprises a SiGe triode and a second active region adjacent to the first active region; and the metal interconnection structure is used for electrically leading out the MOS tube and the SiGe triode, and a drain region or a source region of the MOS tube is electrically connected with a base region of the SiGe triode. According to the technical scheme, the MOS transistor and the SiGe triode are combined, so that the output power is large, the conversion efficiency is high, and integration with the MOS transistor is easier; in addition, the MOS transistor and the SiGe triode are formed on the same substrate, so that substrate-level packaging is realized, the integration level is improved, and the cost is reduced; the adjacent active regions are isolated through the shallow trench isolation structures, so that the electrical performance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power amplifiers, and in particular to a radio frequency power amplifier structure and a radio frequency power amplifier circuit. Background Art

[0002] The RF power amplifier (RF PA) is the main part of the transmission system. In the front-end circuit of the transmitter, the RF signal power generated by the modulation oscillation circuit is very small, and it needs to go through a series of amplifications to obtain sufficient RF power before it can be fed to the antenna for radiation.

[0003] The main technical indicators of RF power amplifiers are output power and efficiency. How to improve output power and efficiency is the core of RF power amplifier design goals.

[0004] Currently, the mainstream process for power amplifiers is still the GaAs process. Although it has advantages such as high electron mobility and high power, it also has certain disadvantages, such as high cost, difficulty in integration with MOS devices, and poor process integration.

[0005] Therefore, it is necessary to improve the RF power amplifier to increase process integration. Summary of the invention

[0006] The present invention provides a radio frequency power amplifier structure and a radio frequency power amplifier circuit to solve the problems of high cost and poor process integration of radio frequency power amplifiers in the prior art.

[0007] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0008] According to a first aspect of the present invention, the present invention provides a radio frequency power amplifier structure, comprising:

[0009] A substrate; the substrate comprises an active area and a shallow trench isolation structure, and adjacent active areas are isolated by the shallow trench isolation structure;

[0010] A first amplification module, comprising at least one MOS tube, located in a first active area of ​​the substrate;

[0011] A second amplification module, including a SiGe triode, is located in a second active area adjacent to the first active area;

[0012] The metal interconnection structure is used to electrically lead out the MOS tube and the SiGe triode, and the drain region or source region of the MOS tube is electrically connected to the base region of the SiGe triode.

[0013] Optionally, the number of the MOS tubes is two or more, all the MOS tubes are cascaded to each other, and the drain region or source region of the last-stage MOS tube is electrically connected to the base region of the SiGe triode.

[0014] Optionally, the MOS tubes are electrically connected via their drain regions or source regions.

[0015] Optionally, the substrate comprises a base plate, a buried oxide layer and a top silicon layer stacked in sequence, the SiGe triode is formed in a second active region of the top silicon layer, wherein the thickness of the top silicon layer in the second active region is less than the thickness of the top silicon layer in other regions; the SiGe triode comprises:

[0016] A collector region formed by heavily doping the top silicon layer of the second active region;

[0017] A base region, formed by a SiGe layer formed on the collector region;

[0018] The emitter region is formed by heavily doping the second top silicon layer formed on the base region, and the emitter region covers a portion of the surface of the base region and exposes a portion of the surface of the base region.

[0019] Optionally, the metal interconnection structure includes the metal interconnection structure of each MOS tube and the metal interconnection structure of the SiGe triode; the metal interconnection structure of the SiGe triode includes a first base region electrode structure, a first emitter region electrode structure and a first collector region electrode structure; wherein:

[0020] A first insulating layer is formed above the substrate, and the metal interconnection structure of each MOS tube, the first emitter region electrode structure, and the first base region electrode structure are located in the first insulating layer, and the top end is exposed from the top surface of the first insulating layer; the bottom end of the metal interconnection structure of each MOS tube contacts the gate and the source region and / or the drain region of each MOS tube respectively, the bottom end of the first emitter region electrode structure contacts the emitter region, and the bottom end of the first base region electrode structure contacts the SiGe layer;

[0021] The first collector region electrode structure is located in the substrate and the buried oxide layer, with a top end contacting the collector region and a bottom end exposed from the bottom surface of the substrate.

[0022] Optionally, the collector region electrode structure is a TSV through-hole structure, and the TSV through-hole penetrates the buried oxide layer and the substrate to serve as an output port of the SiGe transistor.

[0023] Optionally, the second active region also includes a first heavily doped region, which is located between the collector region, the base region, the emitter region and the shallow trench isolation structure; wherein the first heavily doped region contacts the collector region, and an insulating side wall is formed between the first heavily doped region and the base region and the emitter region.

[0024] Optionally, the metal interconnection structure includes the metal interconnection structure of each MOS tube and the metal interconnection structure of the SiGe triode; the metal interconnection structure of the SiGe triode includes a second base region electrode structure, a second emitter region electrode structure and a second collector region electrode structure; wherein:

[0025] A second insulating layer is formed above the substrate, and the metal interconnection structure of each MOS tube, the second emitter region electrode structure, the second base region electrode structure and the second collector region electrode structure are located in the second insulating layer, and the top ends are exposed from the top surface of the second insulating layer;

[0026] The bottom end of the metal interconnect structure of each MOS tube contacts the gate and source region and / or drain region of each MOS tube respectively;

[0027] The bottom end of the second emitter region electrode structure contacts the emitter region, the bottom end of the second base region electrode structure contacts the base region, and the bottom end of the second collector region electrode structure contacts the first heavily doped region.

[0028] According to a second aspect of the present invention, there is provided a radio frequency power amplifier circuit, which comprises: at least one MOS tube, a SiGe triode, and an input voltage; wherein,

[0029] The MOS transistor and the SiGe triode are located on the same substrate;

[0030] The gate of the MOS tube is coupled to the input voltage, the drain region or the source region of the MOS tube is coupled to the base region of the SiGe transistor, and the collector region of the SiCe transistor serves as the output end of the radio frequency power amplifier circuit.

[0031] Optionally, the MOS tubes include two or more;

[0032] The MOS transistor and the SiGe triode are located on the same substrate;

[0033] All MOS tubes are cascaded with each other, wherein the gate of the MOS tube of the first stage is coupled to the input voltage, the drain region or source region of the MOS tube of the last stage is coupled to the base region of the SiGe transistor, and the collector region of the SiCe transistor serves as the output end of the RF power amplifier circuit.

[0034] The radio frequency power amplifier structure and radio frequency power amplifier circuit provided by the present invention can provide a higher power output and a higher conversion efficiency by combining a first amplifier module composed of a MOS tube with a second amplifier module composed of a SiGe transistor to form a radio frequency power amplifier with at least two stages of amplification; moreover, the amplifier module and the SiGe transistor are formed on the same substrate, and the combination of the SiGe transistor and the MOS does not need to be achieved through bonding packaging, thereby improving the integration level and reducing the cost.

[0035] In addition, adjacent active areas of the substrate are isolated by a shallow trench isolation structure to prevent mutual interference between different devices and improve electrical performance.

[0036] In an optional solution of the present invention, the number of MOS tubes in the amplification module is two or more, all MOS tubes are cascaded to each other, and multiple MOS tubes form multi-stage amplification, thereby further improving the output power.

[0037] In an optional scheme of the present invention, the emitter region electrode structure and the base region electrode structure of the SiGe triode and the metal interconnection structure of each MOS tube are led out from the side of the top silicon layer (i.e., the front side of the substrate); the collector region electrode structure is led out from the side of the buried oxide layer (i.e., the back side of the substrate); since the collector region electrode structure is led out from the back side, the density of the metal interconnection structure on the front side of the substrate is reduced, making the line arrangement more sparse and the circuit more stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0039] Figure 1 is a cross-sectional view of a radio frequency power amplifier structure according to one embodiment of the present invention;

[0040] Figure 2 A circuit diagram of a radio frequency power amplifier structure according to an embodiment of the present invention;

[0041] Figure 3 is a cross-sectional view of a radio frequency power amplifier structure according to another embodiment of the present invention;

[0042] Figure 4 is a cross-sectional view of a first amplifying module and a second amplifying module according to another embodiment of the present invention;

[0043] Figure 5 A circuit diagram of a radio frequency power amplifier structure according to another embodiment of the present invention;

[0044] Figure 6 A cross-sectional view of a first amplifying module and a second amplifying module according to another embodiment of the present invention;

[0045] Figure 7 A cross-sectional view of a first amplifying module and a second amplifying module according to another embodiment of the present invention;

[0046] Figure 8 A circuit diagram of a radio frequency power amplifier structure according to another embodiment of the present invention;

[0047] Fig. 9 is a cross-sectional view of a metal interconnect structure according to an embodiment of the present invention;

[0048] Fig.10 is a cross-sectional view of a metal interconnect structure according to another embodiment of the present invention;

[0049] Description of reference numerals:

[0050] 10-substrate;

[0051] 101-Substrate;

[0052] 102- buried oxygen layer;

[0053] 103-top silicon layer;

[0054] 11- shallow trench isolation structure;

[0055] 21-SiGe transistor;

[0056] 211-collector area;

[0057] 212-base region;

[0058] 213-launch area;

[0059] 22-first MOS tube;

[0060] 221-well region;

[0061] 222-gate;

[0062] 223- source region or drain region;

[0063] 224-drain region or source region;

[0064] 23- second MOS tube;

[0065] 24- the third MOS tube;

[0066] 3-Metal interconnect structure;

[0067] 31-Metal interconnection structure of MOS tube;

[0068] 32-first base electrode structure;

[0069] 33-first emission region electrode structure;

[0070] 34- first collector region electrode structure;

[0071] 35-a first heavily doped region;

[0072] 36-insulated side wall;

[0073] 37-second base electrode structure;

[0074] 38-second emission region electrode structure;

[0075] 39-second collector region electrode structure;

[0076] 41- a first insulating layer;

[0077] 42- a second insulating layer;

[0078] 51-first metal interconnection line;

[0079] 61- conductive contact layer;

[0080] 71-Insulation layer. DETAILED DESCRIPTION

[0081] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0082] In the description of the specification of the present invention, it is necessary to understand that the orientation or position relationship indicated by the terms "upper part", "lower part", "upper end", "lower end", "lower surface", "upper surface", etc. is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0083] In the description of the present specification, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0084] In the description of the present invention, "plurality" means a plurality, such as two, three, four, etc., unless otherwise clearly and specifically defined.

[0085] In the description of the present invention, unless otherwise clearly specified and limited, the term "connection" and other terms should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0086] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0087] As pointed out in the background technology, the mainstream process of power amplifiers is still the GaAs process. Although it has advantages such as high electron mobility and high power, it also has certain disadvantages. For example, due to its process limitations, the size of the GaAs substrate is generally 6 inches. If it is to be combined with other devices to achieve multi-stage amplification, the amplifier tubes on different substrates need to be bonded and then packaged for integration, which can easily cause current loss, poor integration, and high cost.

[0088] In view of this, the present invention proposes a radio frequency power amplifier structure for receiving and amplifying an input voltage to generate an output voltage, which includes:

[0089] Substrate; the substrate includes an active area and a shallow trench isolation structure, and adjacent active areas are isolated by the shallow trench isolation structure;

[0090] A first amplifying module, comprising at least one MOS tube, located in a first active region of the substrate;

[0091] A second amplification module, including a SiGe triode, is located in a second active area adjacent to the first active area;

[0092] The metal interconnection structure is used to electrically lead out the MOS tube and the SiGe triode, and the drain region or source region of the MOS tube is electrically connected to the base region of the SiGe triode.

[0093] The radio frequency power amplifier structure provided by the present invention can provide greater power output and higher conversion efficiency by combining a first amplification module composed of a MOS tube with a second amplification module composed of a SiGe triode; the MOS tube and the SiGe triode are formed on the same substrate, and the combination of the SiGe triode and the MOS tube does not need to be realized by bonding packaging, thereby improving the integration and reducing the cost. In addition, adjacent active areas are isolated by a shallow trench isolation structure to prevent mutual interference between different devices and improve electrical performance.

[0094] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0095] Please refer to Figure 1-Figure 2 ,in, Figure 1 is a cross-sectional view of a SiGe triode and an amplification module of a radio frequency power amplifier structure according to an embodiment of the present invention, Figure 2 FIG. 4 is a circuit diagram of a radio frequency power amplifier structure according to an embodiment of the present invention.

[0096] like Figure 1 As shown, the RF power amplifier structure provided in one embodiment of the present invention includes: a substrate 10, a first amplifying module, a second amplifying module and a metal interconnection structure 3. Among them, the substrate 10 includes an active area and a shallow trench isolation structure 11, and adjacent active areas are isolated by the shallow trench isolation structure 11. The first amplifying module includes at least one MOS tube, which is located in the first active area of ​​the substrate 10. The second amplifying module includes: a SiGe triode 21, which is located in the second active area of ​​the substrate 10 adjacent to the first active area. The metal interconnection structure 3 is used to electrically lead out the MOS tube and the SiGe triode, and the drain region or source region of the MOS tube 22 is electrically connected to the base region of the SiGe triode 21 (not shown in the electrical connection diagram). In this embodiment, the first amplifying module includes a MOS tube: the first MOS tube 22 as an example.

[0097] In one embodiment, the first MOS transistor 22 may be an NMOS transistor. When used for amplification, the gate serves as an input terminal and the drain serves as an output terminal, and is electrically connected to the base region of the SiGe transistor 21. The circuit diagram of the RF power amplifier structure is shown in FIG. Figure 2 shown.

[0098] In another embodiment, the first MOS transistor 22 may also be a PMOS transistor. When used for amplification, the source region serves as an output end and is electrically connected to the base region of the SiGe transistor 21. The specific circuit is the same as that of the NMOS and will not be described in detail here.

[0099] The RF power amplifier structure of the above-mentioned embodiment of the present invention can provide a higher power output and a higher conversion efficiency by combining a first amplification module composed of a MOS tube with a second amplification module composed of a SiGe triode to form a RF power amplifier with at least two stages of amplification; moreover, the MOS tube and the SiGe triode are formed on the same substrate, and the combination of the SiGe triode and the MOS tube does not need to be achieved through bonding packaging, thereby improving the integration level and reducing the cost; in addition, adjacent active areas of the substrate are isolated by a shallow trench isolation structure to prevent mutual interference between different devices and improve the electrical performance.

[0100] As an embodiment, the substrate 10 includes a base plate 101, a buried oxide layer 102 and a top silicon layer 103 stacked in sequence. The SiGe transistor 21 is formed in the second active region of the top silicon layer, wherein the thickness of the top silicon layer in the second active region is less than that of the top silicon layer in other active regions.

[0101] The SiGe transistor 21 specifically includes a collector region 211, a base region 212 and an emitter region 213. Figure 1 As shown. The collector region 211 is formed by heavily doping the top silicon layer of the second active region. The base region 212 is located above the collector region 211 and is formed by a SiGe layer formed on the collector region 211. The emitter region 213 is located above the base region 212 and covers a portion of the surface of the base region and exposes a portion of the surface of the base region for electrical extraction of the base region; it is formed by heavily doping the second top silicon layer formed on the base region.

[0102] The SiGe triode is formed in the second active region of the top silicon layer. Specifically, after etching and removing a portion of the top silicon layer in the second active region, the thickness of the remaining top silicon layer is less than that of the top silicon layer in other active regions. The top silicon layer in the second active region is heavily doped to form a collector region 211; a SiGe layer of a preset thickness is formed on the collector region 211, and the SiGe layer is heavily doped to form a base region 212; a cap silicon layer covering part of the base region 212 is formed above the base region 212, and the material of the cap silicon layer is the same as that of the top silicon layer. A preset position of the cap silicon layer is heavily doped to form an emitter region 213; an insulating layer 71 is formed on the base region 212 not covered by the emitter region 213, and the thickness of the insulating layer is the same as that of the emitter region, and is flush with the height of other active regions. Among them, the sum of the thickness of the collector region 211, the thickness of the base region 212, and the thickness of the emitter region 213 is equal to the thickness of the top silicon layer in other active regions. The material of the insulating layer 71 may be silicon oxide, which can improve the insulation performance of the metal interconnection structure between various regions of the SiGe transistor.

[0103] In the above embodiment, the collector region, base region, and emitter region of the SiGe transistor are arranged longitudinally along the depth direction, which saves the lateral space of the wafer and allows more components to be arranged on the same wafer.

[0104] As an example, the collector region may be doped with N. The SiGe layer in the base region may be a doped SiGe layer, whose doping type is different from that of the collector region. When the collector region is N-doped, the SiGe layer is doped with P. The emitter region may be doped with N, which is different from that of the SiGe layer. When the SiGe layer is P-doped, the emitter region may be doped with N.

[0105] In some embodiments, the surface of the emitter region is as flush as possible with the surface of the top silicon layer in other regions to facilitate subsequent processes. As an implementation, the MOS transistor includes: a well region 221, a gate 222, a source region, and a drain region (223, 224). The well region 221 is located in the first active region; the gate 222 is located above the well region 221; the source region and the drain region are respectively located in the well region 221 on both sides of the gate 222, such as Figure 1 shown.

[0106] The gate 222 of the MOS tube may include a gate oxide layer and a polysilicon layer, and the gate oxide layer and the polysilicon layer are sequentially stacked on the first active region.

[0107] As an implementation mode, when the MOS tube 22 is an NMOS tube, its formation method may be: by performing P-type doping in the top silicon of the first active region to form a P-type well region; depositing a gate oxide layer and a polysilicon layer on the substrate in sequence, etching the gate oxide layer and the polysilicon layer to form a gate on the P-type well region, performing N-type doping in the P-type well regions on both sides of the gate to form a source region and a drain region respectively. When the MOS tube 22 is a PMOS tube, its formation method may be: by performing N-type doping in the top silicon of the first active region to form an N-type well region; then forming a gate on the N-type well region, performing P-type doping in the N-type well regions on both sides of the gate to form a source region and a drain region respectively.

[0108] As an implementation mode, the MOS tube 22 can be formed after the SiGe triode is formed, or the MOS tube 22 can be prepared before the SiGe triode is formed. The MOS tube 22 can also form a well region of the MOS tube in the first active region before the SiGe triode is prepared, form a mask layer on the active region where the SiGe triode does not need to be formed, and form the gate, source region, and drain region of the MOS tube in the first active region after the SiGe triode is formed in the second active region. The formation order of the MOS and SiGe triode is not limited here.

[0109] The metal interconnect structure 3 in the RF power amplifier structure is used to electrically lead out the MOS tube and the SiGe transistor. The drain region or source region of the MOS tube 22 is electrically connected to the base region of the SiGe transistor 21 .

[0110] like Figure 1 As shown, in one embodiment, the metal interconnection structure for electrically leading out the MOS transistor is located on the front side of the substrate, and the metal interconnection structure of the MOS transistor is located in the first insulating layer 41 formed on the substrate, and the top is exposed from the top surface of the first insulating layer, and the bottom is respectively in contact with the gate, source region and / or drain region of the MOS transistor. The metal interconnection structure for electrically leading out the emitter region and the base region of the SiGe triode is also located in the first insulating layer 41 on the front side of the substrate, that is, the first emitter region electrode structure and the first base region electrode structure are located in the first insulating layer 41 and the top is exposed from the top surface of the first insulating layer, the bottom end of the first emitter region electrode structure contacts the emitter region, and the bottom end of the first base region electrode structure contacts the SiGe layer. The first collector region electrode structure for electrically leading out the collector region of the SiGe triode is located in the substrate 101 and the buried oxide layer 102 on the back side of the substrate, and the top is in contact with the collector region 211, and the bottom is exposed from the bottom surface of the substrate 101. Wherein, the material of the substrate 101 is silicon oxide.

[0111] Please refer to Figure 3 In other embodiments, the metal interconnection structure for electrically leading out the MOS tube and the metal interconnection structure for electrically leading out the emitter region, base region, and collector region of the SiGe triode are all located on the front side of the substrate. Specifically, the substrate 10 includes a base plate 101, a buried oxide layer 102, and a top silicon layer 103 stacked in sequence. The substrate is an SOI wafer. The structure of the SiGe triode is similar to Figure 1 The structure of the SiGe triode in the embodiment shown is similar, and the difference is that: the second active region also includes a first heavily doped region 35, and the first heavily doped region is located between the collector region 211, the base region 212, the emitter region 213 and the shallow trench isolation structure; wherein the first heavily doped region contacts the collector region 211, and an insulating sidewall 36 is formed between the first heavily doped region 35 and the base region 212 and the emitter region 213. The first heavily doped region 35 contacts the collector region 211, and is used for electrical extraction of the collector region. wherein an insulating sidewall 36 is formed between the first heavily doped region 35 and the base region 212 and the emitter region 213, and the first heavily doped region 35 is insulated from the base region and the emitter region. The metal interconnection structure is located in a second insulating layer 42 formed on the substrate, and the top end is exposed from the top surface of the second insulating layer 42, and the bottom end contacts the gate, source region and / or drain region of the MOS tube, the base region, the emitter region and the first heavily doped region 35 of the SiGe triode.

[0112] Specifically, the metal interconnection structure includes the metal interconnection structure of each MOS tube and the metal interconnection structure of the SiGe triode; the metal interconnection structure of the SiGe triode includes a second base region electrode structure, a second emitter region electrode structure and a second collector region electrode structure; wherein: a second insulating layer is formed above the substrate, the metal interconnection structure of each MOS tube, the second emitter region electrode structure, the second base region electrode structure and the second collector region electrode structure are located in the second insulating layer, and the top end is exposed from the top surface of the second insulating layer; the bottom end of the metal interconnection structure of each MOS tube contacts the gate and the source region and / or drain region of each MOS tube respectively; the bottom end of the second emitter region electrode structure contacts the emitter region, the bottom end of the second base region electrode structure contacts the base region, and the bottom end of the second collector region electrode structure contacts the first heavily doped region.

[0113] like Figure 1-Figure 3 In the embodiment shown, the number of MOS tubes is one. In different embodiments, the number of MOS tubes can also be two or more. In this case, all MOS tubes are cascaded with each other, that is, all MOS tubes are used as amplifier tubes to form multi-stage amplification; each MOS tube is electrically connected through its drain region or source region, and the drain region or source region of the last stage MOS tube is electrically connected to the base region of the SiGe triode. By setting two or more MOS tubes, the output power of the RF power amplifier structure is further improved. Figure 4-Figure 8 The case where the number of MOS tubes is two or more is described in detail.

[0114] Please refer to further Figure 4 and Figure 5 ,in, Figure 4 is a cross-sectional view of a first amplifying module and a second amplifying module according to another embodiment of the present invention; Figure 5 FIG. 4 is a circuit diagram of a radio frequency power amplifier structure according to another embodiment of the present invention.

[0115] like Figure 4 As shown, in another embodiment of the present invention, the first amplification module is Figure 1 A MOS tube is added to the structure shown in the figure: a second MOS tube 23, that is, the number of MOS tubes is 2. The second MOS tube 23 is also formed on the substrate 10, the output end of the first MOS tube 22 is electrically connected to the input end of the second MOS tube 23, and the output end of the second MOS tube 23 is electrically connected to the base region of the SiGe triode 21, as shown in FIG. Figure 5 The circuit is shown in the figure.

[0116] exist Figure 4In the illustrated embodiment, the SiGe transistor 21, the first MOS transistor 22, and the second MOS transistor 23 are arranged in sequence from left to right, the number of the first active regions may be two, the first MOS transistor 22 is located in one of the first active regions, the second MOS transistor 23 is located in the other first active region, and the two first active regions are located on the same side of the SiGe transistor 21. Of course, it should be appreciated that the arrangement positions of the SiGe transistor 21, the first MOS transistor 22, and the second MOS transistor 23 on the substrate can be freely set as needed, such as: the first MOS transistor 22 and the second MOS transistor 23 can be located on both sides of the SiGe transistor 21, such as Figure 6 As shown, the first MOS transistor 22 is located in a first active region adjacent to one side of the second active region, and the second MOS transistor 23 is located in another first active region adjacent to the other side of the second active region.

[0117] In one implementation, the first MOS transistor 22 and the second MOS transistor 23 may be of the same type. For example, they may both be NMOS transistors, in which case the drain of the first MOS transistor 22 serves as its output terminal, and the source region of the second MOS transistor 23 serves as its input terminal, that is, the drain region of the first MOS transistor 22 is electrically connected to the source region of the second MOS transistor 23. Of course, in different examples, the second MOS transistor 23 and the first MOS transistor 22 may both be PMOS, in which case the source of the first MOS transistor 22 serves as its output terminal, and the drain of the second MOS transistor 23 serves as its input terminal, that is, the source region of the first MOS transistor 22 is electrically connected to the drain region of the second MOS transistor 23.

[0118] In another embodiment, when the second MOS transistor 23 is of the same type as the first MOS transistor 22, the second MOS transistor and the first MOS transistor can be arranged in the same active region, that is, the number of the first active region is one. Figure 7 In this embodiment, the arrangement of shallow trench isolation structures can be reduced, thereby reducing the lateral area occupied by the substrate.

[0119] When the second MOS transistor 23 is of the same type as the first MOS transistor 22, the source regions and drain regions of the two are of the same doping type. For example, when both are NMOS transistors, the source regions and drain regions of the two are N-type doped; when both are PMOS transistors, the source regions and drain regions of the two are P-type doped. Since the source regions and drain regions of the two are of the same doping type, the electrical connection terminals of the two can be shared. That is, when the first MOS transistor 22 and the second MOS transistor 23 are both NMOS transistors, the drain region of the first MOS transistor 22 is shared with the source region of the second MOS transistor 23. Figure 7As shown. Similarly, when the first MOS transistor 22 and the second MOS transistor 23 are both PMOS transistors, the source region of the first MOS transistor 22 and the drain region of the second MOS transistor 23 are shared. By sharing the source region and the drain region, the substrate area occupied by the MOS transistor is further reduced, so that more components can be arranged on the substrate of the same size; in addition, since the source region and the drain region are shared, the interconnection has been achieved, so that the shared area does not need to be connected through the metal interconnection structure, which is conducive to reducing the arrangement density of the metal interconnection structure, and then reducing the arrangement density of the metal interconnection line, reducing the risk of short circuit, and improving the stability of the structure.

[0120] Preferably, when all MOS tubes are NMOS tubes, the MOS tube of the first stage can be a common-source amplifier, the gate of the MOS of the first stage is connected to the input voltage, and its source region is connected to the ground voltage to provide sufficient gain; the remaining MOS tubes can be common-gate amplifiers, and the gates of the remaining MOS tubes are connected to a fixed voltage to provide sufficient input impedance.

[0121] In another embodiment, the type of the second MOS transistor 23 and the first MOS transistor 22 may also be different. For example, the first MOS transistor 22 may be an NMOS, and the second MOS transistor 23 may be a PMOS. When used as an amplifier, the drain of the first MOS transistor 22 serves as its output end, and the drain of the second MOS transistor 23 serves as its input end. At this time, the drain region of the first MOS transistor 22 is electrically connected to the drain region of the second MOS transistor 23. Of course, in different examples, the first MOS transistor 22 may also be a PMOS, and the second MOS transistor 23 may be an NMOS. When used as an amplifier, the source of the first MOS transistor 22 serves as its output end, and the source of the second MOS transistor 23 serves as its input end. At this time, the source region of the first MOS transistor 22 is electrically connected to the source region of the second MOS transistor 23.

[0122] like Figure 4-Figure 7 In the embodiment shown, the number of MOS transistors is two. In different embodiments, the number of MOS transistors may be more than two, such as Figure 8 As shown, Figure 8 In the figure, three are taken as an example, namely: the first MOS tube 22, the second MOS tube 23, and the third MOS tube 24; the setting principle of more than three is similar, which will not be repeated here.

[0123] Please refer to further Figure 9-10 , the following will be combined Figure 9-10 The metal interconnect structure in the radio frequency power amplifier structure of the embodiment of the present invention is described in detail.

[0124] like Fig. 9 and Fig.10As shown, the metal interconnection structure in the embodiment of the present invention includes the metal interconnection structure 31 of each MOS transistor and the metal interconnection structure of the SiGe transistor.

[0125] In one embodiment, the metal interconnect structure of the SiGe transistor includes a first base electrode structure 32, a first emitter electrode structure 33, and a first collector electrode structure 34. Fig. 9 As shown, the metal interconnect structure 31 of each MOS tube and the first base electrode structure 32 and the first emitter electrode structure 33 of the SiGe triode are led out from the front side of the substrate; the first collector electrode structure 34 is led out from the back side of the substrate, as shown in FIG. Fig. 9 As shown. Specifically: a first insulating layer 41 is formed above the substrate, and the metal interconnection structure of each MOS tube, the first base region electrode structure 32, and the first emitter region electrode structure 33 are located in the first insulating layer 41, and the top is exposed from the top surface of the first insulating layer 41. The bottom end of the metal interconnection structure 31 of each MOS tube contacts the gate and the source region and / or drain region of each MOS tube respectively; the bottom end of the first emitter region electrode structure 33 contacts the emitter region, and the bottom end of the first base region electrode structure 32 contacts the base region. The first collector region electrode structure 34 is located in the substrate 101 and the buried oxide layer 102, and the top contacts the collector region, and the bottom is exposed from the bottom surface of the substrate 101.

[0126] In this embodiment, by leading the first collector region electrode structure 34 out from the back side of the substrate, it is helpful to reduce the setting density of the metal interconnection structure on the front side of the substrate, so that the setting space of the metal interconnection structure on the front side of the substrate is larger and easier; this in turn helps to reduce the setting density of the metal interconnection lines, reduce the risk of short circuits, and improve the stability of the circuit.

[0127] in, Fig. 9 In the example, the first MOS tube and the second MOS tube are both NMOS tubes, the gate electrode of the first MOS tube is used as the input terminal, and the electrode structure of the drain region of the second MOS tube is electrically connected to the first base region electrode structure 32 of the SiGe triode through the first metal interconnection line 51; since the first MOS tube and the second MOS tube are in the same active region, the drain region of the second MOS tube is shared with the source region of the first MOS tube to achieve electrical connection between the two, and the integration of the three-stage amplifier is achieved through the electrical connection of the first MOS tube, the second MOS tube, and the SiGe triode on the same substrate. If the first MOS tube and the second MOS tube are not in the same active region, the drain region of the second MOS tube is not shared with the source region of the first MOS tube, and the source region / drain region of the first MOS tube and the second MOS tube are both connected with an electrode structure, and the drain region electrode structure of the first MOS tube is electrically connected to the source region electrode structure of the second MOS tube through a second metal interconnection line (not shown).

[0128] As an example, Fig. 9 The method for preparing the RF power amplifier structure in which the first collector region electrode structure is led out from the back side as shown, for example, includes: providing an SOI substrate, which includes a bottom silicon layer, a buried oxide layer, and a top silicon layer distributed in sequence from bottom to top; preparing the above-mentioned SiGe triode, the first MOS tube, and the second MOS tube in the top silicon layer; preparing the metal interconnection structure 31 of each MOS tube and the first base region electrode structure 32 and the first emitter region electrode structure 33 of the SiGe triode on the front side of the substrate; thinning the back side of the substrate to remove the bottom silicon to expose the buried oxide layer; forming an oxide layer at the bottom of the buried oxide layer as a substrate, and preparing the first collector region electrode structure 34 in the substrate and the buried oxide layer.

[0129] As an example, the first collector region electrode structure may be implemented by using a TSV through-hole structure, where the TSV through-hole penetrates the buried oxide layer and the substrate to serve as an output port of the SiGe transistor.

[0130] In another embodiment, the second active region where the SiGe triode is located further includes a first heavily doped region 35, and the first heavily doped region is located between the collector region, the base region, the emitter region and the shallow trench isolation structure; wherein the first heavily doped region contacts the collector region 211, and an insulating sidewall 35 is formed between the first heavily doped region and the base region 212 and the emitter region 213. The metal interconnection structure of the SiGe triode includes a second base region electrode structure 37, a second emitter region electrode structure 38 and a second collector region electrode structure 39. Fig.10 As shown, the metal interconnection structure 31 of each MOS tube and the second base electrode structure 37, the second emitter electrode structure 38, and the second collector electrode structure 39 of the SiGe triode are all led out from the front side of the substrate. Specifically, a second insulating layer 42 is formed above the substrate on which the SiGe triode and the MOS tube are formed, and the metal interconnection structure 31, the second base electrode structure 37, the second emitter electrode structure 38, and the second collector electrode structure 39 of each MOS tube are located in the second insulating layer 42, and the top is exposed from the top surface of the second insulating layer 42. The bottom end of the metal interconnection structure 31 of each MOS tube contacts the gate and the source and / or drain region of each MOS tube respectively; the bottom end of the second base electrode structure 37 contacts the base region, the bottom end of the second emitter electrode structure 38 contacts the emitter region, and the bottom end of the second collector electrode structure 39 contacts the first heavily doped region 35.

[0131] Fig.10 The electrical connections between the MOS tubes and SiGe transistors are not shown. Fig.10In the example, the first MOS transistor and the second MOS transistor are of different types. Specifically, one of the first MOS transistor and the second MOS transistor is NMOS and the other is PMOS. Of course, as described above, the types of the first MOS transistor and the second MOS transistor can be the same or different, which are all within the protection scope of the present invention.

[0132] As an example, Fig.10 The method for preparing the RF power amplifier structure in which all electrode structures are led out from the front side includes, for example: providing an SOI substrate, which includes a bottom silicon layer, a buried oxide layer, and a top silicon layer distributed from bottom to top; preparing the above-mentioned SiGe triode, the first MOS transistor, and the second MOS transistor in the top silicon layer; preparing the metal interconnection structure 31 of each MOS transistor and the second base electrode structure 37, the second emitter electrode structure 38, and the second collector electrode structure 39 of the SiGe triode on the front side of the substrate. At this time, the bottom silicon layer of the SOI substrate is the base plate.

[0133] It should be noted that the number of collector region electrode structures can be two, such as Fig.10 As shown, the two collector region structures are located on both sides of the emitter region. Of course, the number of collector region electrode structures can also be one, such as Fig. 9 In addition, when the electrode structure is led out from the front side of the substrate, the collector region electrode structure is located on one side of the emitter region. Similarly, the number of base region electrode structures can be two, such as Fig.10 As shown, the two base electrode structures are located on both sides of the emitter region. And the base electrode structure can also be one, such as Fig. 9 As shown, it is located on one side of the emission area.

[0134] In a preferred embodiment, a conductive contact layer 61 is provided on the surface of the electrode lead-out position of each MOS tube and SiGe transistor, that is, the gate, source region, drain region of the MOS tube and the base region, emitter region, collector region of the SiGe transistor. Fig. 9 and Fig.10 As shown, each region is electrically connected to the metal interconnect structure through a conductive contact layer 61, so that the electrical connection performance is better. The material of the conductive contact layer is metal silicide. Specifically, the metal silicide can be: cobalt silicide, titanium silicide, nickel silicide, etc.

[0135] In a preferred embodiment, an insulating layer 71 may be provided between adjacent conductive contact layers of each region of the SiGe transistor, and between the conductive contact layer and the boundary of the second active region. Fig. 9 and Fig.10 As shown; thereby, the insulation performance between the electrode structures of the SiGe triode is better, and thus the electrical performance is better.

[0136] Accordingly, the embodiment of the present invention further provides a radio frequency power amplifier circuit, please continue to refer to Figure 2 The amplifier circuit includes: at least one MOS tube, a SiGe transistor, and an input voltage. The MOS tube and the SiGe transistor are located on the same substrate; the gate of the MOS tube is coupled to the input voltage, the drain region or source region of the MOS tube is coupled to the base region of the SiGe transistor, and the collector region of the SiCe transistor serves as the output end of the RF power amplifier circuit.

[0137] In one embodiment, the RF power amplifier circuit may include a first MOS tube 22 and a SiGe transistor 21, and the circuit is used to receive and amplify an input voltage to generate an output voltage. Specifically, the first MOS tube 22 may be an NMOS tube, the gate of the NMOS tube may be connected to an input voltage source Vi, the source terminal of the NMOS may be connected to a first voltage level (or ground voltage or 0V), the drain terminal of the NMOS tube is coupled to the base terminal of the SiGe transistor 21, and the emitter terminal of the SiGe transistor 21 may be connected to a second voltage level (or ground voltage or 0V), and the collector region of the SiGe transistor 21 serves as the voltage output terminal RF-OUT of the circuit.

[0138] As an embodiment, the RF power amplifier circuit further includes an auxiliary matching circuit to improve the performance and stability of the RF power amplifier circuit. The matching circuit includes other auxiliary components such as capacitors and inductors. Figure 2 As shown, the first capacitor is connected in series to the output end of the SiGe transistor, the first capacitor is connected to the first end of the inductor, and the second end of the inductor is connected to the output end of the amplifier circuit. The first end of the second capacitor is connected to the second end of the inductor, and the second end of the second capacitor is grounded. Those skilled in the art can set appropriate capacitors, resistors, inductors and other auxiliary devices according to specific circumstances to improve circuit performance and stability, which is not limited here.

[0139] Please refer to further Figure 5 , Figure 8 ,like Figure 5 , Figure 8 As shown, in some other embodiments of the present invention, the RF power amplifier circuit includes: two or more MOS tubes, SiGe transistors, and an input voltage; wherein the MOS tube and the SiGe transistor are located on the same substrate; all MOS tubes are cascaded with each other, wherein the gate of the MOS tube of the first stage is coupled to the input voltage Vi, the drain region or source region of the MOS tube of the last stage is coupled to the base region of the SiGe transistor, and the collector region of the SiCe transistor serves as the output terminal RF-OUT of the RF power amplifier circuit.

[0140] Figure 5In the example of two NMOS transistors, each stage of MOS transistors has a drain as an output, the drain of the first stage MOS transistor is connected to the source of the last stage MOS transistor to achieve cascade connection, and the drain of the last stage MOS transistor is coupled to the base of the SiGe transistor. Specifically, the gate of the first stage MOS transistor 22 can be connected to an input voltage source Vi, the source terminal of the first stage MOS transistor 22 can be connected to a first voltage level (or ground voltage or 0V), the drain terminal of the first stage MOS transistor 22 is coupled to the source terminal of the second stage MOS transistor 23, the gate terminal of the second stage MOS transistor 23 can be connected to a fixed voltage VG (or ground voltage), where the fixed voltage can be used as a common reference terminal for the input signal and the output signal of the second stage MOS transistor 33, the drain terminal of the second stage MOS transistor 23 is coupled to the base terminal of the SiGe transistor 21, and the emitter terminal of the SiGe transistor 21 can be connected to a second voltage level (or ground voltage or 0V), and the collector region of the SiGe transistor 21 serves as the voltage output terminal RF-OUT of the circuit. In different embodiments, both MOS tubes can be PMOS tubes, and when the PMOS tube is used as an amplifier, the source is used as an output. The types of the two MOS tubes can also be different, the drain of the NMOS tube is used as an output, and the source of the PMOS tube is used as an output.

[0141] As an embodiment, the RF power amplifier circuit further includes an auxiliary matching circuit to improve the performance and stability of the RF power amplifier circuit. The matching circuit includes other auxiliary components such as capacitors and inductors. Figure 5 As shown, the first capacitor is connected in series to the output end of the SiGe transistor, the first capacitor is connected to the first end of the inductor, and the second end of the inductor serves as the output end of the amplifier circuit. The first end of the second capacitor is connected to the second end of the inductor, and the second end of the second capacitor is grounded. Those skilled in the art can set appropriate capacitors, resistors, inductors and other auxiliary devices according to specific circumstances to improve circuit performance and stability, which is not limited here.

[0142] In summary, the present invention provides a radio frequency power amplifier structure and a radio frequency power amplifier circuit. By combining a first amplifier module composed of a MOS tube with a second amplifier module composed of a SiGe transistor to form a radio frequency power amplifier with at least two stages of amplification, a greater power output and a higher conversion efficiency can be provided, and the SiGe transistor is easier to integrate with the MOS tube; in addition, the MOS tube and the SiGe transistor are formed on the same substrate, realizing substrate-level packaging, thereby improving integration and reducing costs.

[0143] In the description of this specification, the description with reference to the terms "an implementation", "an example", "a specific implementation process", "an example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A radio frequency power amplifier structure, characterized in that: include: A substrate; the substrate comprises an active area and a shallow trench isolation structure, and adjacent active areas are isolated by the shallow trench isolation structure; A first amplification module, comprising at least one MOS tube, located in a first active area of ​​the substrate; A second amplification module, including a SiGe triode, is located in a second active area adjacent to the first active area; The metal interconnection structure is used to electrically lead out the MOS tube and the SiGe triode, and the drain region or source region of the MOS tube is electrically connected to the base region of the SiGe triode.

2. The radio frequency power amplifier structure according to claim 1, characterized in that: The number of the MOS tubes is two or more, all the MOS tubes are cascaded, and the drain region or source region of the last stage MOS tube is electrically connected to the base region of the SiGe triode.

3. The RF power amplifier structure according to claim 2, characterized in that: The MOS tubes are electrically connected through their drain regions or source regions.

4. The radio frequency power amplifier structure according to any one of claims 1 to 3, characterized in that: The substrate comprises a base plate, a buried oxide layer and a top silicon layer stacked in sequence, the SiGe triode is formed in a second active region of the top silicon layer, wherein the thickness of the top silicon layer in the second active region is less than the thickness of the top silicon layer in other active regions; the SiGe triode comprises: A collector region formed by heavily doping the top silicon layer of the second active region; A base region, formed by a SiGe layer formed on the collector region; The emitter region is formed by heavily doping the second top silicon layer formed on the base region, and the emitter region covers a portion of the surface of the base region and exposes a portion of the surface of the base region.

5. The radio frequency power amplifier structure according to claim 4, characterized in that: The metal interconnection structure includes the metal interconnection structure of each MOS tube and the metal interconnection structure of the SiGe triode; the metal interconnection structure of the SiGe triode includes a first base region electrode structure, a first emitter region electrode structure and a first collector region electrode structure; wherein: A first insulating layer is formed above the substrate, and the metal interconnection structure of each MOS tube, the first emitter region electrode structure, and the first base region electrode structure are located in the first insulating layer, and the top end is exposed from the top surface of the first insulating layer; the bottom end of the metal interconnection structure of each MOS tube contacts the gate and the source region and / or the drain region of each MOS tube respectively, the bottom end of the first emitter region electrode structure contacts the emitter region, and the bottom end of the first base region electrode structure contacts the SiGe layer; The first collector region electrode structure is located in the substrate and the buried oxide layer, with a top end contacting the collector region and a bottom end exposed from the bottom surface of the substrate.

6. The radio frequency power amplifier structure according to claim 5, characterized in that: The collector region electrode structure is a TSV through-hole structure, and the TSV through-hole penetrates the buried oxide layer and the substrate to serve as an output port of the SiGe transistor.

7. The radio frequency power amplifier structure according to claim 4, characterized in that: The second active region also includes a first heavily doped region, which is located between the collector region, the base region, the emitter region and the shallow trench isolation structure; wherein the first heavily doped region contacts the collector region, and an insulating side wall is formed between the first heavily doped region and the base region and the emitter region.

8. The radio frequency power amplifier structure according to claim 7, characterized in that: The metal interconnection structure includes the metal interconnection structure of each MOS tube and the metal interconnection structure of the SiGe triode; the metal interconnection structure of the SiGe triode includes a second base electrode structure, a second emitter electrode structure and a second collector electrode structure; wherein: A second insulating layer is formed above the substrate, and the metal interconnection structure of each MOS tube, the second emitter region electrode structure, the second base region electrode structure and the second collector region electrode structure are located in the second insulating layer, and the top ends are exposed from the top surface of the second insulating layer; The bottom end of the metal interconnect structure of each MOS tube contacts the gate and source region and / or drain region of each MOS tube respectively; The bottom end of the second emitter region electrode structure contacts the emitter region, the bottom end of the second base region electrode structure contacts the base region, and the bottom end of the second collector region electrode structure contacts the first heavily doped region.

9. A radio frequency power amplifier circuit, characterized in that: include: At least one MOS tube, SiGe transistor, input voltage; wherein, The MOS transistor and the SiGe triode are located on the same substrate; The gate of the MOS tube is coupled to the input voltage, the drain region or the source region of the MOS tube is coupled to the base region of the SiGe transistor, and the collector region of the SiCe transistor serves as the output end of the radio frequency power amplifier circuit.

10. The radio frequency power amplifier circuit according to claim 9, characterized in that: The MOS tubes include two or more; The MOS transistor and the SiGe triode are located on the same substrate; All MOS tubes are cascaded with each other, wherein the gate of the MOS tube of the first stage is coupled to the input voltage, the drain region or source region of the MOS tube of the last stage is coupled to the base region of the SiGe transistor, and the collector region of the SiCe transistor serves as the output end of the RF power amplifier circuit.

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