Integrated circuit structure and manufacturing method thereof

Abstract

The present disclosure provides an integrated circuit (IC) structure in accordance with some embodiments. The IC structure includes a circuit structure having a semiconductor device formed on a first substrate, an interconnect structure over the semiconductor device; and a heat dissipation structure formed on the second substrate. The second substrate is bonded to the circuit structure such that the heat dissipation structure is interposed between the first substrate and the second substrate. The heat dissipation structure includes a diamond-like carbon (DLC) layer. The DLC layer includes a bottom portion having a large grain size and a top portion having a fine DLC grain size. The present disclosure also provides a method of fabricating an integrated circuit (IC) structure according to some embodiments.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit structures and methods for manufacturing the same. Background Art

[0002] Many technological advances have occurred in the field of 3D IC packaging, including stacking and bonding multiple chips together. Each chip includes at least one functional IC, such as an IC configured to perform logic functions, memory functions, digital functions, analog functions, mixed signal functions, radio frequency (RF) functions, I / O functions, communication functions (e.g., providing support for wired and / or wireless communications by implementing desired communication protocols, such as 5G (i.e., fifth generation) wireless communication protocols, Ethernet communication protocols, IB communication protocols, etc.), power management functions, other functions, or combinations thereof. Some of these involve capacitors.

[0003] As 3D IC stacking technology continues to advance, integrated chips may encounter various problems, including heat dissipation problems, which may further lead to other problems, such as bonding and stress problems. Therefore, although existing 3DIC structures and methods of manufacturing the 3DIC structures are generally sufficient for their intended purposes, they are not satisfactory in all aspects. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, an integrated circuit (IC) structure is provided, comprising: a circuit structure having a semiconductor device formed on a first substrate and an interconnection structure above the semiconductor device; and a heat dissipation structure formed on a second substrate, wherein the second substrate is bonded to the circuit structure so that the heat dissipation structure is between the first substrate and the second substrate, the heat dissipation structure comprising a diamond-like carbon (DLC) layer, and the DLC layer comprising a bottom portion having a large grain size and a top portion having a fine grain size.

[0005] According to another aspect of an embodiment of the present application, a method for manufacturing an integrated circuit (IC) structure is provided, comprising: forming a circuit structure having a semiconductor device formed on a first substrate and an interconnection structure above the semiconductor device; forming a heat dissipation structure on a second substrate; and bonding the second substrate to the circuit structure so that the heat dissipation structure is interposed between the first substrate and the second substrate, wherein forming the heat dissipation structure comprises forming a diamond-like carbon (DLC) layer, the diamond-like carbon layer comprising a bottom portion of the DLC layer having a large DLC grain size and a top portion of the DLC layer having a fine grain size.

[0006] According to another aspect of an embodiment of the present application, a method for manufacturing an integrated circuit (IC) structure is provided, comprising: forming a first stack of a first semiconductor layer of a first semiconductor material and a second semiconductor layer of a second semiconductor material alternately stacked on a first substrate; forming a first diamond-like carbon (DLC) layer on the first stack; forming a second stack of a third semiconductor layer of a first semiconductor material and a fourth semiconductor layer of a second semiconductor material alternately stacked on a second substrate; forming a second DLC layer on the second stack; bonding the second substrate to the first substrate so that the first DLC layer and the second DLC layer are directly bonded together, wherein the first DLC layer has a first non-uniform structure and the second DLC layer has a second non-uniform structure; thinning the first substrate; and forming complementary field effect transistors (CFETs) in the first stack and the second stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, the size of the various components may be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the drawings illustrate only typical embodiments of the present application and therefore should not be considered to be limiting of the scope, as the present application may be equally well applied to other embodiments.

[0008] Figure 1 A cross-sectional view of an integrated circuit (IC) structure according to various aspects of the present disclosure is shown.

[0009] Figure 2A-2B Part or all of the present disclosure shows the formation of various aspects Figure 1 Flowchart of a method for IC structure.

[0010] Figure 3-Figure 10 According to the embodiment of the present disclosure, Figure 2A-2B Methods for illustrating cross-sectional views of IC structures at various intermediate stages of fabrication and processing.

[0011] Fig.11 is a flow chart of a method of forming part or all of an IC structure according to various aspects of the present disclosure.

[0012] Figure 12-14 According to the embodiment of the present disclosure, Fig.11 Methods for illustrating cross-sectional views of IC structures at various intermediate stages of fabrication and processing.

[0013] Fig.15 A cross-sectional view of an IC structure according to various aspects of the present disclosure is shown.

[0014] Fig.16According to the present disclosure, part or all of the Fig.15 Flowchart of a method for IC structure.

[0015] Figure 17-Figure 26 The embodiment according to the present disclosure is shown Fig.16 Methods for illustrating cross-sectional views of IC structures at various intermediate stages of fabrication and processing. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0018] In addition, when a number or a series of numbers is described using "about," "approximately," etc., the term is intended to encompass numbers within a reasonable range taking into account variations inherent in the manufacturing process as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing features having properties associated with the numbers, the number or range of numbers includes a reasonable range of the described numbers, such as within + / -10% of the described numbers. For example, a material layer having a thickness of "about 5 nm" may include a size range of 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer is + / -15% known to those of ordinary skill in the art. In addition, the present disclosure may repeat figure numerals and / or characters in various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate the relationship between the various embodiments and / or configurations discussed.

[0019] The present disclosure relates to an integrated circuit (IC) structure and a method for manufacturing the same, and more specifically, to a complementary field effect transistor (CFET) device with an enhanced heat dissipation structure. The present disclosure also relates to methods and structures for IC structures with advanced packaging structures, such as three-dimensional IC (3DIC) structures, and methods for manufacturing the same. A 3DIC structure is a stacked structure with heterogeneous integration, such as a logic device stacked on a memory device, or vice versa. Specifically, in the disclosed embodiments, the 3DIC structure includes a CFET structure including an n-type FET (nFET) and a p-type FET (pFET) stacked vertically on each other.

[0020] In the disclosed embodiments, the IC structure includes a transistor structure having a plurality of vertically stacked transistors, each vertically stacked transistor including a plurality of vertically stacked nanowires or nanosheets as channels and a gate structure surrounding each channel. More specifically, the IC structure includes a complementary field effect transistor (CFET) structure and a method of manufacturing a CFET. The CFET may include an N-type FET vertically above a P-type FET or a P-type FET vertically above an N-type FET.

[0021] In some embodiments, the IC structure includes a carrier substrate, which is bonded to another substrate on which an integrated circuit is formed. The carrier substrate also includes a heat dissipation structure formed thereon, and the heat dissipation structure is configured between the integrated circuit and the carrier substrate to provide heat dissipation. It should be understood that the structures provided are only some embodiments, and the IC structure may include more than two semiconductor structures bonded together with similar bonding structures. The IC structure includes a heat dissipation structure of a diamond-like carbon (DLC) layer, and the DLC layer has a top portion with a fine grain size. In some embodiments, the heat dissipation structure of the DLC includes a hierarchical structure, and the grain size of the hierarchical structure gradually decreases from bottom to top. Therefore, the top surface of the DLC layer is a natural plane.

[0022] A DLC layer having a non-uniform grain size is formed on a carrier substrate. Specifically, forming the DLC layer includes forming a bottom portion having a large grain size and then forming a top portion having a fine grain size smaller than the large grain size. The DLC layer has a high thermal conductivity. However, DLC is difficult to be flattened due to the large grain size and high hardness. In the disclosed DLC layer, the top portion has a fine grain size, has reduced roughness and improved flatness.

[0023] The process conditions for forming the disclosed DLC layer are controlled to form a DLC layer having different grain sizes. The DLC layer includes a bottom portion having a large grain size and a top portion having a small grain size. In a disclosed embodiment, the bottom portion of the DLC layer includes a grain size greater than 500 nm; and the top portion of the DLC layer includes a grain size less than 500 nm. In a further embodiment, the bottom portion of the DLC layer includes a grain size ranging between 500 nm and 5000 nm; and the top portion of the DLC layer includes a grain size ranging between 5 nm and 500 nm.

[0024] The process conditions are described below according to some embodiments. In some embodiments, the DLC layer is formed by a suitable method, such as chemical vapor deposition (CVD) (e.g., plasma CVD), other suitable methods, or combinations thereof. The CVD process is performed with a precursor including a carbon-containing chemical, such as a benzene (C6H6) nitrogen mixture. During the deposition (e.g., CVD) process, the bottom portion is deposited at a first pressure (processing chamber pressure) P1 for a first duration, and the top portion is deposited at a second pressure P2 for a second duration. P2 is greater than P1. In some embodiments, P1 is less than 5 Torr and P2 is greater than 5 Torr. In some embodiments, the first pressure P1 ranges between 1 mTorr and 5 Torr, and the second pressure P2 ranges between 5 Torr and 50 Torr. In some embodiments, depositing the bottom portion of the DLC layer includes depositing the bottom portion of the DLC layer at a first deposition temperature T1; and depositing the top portion of the DLC layer includes depositing the top portion of the DLC layer at a second deposition temperature T2 less than T1. In some embodiments, the first deposition temperature T1 ranges between 400°C and 1200°C. The second deposition temperature T2 is between 100°C and 1200°C. In some embodiments, depositing each of the bottom portion and the top portion of the DLC layer includes performing a CVD process with a radio frequency (RF) power between 50 W and 50 kW.

[0025] In some embodiments, the thickness of such a DLC layer ranges between 1 μm and 20 μm, and the surface roughness of the top surface of the DLC layer is less than 0.5 μm. Roughness is defined as the maximum height difference across the top surface of the DLC layer.

[0026] In some embodiments, the disclosed IC structure is formed by appropriate procedures at various manufacturing stages, such as a monolithic process. The monolithic process is described below according to some embodiments. A semiconductor stack of Si / SiGe is formed on a first substrate and patterned to form a fin active area, a dummy gate stack is formed by deposition and patterning, a bottom gate isolation layer is formed by etching a recessed source / drain (S / D) region, an internal spacer is formed by deposition and etching, a bottom S / D component is formed by epitaxial growth, a bottom S / D isolation layer is formed, a top S / D component is formed on the bottom S / D isolation layer, the dummy gate is removed, the SiGe layer is removed by etching to release the channel, a bottom metal gate stack is formed to surround the bottom channel, a top metal gate stack is formed to surround the top channel, a self-aligned cap (SAC) is formed, and an interconnect structure is formed.

[0027] A DLC layer is formed on a second substrate (carrier substrate) by the disclosed method, a chemical mechanical polishing (CMP) process is performed on the DLC layer, and the second substrate is bonded to the first substrate. Since the disclosed DLC layer includes DLC with a fine grain size on the top, the top surface is substantially planar, and a CMP process with higher flatness can be achieved.

[0028] The first and second substrates are bonded together such that the DLC layer of the second substrate is directly bonded to the front side of the first substrate. After bonding, the first substrate is thinned from the back side and a backside interconnect structure is formed on the back side of the first substrate.

[0029] The present disclosure also provides some alternative embodiments of the IC structure and methods for manufacturing the same. In some embodiments, the IC structure includes a first substrate bonded to a second substrate, and each substrate has a stack of first and second semiconductor layers alternately stacked. Each substrate also includes a heat dissipation structure formed thereon and configured between the two substrates bonded together to provide a bonding interface and heat dissipation. In a further implementation of the embodiment, using the above-disclosed method, a DLC layer is formed on the first substrate and the second substrate, respectively, and then the first substrate is bonded to the second substrate through the DLC layer. Then, the first substrate is thinned, and a CFET device and an interconnect structure are formed on the first substrate from the back side using a similar procedure (e.g., a single-chip process) as described above. In this case, in addition to the heat dissipation structure and the bonding structure, the DLC layer in the bonding interface also acts as an isolation component between the top device and the bottom device.

[0030] In some embodiments, the first substrate is a semiconductor substrate such as a silicon substrate, and the second substrate is a semiconductor substrate or alternatively a dielectric substrate such as one of a silicon nitride substrate, a silicon oxide substrate, and an aluminum oxide substrate.

[0031] The IC structure with DLC layer and the manufacturing method thereof are described in further detail below. The IC structure formed by a monolithic process is first described below according to some embodiments. Figure 1 is a cross-sectional view of an IC structure 100 having a CFET, according to some embodiments.

[0032] refer to Figure 1 , an IC structure 100 having a CFET is formed by a monolithic method. As an exemplary embodiment, Figure 1 A CFET device formed on a substrate 102 is shown, wherein an n-type FET (NFET) and a p-type (PFET) are stacked vertically on each other, thereby reducing circuit area and improving device performance. The CFET device can be formed in any suitable process, such as a monolithic process, a sequential process, a parallel process, other suitable processes, or a combination thereof. Taking a monolithic process as an example, in a monolithic process, both NFET and PFET are formed on the same substrate, for example, NFET is first formed on the same substrate 102, and then PFET is formed.

[0033] IC structure 100 includes various field effect transistors formed on substrate 102, each FET device having multiple channels stacked vertically, such as a gate-all-around (GAA) structure. In particular, bottom device 104B (such as a PFET) and top device 104T (such as an NFET) are stacked vertically on top of each other.

[0034] More specifically, the bottom device 104B of the IC structure 100 includes a plurality of channels 106; a gate stack 108 wrapped around the channels 106; and a source / drain (S / D) feature 110, the S / D features 110 being disposed on both sides of the channels 106 and connected to the vertically stacked channels 106. The bottom device 104B also includes an internal spacer 112 inserted between the gate stack 108 and the S / D features 110 to provide isolation therebetween. The internal spacer 112 includes one or more dielectric materials, such as silicon oxide, silicon nitride, other suitable dielectric materials, or combinations thereof.

[0035] The gate stack 108 also includes a gate dielectric layer 108b and a gate electrode 108a disposed on the gate dielectric layer 108b. In the present embodiment, the gate dielectric layer 108b includes a high-k dielectric material and the gate electrode 108a includes a metal or a metal alloy. In some examples, the gate electrode 108a may include a plurality of sublayers. The high-k dielectric material may include a metal oxide, a metal nitride, such as LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Al2O3, Si3N4, oxynitride (SiON) or other suitable dielectric materials. The gate electrode 108a may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Ru and Co, any suitable conductive material or combination thereof. In some embodiments, different metal materials are used for nFET and pFET devices with respective work functions to enhance device performance. In some embodiments, the gate stack 108 may further include an interface layer 108c between the channel 106 and the high-k dielectric material to improve integration. The interface layer 108c may include silicon oxide.

[0036] Similarly, the top device 104T of the IC structure 100 includes a plurality of channels 206; a gate stack 208 wrapped around the channels 206; and source / drain (S / D) features 210, the S / D features 210 being disposed on both sides of the channels 206 and connected to the vertically stacked channels 206. The bottom device 104B also includes an internal spacer 212 inserted between the gate stack 208 and the S / D features 210 to provide isolation therebetween. The internal spacer 212 includes one or more dielectric materials, such as silicon oxide, silicon nitride, other suitable dielectric materials, or combinations thereof.

[0037] The gate stack 208 also includes a gate dielectric layer 208b and a gate electrode 208a disposed on the gate dielectric layer 208b. In the present embodiment, the gate dielectric layer 208b includes a high-k dielectric material, and the gate electrode 208a includes a metal or a metal alloy. In some examples, the gate electrode 208a may include a plurality of sublayers. In some embodiments, different metal materials are used for nFET and pFET devices with respective work functions to enhance device performance. In some embodiments, the gate stack 208 may further include an interface layer 208c between the channel 206 and the high-k dielectric material to improve integration. The interface layer 208c may include silicon oxide.

[0038] The top device 104T (e.g., NFET) and the bottom device 104B (e.g., PFET) are vertically stacked and isolated from each other by isolation features (e.g., S / D isolation features 114 of one or more dielectric materials and gate isolation layers 118 of one or more dielectric materials). In some embodiments, an etch stop layer 116 may be disposed around the S / D isolation features 114 and include different dielectric materials to achieve etching selectivity.

[0039] The integrated circuit structure 100 also includes a gate spacer 220 of one or more dielectric materials, which is disposed on the sidewalls of the gate stack 208; an S / D contact 222 of one or more conductive materials, which lands on the S / D component 210 to couple the S / D component 210 to a power source; and a self-aligned cap (SAC) 226 of one or more dielectric materials, which is aligned with the gate stack 208 and lands on the gate stack 208. The S / D contact 222 can be further surrounded by a barrier layer 224 of one or more dielectric materials or alternative conductive materials. In some examples, the barrier layer 224 includes a conductive material, such as a titanium film and a titanium nitride film or a tantalum film and a tantalum nitride film. In some other examples, the barrier layer 224 includes a dielectric material, such as silicon nitride, other suitable dielectric materials, or a combination thereof. In this case, the dielectric layer is deposited and etched by a plasma etching process to remove the bottom portion of the barrier layer, thereby having good electrical wiring.

[0040] Figure 2A and Figure 2B is a process flow diagram of a method 300 of fabricating the IC structure 100 . Figures 3 to 11 is a cross-sectional view of an IC structure 100 at various stages of manufacture according to some embodiments. Figure 2A and Figure 2B as well as Figures 3 to 11 The IC structure 100 and the method 300 are collectively described.

[0041] refer to Figure 2A and Figure 3 At operation 302, the method 300 receives or provides a workpiece having a substrate 102 and a semiconductor stack 120, the semiconductor stack 120 having first and second semiconductor layers 120a, 120b interleaved on the substrate 102. The first semiconductor layer 120a includes a first semiconductor material, the second semiconductor layer 120b includes a second semiconductor material, and an intermediate layer 120c of the first semiconductor layer 120a has a higher concentration of the first semiconductor material than the rest of the first semiconductor layer 120a. The first and second semiconductor layers are patterned to form one or more semiconductor stacks as active regions, such as fin active regions.

[0042] In the disclosed embodiment, substrate 102 is a semiconductor substrate, such as a silicon substrate. In some other embodiments, substrate 102 includes germanium, silicon germanium, or other suitable semiconductor materials. Substrate 102 may alternatively be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.

[0043] In some embodiments, the first semiconductor material is silicon germanium, the second semiconductor is silicon, and the intermediate layer 120 c includes silicon germanium and has a higher germanium concentration than the rest of the first semiconductor layer 120 a .

[0044] At operation 304, the method 300 forms a dummy gate structure 124 over a channel region (CR) of the semiconductor stack 120. The dummy gate structure 124 includes a gate spacer 220 and a dummy gate stack 126. At operation 306, the method 300 forms a source / drain (S / D) trench 128 adjacent to the channel region CR, thereby exposing a side surface of the semiconductor stack 120.

[0045] refer to Figure 2A and Figure 4 At operation 308 , the method 300 forms the inner spacer 112 in the channel region CR by a method such as a process including selectively etching the first semiconductor layer 120 a , depositing one or more dielectric materials, and plasma etching.

[0046] refer to Figure 2A and Figure 5 At operation 310, the method 300 epitaxially grows the first S / D feature 110 in the S / D trench 128. At operation 312, the method 300 forms S / D isolation layers 114, 116 over the first S / D feature 110 by a method such as a process including depositing an etch stop layer 116, depositing a dielectric material layer 114, performing a chemical mechanical polishing (CMP) process, and etching back to recess the S / D isolation layers 114, 116.

[0047] Still reference Figure 2A and Figure 5 At operation 314 , the method 300 epitaxially grows the second S / D feature 210 in the S / D trench 128 and over the S / D isolation layers 114 , 116 .

[0048] Still reference Figure 2B and Figure 5At operation 316, the method 300 forms an interlayer dielectric (ILD) layer 130 over the second S / D feature 210 by a method such as a process including deposition and CMP. The ILD structure may further include an etch stop layer 132 having a dielectric material different from the bulk dielectric material of the ILD layer 130 to achieve etch selectivity.

[0049] refer to Figure 2B and Figure 6 At operation 318 , the method 300 removes the dummy gate stack 126 from the dummy gate structure 124 , thereby creating the gate trench 134 . At operation 320 , the method 300 removes the intermediate layer 120 c and replaces it with the gate isolation layer 118 .

[0050] refer to Figure 2B and Figure 7 At operation 322 , the method 300 forms the suspended semiconductor channels 106 , 206 by removing the remaining first semiconductor layer 120 a and leaving the second semiconductor layer 120 b , respectively.

[0051] refer to Figure 2B and Figure 8 At operation 324, the method 300 forms a gate dielectric layer (referred to as 108b, 108c and 208b, 208c, respectively) over the channel region CR and wraps around each suspended semiconductor channel 106, 206 or a subset thereof. Specifically, the dielectric layer 108c, 208c is an interface layer; the dielectric layer 108b, 208b is a dielectric material layer with a high dielectric constant.

[0052] refer to Figure 2B and Fig. 9 At operation 326, method 300 may process the gate dielectric layer, such as thermal annealing. At operation 328, method 300 deposits a gate metal over the gate dielectric layer. The gate metal may be referred to as a (metal) gate electrode 108a, 208a, and after forming the metal gate electrode, a metal gate structure 108, 208 is formed. The gate electrode may include one or more metal layers having different compositions. In addition, the materials of the gate electrodes 108a and 208a may be different materials, such as metals having different work functions.

[0053] refer to Figure 2B and Fig.10At operation 330, the method 300 forms S / D contacts 222, 224 on the first and second S / D components by a suitable method, such as a process including patterning, deposition, and CMP processes. At operation 332, the method 300 may form a SAC component 226 that is self-aligned with the gate stack 208 by, for example, a process including etching to recess the gate stack, depositing one or more dielectric materials, and performing a CMP process. The method 300 may perform other operations to complete the manufacture of the IC structure 100. The present disclosure contemplates additional processing. Additional operations may be provided before, during, and after the method 300, and some of the operations described may be moved, replaced, or eliminated for additional embodiments of the method 300. For example, an interconnect structure 230 may be further formed to couple various devices into the integrated circuit, and other components such as a bonding layer 232 may be further formed on the interconnect structure to provide a bonding surface. In some embodiments, the interconnect structure 230 includes contacts, vias, and metal lines distributed in multiple metal layers. In a copper interconnect, the conductive component includes copper and may further include a barrier layer. The copper interconnect structure is formed by a damascene process. The damascene process includes depositing an ILD layer; patterning the ILD layer to form trenches; depositing various materials (such as a barrier layer and copper); and performing a CMP process. The damascene process can be a single damascene process or a dual damascene process. The deposition of copper can include PVD to form a seed layer and electroplating to form bulk copper on the copper seed layer. Other metals, such as ruthenium, cobalt, tungsten, or aluminum, can be used to form the interconnect structure.

[0054] The IC structure 100 thus formed is further bonded to a carrier substrate having a DLC layer formed by the disclosed method. Fig.11 , Fig.12 , Fig.13 and Fig.14 Described in further detail. Fig.11 is a flow chart of method 350, Fig.12 , Fig.13 and Fig.14 are cross-sectional views of a workpiece 250 at various stages of manufacture, constructed in accordance with some embodiments.

[0055] refer to Fig.11 and Fig.12 , method 350 proceeds to carrier wafer structure 240. At operation 352, a carrier substrate 242 is received or provided. In some embodiments, carrier substrate (or second substrate) 242 is a dielectric substrate, such as a silicon nitride substrate, a silicon oxide substrate, or an aluminum oxide substrate. In some embodiments, carrier substrate 242 is a semiconductor substrate such as a silicon substrate, or alternatively a substrate having other suitable materials.

[0056] At operation 354, a diamond-like carbon (DLC) layer 244 is deposited on the carrier substrate 242. In the disclosed embodiment, the DLC layer also functions as a heat dissipation structure and a bonding structure. Specifically, the DLC layer 244 includes a bottom portion 244B and a top portion 244T having different grain sizes. The top portion 244T of the DLC layer 244 has a fine grain size, while the bottom portion 244B of the DLC layer 244 has a large grain size that is larger than the fine grain size. The grain size is generally distributed. In this sense, the average grain size of the top portion 244T of the DLC layer 244 is smaller than the average grain size of the bottom portion 244B. In the disclosed embodiment, the bottom portion 244B of the DLC layer 244 includes a grain size greater than 500nm; and the top portion 244T of the DLC layer 244 includes a grain size less than 500nm. In a further embodiment, the bottom portion 244B of the DLC layer 244 includes a grain size ranging between 500nm and 5000nm; and the top portion 244T of the DLC layer 244 includes a grain size ranging between 5nm and 500nm. In some embodiments, the thickness of the DLC layer 244 ranges between 1μm and 20μm, and the top surface of the DLC layer 244 has a surface roughness of less than 0.5μm. Roughness is defined as the maximum height difference of the top surface of the DLC layer. In some embodiments, the DLC layer 244 includes a graded structure in which the grain size gradually decreases from the bottom to the top. Therefore, the top surface of the DLC layer 244 is substantially formed to be flat.

[0057] The DLC layer 244 has a higher thermal conductivity. However, DLC is difficult to be planarized due to its large grain size and high hardness. In the disclosed DLC layer 244, the top portion 244T has a fine grain size, reduced roughness and improved planarity.

[0058] The process conditions for forming the disclosed DLC layer are controlled to form DLC with different grain sizes having reduced surface roughness. The process conditions are described below according to some embodiments. In some embodiments, the DLC layer is formed by a suitable method, such as chemical vapor deposition (CVD), such as plasma CVD, other suitable methods or combinations thereof. The CVD process is implemented with a precursor including a carbon-containing chemical, such as a benzene (C6H6) nitrogen mixture. During the deposition (e.g., CVD) process, the bottom portion is deposited at a first pressure (processing chamber pressure) P1 for a first duration, and the top portion is deposited at a second pressure P2 for a second duration. P2 is greater than P1. In some embodiments, P1 is less than 5 Torr and the second pressure P2 is greater than 5 Torr. In some embodiments, the first pressure P1 ranges between 1 mTorr and 5 Torr, and the second pressure P2 ranges between 5 Torr and 50 Torr. In some embodiments, depositing the bottom portion of the DLC layer includes depositing the bottom portion of the DLC layer at a first deposition temperature T1; and depositing the top portion of the DLC layer includes depositing the top portion of the DLC layer at a second deposition temperature T2 less than T1. In some embodiments, the first deposition temperature T1 ranges between 400° C. and 1200° C. The second deposition temperature T2 is between 100° C. and 1200° C. In some embodiments, depositing each of the bottom portion and the top portion of the DLC layer includes performing a CVD process with a radio frequency (RF) power between 50 W and 50 kW.

[0059] For the hierarchical structure of DLC layer 244, the process conditions are controlled to continuously change from the range of those parameters (such as pressure and temperature) associated with the bottom portion to the range of parameters associated with the top portion. Some parameters (such as RF power) can be kept constant during the deposition process of the entire process of forming DLC ​​layer 244.

[0060] refer to Fig.11 and Fig.13 At operation 356, the method 350 performs a chemical mechanical polishing (CMP) process to further planarize the top surface of the DLC layer 244. Since the roughness of the top surface of the DLC layer 244 is significantly reduced in the present disclosure, CMP can easily and effectively further planarize the top surface while improving the smoothness of the top surface of the DLC layer 244.

[0061] refer to Fig.11 and Fig.14 At operation 358, method 350 bonds carrier substrate 242 to IC structure 100 in a front-to-front bonding mode such that DLC layer 244 is bonded to bonding layer 232 of integrated circuit structure 100, thereby forming a bonded IC structure 250. Due to the reduction in surface roughness, bonding strength and bonding quality are improved.

[0062] After bonding, the method 350 thins the first substrate 102 from the back side at operation 360. At operation 362, a backside interconnect structure is formed on the back side of the IC structure 250. The method 350 may include other manufacturing operations before, during, or after the operations described above.

[0063] Other embodiments of IC structures having the disclosed DLC layers are provided herein. Fig.15 A cross-sectional view of an IC structure (workpiece) 500 having a CFET device is shown in accordance with some embodiments. Fig.16 is a flow chart of a method 400 constructed according to some embodiments. Figure 17-Figure 26 A cross-sectional view of an IC structure 500 at various stages of fabrication and processed by method 400 is shown in accordance with some embodiments. IC structure 500 and method 400 are described together below. IC structure 500 is different from IC structure 250. Specifically, DLC layer 530 is embedded in the CFET device and serves as a bonding layer, heat sink layer, and additional gate isolation layer.

[0064] refer to Fig.16 and Fig.17 , prepare a bottom device structure 510. At operation 402, a first stack 514 of a first semiconductor layer of a first semiconductor material and a second semiconductor layer of a second semiconductor material is formed over a first substrate 512, such that the first semiconductor layer and the second semiconductor layer are alternately stacked. The first semiconductor material and the second semiconductor material have different compositions. For example, the first semiconductor material is silicon germanium and the second semiconductor material is silicon. The second semiconductor layer is ultimately used as a channel and is appropriately doped, for example, doped with a P-type dopant (e.g., boron) according to some embodiments.

[0065] At operation 404, a first DLC layer 516 is formed on the first stack 514. The DLC layer 516 is similar to the DLC layer 244, and the formation of the DLC layer 516 is similar to the formation of the DLC layer 244, such as Fig.12 and Fig.13As shown. For example, the DLC layer 516 includes a bottom portion and a top portion having different grain sizes. The top portion of the DLC layer 516 has a fine grain size, while the bottom portion of the DLC layer has a large grain size that is larger than the fine grain size. In the disclosed embodiment, the bottom portion of the DLC layer 516 includes a grain size greater than 500nm; and the top portion of the DLC layer 516 includes a grain size less than 500nm. In a further implementation of the embodiment, the bottom portion of the DLC layer 516 includes a grain size ranging between 500nm and 5000nm; and the top portion of the DLC layer 516 includes a grain size ranging between 5nm and 500nm. In some embodiments, the thickness of the DLC layer 516 ranges between 1μm and 10μm, and the top surface of the DLC layer has a surface roughness of less than 0.5μm. In some embodiments, the DLC layer 516 includes a graded structure in which the grain size decreases from the bottom portion to the top portion. Therefore, the top surface of the DLC layer 516 is substantially formed to be flat. The formation of DLC layer 516 includes deposition with varying conditions as described for DLC layer 244. A CMP process is applied to DLC layer 516 to further planarize the top surface.

[0066] refer to Fig.16 and Fig.18 , preparing a top device structure 520. At operation 406, a second stack 524 of a third semiconductor layer of a third semiconductor material and a fourth semiconductor layer of a fourth semiconductor material is formed on a second substrate 522, so that the third and fourth semiconductor layers are alternately stacked. The third and fourth semiconductor materials are different in composition. For example, the third semiconductor material is silicon germanium, and the fourth semiconductor material is silicon. Specifically, the third and fourth semiconductor materials in the second stack 524 can be different from the first and second semiconductor materials in the first stack 514. The fourth semiconductor layer is ultimately used as a channel and is appropriately doped, for example, doped with an N-type dopant (e.g., phosphorus) according to some embodiments.

[0067] At operation 408, a second DLC layer 526 is formed on the second stack 524. The DLC layer 526 is similar to the DLC layer 516, and the formation of the DLC layer 526 is similar to the formation of the DLC layer 516. Similar descriptions are not repeated.

[0068] refer to Fig.16 and Fig.19 At operation 410, the bottom device structure 510 and the top device structure 520 are bonded together by the first DLC layer 516 and the second DLC layer 526. The bonding strength is significantly enhanced due to the reduced surface roughness of the DLC layers 516 and 526. The first DLC layer 516 and the second DLC layer 526 together function as a bonding interface and heat dissipation, and are referred to as DLC layers 530.

[0069] refer to Fig.16 and Fig. 20 At operation 410 , the second substrate 522 is thinned such that the second stack 524 is exposed from the back side.

[0070] Thereafter, the method 400 proceeds to operation 300 to form a CFET device by a monolithic process. Operation 300 is similar to Figure 2A-2B 300 in the method, and includes a plurality of sub-operations, such as operations 302 to 332. Compared to the IC structure 100, the first stack 514, the second stack 524, and the DLC layer 530 are collectively used as the semiconductor stack 120 of the IC structure 100, such as Figure 4 The stack 120 shown. The DLC layer 530 acts as an intermediate layer 120c of the IC structure 100. However, the DLC layer 530 can be used as a gate isolation layer and remain in the final structure. In this case, operation 320 in method 300 is eliminated in the present method 400. Operation 302 includes patterning the semiconductor stack to form a fin active area. The various sub-operations in operation 300 are briefly described below. For simplicity, similar descriptions are not repeated.

[0071] refer to Fig.16 , Figure 2A and Fig.21 At operation 302, the semiconductor stack 120 is patterned to form a fin active region. At operation 304, a dummy gate structure 124 is formed on the semiconductor stack 120 by deposition and patterning. The patterning process may use a hard mask 532. The hard mask 532 may include more than one material, such as a silicon oxide film and a silicon nitride film. The dummy gate structure 124 includes a gate stack 126 and a gate spacer 220 disposed on the sidewall of the gate stack 126. At operation 306, the S / D region of the semiconductor stack 120 is recessed by etching to form an S / D trench. At operation 308, internal spacers 112, 212 are formed.

[0072] refer to Fig.16 , Figure 2A and Fig. 22 At operation 310, a first (bottom) S / D feature 110 is formed by epitaxial growth.

[0073] refer to Fig.16 , Figure 2A and Fig.23 At operation 312 , S / D isolation layers 114 , 116 are formed on the bottom S / D feature 110 .

[0074] refer to Fig.16 , Figure 2A and Fig.24At operation 314, a second (top) S / D feature 210 is formed by epitaxial growth.

[0075] Still reference Fig.16 , Figure 2B and Fig.24 , at operation 316, ILD layers 130, 132 are formed. For example, the second S / D feature 210 is first recessed by selective etching; an etch stop layer 132 (e.g., silicon oxide) is deposited; a thick dielectric layer 130 such as a low-k dielectric material, silicon oxide, or a combination thereof is deposited on the etch stop layer 132; and a CMP process is applied to planarize the top surface. At operation 318, the dummy gate stack 126 is removed by etching, thereby producing a gate trench. At operation 322, the remaining first semiconductor layer is removed by etching through the gate trench to form a suspended channel 106, 206. Metal gates 108, 208 are further formed to wrap around the channel 106. Specifically, at operation 324, a gate dielectric layer (such as 108b / 108c, 208b / 208c) is formed. At operation 328, gate electrodes (e.g., 108a, 208a) are formed, which are respectively at Fig.24 , but for simplicity, Fig.26 At operation 332, a SAC 226 is formed on the gate electrode 208a.

[0076] refer to Fig.16 , Figure 2B and Fig.25 , S / D contacts 222, 224 are formed over the S / D components 110, 210. For example, the ILD layer 130 is patterned to form contact holes; a barrier layer 224 is deposited in the contact holes; a metal material 222 is deposited in the contact trenches; and a CMP process may be further applied to planarize the top surface. The method 400 may include block 414 to perform other manufacturing processes, such as forming an interconnect structure.

[0077] refer to Fig.26 , further illustrating the IC structure 500 thus formed. The IC structure 500 is similar to Figure 1 The IC structure 100 in FIG. 1 is shown in FIG. 1 . For the sake of brevity, similar descriptions are not repeated. However, the DLC layer 530 is embedded in the CFET device and serves as a gate isolation layer, a bonding interface, and a heat dissipation layer.

[0078] The present disclosure provides an IC structure having a VFET device and a DLC layer, and a manufacturing method according to various embodiments. The DLC layer serves as a bonding interface and a heat dissipation layer, and can be additionally used as a gate isolation layer. Specifically, the DLC layer includes a bottom portion and a top portion having different grain sizes. The top portion of the DLC layer has a fine grain size, while the bottom portion of the DLC layer has a large grain size that is larger than the fine grain size. The method of forming the DLC layer includes various parameters, such as pressure and temperature, to change the grain size. The disclosed DLC layer has a reduced surface roughness and an improved CMP process, which further enhances the performance and reliability of the IC structure, such as bonding strength.

[0079] In one example aspect, the present disclosure provides an integrated circuit (IC) structure. The IC structure includes: a circuit structure having a semiconductor device formed on a first substrate, an interconnect structure above the semiconductor device; and a heat dissipation structure formed on a second substrate. The second substrate is bonded to the circuit structure so that the heat dissipation structure is interposed between the first substrate and the second substrate. The heat dissipation structure includes a diamond-like carbon (DLC) layer. The DLC layer includes a bottom portion having a large grain size and a top portion having a fine DLC grain size.

[0080] In some embodiments, a bottom portion of the DLC layer comprises a grain size greater than 500 nm; and a top portion of the DLC layer comprises a grain size less than 500 nm.

[0081] In some embodiments, the thickness of the DLC layer ranges between 1 μm and 20 μm; and the top surface of the DLC layer has a surface roughness of less than 0.5 μm.

[0082] In some embodiments, the grain size of the DLC layer decreases from the second substrate toward the circuit structure.

[0083] In some embodiments, the DLC layer includes a top surface and a bottom surface on the second substrate, and the DLC layer includes a graded structure in which a grain size continuously increases from the top surface to the bottom surface of the DLC layer.

[0084] In some embodiments, the first substrate is a semiconductor substrate and the second substrate is a dielectric substrate.

[0085] In some embodiments, the dielectric substrate is one of a silicon nitride substrate, a silicon oxide substrate, and an aluminum oxide substrate.

[0086] In some embodiments, the semiconductor device includes a complementary field effect transistor (CFET) device.

[0087] In another example aspect, the present disclosure provides a method of manufacturing an integrated circuit (IC) structure. The method includes: forming a circuit structure having a semiconductor device formed on a first substrate and an interconnect structure above the semiconductor device; forming a heat dissipation structure on a second substrate; and bonding the second substrate to the circuit structure so that the heat dissipation structure is interposed between the first substrate and the second substrate. Forming the heat dissipation structure includes forming a diamond-like carbon (DLC) layer, the diamond-like carbon layer including a bottom portion of the DLC layer having a large DLC grain size and a top portion of the DLC layer having a fine grain size.

[0088] In some embodiments, forming a heat dissipation structure on the second substrate includes: depositing a bottom portion of the DLC layer includes depositing the bottom portion of the DLC layer at a first pressure P1; and depositing a top portion of the DLC layer includes depositing the top portion of the DLC layer at a second pressure P2 greater than P1.

[0089] In some embodiments, the first pressure P1 is less than 5 Torr, and the second pressure P2 is greater than 5 Torr.

[0090] In some embodiments, the first pressure P1 ranges between 1 mTorr and 5 Torr, and the second pressure P2 ranges between 5 Torr and 50 Torr.

[0091] In some embodiments, depositing the bottom portion of the DLC layer includes depositing the bottom portion of the first DLC layer at a first deposition temperature T1; and depositing the top portion of the DLC layer includes depositing the top portion of the DLC layer at a second deposition temperature T2 less than T1.

[0092] In some embodiments, depositing the bottom portion of the DLC layer includes depositing the bottom portion of the DLC layer with a first radio frequency (RF) power ranging between 50W and 50kW; and depositing the top portion of the DLC layer includes depositing the top portion of the DLC layer with a second RF power ranging between 50W and 50kW.

[0093] In some embodiments, forming the heat dissipation structure on the second substrate includes depositing the DLC layer at a pressure that varies continuously from a first pressure to a second pressure greater than the first pressure.

[0094] In some embodiments, forming a circuit structure having a semiconductor device formed on a first substrate and an interconnect structure above the semiconductor device includes forming a complementary field effect transistor (CFET) on the first substrate; and bonding a second substrate to the circuit structure includes bonding a dielectric substrate to the circuit structure.

[0095] In some embodiments, a bottom portion of the DLC layer comprises a grain size greater than 500 nm; and a top portion of the DLC layer comprises a grain size less than 500 nm.

[0096] In another example aspect, the present disclosure provides a method for manufacturing an integrated circuit (IC) structure. The method includes: forming a first stack of a first semiconductor layer of a first semiconductor material and a second semiconductor layer of a second semiconductor material alternately stacked on a first substrate; forming a first diamond-like carbon (DLC) layer on the first stack; forming a second stack of a third semiconductor layer of a first semiconductor material and a fourth semiconductor layer of a second semiconductor material alternately stacked on a second substrate; forming a second DLC layer on the second stack; bonding the second substrate to the first substrate so that the first DLC layer and the second DLC layer are directly bonded together, wherein the first DLC layer has a first non-uniform structure and the second DLC layer has a second non-uniform structure; thinning the first substrate; and forming complementary field effect transistors (CFETs) in the first stack and the second stack.

[0097] In some embodiments, forming a first DLC layer on a first substrate includes: depositing a bottom portion of the first DLC layer with a first pressure P1 ; and depositing a top portion of the first DLC layer with a second pressure P2 greater than P1 .

[0098] In some embodiments, the first pressure P1 ranges between 1 mTorr and 5 Torr, and the second pressure P2 ranges between 5 Torr and 50 Torr.

[0099] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. An integrated circuit structure, comprising: A circuit structure having a semiconductor device formed on a first substrate and an interconnect structure above the semiconductor device; as well as A heat dissipation structure is formed on the second substrate, wherein The second substrate is bonded to the circuit structure so that the heat dissipation structure is interposed between the first substrate and the second substrate, The heat dissipation structure includes a diamond-like carbon layer, and The diamond-like carbon layer includes a bottom portion having a large grain size and a top portion having a fine grain size.

2. The integrated circuit structure according to claim 1, wherein The bottom portion of the diamond-like carbon layer comprises a grain size greater than 500 nm; and The top portion of the diamond-like carbon layer includes a grain size less than 500 nm.

3. The integrated circuit structure according to claim 1, wherein The thickness of the diamond-like carbon layer ranges between 1 μm and 20 μm; and The top surface of the diamond-like carbon layer has a surface roughness less than 0.5 μm.

4. The integrated circuit structure according to claim 1, wherein: A grain size of the diamond-like carbon layer decreases from the second substrate toward the circuit structure.

5. The integrated circuit structure of claim 4, wherein The diamond-like carbon layer includes a top surface and a bottom surface on the second substrate, and The diamond-like carbon layer includes a hierarchical structure in which a grain size continuously increases from a top surface to a bottom surface of the diamond-like carbon layer.

6. A method of manufacturing an integrated circuit structure, comprising: forming a circuit structure having a semiconductor device formed on a first substrate and an interconnect structure above the semiconductor device; forming a heat dissipation structure on the second substrate; as well as The second substrate is bonded to the circuit structure so that the heat dissipation structure is interposed between the first substrate and the second substrate, wherein forming the heat dissipation structure includes forming a diamond-like carbon layer, the diamond-like carbon layer including a bottom portion of the diamond-like carbon layer having a large grain size and a top portion of the diamond-like carbon layer having a fine grain size.

7. The method according to claim 6, wherein: Forming a heat dissipation structure on the second substrate includes: Depositing the bottom portion of the diamond-like carbon layer includes depositing the bottom portion of the diamond-like carbon layer at a first pressure P1; and Depositing the top portion of the diamond-like carbon layer includes depositing the top portion of the diamond-like carbon layer at a second pressure P2 greater than P1.

8. The method according to claim 6, wherein forming the circuit structure having a semiconductor device formed on a first substrate and an interconnect structure over the semiconductor device includes forming a complementary field effect transistor on the first substrate; and Bonding the second substrate to the circuit structure includes bonding a dielectric substrate to the circuit structure.

9. The method according to claim 6, wherein The bottom portion of the diamond-like carbon layer comprises a grain size greater than 500 nm; and The top portion of the diamond-like carbon layer includes a grain size less than 500 nm.

10. A method of manufacturing an integrated circuit structure, comprising: forming a first stack of first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternately stacked on a first substrate; forming a first diamond-like carbon layer on the first stack; forming a second stack of third semiconductor layers of the first semiconductor material and fourth semiconductor layers of the second semiconductor material alternately stacked on a second substrate; forming a second diamond-like carbon layer on the second stack; bonding the second substrate to the first substrate such that the first diamond-like carbon layer and the second diamond-like carbon layer are directly bonded together, wherein the first diamond-like carbon layer has a first non-uniform structure and the second diamond-like carbon layer has a second non-uniform structure; thinning the first substrate; and Complementary field effect transistors are formed in the first stack and the second stack.

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