Stacked field effect transistor devices and related fabrication methods

Abstract

Stacked field effect transistor (FET) devices and related fabrication methods are provided. The stacked FET device includes a lower FET having lower channel layers and a lower work function metal (WFM) layer between the lower channel layers. The stacked FET device includes an upper FET on top of a lower FET. The upper FET has upper channel layers and an upper WFM layer between the upper channel layers. Further, the stacked FET device includes an insulating capping layer on the upper WFM layer.

Description

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 597,122, filed on November 8, 2023, entitled “INTEGRATED CIRCUIT DEVICES INCLUDING SELF-ALIGNED GATE CUT AND METHODS OF FORMING THE SAME,” and U.S. Provisional Patent Application No. 63 / 548,052, filed on November 10, 2023, entitled “METHOD OF CO-INTEGRATION OF STACKED FIELD-EFFECT TRANSISTOR WITH SEPARATE GATE STRUCTURE AND STACKED FIELD-EFFECT TRANSISTOR WITH COMMON GATE STRUCTURE USING TRI-LAYER DUMMY GATE STRUCTURE,” and U.S. Patent Application No. 18 / 763,180, filed on July 3, 2024, the disclosure of each of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates generally to the field of semiconductor devices, and more particularly, to three-dimensional transistor structures. Background Art

[0003] The size of transistors in integrated circuit (IC) devices has continued to decrease to smaller logic elements. This has led to gate-all-around (GAA) structures such as multi-bridge channel field effect transistors (MBCFETs). TM ) and nanosheet FET (NSFET). In addition, as technology to increase transistor density has continued to develop, three-dimensional device structures such as stacked transistors are being considered.

[0004] A stacked transistor (or "transistor stack") may include a first transistor and a second transistor. The first transistor may be a transistor of a first type (e.g., an n-type metal oxide semiconductor (NMOS) transistor), and the second transistor may be a transistor of a second type (e.g., a p-type metal oxide semiconductor (PMOS) transistor). The first type of transistor and the second type of transistor may be complementary to each other and thus may be part of a complementary metal oxide semiconductor (CMOS) IC device. The first transistor and the second transistor may be stacked in any order (e.g., the first transistor on top of the second transistor, or the second transistor on top of the first transistor), thereby producing a stack including a top / upper transistor and a bottom / lower transistor. Summary of the invention

[0005] According to some embodiments herein, a stacked FET device may include a lower FET having a lower channel layer and a lower work function metal (WFM) layer between the lower channel layers. The stacked FET device may include an upper FET on top of the lower FET. The upper FET may have an upper channel layer and an upper WFM layer between the upper channel layers. In addition, the stacked FET device may include an insulating cap layer on the upper WFM layer.

[0006] According to some embodiments herein, a stacked FET device may include a lower FET having a lower channel layer and a lower gate material between the lower channel layers. The stacked FET device may include an upper FET on top of the lower FET. The upper FET may include an upper channel layer and an upper gate material between the upper channel layers. The stacked FET device may include an insulating capping layer in contact with the upper gate material. In addition, the stacked FET device may include a gate cutout adjacent to a side surface of the upper gate material.

[0007] According to some embodiments herein, a method of forming a stacked FET device may include forming a nanosheet stack and a dummy gate structure on the nanosheet stack. The nanosheet stack may include a lower channel layer and an upper channel layer on the lower channel layer. The dummy gate structure may include a semiconductor sacrificial layer. The method may include etching the semiconductor sacrificial layer to expose the sidewalls of the upper channel layer. The method may include forming a WFM on the exposed sidewalls of the upper channel layer and between the upper channel layers. The method may include forming an insulating cap layer on the WFM. In addition, the method may include forming a gate cutout adjacent to a side surface of the WFM. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a schematic block diagram of a transistor stack of a transistor device according to some embodiments herein.

[0009] Figure 1B is Figure 1A Schematic block diagram of a gate cut between two transistor stacks of a transistor device.

[0010] Figure 1C yes Figure 1A An example plan view of a transistor device.

[0011] Figure 1D yes Figure 1C An example cross-sectional view of a transistor device along line AA'.

[0012] Figure 1E yes Figure 1C An example cross-sectional view of a transistor device along line BB'.

[0013] Figure 1F and Figure 1G yes Figure 1C An example cross-sectional view of a transistor device along line CC'.

[0014] Figures 2A to 2Z It is shown that the formation Figure 1C to Figure 1F A cross-sectional view of the operation of the transistor device.

[0015] Figures 3A to 3AC is shown relative to Figures 2A to 2Z A cross-sectional view of the operation of the modified operation.

[0016] Figure 4 is with Figures 2A to 2Z and Figures 3A to 3AC The operations shown correspond to the flowchart. DETAILED DESCRIPTION

[0017] According to the embodiments herein, a transistor device including a self-aligned gate cut is provided. Each gate cut is formed after forming an insulating cap layer on an upper gate material (such as an upper work function metal (WFM)). The upper gate material and the insulating cap layer can help the gate cut to self-align, and the gate cut can be spaced apart from adjacent transistors. Because the gate cut is sufficiently spaced apart from adjacent transistors, even if the gate cut is misaligned, the risk of damaging the channel layer of the transistor when forming the gate cut can be reduced. In contrast, the misalignment of the gate cut in a conventional transistor device can damage adjacent transistors in the conventional transistor device. For example, a misaligned gate cut in a conventional transistor device can be so close to the transistor that its formation (e.g., an etching operation / process for forming the gate cut) damages the channel layer or other layers of the transistor.

[0018] In some embodiments herein, a transistor device may include a stacked transistor having a nanosheet. As the pitch of the gate and the pitch of the nanosheet continue to scale down, it may be difficult to implement a gate cut that is separated from an adjacent stacked transistor. As an example, the space (e.g., lateral distance) between the gate cut of the stacked transistor and the nanosheet may decrease as the pitch of the nanosheet is scaled down, thereby increasing the risk of damaging the nanosheet (e.g., recessing the nanosheet) during the formation of the gate cut. However, according to embodiments herein, self-alignment techniques may be implemented to form a gate cut with sufficient spacing from the stacked transistor to limit (e.g., prevent) damage to the nanosheet.

[0019] Example embodiments will be described in more detail with reference to the accompanying drawings.

[0020] Figure 1Ais a schematic block diagram of a transistor stack 101 of a transistor device 100 according to some embodiments herein. The transistor stack 101 includes a lower transistor Tb and an upper transistor Ta, the lower transistor Tb having a stack of a lower semiconductor channel layer (or, lower channel layer) 120b, and the upper transistor Ta having a stack of an upper semiconductor channel layer (or, upper channel layer) 120a. The upper semiconductor channel layer 120a and the lower semiconductor channel layer 120b may include, for example, silicon, and may not contain germanium or carbon. The lower transistor Tb is between the upper transistor Ta and the substrate 110 (e.g., a silicon substrate or other semiconductor substrate) in the vertical direction Z. In addition, in some embodiments, an isolation layer / region 130 (such as an intermediate dielectric isolation (MDI) layer / region) may be used as a spacer between the lower transistor Tb and the upper transistor Ta. Therefore, the isolation layer / region 130 may be referred to as a "spacer" herein.

[0021] The lower channel layer 120b of the lower transistor Tb is between a pair of lower source / drain (S / D) regions 140 electrically connected to the lower channel layer 120b in the first horizontal (i.e., lateral) direction X. The first horizontal direction X and the vertical direction Z may be perpendicular to each other, and the second horizontal (i.e., lateral) direction Y may be perpendicular to each of the first horizontal direction X and the vertical direction Z. Each lower channel layer 120b may be implemented by, for example, a nanosheet or a nanowire between the lower S / D regions 140. Similarly, the upper channel layer 120a of the upper transistor Ta may be between a pair of upper S / D regions 150 electrically connected to the upper channel layer 120a in the first horizontal direction X, and each upper channel layer 120a may be implemented by, for example, a nanosheet or a nanowire between the upper S / D regions 150.

[0022] In some embodiments, the upper S / D region 150 may include a semiconductor material different from the semiconductor material of the lower S / D region 140. As an example, the upper S / D region 150 may include silicon germanium and the lower S / D region 140 may include silicon carbide, or vice versa. In other embodiments, the upper S / D region 150 may include the same semiconductor material as the semiconductor material of the lower S / D region 140.

[0023] For the sake of simplicity, Figure 1A Only one transistor stack 101 is shown in FIG. 1 . However, according to some embodiments, the transistor device 100 may include two transistor stacks 101 , three transistor stacks 101 , four transistor stacks 101 , or more transistor stacks 101 .

[0024] Figure 1B is Figure 1ASchematic block diagram of a gate cut 160 between two transistor stacks 101a, 101b of a transistor device 100. The gate cut 160 is on a substrate 110 and is adjacent to each of the transistor stacks 101a, 101b. As used herein with respect to the gate cut 160 and the transistor stacks 101a, 101b on opposite sides of the gate cut 160, the term "adjacent" means that no other transistor stack 101 is between the gate cut 160 and the transistor stacks 101a, 101b. In addition, as used herein with respect to the sidewalls of the gate cut 160 and the side surface of the upper gate material (e.g., upper WFM) of one of the transistor stacks 101a, 101b, the term "adjacent" means that the sidewalls of the gate cut 160 are closer to the other of the transistor stacks 101a, 101b than to one of the transistor stacks 101a, 101b.

[0025] The transistor stack (or, first transistor stack) 101a is Figure 1A The transistor stack 101 is Figure 1B 101a to distinguish it from the transistor stack (or, the second transistor stack) 101b. Figure 1B As shown in , the first gate 170 is on the transistor stack 101a, and the second gate 170 is on the transistor stack 101b. The gate cutout 160 includes an insulating material (eg, silicon nitride) that electrically isolates the two gates 170 from each other. The gates 170 may each include one or more conductive materials (such as one or more WFMs).

[0026] Figure 1C is an exemplary plan view of the transistor device 100. Figure 1C As shown in , the transistor device 100 includes one or more gates 170 on the upper channel layer 120a of the upper transistor Ta and the lower channel layer 120b of the lower transistor Tb. Line A-A' extends along the channel width of the upper channel layer 120a of the upper transistor Ta in the first horizontal direction X. Line BB' extends along the channel width of the lower channel layer 120b of the lower transistor Tb in the first horizontal direction X. Line A-A' and line BB' are spaced apart from each other in the second horizontal direction Y. Line CC' passes through the gate 170 lengthwise (i.e., longitudinally) in the second horizontal direction Y.

[0027] For simplicity of illustration, Figure 1C Only one transistor stack 101 ( Figure 1A ), the transistor stack 101 includes an upper transistor Ta and a lower transistor Tb. However, in some embodiments, such as Figure 1F , Figure 1G , Figure 2Y , Figure 2Z , Figure 3AB and Figure 3AC As shown in FIG. 1 , line CC′ may extend to pass through both transistor stacks 101 a , 101 b .

[0028] Figure 1D The transistor device 100 is along Figure 1C Example cross-sectional view of line A-A'. Figure 1D As shown in FIG. 1 , the upper gate 170 a may be on the upper channel layer 120 a of the upper transistor Ta of the transistor stack 101 ( FIG. 1 ), and the lower gate 170 b may be on the lower transistor Tb of the transistor stack 101 ( Figure 1B ). The upper gate 170a is an upper conductive gate (e.g., an upper WFM layer) that may be between the upper channel layers 120a (in the vertical direction Z) and may be spaced apart from the upper S / D region 150 in the direction X by an insulating spacer 172. The insulating spacer 172 may be on the sidewall of the upper gate 170a and between the upper channel layers 120a in the vertical direction Z.

[0029] Likewise, the lower gate 170b is a lower conductive gate (e.g., a lower WFM layer) that may be between the lower channel layers 120b (in the vertical direction Z). The lower gate 170b may be spaced apart from the lower S / D region 140 in the direction X by an insulating spacer 172, which may be on the sidewalls of the lower gate 170b and between the lower channel layers 120b in the vertical direction Z. In some embodiments, the insulating spacer 172 may contact the lower S / D region 140, the upper S / D region 150, the sidewalls of the lower gate 170b, and the sidewalls of the upper gate 170a. The sidewalls of the lower channel layer 120b may contact the lower S / D region 140, and the sidewalls of the upper channel layer 120a may contact the upper S / D region 150.

[0030] The upper gate 170a and the lower gate 170b may each include a metal or a semiconductor material. As an example, the upper gate 170a and the lower gate 170b may each include different metals. In some embodiments, the metals may be different WFMs. For example, when the lower transistor Tb ( Figure 1A ) may be an NMOS transistor, the lower gate 170 b may include a lower WFM layer including aluminum, and when the upper transistor Ta ( Figure 1A ) may be a PMOS transistor, the upper gate 170a may include an upper WFM layer of titanium nitride. In addition, tungsten (or another metal) may be formed on the lower WFM layer and / or the upper WFM layer. Therefore, the lower gate 170b may include a lower WFM layer and tungsten (or another metal), and the upper gate 170a may include an upper WFM layer and tungsten (or another metal).

[0031] According to some embodiments, the insulating spacers 172 may include, for example, a nitride (eg, silicon nitride). Because the insulating spacers 172 may be located between nanosheets / nanowires within a transistor, the insulating spacers 172 may also be referred to herein as “inter-spacers”.

[0032] The upper transistor Ta and the lower transistor Tb may be different types of MOSFETs. Therefore, the transistor device 100 may be a stacked FET device. For example, the upper transistor Ta and the lower transistor Tb may be a PMOS transistor and an NMOS transistor, respectively, or vice versa. As an example, the PMOS transistor and the NMOS transistor may be provided by S / D regions including silicon germanium and silicon carbide, respectively. In some embodiments, the spacer 130 may separate the lower channel layer 120b of the lower transistor Tb from the upper channel layer 120a of the upper transistor Ta. The spacer 130 may include, for example, silicon boron carbon nitride (SiBCN).

[0033] For simplicity of illustration, Figure 1D The gate insulating layer is omitted in the figure in FIG. However, it will be understood that the gate insulating layer may extend between each channel layer 120 and the gate 170 . The gate insulating layer may wrap each channel layer 120 and may be thinner than the spacer 130 .

[0034] According to some embodiments, the first insulating layer 112 may be in a recess of the substrate 110. The second insulating layer 114 may also be in the recess and may extend above the substrate 110 to, for example, the height of the uppermost surface of the upper gate 170a. The third insulating layer 152 may be between the lower S / D region 140 and the upper S / D region 150 in the vertical direction Z. In addition, the third insulating layer 152 may be on the upper surface of each of the upper S / D regions 150. The fourth insulating layer 132 may be on the sidewalls of the upper gate 170a, the lower gate 170b, and the upper surface of the insulating layer 114, and the fifth insulating layer 134 may be between the upper gate 170a and the lower gate 170b. The sixth insulating layer 178 may be between the fourth insulating layer 132 and the third insulating layer 152, and between the fifth insulating layer 134 and the third insulating layer 152.

[0035] The fourth insulating layer 132 and the fifth insulating layer 134 may include the same insulating material (e.g., SiBCN) as the insulating material of the spacer 130, and such insulating material may be different from the insulating material of the first insulating layer 112 and different from the insulating materials of the second insulating layer 114 and the third insulating layer 152. For example, the fourth insulating layer 132, the fifth insulating layer 134 and the spacer 130 may each be part of the insulating structure / insulating layer (or, insulating material) 176 (i.e., the same insulating material). As an example, the vertical portion of the insulating material 176 may be provided by the fourth insulating layer 132, and the lateral portion of the insulating material 176 may be provided by the spacer 130 and the fifth insulating layer 134. Therefore, the spacer 130 may be referred to herein as the "lateral portion" of the insulating material 176, and the fourth insulating layer 132 may be referred to herein as the "vertical portion" (or "plural vertical portions") of the insulating material 176. In some embodiments, the first insulating layer 112 may include an insulating material different from the insulating material of the second insulating layer 114 and the third insulating layer 152. As an example, the first insulating layer 112 may include a nitride (eg, silicon nitride), and the second insulating layer 114 and the third insulating layer 152 may each include an oxide (eg, silicon oxide).

[0036] The transistor device 100 may include an insulating cover layer 180 on the upper gate 170a. For example, the insulating cover layer 180 may be on the upper surface of the upper gate 170a and / or on the side surface of the upper gate 170a. In some embodiments, the insulating cover layer 180 may be in contact with the upper surface of the upper gate 170a and / or in contact with the side surface of the upper gate 170a. The insulating cover layer 180 may be a relatively thin layer and may therefore be referred to herein as a "liner" layer. As an example, the insulating cover layer 180 may be thinner than the spacer 130 in the vertical direction Z.

[0037] Figure 1E The transistor device 100 is along Figure 1C Example cross-sectional view of line BB'. Figure 1E As shown in FIG. 1 , the insulating capping layer 180 may be on the upper surface of the upper gate 170 a (eg, in contact with the upper surface of the upper gate 170 a). The insulating capping layer 180 may include, for example, silicon nitride. In some embodiments, the insulating capping layer 180 may include a gate cutout ( Figure 1B ) of the insulating material (e.g., silicon nitride).

[0038] For simplicity of illustration, Figure 1E The insulating spacer 172 is omitted in the figure ( Figure 1D ). However, in some embodiments, Figure 1E In the cross-section shown in FIG. 1 , an insulating spacer 172 may exist between the lower S / D region 140 and the lower gate 170 b.

[0039] Figure 1F and Figure 1G The transistor device 100 is along Figure 1C Example cross-sectional view of line CC'. Figure 1F An example is shown in which the gate cut 160 is spaced apart from both the insulating capping layer 180 of the transistor stack 101a and the insulating capping layer 180 of the transistor stack 101b in the second horizontal direction Y. Therefore, the gate cut 160 is not misaligned with respect to the transistor stacks 101a, 101b.

[0040] In contrast, Figure 1G An example is shown in which the gate cut 160 is misaligned so that the gate cut 160 is closer to the transistor stack 101a than to the transistor stack 101b in the second horizontal direction Y. For example, the gate cut 160 may be misaligned so that the gate cut 160 contacts the insulating cover layer 180 of the transistor stack 101a. However, even when the gate cut 160 is misaligned relative to the transistor stacks 101a, 101b, the insulating cover layer 180 may space the gate cut 160 from the channel layer 120 of the transistor stacks 101a, 101b so that the misaligned gate cut 160 does not damage the transistor stacks 101a, 101b.

[0041] In some embodiments, the insulating capping layer 180 may be formed on the upper surface of the upper gate 170a of each of the transistor stacks 101a, 101b. 1 For example, Figure 1F and Figure 1G As shown in the cross-sectional view of FIG. 1 , the insulating cap layer 180 may contact the upper surface s of the upper gate 170a. 1 The entire width (in the second horizontal direction Y) of .

[0042] The gate cut 160 (eg, the sidewall of the gate cut 160 ) may be aligned with a side surface s of an upper gate 170 a of the transistor stack 101 a (eg, the upper gate 170 a on the transistor stack 101 a ) in the second horizontal direction Y. 2 The lower gate 170 b of the transistor stack 101 a (eg, the lower gate 170 b on the transistor stack 101 a ) may be disposed in the second horizontal direction Y between the gate cutout 160 and the side surface s. 2 As an example, the lower gate 170b may be spaced apart from the sidewall of the gate cutout 160 and the side surface of the upper gate 170a. 2 In addition, the upper gate 170a (eg, the lower surface s of the upper gate 170a) 3 ) may be wider than the lower channel layer 120b vertically overlapping the upper gate 170a in the second horizontal direction Y. According to some embodiments, the lower surface s 3The gate electrode 170a may be on (eg, in contact with) the spacer 130 and the lower gate 170b.

[0043] Figure 1F and Figure 1G It is also shown that the spacer 130 may include an extension portion EP vertically overlapping the lower channel layer 120b and not vertically overlapping the upper channel layer 120a. The upper gate 170a and the insulating cap layer 180 may vertically overlap the extension portion EP. In some embodiments, the lower channel layer 120b (e.g., the lower nanosheet) may be wider than the upper channel layer 120a (e.g., the upper nanosheet) in the second horizontal direction Y. For example, the width of the lower channel layer 120b may be more than twice the width of the upper channel layer 120a. According to some embodiments, the spacer 130 may have the same width as the width of the lower channel layer 120b.

[0044] Figures 2A to 2Z It is shown that the formation Figure 1C to Figure 1F A cross-sectional view of the operation of the transistor device 100, and Figure 4 is with Figure 2Z The operations shown in the flowchart correspond to the following. Figure 2A , Figure 2D , Figure 2G , Figure 2J , Figure 2M , Figure 2P , Figure 2S and Figure 2V is with Figure 1C The cross-sectional view corresponding to the line AA'. Figure 2B , Figure 2E , Figure 2H , Figure 2K , Figure 2N , Figure 2Q , Figure 2T and Figure 2W is with Figure 1C The cross-sectional view corresponding to the line BB'. In addition, Figure 2C , Figure 2F , Fig.2I , Figure 2L , Fig.2O , Figure 2R , Figure 2U and Figure 2X to Figure 2Z is with Figure 1C The cross-sectional view corresponding to the line CC'.

[0045] like FIG. 2A to FIG. 2C and Figure 4As shown in , the operation of forming the transistor device 100 may include forming a stack of semiconductor channel layers 120 on a substrate 110 (block 410). In some embodiments, the channel layers 120 may be nanosheets, and thus the stack may be a nanosheet stack. The lower stack includes a lower channel layer 120b, and the upper stack includes an upper channel layer 120a. The lower stack is separated from the upper stack by a sacrificial isolation layer 262. In addition, sacrificial gate layers 270 may be stacked alternately with the channel layers 120 on the substrate 110. The sacrificial isolation layer 262 may be between an upper sacrificial gate layer in the sacrificial gate layers 270 and a lower sacrificial gate layer in the sacrificial gate layers 270.

[0046] The upper stack and the lower stack each form a transistor stack 101 ( Figure 1A ) portion. The lower channel layer 120b forms the lower transistor Tb ( Figure 1A ) portion, and the upper channel layer 120 a forms an upper transistor Ta ( Figure 1A ) part.

[0047] Although the plural term "stack" is used in some examples herein to easily distinguish the upper channel layer from the lower channel layer in the channel layer 120, because the upper channel layer 120a is stacked on top of the lower channel layer 120b, the singular term "stack" may also be used to describe the overall structure. Thus, the term "nanosheet stack" may refer to (i) a stack including both the upper channel layer 120a and the lower channel layer 120b, or (ii) a stack including only one of the upper channel layer 120a and only the lower channel layer 120b and stacked with another stack including only the upper channel layer 120a and only the lower channel layer 120b.

[0048] The channel layer 120 is a semiconductor layer including, for example, silicon (eg, polysilicon). In subsequent processes / operations, the upper gate 170a and the lower gate 170b ( Figure 1D ) to replace the sacrificial gate layer 270. In addition, in subsequent processes / operations, the spacer / MDI layer 130 ( Figure 1D ) replaces the sacrificial isolation layer 262. The sacrificial gate layer 270 may include, for example, silicon germanium. Therefore, the sacrificial gate layer 270 may have an etching selectivity relative to the channel layer 120. The sacrificial gate layer 270 may also have an etching selectivity relative to the sacrificial isolation layer 262. For example, the sacrificial isolation layer 262 and the sacrificial gate layer 270 may each include silicon germanium, but have different concentrations of germanium. As an example, the sacrificial isolation layer 262 may have a higher concentration of germanium (e.g., 55%) than the concentration of germanium of the sacrificial gate layer 270 (e.g., 25%).

[0049] In some embodiments, a seventh insulating layer 214 may be formed on the sidewalls of the alternately stacked channel layers 120 and sacrificial gate layers 270 and on the uppermost surface of the uppermost channel layer in the upper channel layer 120a. In addition, a first insulating layer 112 may be formed in a recess of the substrate 110, and a second insulating layer 114 may be formed in a recess on top of the first insulating layer 112. The second insulating layer 114 and the seventh insulating layer 214 may include the same insulating material (e.g., oxide), and in some embodiments may be a single continuous layer without an interface or separation between the second insulating layer 114 and the seventh insulating layer 214. The insulating material of the second insulating layer 114 and the seventh insulating layer 214 may be different from the insulating material of the first insulating layer 112, and the first insulating layer 112 may include, for example, a nitride (e.g., silicon nitride).

[0050] A dummy gate structure may be formed on the channel layer 120. The dummy gate structure may include a sacrificial layer 272, which will be used as an upper gate 170a, a lower gate 170b ( Figure 1F ) (e.g., a WFM layer). The sacrificial layer 272 may be on the top and sidewalls of the upper channel layer 120a and the lower channel layer 120b. The sacrificial layer 272 may include a semiconductor material and may be referred to herein as a "semiconductor sacrificial layer". The semiconductor material may include, for example, polysilicon and may have an etching selectivity relative to the channel layer 120, the sacrificial gate layer 270 and / or the sacrificial isolation layer 262.

[0051] According to some embodiments, seventh insulating layer 214 may be between sacrificial layer 272 and channel layer 120. For example, sacrificial layer 272 may contact seventh insulating layer 214.

[0052] like Figures 2D to 2F As shown in , the sacrificial layer 272 may be etched to form an opening in the sacrificial layer 272. For example, the sacrificial layer 272 may be etched to expose the sidewalls of the sacrificial layer 272 and a portion of the upper surface of the substrate 110. In some embodiments, the etching may be reactive-ion etching (RIE). As an example, an etching mask may be formed on the uppermost surface of the sacrificial layer 272 and patterned, and then the RIE may be performed while the etching mask is in place. In addition, the sacrificial isolation layer 262 may be removed by performing a selective etching that leaves the sacrificial gate layer 270 between the channel layers 120 ( FIG. 2A to FIG. 2C ).

[0053] An insulating layer / insulating material 176 including an MDI layer / spacer 130 and a vertical portion 132 may be formed after etching the sacrificial layer 272 and the sacrificial isolation layer 262. The spacer 130 may be formed in the openings formed by removing the sacrificial isolation layer 262. The vertical portion 132 may be in some of the openings etched in the sacrificial layer 272. In addition, the lower S / D region 140 and the upper S / D region 150 may be formed in other of the openings etched in the sacrificial layer 272. The third insulating layer 152, the sixth insulating layer 178 may also be formed in other of the openings, and the insulating spacer 172 may be formed on the sidewall of the sacrificial gate layer 270 through the other of the openings.

[0054] In some embodiments, the S / D regions 140, 150 may be formed by epitaxial growth. For example, the lower S / D region 140 may be epitaxially grown from the lower channel layer 120b, and the upper S / D region 150 may be epitaxially grown from the upper channel layer 120a. According to some embodiments, the channel layer 120 may include silicon, and the lower S / D region 140 and / or the upper S / D region 150 may include silicon, silicon carbide, or silicon germanium.

[0055] In some embodiments, a third insulating layer 152 may be formed between the lower S / D region 140 and the upper S / D region 150 and on the upper surface of each of the upper S / D regions 150 in the vertical direction Z. According to some embodiments, a planarization operation / process (e.g., chemical mechanical planarization (CMP)) may be performed after forming the fourth insulating layer 132 and the third insulating layer 152. In addition, the fourth insulating layer 132 and the fifth insulating layer 134 may include the same insulating material (e.g., SiBCN) as the insulating material of the spacer 130, and such insulating material may be different from the insulating material (e.g., oxide) of the third insulating layer 152 and the seventh insulating layer 214.

[0056] In some embodiments, insulating spacers 172 may be formed on the sidewalls of the sacrificial gate layer 270 and between the channel layers 120 in the vertical direction Z. For example, the sacrificial gate layer 270 may be etched to form openings in the sacrificial gate layer 270 between the channel layers 120. The sacrificial gate layer 270 may be exposed through the openings, and insulating spacers 172 may be formed in the openings. The insulating spacers 172 may include the same insulating material (e.g., silicon nitride) as the insulating material of the first insulating layer 112 and the sixth insulating layer 178, and the insulating material of the first insulating layer 112 and the sixth insulating layer 178 may be different from the insulating material of the third insulating layer 152, and different from the insulating material of the fourth insulating layer 132 and the fifth insulating layer 134.

[0057] like Figure 2G to Figure 2I and Figure 4As shown in , the sacrificial layer 272 may be etched (block 415) (e.g., the sacrificial layer 272 may be patterned / recessed) to form openings 276, 278 in the upper region of the sacrificial layer 272. The first opening 276 may remove the sacrificial layer 272 from between the sidewalls of the vertical portion 132, so that the sidewalls of the vertical portion 132 may be exposed. The second opening 278 may expose the upper surface of the extension portion EP of the spacer 130, wherein the extension portion does not vertically overlap with the upper channel layer 120a. The second opening 278 may also expose the sidewalls of the upper channel layer 120a. Each opening 276, 278 may also be referred to herein as a "recess" in the sacrificial layer 272. In some embodiments, because Figure 2H and Fig.2I The cross sections shown in intersect each other, so Figure 2H The first opening 276 shown in FIG. 1 may be connected to Fig.2I The second opening 278 shown in FIG. Fig.2I The second opening 278 shown in FIG. 2 is vertically stacked).

[0058] like Figure 2J to Figure 2L and Figure 4 As shown in FIG. 1 , the upper gate 170 a (ie, the upper gate material) may be formed in the first opening 276 ( Figure 2G and Figure 2H ) and the second opening 278 ( Fig.2I ) (block 420), and replaces the upper sacrificial gate layer in the sacrificial gate layer 270. In some embodiments, as Figure 2L As shown in , the upper gate 170a may include an upper WFM layer, which may be between the upper channel layers 120a, on the exposed sidewalls of the upper channel layers 120a, and on the extension portion EP of the spacer 130. The upper WFM layer may be formed by, for example, metal deposition in the openings 276, 278 followed by a metal CMP operation / process.

[0059] like Figure 2M to Figure 2O As shown in FIG. 1 , the upper portion of the upper gate 170 a may be recessed to form a third opening 282 . The third opening 282 may expose an upper sidewall of the vertical portion 132 and / or an upper sidewall of the sacrificial layer 272 .

[0060] like Figure 2P to Figure 2R and Figure 4 As shown in FIG. , the third opening 282 ( Figure 2M to Figure 2O ) in the third opening 282 (block 425). Thus, the insulating capping layer 180 may be on top of the upper gate 170a and between the upper sidewalls of the vertical portion 132 and / or the upper sidewalls of the sacrificial layer 272. The insulating capping layer 180 may be formed by, for example, depositing silicon nitride in the third opening 282 and then performing a CMP operation / process.

[0061] like Figure 2S to Figure 2UAs shown in FIG. , by removing the sacrificial layer 272 ( Figure 2R ), removing the remaining (eg, lower) portion of the seventh insulating layer 214 ( Figure 2Q ) and remove the lower sacrificial gate layer of the sacrificial gate layer 270 to form the fourth opening 284. As an example, the sacrificial layer 272 may be removed by a polysilicon removal operation / process, and the seventh insulating layer 214 may be removed by an oxide removal operation / process. In some embodiments, the seventh insulating layer 214 may be removed by an extra gate (EG) oxide removal operation / process. In addition, because the sacrificial gate layer 270 may have an etching selectivity relative to the lower channel layer 120b, the sacrificial gate layer 270 may be removed from between the lower channel layers 120b. Figure 2P As a result of removing the sacrificial layer 272 , the sacrificial gate layer 270 , and the seventh insulating layer 214 , the upper and lower surfaces of the lower channel layer 120 b and the lower sidewalls of the vertical portions 132 may be exposed.

[0062] like Figure 2V to Figure 2X and Figure 4 As shown in FIG. 4 , a lower gate 170 b (i.e., a lower gate material) may be formed in the fourth opening 284 (block 430). In some embodiments, the lower gate 170 b may include a lower WFM layer, which may be between the lower channel layers 120 b. The lower WFM layer may be formed by, for example, performing a metal deposition in the fourth opening 284 followed by a metal CMP operation / process. According to some embodiments, the lower gate 170 b may be formed on the sidewalls of the insulating cap layer 180 and on the side and lower surfaces of the upper gate 170 a.

[0063] According to some embodiments, the lower WFM layer of the lower gate 170b may include a first metal (eg, aluminum), and the upper WFM layer of the upper gate 170a may include a second metal different from the first metal (eg, titanium nitride). Figure 2V to Figure 2X Although omitted in the drawings, according to some embodiments, a gate insulating layer may be formed between each metal layer and the channel layer 120 .

[0064] like Figure 2Y As shown in Figures 2A to 2X The operation may set up multiple transistor stacks 101. For example, at this stage of the manufacturing process, the lower gate 170b may be shared by the first transistor stack 101a and the second transistor stack 101b. The gate cutout 160 ( Figure 1F ) to electrically isolate the lower gate 170b of the first transistor stack 101a from the lower gate 170b of the second transistor stack 101b. In some embodiments, the first transistor stack 101a and the second transistor stack 101b may each have a Figure 2XThus, each transistor stack 101a, 101b may have an insulating capping layer 180 on (eg, on an upper surface of) the upper gate 170a.

[0065] like Figure 2Z As shown in , a fifth opening 286 may be formed in the lower gate 170b between the first transistor stack 101a and the second transistor stack 101b in the second horizontal direction Y. The fifth opening 286 separates the lower gate 170b of the first transistor stack 101a from the lower gate 170b of the second transistor stack 101b. According to some embodiments, the upper surface of the second insulating layer 114 may be exposed through the fifth opening 286.

[0066] Refer again Figure 1F and Figure 4 , can be found at the fifth opening 286 ( Figure 2Z ) in the fifth opening 286 (block 435). For example, the gate cutout 160 may be formed by forming an insulating material (e.g., silicon nitride) in the fifth opening 286. Thus, the gate cutout 160 may separate and electrically isolate the lower gate 170b of the first transistor stack 101a from the lower gate 170b of the second transistor stack 101b. When the fifth opening 286 is not misaligned, the gate cutout 160 may be set after forming the gate cutout 160. Figure 1F On the other hand, when the fifth opening 286 is not aligned, the gate cutout 160 may be formed after the fifth opening 286 is aligned. Figure 1G The structure shown in .

[0067] Because the transistor stack may have an upper gate 170a in contact with a lower gate 170b, Figure 1F and Figure 1G The structure shown in FIG. 1 may be referred to herein as a "common gate" (rather than a separate gate) structure. Figures 2A to 2Z The operations shown in may be referred to herein as forming a Figure 1F and Figure 1G The operation of the "common gate" structure is shown in FIG.

[0068] Figures 3A to 3AC is shown relative to Figures 2A to 2Z A cross-sectional view of the operation of the modified operation. Figures 3A to 3AC The operation can be used to form a gate electrode 170a ( Figure 3AB ) does not contact the lower gate 170b ( Figure 3AB ) of a transistor stack 101 having a separate gate structure.

[0069] like FIG. 3A to FIG. 3C and Figure 4As shown in , the operation may include forming a stack of semiconductor channel layers 120 on a substrate 110 (block 410). A multi-layer dummy gate structure 374 may then be formed on the channel layer 120. The dummy gate structure 374 may include, for example, a lower sacrificial layer 272b, an upper sacrificial layer 272a, and an eighth insulating layer 338 between the upper sacrificial layer 272 and the lower sacrificial layer 272b in the vertical direction Z. Therefore, the dummy gate structure 374 may have three layers and may therefore be referred to herein as a "three-layer" dummy gate structure, in which the eighth insulating layer is a middle layer.

[0070] In some embodiments, the lower sacrificial layer 272b and the upper sacrificial layer 272a may include FIG. 2A to FIG. 2C The lower sacrificial layer 272b and the upper sacrificial layer 272a ( Figure 3AA ). As a result, the eighth insulating layer 338 may be between the upper surface of the lower gate 170b and the lower surface of the upper gate 170a. The eighth insulating layer 338 may include, for example, the same insulating material as the first insulating layer 112 and the sixth insulating layer 178 (e.g., silicon nitride). In addition, the eighth insulating layer 338 may be a centering (e.g., middle) layer of the multi-layer dummy gate structure 374 that helps when forming the upper gate 170a. As an example, when a recess is formed in the dummy gate structure 374 in which the upper gate 170a is subsequently formed, the eighth insulating layer 338 may be used as an etch stop layer. Although other layers of the dummy gate structure 374 may be removed after the recess is formed, at least a portion of the eighth insulating layer 338 may be retained. Therefore, the transistor device 100 may include the eighth insulating layer 338 between the lower gate 170b and the upper gate 170a in the vertical direction Z.

[0071] like Figures 3D to 3F As shown in , the spacer 130 may be formed adjacent to the eighth insulating layer 338. For example, the sidewalls of the spacer 130 may overlap with the sidewalls of the eighth insulating layer 338 in the second horizontal direction Y. Figures 2D to 2F The described process / operation is used to form the spacer 130 .

[0072] like FIG. 3G to FIG. 3I As shown in , a sixth opening 376 may be formed. Figure 4 As shown in FIG. 4 , the upper sacrificial layer 272a may be etched (e.g., patterned / recessed) (block 415) to form a sixth opening 376. In some embodiments, the sixth opening 376 may expose a portion of the upper surface of the eighth insulating layer 338 that may serve as an etch stop layer when etching the upper sacrificial layer 272a. Therefore, when forming the sixth opening 376, the lower sacrificial layer 272b may not be etched.

[0073] like Figure 3J to Figure 3L and Figure 4 As shown in FIG. , the sixth opening 376 ( FIG. 3G to FIG. 3I ) to form an upper gate 170a (block 420). Figure 2J to Figure 2L As described, the upper gate 170a may include an upper WFM layer. In addition, the upper gate 170a may vertically overlap a portion of the eighth insulating layer 338. For example, a lower surface of the upper gate 170a may contact an upper surface of the eighth insulating layer 338.

[0074] like Figure 3M As shown in FIG. 1 , the seventh opening 378 may be formed by removing the remaining portion of the upper sacrificial layer 272a after forming the upper gate 170a. For example, the upper sacrificial layer 272a may be removed by a polysilicon removal operation / process. The seventh opening 378 may expose the upper surface of the upper gate 170a. 1 and side surface s 2 The seventh opening 378 may also expose a portion of the upper surface of the eighth insulating layer 338. In addition, the lower surface s of the upper gate 170a 3 The first portion of the spacer 130 may be in contact with the upper surface of the spacer 130, and the lower surface s 3 The second portion of the eighth insulating layer 338 may make contact with a portion of the upper surface of the eighth insulating layer 338 that is not exposed by the seventh opening 378 .

[0075] like Figure 3N to Figure 3P and Figure 4 As shown in FIG. 1 , the upper surface s of the upper gate 170 a may be 1 ( Figure 3M ) and side surface s 2 ( Figure 3M ) is formed on the insulating capping layer 180 (block 425). As an example, the insulating capping layer 180 may be formed from the upper surface s of the upper gate 170a. 1 Continuously extending to the side surface s of the upper gate 170a 2 In some embodiments, the insulating capping layer 180 may be formed from the upper surface of the upper gate 170a. 1 The insulating cover layer 180 may continuously extend to the upper surface of the eighth insulating layer 338. Therefore, the insulating cover layer 180 may be in contact with the eighth insulating layer 338.

[0076] According to some embodiments, the exposed upper surface s 1 , exposed side surface s 2 An insulating material (eg, silicon nitride) is conformally deposited on the exposed portion of the upper surface of the eighth insulating layer 338 to form an insulating capping layer 180. The insulating capping layer 180 has a side surface s 2The portion above may be referred to herein as a “sidewall insulating layer.” Furthermore, the insulating capping layer 180 and the eighth insulating layer 338 may include the same insulating material (eg, silicon nitride), and thus there may be no visible / discernible boundary between the insulating capping layer 180 and the eighth insulating layer 338 .

[0077] like Figure 3Q As shown in , the upper portion of the insulating cover layer 180 may be removed. As an example, the insulating cover layer 180 may be recessed to expose the upper surface s of the upper gate 170a. 1 In addition, the horizontal portion of the insulating cover layer 180 on the eighth insulating layer 338 may be thinned or removed. However, the vertical portion of the insulating cover layer 180 may remain on the side surface s of the upper gate 170a. 2 On, and may contact the eighth insulating layer 338.

[0078] like Figure 3R As shown in FIG. 1 , a portion of the eighth insulating layer 338 that does not vertically overlap the upper gate 170 a and does not contact the vertical portion of the insulating cover layer 180 may be recessed. For example, the exposed portion of the eighth insulating layer 338 may be removed. The remaining portion of the eighth insulating layer 338 may have an upper surface including a lower surface s that is aligned with the upper gate 170 a. 3 A first portion in contact with the vertical portion of the insulating cover layer 180 and a second portion in contact with a lower surface of the vertical portion of the insulating cover layer 180 .

[0079] like Figure 3S to Figure 3U As shown in FIG. , the lower sacrificial layer 272 b ( Figure 3R ), thereby forming an eighth opening 382. As an example, the lower sacrificial layer 272b may be removed by a polysilicon removal operation / process. The eighth opening 382 may expose the sidewalls of the seventh insulating layer 214, the sidewalls of the vertical portion 132, and the lower surface of the eighth insulating layer 338.

[0080] like Figure 3V to Figure 3X As shown in , the sacrificial gate layer 270 may be removed by, for example, selectively etching the sacrificial gate layer 270 relative to the lower channel layer 120 b. Figure 3U ). The seventh insulating layer 214 may also be removed by, for example, an additional gate (EG) oxide removal operation / process. As a result of removing the sacrificial gate layer 270 and the seventh insulating layer 214, a ninth opening 384 may be formed between and beside the lower channel layer 120b.

[0081] like Figure 3Y to Figure 3AA and Figure 4 As shown in the ninth opening 384 ( Figure 3V to Figure 3X ) to form a lower gate 170b (block 430). Figure 2V to Figure 2X As described, the lower gate 170b may include a lower WFM layer.

[0082] Figure 3AA The insulating cap layer 180 shown in FIG. 1 separates (eg, electrically isolates) the upper gate 170a from the lower gate 170b, thereby providing a separate gate structure. Figures 2A to 2Z The operation shown in FIG. 1 sets a common gate structure. According to a further embodiment, the lower sacrificial layer 272b ( Figure 3R ) and then through the side surface s of the upper gate 170a 2 ( Figure 3R ) remove the insulating cover layer 180 to set up a common gate structure.

[0083] like Figure 3AB and Figure 3AC As shown in Figures 3A to 3AA The operation may form a plurality of transistor stacks 101. For example, Figure 3AB and Figure 3AC A first transistor stack 101 a and a second transistor stack 101 b spaced apart from each other in a second horizontal direction Y are shown.

[0084] Reference Figure 3AB and 3AC as well as Figure 4 A gate cutout 160 may be formed in the lower gate 170b between the first transistor stack 101a and the second transistor stack 101b (block 435). As a result, the lower gate 170b may be separated into the lower gate 170b of the first transistor stack 101a and the lower gate 170b of the second transistor stack 101b.

[0085] Figure 3AB The gate cutout 160 is shown without misalignment. Figure 3AC A case where the gate cut 160 is misaligned is shown. When the gate cut 160 is misaligned, the gate cut 160 may contact a sidewall of the insulating capping layer 180 .

[0086] also, Figure 3AB and Figure 3AC In some embodiments, the insulating capping layer 180 may remain on the upper surface of the upper gate 170a. 1 ( Figure 3AA ). For example, you can omit Figure 3Q In other embodiments, the insulating cover layer 180 is recessed. Figure 3AB and Figure 3AC Unlike the illustration in FIG. 1 , the insulating cap layer 180 may not be on the upper surface of the upper gate 170a. 1 superior.

[0087] According to the embodiments herein, the transistor device 100 ( Figure 1A) can provide various advantages. These advantages include providing a method that can reduce the transistor stack 101 ( Figure 1A ) of the risk of damage to the self-aligned gate cutout 160 ( Figure 1F ), thereby helping to reduce the overall area of ​​the transistor device 100 including the transistor stack 101. For example, the gate cut 160 may use the upper gate 170a ( Figure 1F ) (eg, the upper WFM layer) is used for self-alignment so that the gate cut 160 is aligned with the lower channel layer 120 b ( Figure 1A ) have a sufficient spacing. The insulating cover layer 180 may be formed on the upper surface of the upper gate 170a. 1 ( Figure 1F ) and / or side surfaces 2 ( Figure 3R ), and even when the gate cut 160 is misaligned, the insulating capping layer 180 can help to laterally space the gate cut 160 from the channel layer 120 of the transistor stack 101. As an example, when the insulating capping layer 180 is disposed on the side surface s 2 When the insulating cap layer 180 is formed on the substrate, the thickness of the insulating cap layer 180 can control the spacing between the gate cut 160 and the channel layer 120 of the transistor stack 101 .

[0088] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the teachings of the present disclosure, and therefore the present disclosure should not be construed as being limited to the example embodiments set forth herein. On the contrary, these example embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present invention will be conveyed to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals always represent the same elements.

[0089] Example embodiments are described herein with reference to cross-sectional illustrations that are schematic diagrams of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations resulting, for example, from manufacturing techniques and / or tolerances, are to be expected. Thus, the embodiments herein should not be construed as limited to the specific shapes shown herein but may include deviations in shapes resulting, for example, from manufacturing.

[0090] It should also be noted that in some optional embodiments, the function / action pointed out in the flow chart frame here may not occur in the order pointed out in the flow chart. For example, depending on the function / action involved, the two frames shown continuously may actually be performed substantially simultaneously, or the frame may sometimes be performed in reverse order. In addition, the function of a given frame of a flow chart and / or block diagram may be divided into a plurality of frames, and / or the function of two or more frames in a flow chart and / or block diagram may be integrated at least in part. Finally, without departing from the scope of the present invention, other frames may be added / inserted between the frames shown, and / or frame / operation may be omitted.

[0091] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0092] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the disclosure. As used herein, the singular forms "a", "one", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that the terms "include" and / or "comprise" when used in this specification indicate the presence of stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0093] It will be understood that when an element is referred to as being "coupled to," "connected to," or "responsive to," or "on" another element, the element may be directly coupled to, directly connected to, or directly responsive to, or directly on, the other element, or there may be intermediate elements. In contrast, when an element is referred to as being "directly coupled to," "directly connected to," or "directly responsive to," or "directly on," another element, there are no intermediate elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, the symbol " / " (e.g., when used in the term "source / drain") will be understood to be equivalent to the term "and / or."

[0094] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present embodiment, the first element may be referred to as the second element.

[0095] For ease of explanation, spatially relative terms such as "under", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figure. It will be understood that the spatially relative terms are intended to include different orientations of the device in use or in operation in addition to the orientation depicted in the figure. For example, when the device in the figure is turned over, the element described as "under" or "below" other elements or features will subsequently be oriented as "above" the other elements or features. Therefore, the term "under" may include both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0096] Many different embodiments have been disclosed herein in conjunction with the above description and accompanying drawings. It will be understood that literally describing and illustrating every combination and subcombination of these embodiments would be overly repetitive and obscure. Therefore, this specification including the accompanying drawings should be construed as constituting a complete written description of all combinations and subcombinations of the embodiments described herein, as well as the manner and process of making and using them, and should support claims to any such combination or subcombination.

[0097] The subject matter disclosed above is considered to be illustrative and not restrictive, and the appended claims are intended to cover all such modifications, improvements, and other embodiments that fall within the scope of the invention. Therefore, to the maximum extent allowed by law, the scope will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

1. A stacked field effect transistor device, comprising: A lower field effect transistor comprises a lower channel layer and a lower work function metal layer, wherein the lower work function metal layer is between the lower channel layers; an upper field effect transistor on top of the lower field effect transistor, the upper field effect transistor comprising an upper channel layer and an upper work function metal layer, the upper work function metal layer being between the upper channel layers; and An insulating cover layer is on the upper work function metal layer.

2. The stacked field effect transistor device according to claim 1, wherein: The insulating cover layer contacts the upper surface of the upper work function metal layer.

3. The stacked field effect transistor device according to claim 1, in, The lower work function metal layer is on a side surface of the upper work function metal layer, and The upper work function metal layer is wider than the lower channel layer.

4. The stacked field effect transistor device according to claim 1, wherein: The upper work function metal layer contacts the lower work function metal layer.

5. The stacked field effect transistor device according to claim 1, wherein: The insulating cover layer is on a side surface of the upper work function metal layer and separates the upper work function metal layer from the lower work function metal layer.

6. The stacked field effect transistor device of claim 1 , further comprising: An etch stop layer is on the lower surface of the upper work function metal layer.

7. The stacked field effect transistor device of claim 1 , further comprising: Isolation region, separating the lower channel layer from the upper channel layer, The lower surface of the upper work function metal layer contacts the upper surface of the isolation region.

8. The stacked field effect transistor device of claim 1 , further comprising: A gate cutout is adjacent to a side surface of the upper work function metal layer.

9. The stacked field effect transistor device according to claim 8, wherein: The gate cutout contacts the insulating capping layer.

10. The stacked field effect transistor device of claim 8, further comprising: A second lower field effect transistor comprises a second lower channel layer and a second lower work function metal layer, wherein the second lower work function metal layer is between the second lower channel layer; a second upper field effect transistor on top of the second lower field effect transistor, the second upper field effect transistor comprising a second upper channel layer and a second upper work function metal layer, the second upper work function metal layer being between the second upper channel layer; as well as a second insulating cover layer, on an upper surface of the second upper work function metal layer, The gate cutout is adjacent to a side surface of the second upper work function metal layer and is between the upper work function metal layer and the second upper work function metal layer.

11. A stacked field effect transistor device comprising: A lower field effect transistor comprises a lower channel layer and a lower gate material, wherein the lower gate material is between the lower channel layer; an upper field effect transistor on top of the lower field effect transistor, the upper field effect transistor comprising an upper channel layer and an upper gate material, the upper gate material being between the upper channel layers; an insulating cap layer in contact with the upper gate material; and A gate cutout is formed adjacent to a side surface of the upper gate material.

12. The stacked field effect transistor device of claim 11, wherein: The upper gate material includes an upper work function metal.

13. The stacked field effect transistor device of claim 12, wherein: The lower gate material includes a lower work function metal.

14. The stacked field effect transistor device of claim 13, wherein: The lower work function metal is in contact with the upper work function metal.

15. The stacked field effect transistor device of claim 13, wherein: The lower work function metal is separated from the upper work function metal by an insulating capping layer.

16. A method of forming a stacked field effect transistor device, the method comprising: forming a nanosheet stack and a dummy gate structure on the nanosheet stack, wherein the nanosheet stack includes a lower channel layer and an upper channel layer on the lower channel layer, and wherein the dummy gate structure includes a semiconductor sacrificial layer; etching the semiconductor sacrificial layer to expose the sidewalls of the upper channel layer; forming a work function metal on exposed sidewalls of the upper channel layer and between the upper channel layers; forming an insulating capping layer on the work function metal; and A gate cut is formed adjacent to a side surface of the work function metal.

17. The method according to claim 16, in, Work function metals are upper work function metals. The method further comprises forming a lower work function metal between the lower channel layers, and The step of forming a gate cutout includes forming a gate cutout in a lower work function metal.

18. The method according to claim 17, wherein: The lower work function metal is on a side surface of the upper work function metal.

19. The method according to claim 17, in, The semiconductor sacrificial layer is an upper semiconductor sacrificial layer, Before etching the semiconductor sacrificial layer, the dummy gate structure further includes a lower semiconductor sacrificial layer and an etching stop layer between the lower semiconductor sacrificial layer and the upper semiconductor sacrificial layer, and After replacing the upper semiconductor sacrificial layer with the upper work function metal and replacing the lower semiconductor sacrificial layer with the lower work function metal, the etching stop layer is between the upper work function metal and the lower work function metal.

20. The method according to claim 16, wherein: The steps of forming the insulating cover layer include: recessing the upper surface of the work function metal; and An insulating capping layer is formed on an upper surface of the recess of the work function metal.

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