Semiconductor Device and Preparation Method

Abstract

The present application relates to the field of semiconductor technology, and provides a semiconductor device and a preparation method, the preparation method comprising: providing a substrate, forming a buried oxide layer on one side of the substrate; performing ion implantation on the side of the buried oxide layer facing the substrate; forming an epitaxial layer and a hard mask layer on the side of the buried oxide layer away from the substrate; performing deep trench isolation etching on the hard mask layer and the epitaxial layer to form a deep trench; etching the deep trench to penetrate the buried oxide layer, and filling the deep trench with polysilicon; performing chemical mechanical polishing to the hard mask layer, and then removing the hard mask layer; and forming an active layer on the side of the epitaxial layer away from the buried oxide layer. By adopting the present application, it is beneficial to improve the ability of semiconductor devices to resist ionizing radiation and improve the reliability of semiconductor devices used in harsh environments.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the progress of space technology, there is an increasing demand for the integration of electronic systems. At the same time, devices are required to have radiation resistance. In the field of CMOS (Complementary Metal - Oxide - Semiconductor), SOI (Silicon - On - Insulator) devices have been widely studied due to their excellent radiation resistance. SOI BCD devices refer to semiconductor devices based on SOI that integrate Bipolar (Bipolar Transistor), CMOS, and DMOS (Diffused Metal - Oxide - Semiconductor) simultaneously, such as Smart Power IC (Smart Power Integrated Circuit). Existing SOI - based Smart Power ICs still have deficiencies in terms of TID (Total Ionizing Dose) protection ability, resulting in insufficient anti - ionizing radiation ability of SOI BCD devices and affecting the reliability of chips in harsh environments.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present invention, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] Aiming at the problems in the prior art, the purpose of this application is to provide a semiconductor device and a manufacturing method thereof, which can improve the anti - ionizing radiation ability of the semiconductor device and the reliability of the semiconductor device when used in harsh environments.

[0005] An embodiment of this application provides a manufacturing method of a semiconductor device. The semiconductor device is an SOI BCD device, and the method includes the following steps:

[0006] Provide a P - type substrate, and an buried oxide layer is provided on one side of the P - type substrate;

[0007] Perform N - type ion implantation on the side of the buried oxide layer facing the P - type substrate to form a lightly doped N - type region and a heavily doped N - type region located in the lightly doped N - type region;

[0008] An epitaxial layer and a hard mask layer are formed on a side of the buried oxide layer facing away from the P-type substrate;

[0009] Deep trench isolation etching is performed on the hard mask layer and the epitaxial layer to form deep trenches;

[0010] The deep trenches are etched until they penetrate the buried oxide layer, and polysilicon is filled in the deep trenches, and the deep trenches are opposite to the heavily doped N-type regions;

[0011] After chemical mechanical polishing to the hard mask layer, the hard mask layer is removed;

[0012] An active layer is formed on a side of the epitaxial layer facing away from the buried oxide layer;

[0013] An interlayer dielectric layer is formed on a side of the active layer facing away from the epitaxial layer;

[0014] A plurality of contact holes are formed in the interlayer dielectric layer, and some of the contact holes are opposite to the polysilicon filled in the deep trenches;

[0015] Conductive metal is filled in the contact holes, and the semiconductor device is configured to receive an external bias voltage and apply it to the heavily doped N-type region through the conductive metal and the polysilicon in the deep trenches.

[0016] In some embodiments, after deep trench isolation etching is performed on the hard mask layer and the epitaxial layer to form deep trenches, the following steps are further included:

[0017] Angled heavy ion implantation is performed on sidewalls of the deep trenches.

[0018] In some embodiments, after deep trench isolation etching is performed on the hard mask layer and the epitaxial layer to form deep trenches, the following steps are further included:

[0019] An isolation layer is formed on sidewalls of the deep trenches.

[0020] In some embodiments, forming an isolation layer on sidewalls of the deep trenches includes the following steps:

[0021] Tetraethyl orthosilicate is grown to form an isolation layer on a side of the hard mask layer facing away from the epitaxial layer and in the deep trenches.

[0022] In some embodiments, etching the deep trenches until they penetrate the buried oxide layer includes the following steps:

[0023] The deep trenches are etched using a full etch process to expand the cavity diameter of the deep trenches and make the deep trenches penetrate the buried oxide layer.

[0024] In some embodiments, filling polysilicon in the deep trenches includes: filling N-type polysilicon in the deep trenches.

[0025] In some embodiments, removing the hard mask layer includes removing the hard mask layer by dry etching or wet etching.

[0026] An embodiment of the present application further provides a semiconductor device obtained by using the preparation method of the semiconductor device. The semiconductor device is a SOI BCD device and includes:

[0027] A P-type substrate;

[0028] A buried oxide layer is provided on one side of the P-type substrate. A lightly doped N-type region and a heavily doped N-type region located in the lightly doped N-type region are formed on the side of the P-type substrate facing the buried oxide layer;

[0029] An epitaxial layer is formed on the side of the buried oxide layer facing away from the P-type substrate. A deep trench is formed in the epitaxial layer and the buried oxide layer, and polysilicon is filled in the deep trench. The deep trench is opposite to the heavily doped N-type region;

[0030] An active layer is formed on the side of the epitaxial layer facing away from the buried oxide layer;

[0031] An interlayer dielectric layer is formed on the side of the active layer facing away from the epitaxial layer;

[0032] A plurality of contact holes are formed in the interlayer dielectric layer, and some of the contact holes are opposite to the polysilicon filled in the deep trench;

[0033] Conductive metal is filled in the contact holes. The semiconductor device is configured to receive an external bias voltage and apply it to the heavily doped N-type region through the conductive metal and the polysilicon in the deep trench.

[0034] The semiconductor device and the preparation method provided by the present application have the following advantages:

[0035] Based on the deep trench isolation technology, the present application is further expanded to fabricate a polysilicon-filled deep trench isolation that penetrates the buried oxide layer in the SOI substrate. The charge accumulated in the buried oxide layer is led out of the substrate through the polysilicon part in the deep trench isolation, avoiding the retention of charge in the buried oxide layer, restoring the electric field balance of the buried oxide layer, preventing the ionization radiation from charging the buried oxide layer due to the Bragg effect and resulting in an accidental inversion layer, which is beneficial to improving the anti-ionization radiation ability of the semiconductor device, improving the reliability of the semiconductor device when used in a harsh environment, and beneficial to improving the comprehensive performance of space technology equipment. Description of the Drawings

[0036] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other accompanying drawings based on these drawings without creative efforts.

[0037] Figure 1 It is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application.

[0038] Figure 2 It is a schematic diagram of ion implantation performed below the buried oxide layer according to an embodiment of the present application.

[0039] Figure 3 It is a schematic diagram after forming a hard mask layer according to an embodiment of the present application.

[0040] Figure 4 It is a schematic diagram after coating a photoresist on the hard mask layer according to an embodiment of the present application.

[0041] Figure 5 It is a schematic diagram after lithography according to an embodiment of the present application.

[0042] Figure 6 It is a schematic diagram of thermally oxidizing to form a linear oxide layer according to an embodiment of the present application.

[0043] Figure 7 It is a schematic diagram after forming a deep trench according to an embodiment of the present application.

[0044] Figure 8 It is a schematic diagram after forming an isolation layer according to an embodiment of the present application.

[0045] Figure 9 It is a schematic diagram after making the deep trench penetrate the buried oxide layer according to an embodiment of the present application.

[0046] Figure 10 It is a schematic diagram after filling polysilicon according to an embodiment of the present application.

[0047] Figure 11 It is a schematic diagram after performing chemical mechanical polishing according to an embodiment of the present application.

[0048] Figure 12 It is a schematic diagram after forming an active layer according to an embodiment of the present application.

[0049] Figure 13 It is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present application. Detailed implementation manners

[0050] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their repetitive description will be omitted. The terms "or" or "or" in the specification may mean "and" or "or". Spatial relationship terms such as "on..." can be used herein to describe the relationship of one element or feature shown in the figure with other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the figure is flipped, an element or feature described as "on..." will be oriented "under..." other elements or features. Thus, the exemplary term "on..." can include both the upper and lower orientations. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptive terms used herein are accordingly interpreted.

[0051] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups thereof are not excluded from being present or added. At the same time, as used herein, the term "and / or" includes any and all combinations of the related listed items. Although terms such as "first" or "second" are used in this specification to denote certain features, they are only for representational purposes and do not limit the quantity and importance of the specific features.

[0052] Aiming at the problem of insufficient anti-ionizing radiation ability of SOI BCD devices in the prior art, the present application provides a method for manufacturing a semiconductor device and a semiconductor device obtained by using this manufacturing method, aiming to improve the anti-ionizing radiation ability of SOI BCD devices so that the semiconductor device can be used in ionizing radiation scenarios. The present application is applied to the manufacture of SOI BCD devices, integrating bipolar transistors (Bipolar), CMOS logic circuits and DMOS power devices on the same chip.

[0053] As Figure 1 shown, an embodiment of the present application provides a method for manufacturing a semiconductor device, including the following steps:

[0054] S100: Provide a substrate, and a buried oxide layer (Buried Oxide, BOX) is provided on one side of the substrate;

[0055] In this embodiment, the substrate is a P-type substrate;

[0056] The buried oxide layer is a silicon dioxide layer, i.e., an insulating layer. When obtaining a substrate, a substrate with a buried oxide layer already provided thereon is obtained. This application does not involve the formation process of the buried oxide layer. Above the buried oxide layer is a P-type single crystal silicon film layer (P-type silicon thin film), i.e., the lower half of the top silicon layer used to make the device.

[0057] S200: performing N-type ion implantation on a side of the buried oxide layer facing the substrate to form a lightly doped N-type region and a heavily doped N-type region located in the lightly doped N-type region;

[0058] Ion implantation is an important process for accurately controlling the distribution of impurities in semiconductor manufacturing. The purpose of step S200 is to form a specific type of doped region on the side of the buried oxide layer facing the substrate to improve the electrical performance of the device. In this embodiment, the N-type doped region formed by ion implantation on the side of the single crystal silicon substrate structure close to the buried oxide layer is a local doped region.

[0059] In this embodiment, step S200 includes: performing N-type doping ion implantation on a side of the buried oxide layer facing the substrate to form an N-type doping region; specifically, performing ion implantation below the buried oxide layer where a P-type active region (AA region) is to be formed; N-type doping is usually performed by implanting pentavalent impurity elements such as phosphorus (P) and arsenic (As), so that a large number of free electrons exist in the doping region as majority carriers; in the subsequent device manufacturing process, the P-type active region and the N-type doping region will form a specific PN junction structure, thereby realizing the electrical function of the device;

[0060] S300: forming an epitaxial layer and a hard mask layer on a side of the buried oxide layer away from the substrate;

[0061] The epitaxial layer is a layer of semiconductor material formed by epitaxial growth technology on the side of the buried oxide layer away from the substrate; in this embodiment, the epitaxial layer is a P-type epitaxial layer (P-EPI); the hard mask layer is a thin film with a certain hardness and chemical stability formed on the P-type epitaxial layer, and the main function of the hard mask layer is to protect the epitaxial layer in the subsequent etching process to ensure that the etching process can be accurately performed in the specified area;

[0062] S400: performing deep trench isolation etching on the hard mask layer and the epitaxial layer to form a deep trench;

[0063] In this embodiment, a DTI Etch (Deep Trench Isolation Etch) method is used to form a longitudinal deep trench in the hard mask layer and the epitaxial layer;

[0064] S500: etching the deep trench to penetrate the buried oxide layer, and filling the deep trench with polysilicon;

[0065] In this embodiment, filling the deep trench with polysilicon includes: filling the deep trench with N-type doped polysilicon (N-Poly); polysilicon is a semiconductor material with good conductivity and thermal stability, and is often used to fill deep trenches to achieve electrical connection and isolation;

[0066] S600: After chemical mechanical polishing to the hard mask layer, remove the hard mask layer;

[0067] Chemical Mechanical Polishing (CMP) is a process for flattening the surface of a semiconductor chip. Through chemical mechanical polishing, excess polysilicon on the surface of the chip can be removed to make the surface highly flat. In this embodiment, in step S600, the hard mask layer is removed by dry etching or wet etching. Dry etching uses plasma to chemically react with the hard mask layer material to remove it layer by layer. Wet etching uses chemical solution to chemically react with the hard mask layer material to dissolve and remove it. Dry etching or wet etching is selected according to the material and process requirements of the hard mask layer.

[0068] S700: forming an active layer on the side of the epitaxial layer away from the buried oxide layer; that is, completing the FEOL (Front End Of Line) manufacturing. The active layer is the key area for realizing electrical functions in semiconductor devices, which includes various active devices such as transistors and diodes. The process of forming the active layer usually includes multiple process steps such as photolithography, ion implantation, and diffusion;

[0069] S800: forming an interlayer dielectric layer on a side of the active layer away from the epitaxial layer; forming a plurality of contact holes in the interlayer dielectric layer, wherein some of the contact holes are opposite to the polysilicon filled in the deep trench;

[0070] S900: Filling a conductive metal in the contact hole, the semiconductor device being configured to receive an external bias voltage and applying the bias voltage to the heavily doped N-type region through the conductive metal and the polysilicon in the deep trench.

[0071] The SOI BCD device realizes the integration of BCD based on silicon-on-insulator materials. The SOI structure consists of a top silicon layer (Active Layer), a buried oxide layer (BOX), and a substrate silicon layer (Substrate). The buried oxide layer plays a role in electrical isolation, significantly reducing the parasitic capacitance between the devices on the top silicon and the substrate silicon. In the SOI BCD device, each structure is fabricated on the top silicon and its epitaxial layer, and the buried oxide layer is used for isolation, reducing the mutual interference between devices. When high-energy particles penetrate the buried oxide layer, charges will be deposited in the buried oxide layer due to the Bragg Peak effect, resulting in charge accumulation. Charge accumulation may cause distortion of the electric field in the buried oxide layer, and then form an unintended inversion layer on the surface of the top silicon (such as a P-type active region), damaging the function of the semiconductor device. The principle of generating the unintended inversion layer is as follows: Ionizing radiation will excite electron-hole pairs at a relatively deep position in the thick oxide layer. Since in the buried oxide layer of silicon dioxide, the electron mobility is about two orders of magnitude higher than that of holes - about 100 times, the electrons in the oxide layer will gradually escape, while the holes will not escape, resulting in the effect that the buried oxide layer is positively charged. Eventually, an unintended inversion layer, that is, a conductive channel, is generated on the side of the buried oxide layer in contact with the top silicon.

[0072] This application further expands based on the deep trench isolation technology. A polysilicon-filled deep trench isolation is fabricated through the buried oxide layer in the SOI substrate. The charge accumulated in the buried oxide layer is led out of the substrate through the polysilicon part in the deep trench isolation, avoiding the retention of charges in the buried oxide layer, restoring the balance of the electric field in the buried oxide layer, preventing the ionization radiation from charging the buried oxide layer due to the Bragg Peak effect and resulting in an unintended inversion layer, which is beneficial to improving the anti-ionization radiation ability of semiconductor devices, enhancing the reliability of semiconductor devices used in harsh environments, and improving the comprehensive performance of space technology equipment. Specifically, since the heavily doped N-type region under the buried oxide layer forms a conductive connection path with the outside through the polysilicon and the conductive metal in the contact hole, a negative bias voltage can be applied to the heavily doped N-type region under the buried oxide layer through this conductive path to offset the built-in electric field caused by the positively charged holes retained in the buried oxide layer, thereby preventing the formation of an unintended inversion layer between the buried oxide layer and the top silicon and improving the performance of semiconductor devices. This negative bias voltage can be applied to the semiconductor device through a separate external port.

[0073] In this embodiment, after step S400: forming a deep trench by etching the hard mask layer and the epitaxial layer for deep trench isolation, the following steps are further included:

[0074] Perform angled heavy ion implantation on the sidewalls of the deep trench. In this embodiment, the angled heavy ion implantation is P-type implantation.

[0075] In the sidewalls of the isolation deep trench, among the radiation-generated electron-hole pairs, the hole migration speed is slower and is easily trapped by the sidewalls of the deep trench, thereby accumulating positive charges in these regions. As the total ionizing dose increases, the amount of accumulated charge also increases. To solve this problem, the present application adopts the method of performing angled heavy ion implantation on the sidewalls of the deep trench to increase the difficulty of forming an inversion layer on the semiconductor side (the single-crystalline silicon side close to the device region) of the sidewalls of the deep trench. This is the key process for protecting the total ionizing dose of the isolation deep trench sidewalls, and heavy ion doping must be carried out. Angled heavy ion implantation is based on ordinary ion implantation and uses high-concentration ions, with the ion beam incident in a direction at a certain angle to the normal of the wafer surface. This implantation method is beneficial to improving the controllability of ion implantation. By precisely controlling the angle and dose of ion implantation, it is beneficial to improve the working performance of semiconductor devices.

[0076] In this embodiment, after the step S400: forming a deep trench by performing deep trench isolation etching on the hard mask layer and the epitaxial layer, the following steps are further included:

[0077] An isolation layer is formed on the sidewalls of the deep trench. In this embodiment, the isolation layer is a silicon dioxide isolation layer, which forms electrical isolation by filling the sidewalls of the deep trench to prevent leakage current between adjacent structures.

[0078] In this embodiment, forming an isolation layer on the sidewalls of the deep trench includes the following steps:

[0079] Tetraethyl orthosilicate (TEOS) is grown to form an isolation layer on the side of the hard mask layer facing away from the epitaxial layer and in the deep trench. Growing tetraethyl orthosilicate can be used as a silicon source for chemical vapor deposition (CVD). A silicon dioxide isolation layer is formed by using a chemical vapor deposition process.

[0080] In this embodiment, the step S500: etching the deep trench until it penetrates the buried oxide layer includes the following steps:

[0081] The deep trench is etched using a blanket etch process to expand the cavity diameter of the deep trench and make the deep trench penetrate the buried oxide layer. The blanket etch process is a maskless etch process, and the trench size is adjusted by isotropic etching (such as wet etching).

[0082] In this embodiment, after the step S700: forming an active layer on the side of the epitaxial layer facing away from the buried oxide layer, the following steps are further included:

[0083] An interlayer dielectric (ILD) layer is formed on the side of the active layer facing away from the epitaxial layer; the interlayer dielectric layer mainly serves to insulate and protect the active layer, preventing short circuits between different metal interconnect layers; the interlayer dielectric layer is usually made of insulating materials such as silicon dioxide or silicon nitride and is formed by methods such as chemical vapor deposition;

[0084] A plurality of contact holes (CT) are formed in the interlayer dielectric layer, and the positions of the contact holes correspond to the positions of the respective terminals in the active layer; the formation of the contact holes requires photolithography and etching processes to precisely define the positions and sizes of the contact holes in the interlayer dielectric layer;

[0085] A conductive metal, such as tungsten, is filled in the contact holes to lead out the respective terminals of the active layer.

[0086] The following combines Figures 2 - 10 Specifically introduce the implementation process of the preparation method of the semiconductor device in a specific example. It can be understood that the structures shown in the figures and the following descriptions are only examples and do not limit the protection scope of this application.

[0087] Figure 2 is a schematic diagram of ion implantation under the buried oxide layer in an embodiment of this application. As Figure 2 shown, corresponding to steps S100 and S200, a P-type substrate 100 is provided, and a buried oxide layer 200 is provided above the P-type substrate 100. The buried oxide layer 200 is generally formed by processes such as oxygen implantation isolation or bonding, and its thickness is determined according to the performance requirements of the device. Ion implantation is performed on the P-type substrate 100 under the buried oxide layer 200 where the P-type AA region is to be fabricated to form an N+ doped region and an N- doped region. By precisely controlling the position and type of ion implantation, precise regulation of device characteristics can be achieved. A P-type silicon film (P-Silicon Film) 300 is also provided above the buried oxide layer 200.

[0088] Figure 3 is a schematic diagram after forming a hard mask layer in an embodiment of this application. Figure 4 is a schematic diagram after coating a photoresist on the hard mask layer in an embodiment of this application. Figure 5 is a schematic diagram after lithography in an embodiment of this application. Figure 6 is a schematic diagram of thermally oxidizing to form a Liner OX to repair the dangling bonds in the sidewall exposed area after deep trench isolation etching with the hard mask layer as a masking layer in an embodiment of this application. Figure 7 is a schematic diagram after forming a deep trench in an embodiment of this application. As Figure 3As shown, corresponding to step S400, a P-type epitaxial layer (P-EPI, P-Epitaxy) 400 and a hard mask layer 500 are formed above the P-type silicon thin film 300. In step S400, deep trench isolation etching is performed on the hard mask layer 500 and the epitaxial layer 400, and the deep trench is formed through two-step etching. As Figure 4 shown, the first step of etching includes: First, a photoresist 1001 is coated on the top of the hard mask layer, the photoresist 1001 is irradiated, and then the hard mask layer 500 is etched to form a trench in the hard mask layer 500, that is, to form a structure as Figure 5 shown, and the pattern of the mask plate is transferred to the hard mask layer 500. As Figure 6 shown, the second step of etching includes: Using the hard mask layer 500 with the existing deep trench planar pattern as a shielding layer, deep trench isolation etching is performed, which is the main process step. The deep trench formed by two-step etching can better realize the electrical function of the deep trench in the semiconductor device. The first etching can focus on controlling the initial shape of the hard mask, and the second etching focuses on expanding the cavity diameter, sidewall angle, and subsequent operation of penetrating to the buried oxide layer 200. Further, as Figure 6 shown, a Liner OX (linear oxide layer) is formed by thermal oxidation on the sidewalls of the deep trench to repair the dangling bonds in the exposed areas of the sidewalls of the epitaxial layer 400 and the P-type silicon thin film 300.

[0089] As Figure 7 shown, after a longitudinal deep trench 600 is formed in the hard mask layer 500, the epitaxial layer 400, and the P-type silicon thin film 300 by using the deep trench isolation etching method, angled heavy ion P-type implantation is performed on the sidewalls of the deep trench 600. This implantation method can form a specific P-type doped region on the sidewalls of the deep trench 600 to adjust the electrical properties of the deep trench 600. Here, the deep trench 600 refers to the trench that longitudinally penetrates the hard mask layer 500, the epitaxial layer 400, and the P-type silicon thin film 300.

[0090] Figure 8 is a schematic diagram after the isolation layer is formed in an embodiment of the present application. As Figure 8As shown, tetraethyl orthosilicate is grown to form an isolation layer 700 on the side of the hard mask layer 500 facing away from the epitaxial layer 400 and in the deep trench 600. Tetraethyl orthosilicate can be used as a silicon source for chemical vapor deposition. The isolation layer 700 of silicon dioxide material is formed by chemical vapor deposition process. Specifically, during chemical vapor deposition, tetraethyl orthosilicate will be heated and decomposed or undergo a chemical reaction to release silicon atoms and other related groups. These silicon atoms will react with other reaction gases or substances and finally deposit on a specific surface to form a silicon dioxide thin film, that is, the isolation layer 700. By covering the sidewalls of the deep trench 600 with the isolation layer 700, electrical isolation is formed to prevent leakage current between adjacent structures. The chemical vapor deposition process can precisely control the thickness and quality of the isolation layer 700 to ensure its good insulation performance.

[0091] Figure 9 It is a schematic diagram after the deep trench penetrates through the buried oxide layer in an embodiment of the present application. Figure 10 It is a schematic diagram after filling polysilicon in an embodiment of the present application. As Figure 9 shown, corresponding to step S500, the deep trench is etched by an adjusted full etch process (BlankEtch) to expand the cavity diameter of the deep trench and make the deep trench penetrate through the buried oxide layer 200 to establish a channel connected to the buried oxide layer 200. Expanding the cavity diameter of the deep trench can provide enough space for subsequent polysilicon filling, and making the deep trench penetrate through the buried oxide layer establishes a channel connected to the buried oxide layer, creating conditions for forming a conductive path. As Figure 10 shown, corresponding to step S500, N-type polysilicon 800 is filled in the deep trench to form a conductive path extending to and passing through the buried oxide layer 200.

[0092] Figure 11 It is a schematic diagram after chemical mechanical polishing in an embodiment of the present application. As Figure 11 shown, corresponding to step S600, DTI-CMP (Deep Trench Isolation - Chemical Mechanical Polishing) treatment is performed until it stops at the hard mask layer 500. DTI-CMP combines the deep trench isolation process and the chemical mechanical polishing process to provide a flat and insulating surface for the subsequent semiconductor device manufacturing process, which helps to improve the performance and reliability of the chip. The hard mask layer 500 serves as an etch stop layer. The hard mask layer 500 can optionally be a silicon nitride (SiN) layer, and the etch stop effect is achieved by utilizing the difference in the polishing rates of silicon nitride and silicon dioxide / polysilicon, which is beneficial for precisely controlling the polishing end point. When polishing reaches the hard mask layer 500, since the polishing rate of the hard mask layer 500 is slower, the polishing can be stopped in time to avoid over-polishing and damaging the underlying epitaxial layer 400.

[0093] Figure 12 It is a schematic diagram after forming an active layer in an embodiment of the present application. As Figure 12As shown, corresponding to step S600, the hard mask layer is removed by dry etching or wet etching to expose the epitaxial layer 400. Corresponding to step S700, an active layer 900 (including processes such as gate formation, source / drain implantation, etc.) is formed on the side of the epitaxial layer 400 away from the buried oxide layer 200, completing the FEOL (Front-End-of-Line) fabrication of the semiconductor device. Figure 12 In it, G, D, and source respectively represent the corresponding positions of the gate, drain, and source. NWL (N-Well Layer) represents the N-type well layer, HNN (High-Voltage N-layer) represents the high-voltage N layer, and PBD (P-type Body Diode) represents the P-type body diode.

[0094] Figure 13 It is a schematic structural diagram of a semiconductor device according to an embodiment of the present application. As Figure 13 shown, an interlayer dielectric layer 110 is formed on the side of the active layer away from the epitaxial layer 400. The interlayer dielectric layer 110 is generally composed of an insulating material such as silicon dioxide, etc., for providing electrical isolation to prevent current short circuits between different layers. A plurality of contact holes 120 are formed in the interlayer dielectric layer 110, and the positions of the contact holes 120 correspond to the positions of each terminal in the active layer. Conductive metal such as tungsten is filled in the contact holes 120 to lead out each terminal of the active layer.

[0095] As Figure 13 shown, an embodiment of the present application further provides a semiconductor device obtained by using the preparation method of the semiconductor device. The semiconductor device includes:

[0096] A P-type substrate 100;

[0097] A buried oxide layer 200 is provided on one side of the P-type substrate 100. A lightly doped N-type region and a heavily doped N-type region located in the lightly doped N-type region are formed on the side of the P-type substrate 100 facing the buried oxide layer 200; thus, an N+ doped region and an N- doped region are formed below the buried oxide layer 200 corresponding to the positions of the active regions. The N+ doped region is formed by implanting high-dose N-type impurity ions, having a high impurity concentration and good conductivity, mainly used for forming an ohmic contact to reduce the contact resistance of the device. The N- doped region is formed by implanting low-dose N-type impurity ions, having a relatively low impurity concentration, and can be used to adjust the electrical properties of the device such as the threshold voltage, etc.;

[0098] The epitaxial layer 400 is formed on the side of the buried oxide layer 200 away from the P-type substrate 100. Deep trenches are formed in the epitaxial layer 400 and the buried oxide layer 200, and polysilicon is filled in the deep trenches. A P-type silicon thin film 300 may also be provided between the buried oxide layer 200 and the epitaxial layer 400, and the deep trenches are opposite to the heavily doped N-type regions.

[0099] The active layer 900 (labeled in Figure 12 ), is formed on the side of the epitaxial layer 400 away from the buried oxide layer 200. The active layer 900 is the core region where semiconductor devices achieve electrical functions, and contains various active devices such as transistors and diodes.

[0100] This semiconductor device is obtained by using the above-mentioned method for manufacturing a semiconductor device, and can achieve the technical effects of the above-mentioned method for manufacturing a semiconductor device, which will not be traced here.

[0101] In this embodiment, as Figure 13 shown, an interlayer dielectric layer 110 is further provided above the active layer 900. A plurality of contact holes 120 are formed in the interlayer dielectric layer, and conductive metal (not shown in the figure), such as tungsten, is filled in the contact holes 120. Some of the contact holes 120 are opposite to the polysilicon filled in the deep trenches. The interlayer dielectric layer 110 mainly plays a role in insulation and protection of the active layer 900, preventing short circuits between different metal interconnect layers. The function of the contact holes 120 is to realize the electrical connection between the active layer 900 and the upper metal interconnect layer. The semiconductor device is configured to receive an external bias voltage and apply it to the heavily doped N-type regions through the conductive metal and the polysilicon in the deep trenches.

[0102] In summary, the semiconductor device and the manufacturing method provided by this application have the following advantages:

[0103] This application further expands based on the deep trench isolation technology, fabricates a polysilicon-filled deep trench isolation that penetrates the buried oxide layer in the SOI substrate, and conducts the charges accumulated in the buried oxide layer out of the substrate through the polysilicon part in the deep trench isolation, avoiding the retention of charges in the buried oxide layer, restoring the electric field balance in the buried oxide layer, preventing the ionization radiation from charging the buried oxide layer due to the Bragg effect and resulting in an accidental inversion layer, which is beneficial to improving the anti-ionization radiation ability of the semiconductor device, improving the reliability of the semiconductor device when used in a harsh environment, and is beneficial to improving the comprehensive performance of space technology equipment.

[0104] The above content is a further detailed description of this application in combination with specific preferred implementation manners. It cannot be determined that the specific implementation of this application is only limited to these descriptions. For those of ordinary skill in the technical field to which this application belongs, without departing from the concept of this application, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of this application.

Claims

1. A method for preparing a semiconductor device, characterized in that: The semiconductor device is a SOI BCD device, and the method comprises the following steps: A P-type substrate is provided, wherein a buried oxide layer is provided on one side of the P-type substrate, and the buried oxide layer is an insulating layer; Performing N-type ion implantation on a side of the buried oxide layer facing the P-type substrate to form a lightly doped N-type region and a heavily doped N-type region located in the lightly doped N-type region, wherein two heavily doped N-type regions are formed on both sides of each of the lightly doped N-type regions; forming an epitaxial layer and a hard mask layer on a side of the buried oxide layer away from the P-type substrate; Performing deep trench isolation etching on the hard mask layer and the epitaxial layer to form deep trenches; Etching the deep trench to penetrate the buried oxide layer, and filling the deep trench with polysilicon, wherein the deep trench is opposite to the heavily doped N-type region; After chemical mechanical polishing to the hard mask layer, removing the hard mask layer; forming an active layer on a side of the epitaxial layer away from the buried oxide layer; forming an interlayer dielectric layer on a side of the active layer away from the epitaxial layer; forming a plurality of contact holes in the interlayer dielectric layer, wherein some of the contact holes are opposite to the polysilicon filled in the deep trench; A conductive metal is filled in the contact hole, and the semiconductor device is configured to receive an external negative bias voltage and apply it to the heavily doped N-type region through the conductive metal and the polysilicon in the deep trench, wherein the negative bias voltage is configured to offset the built-in electric field caused by the positively charged holes retained in the buried oxide layer.

2. The method for preparing a semiconductor device according to claim 1, wherein: After the hard mask layer and the epitaxial layer are subjected to deep trench isolation etching to form deep trenches, the following steps are also included: Angle heavy ion implantation is performed on the sidewalls of the deep trench.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: After the hard mask layer and the epitaxial layer are subjected to deep trench isolation etching to form deep trenches, the following steps are also included: An isolation layer is formed on the sidewall of the deep trench.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: Forming an isolation layer on the sidewall of the deep trench comprises the following steps: TEOS is grown to form an isolation layer on a side of the hard mask layer away from the epitaxial layer and in the deep trench.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: Etching the deep trench to penetrate the buried oxide layer comprises the following steps: The deep trench is etched by adopting a full etching process to expand the cavity diameter of the deep trench and make the deep trench pass through the buried oxide layer.

6. The method for preparing a semiconductor device according to claim 1, wherein: Filling polysilicon in the deep trench includes: filling N-type polysilicon in the deep trench.

7. The method for preparing a semiconductor device according to claim 1, characterized in that: The removing of the hard mask layer includes removing the hard mask layer by dry etching or wet etching.

8. A semiconductor device, characterized in that: The semiconductor device is obtained by the method for preparing a semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is a SOI BCD device and comprises: P-type substrate; A buried oxide layer is provided on one side of the P-type substrate, the buried oxide layer is an insulating layer, and a lightly doped N-type region and a heavily doped N-type region located in the lightly doped N-type region are formed on the side of the P-type substrate facing the buried oxide layer; An epitaxial layer is formed on a side of the buried oxide layer away from the P-type substrate, a deep trench is formed in the epitaxial layer and the buried oxide layer, the deep trench is filled with polysilicon, and the deep trench is opposite to the heavily doped N-type region; An active layer formed on a side of the epitaxial layer away from the buried oxide layer; An interlayer dielectric layer, formed on a side of the active layer away from the epitaxial layer; forming a plurality of contact holes in the interlayer dielectric layer, wherein some of the contact holes are opposite to the polysilicon filled in the deep trench; A conductive metal is filled in the contact hole, and the semiconductor device is configured to receive an external negative bias voltage and apply it to the heavily doped N-type region through the conductive metal and the polysilicon in the deep trench, wherein the negative bias voltage is configured to offset the built-in electric field caused by the positively charged holes retained in the buried oxide layer.

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