Driving circuit, display substrate and display device

Abstract

The present disclosure provides a driving circuit, a display substrate and a display device. The driving circuit comprises an input circuit, a reset circuit, a first node reset circuit and a control node control circuit; the first node reset circuit controls the communication or disconnection between the first node and the first voltage line under the control of the potential of the second node; the control node control circuit controls the communication or disconnection between the control node and the third voltage line under the control of the potential of the first node; the ratio of the channel width-length ratio of the transistor whose gate is electrically connected with the second node included in the first node reset circuit to the channel width-length ratio of the transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24. The present disclosure can reasonably arrange the transistors included in each circuit, effectively prevent the first node from leaking, improve the driving capability of the display product, prevent the noise of the control node from being introduced into the first node through the leakage, improve the stability of the driving circuit, and prevent multiple outputs.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a driving circuit, a display substrate and a display device. BACKGROUND

[0002] In recent years, with the increasing demand of consumers for resolution and refresh rate of display devices, the driving capability of display panels also needs to be upgraded accordingly, and high mobility oxide transistors emerge as the times require. However, the electrical characteristics of the high mobility oxide transistors are that the threshold voltage is more negative than that of the traditional transistors, and part of the transistors in the driving circuit work in the state of gate-source voltage being 0V for a long time, which increases the leakage current and leads to the increase of power consumption. In addition, the transistors in the driving circuit cannot be reasonably arranged in the related technology, the leakage of the first node cannot be effectively prevented, and the driving capability of the display product cannot be improved. The related driving circuit cannot prevent the noise of the control node from being introduced into the first node through leakage, cannot improve the stability of the driving circuit, and cannot prevent multiple outputs. SUMMARY

[0003] In one aspect, the embodiments of the present disclosure provide a driving circuit, comprising an input circuit, a reset circuit, a first node reset circuit and a control node control circuit.

[0004] The input circuit is electrically connected with an input control end, an input end and a first node respectively, and is configured to control the input end and the first node to be in communication or disconnected under the control of an input control signal provided by the input control end.

[0005] The reset circuit is electrically connected with a reset end, the first node and a first voltage line respectively, and is configured to control the first node and the first voltage line to be in communication or disconnected under the control of a reset signal provided by the reset end.

[0006] The first node reset circuit is electrically connected with a second node, the first node and the first voltage line respectively, and is configured to control the first node and the first voltage line to be in communication or disconnected under the control of the potential of the second node.

[0007] The control node control circuit is electrically connected with the first node, a third voltage line and a control node respectively, and is configured to control the control node and the third voltage line to be in communication or disconnected under the control of the potential of the first node.

[0008] The transistors included in the input circuit, the transistors included in the reset circuit and the transistors included in the first node reset circuit are arranged in sequence along the direction away from the display area.

[0009] The ratio of the channel width-length ratio of the transistor whose gate is electrically connected to the second node to the channel width-length ratio of the transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

[0010] Optionally, the driving circuit further comprises a frame reset circuit.

[0011] The frame reset circuit is electrically connected to a frame reset line, the first node and a second voltage line, respectively, and is configured to control the first node to be in communication or disconnected with the second voltage line under the control of a frame reset signal provided by the frame reset line.

[0012] The transistor included in the frame reset circuit is arranged on a side of the transistor included in the first node reset circuit away from the display area.

[0013] Optionally, the input circuit comprises at least two input transistors connected in series with each other, and the reset circuit comprises at least two reset transistors connected in series with each other.

[0014] Optionally, the first node reset circuit comprises at least two transistors connected in series with each other and having gates electrically connected to the second node; or,

[0015] The second node comprises a first second node and a second second node; the first node reset circuit comprises at least two transistors connected in series with each other and having gates electrically connected to the first second node, and at least two transistors connected in series with each other and having gates electrically connected to the second second node.

[0016] Optionally, the frame reset circuit comprises at least two frame reset transistors connected in series with each other.

[0017] Optionally, the transistor included in the control node control circuit is arranged on a side of the transistor included in the input circuit close to the display area.

[0018] Optionally, the control node control circuit comprises a control transistor.

[0019] The gate of the control transistor is electrically connected to the first node, the first pole of the control transistor is electrically connected to the third voltage line, and the second pole of the control transistor is electrically connected to the control node.

[0020] Optionally, the driving circuit further comprises a shutdown reset circuit.

[0021] The shutdown reset circuit is electrically connected to a fourth voltage line and a driving signal output end, respectively, and is configured to control the driving signal output end to be in communication or disconnected with the fourth voltage line under the control of a fourth voltage signal provided by the fourth voltage line.

[0022] Optionally, the power-off reset circuit comprises a transistor arranged close to one side of the transistor of the input circuit.

[0023] Optionally, the power-off reset circuit comprises a power-off reset transistor.

[0024] The gate of the power-off reset transistor and the first pole of the power-off reset transistor are electrically connected to the fourth voltage line, and the second pole of the power-off reset transistor is electrically connected to the driving signal output end.

[0025] Optionally, the input circuit comprises a first input transistor and a second input transistor.

[0026] The gate of the first input transistor is electrically connected to the input control end, the first pole of the first input transistor is electrically connected to the input end, and the second pole of the first input transistor is electrically connected to the control node.

[0027] The gate of the second input transistor is electrically connected to the input control end, the first pole of the second input transistor is electrically connected to the control node, and the second pole of the second input transistor is electrically connected to the first node.

[0028] Optionally, the input control end is a carry signal output end of an adjacent upper level driving circuit, and the input end is a driving signal output end of the adjacent upper level driving circuit; or,

[0029] The input control end and the input end are both carry signal output ends of an adjacent upper level driving circuit.

[0030] Optionally, the reset circuit comprises a first reset transistor and a second reset transistor.

[0031] The gate of the first reset transistor is electrically connected to the reset end, the first pole of the first reset transistor is electrically connected to the first node, and the second pole of the first reset transistor is electrically connected to the control node.

[0032] The gate of the second reset transistor is electrically connected to the reset end, the first pole of the second reset transistor is electrically connected to the control node, and the second pole of the second reset transistor is electrically connected to the first voltage line.

[0033] Optionally, the channel width-length ratio of the transistor of the control node control circuit is smaller than the channel width-length ratio of the second reset transistor.

[0034] Optionally, the first node reset circuit comprises a first pull-down transistor and a second pull-down transistor.

[0035] The gate of the first pull-down transistor is electrically connected with the second node, the first pole of the first pull-down transistor is electrically connected with the first node, and the second pole of the first pull-down transistor is electrically connected with the control node.

[0036] The gate of the second pull-down transistor is electrically connected with the second node, the first pole of the second pull-down transistor is electrically connected with the control node, and the second pole of the second pull-down transistor is electrically connected with the first voltage line.

[0037] Optionally, the ratio of the channel width-length ratio of the second pull-down transistor to the channel width-length ratio of the transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

[0038] Optionally, the channel width-length ratio of the second pull-down transistor is greater than the channel width-length ratio of the first pull-down transistor.

[0039] Optionally, the second node includes a first second node and a second second node.

[0040] The first node reset circuit includes a first pull-down transistor, a second pull-down transistor, a third pull-down transistor, and a fourth pull-down transistor.

[0041] The gate of the first pull-down transistor is electrically connected with the first second node, the first pole of the first pull-down transistor is electrically connected with the first node, and the second pole of the first pull-down transistor is electrically connected with the control node.

[0042] The gate of the second pull-down transistor is electrically connected with the first second node, the first pole of the second pull-down transistor is electrically connected with the control node, and the second pole of the second pull-down transistor is electrically connected with the first voltage line.

[0043] The gate of the third pull-down transistor is electrically connected with the second second node, the first pole of the third pull-down transistor is electrically connected with the first node, and the second pole of the third pull-down transistor is electrically connected with the control node.

[0044] The gate of the fourth pull-down transistor is electrically connected with the second second node, the first pole of the fourth pull-down transistor is electrically connected with the control node, and the second pole of the fourth pull-down transistor is electrically connected with the first voltage line.

[0045] Optionally, the channel width-length ratio of the second pull-down transistor is greater than the channel width-length ratio of the first pull-down transistor, and the channel width-length ratio of the fourth pull-down transistor is greater than the channel width-length ratio of the third pull-down transistor.

[0046] Optionally, a ratio of a channel width-length ratio of the second pull-down transistor to a channel width-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

[0047] A ratio of a channel width-length ratio of the fourth pull-down transistor to a channel width-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

[0048] Optionally, the frame reset circuit includes a first frame reset transistor and a second frame reset transistor.

[0049] A gate of the first frame reset transistor is electrically connected with the frame reset line, a first pole of the first frame reset transistor is electrically connected with the first node, and a second pole of the first frame reset transistor is electrically connected with the control node.

[0050] A gate of the second frame reset transistor is electrically connected with the frame reset line, a first pole of the second frame reset transistor is electrically connected with the control node, and a second pole of the second frame reset transistor is electrically connected with the second voltage line.

[0051] Optionally, the driving circuit further includes a carry signal output circuit, a driving signal output circuit, and an energy storage circuit.

[0052] The carry signal output circuit is electrically connected with the first node, the second node, a carry signal output end, a clock signal end, and the second voltage line, respectively, for controlling the carry signal output end to be in communication or disconnection with the clock signal end under the control of the potential of the first node, and controlling the carry signal output end to be in communication or disconnection with the second voltage line under the control of the potential of the second node.

[0053] The driving signal output circuit is electrically connected with the first node, the second node, a driving signal output end, a clock signal end, and a fourth voltage line, respectively, for controlling the driving signal output end to be in communication or disconnection with the clock signal end under the control of the potential of the first node, and controlling the driving signal output end to be in communication or disconnection with the fourth voltage line under the control of the potential of the second node.

[0054] The energy storage circuit is electrically connected with the first node and the driving signal output end, respectively, for storing energy.

[0055] Optionally, the fourth voltage line is used for providing a fourth voltage signal, and the second voltage line is used for providing a second voltage signal.

[0056] A voltage value of the fourth voltage signal is equal to a voltage value of the second voltage signal, or the voltage value of the second voltage signal is less than the voltage value of the fourth voltage signal.

[0057] Optionally, the driving circuit further comprises a second node control circuit.

[0058] The second node control circuit is electrically connected with the input control end, the first node, the second node and the second voltage line, respectively, for controlling the second node to be connected or disconnected with the second voltage line under the control of an input control signal provided by the input control end, and controlling the potential of the second node under the control of the potential of the first node.

[0059] In a second aspect, the embodiments of the present disclosure provide a display substrate, comprising a substrate and the above-mentioned driving circuit arranged on the substrate.

[0060] Optionally, the display substrate further comprises an electrostatic protection circuit arranged on the substrate.

[0061] The first end of the electrostatic protection circuit is electrically connected with a driving signal line, the second end of the electrostatic protection circuit is electrically connected with a common electrode voltage end through a short circuit line, and the electrostatic protection circuit is used for electrostatic protection.

[0062] The driving signal line comprises a direct current voltage line, a clock signal line, a control voltage line and a frame reset line.

[0063] Optionally, the electrostatic protection circuit comprises a first protection transistor, a second protection transistor and a third protection transistor.

[0064] The gate of the first protection transistor and the first electrode of the first protection transistor are electrically connected with the driving signal line, and the second electrode of the first protection transistor is electrically connected with the gate of the second protection transistor.

[0065] The first electrode of the second protection transistor is electrically connected with the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected with the gate of the third protection transistor.

[0066] The gate of the third protection transistor and the first electrode of the third protection transistor are electrically connected with the short circuit line, and the second electrode of the third protection transistor is electrically connected with the gate of the second protection transistor.

[0067] The channel width-length ratio of the first protection transistor is greater than the channel width-length ratio of the second protection transistor, and the channel width-length ratio of the third protection transistor is greater than the channel width-length ratio of the second protection transistor.

[0068] Optionally, the electrostatic protection circuit comprises a first protection transistor, a second protection transistor, a third protection transistor, a fourth protection transistor and a fifth protection transistor.

[0069] The gate of the first protection transistor and the first pole of the first protection transistor are electrically connected with the driving signal line, and the second pole of the first protection transistor is electrically connected with the gate of the second protection transistor.

[0070] The first pole of the second protection transistor is electrically connected with the gate of the first protection transistor, and the second pole of the second protection transistor is electrically connected with the gate of the third protection transistor.

[0071] The first pole of the third protection transistor is electrically connected with the gate of the second protection transistor, and the second pole of the third protection transistor is electrically connected with the gate of the fourth protection transistor.

[0072] The first pole of the fourth protection transistor is electrically connected with the gate of the third protection transistor, and the second pole of the fourth protection transistor is electrically connected with the gate of the fifth protection transistor.

[0073] The gate of the fifth protection transistor and the first pole of the fifth protection transistor are electrically connected with the short circuit line, and the second pole of the fifth protection transistor is electrically connected with the gate of the fourth protection transistor.

[0074] The channel width-length ratio of the first protection transistor is greater than the channel width-length ratio of the second protection transistor, and the channel width-length ratio of the first protection transistor is greater than the channel width-length ratio of the fourth protection transistor.

[0075] The channel width-length ratio of the third protection transistor is greater than the channel width-length ratio of the second protection transistor, and the channel width-length ratio of the third protection transistor is greater than the channel width-length ratio of the fourth protection transistor.

[0076] The channel width-length ratio of the fifth protection transistor is greater than the channel width-length ratio of the second protection transistor, and the channel width-length ratio of the fifth protection transistor is greater than the channel width-length ratio of the fourth protection transistor.

[0077] In a third aspect, the embodiments of the present disclosure provide a display device, comprising the display substrate. BRIEF DESCRIPTION OF DRAWINGS

[0078] Figure 1 is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0079] Figure 2 is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0080] Figure 3 is a structural diagram of the driving circuit described in at least one embodiment of the present disclosure;

[0081] Figure 4 is a structural diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0082] Figure 5 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0083] Figure 6 is a waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in Figure 5 is a waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in

[0084] Figure 7 is a simulation waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in Figure 5 is a simulation waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in

[0085] Figure 8 is a simulation waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in Figure 5 is a simulation waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in

[0086] Figure 9 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 5

[0087] is a layout diagram of at least one embodiment of the driving circuit shown in Figure 10 Figure 5 is a layout diagram of the gate metal layer in

[0088] Figure 11 Figure 10 is a layout diagram of the semiconductor layer in

[0089] Figure 12 is a layout diagram of the conductive layer in Figure 10

[0090] is a layout diagram of the source-drain metal layer in Figure 13 Figure 10 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0091] Figure 14 Figure 10 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0092] Figure 15 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0093] Figure 16 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure;

[0094] Figure 17 is a circuit diagram of the driving circuit according to at least one embodiment of the present disclosure; ​​​​

[0095] Figure 18 is a circuit diagram of at least one embodiment of an electrostatic protection circuit;

[0096] Figure 19 is a layout diagram of at least one embodiment of an electrostatic protection circuit;

[0097] Figure 20 is a circuit diagram of at least one embodiment of an electrostatic protection circuit;

[0098] Figure 21 is a layout diagram of at least one embodiment of an electrostatic protection circuit. DETAILED DESCRIPTION

[0099] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0100] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two poles of the transistor other than the gate, one pole is referred to as the first pole and the other pole is referred to as the second pole.

[0101] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0102] As shown in FIG. 1, the driving circuit in the embodiments of the present disclosure includes an input circuit 11, a reset circuit 12, a first node reset circuit 13 and a control node control circuit 31. Figure 1 The input circuit 11 is electrically connected with an input control end IK1, an input end I1 and a first node PU respectively, and is configured to control the input end I1 to be connected or disconnected with the first node PU under the control of an input control signal provided by the input control end IK1.

[0103] The reset circuit 12 is electrically connected with a reset end R1, the first node PU and a first voltage line V1 respectively, and is configured to control the first node PU to be connected or disconnected with the first voltage line V1 under the control of a reset signal provided by the reset end R1.

[0104]

[0105] ​The first node reset circuit 13 is electrically connected with the second node PD, the first node PU and the first voltage line V1 respectively, and is used for controlling the communication or disconnection between the first node PU and the first voltage line V1 under the control of the potential of the second node PD.

[0106] The control node control circuit 31 is electrically connected with the first node PU, the third voltage line V3 and the control node N0 respectively, and is used for controlling the communication or disconnection between the control node N0 and the third voltage line V3 under the control of the potential of the first node PU.

[0107] The transistors included in the input circuit 11, the transistors included in the reset circuit 12 and the transistors included in the first node reset circuit 13 are arranged in sequence along the direction away from the display area.

[0108] The ratio of the channel width-length ratio of the transistor whose gate is electrically connected with the second node to the channel width-length ratio of the transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

[0109] Optionally, the first voltage line can be a first low voltage line or a second low voltage line, but is not limited thereto.

[0110] In a specific implementation, the driving circuit according to the embodiments of the present disclosure can include an input circuit 11, a reset circuit 12 and a first node reset circuit 13. The input circuit 11 controls the communication or disconnection between the input end I1 and the first node PU under the control of an input control signal. The reset circuit 12 controls the communication or disconnection between the first node PU and the first voltage line V1 under the control of a reset signal. The first node reset circuit 13 controls the communication or disconnection between the first node PU and the first voltage line V1 under the control of the potential of the second node PD. The transistors included in the input circuit 11, the transistors included in the reset circuit 12 and the transistors included in the first node reset circuit 13 can be arranged in sequence along the direction away from the display area, so as to reasonably arrange the transistors included in each circuit and make good use of the horizontal space of the frame of the display substrate.

[0111] Optionally, the third voltage line can be a high voltage line.

[0112] The driving circuit according to at least one embodiment of the present disclosure adds the control node control circuit 31. When the potential of the first node PU is a high voltage, the potential of the control node N0 is charged to a high voltage. At this time, the leakage path of the first node PU is PU to N0, so as to effectively prevent the leakage of the first node PU and improve the driving capability of the display product.

[0113] In specific implementation, the ratio of the channel width-length ratio of the transistor whose gate is electrically connected to the second node included in the first node reset circuit and the channel width-length ratio of the transistor included in the control node control circuit can be adjusted to prevent the noise of the control node from being introduced into the first node through leakage current, improve the stability of the driving circuit, and prevent multiple outputs.

[0114] Optionally, the channel width-length ratio of the transistor included in the control node control circuit can be 5 / 12, the channel width-length ratio of the transistor whose gate is electrically connected to the second node included in the first node reset circuit can be 30 / 6, and the ratio between the channel width-length ratio of the transistor included in the control node control circuit and the channel width-length ratio of the transistor whose gate is electrically connected to the second node included in the first node reset circuit is 1:12, but the present application is not limited thereto.

[0115] In at least one embodiment of the present application, the input circuit can be electrically connected to an input control end IK1 and an input end I1 respectively, for controlling the communication or disconnection between the input end I1 and the first node PU under the control of an input control signal provided by the input control end IK1.

[0116] In specific implementation, the input control end IK1 and the input end I1 can be different signal ends and access different signals respectively; or,

[0117] The input control end IK1 and the input end I1 can also be the same signal end and access the same signal.

[0118] In at least one embodiment of the present application, the input circuit includes at least two input transistors connected in series with each other, and the reset circuit includes at least two reset transistors connected in series with each other.

[0119] In specific implementation, the input circuit can include at least two transistors whose gates are electrically connected to an input control end and connected in series with each other, and the reset circuit can include at least two transistors whose gates are electrically connected to a reset end and connected in series with each other, so as to replace the transistor whose first pole or second pole is electrically connected to the first node with at least two transistors connected in series, so as to reduce the leakage current of the first node and improve the stability of the driving circuit.

[0120] In at least one embodiment of the present application, the first node reset circuit includes at least two transistors connected in series with each other whose gates are electrically connected to the second node; or,

[0121] The second node includes a first second node and a second second node; the first node reset circuit includes two transistors connected in series with each other whose gates are electrically connected to the first second node, and at least two transistors connected in series with each other whose gates are electrically connected to the second second node.

[0122] In a specific implementation, when the driving circuit adopts one second node, the first node reset circuit can include at least two transistors whose gates are electrically connected to the second node.

[0123] When the driving circuit adopts two second nodes, the first node reset circuit can include two transistors whose gates are electrically connected to the first second node and are connected in series with each other, and at least two transistors whose gates are electrically connected to the second second node and are connected in series with each other.

[0124] At least one embodiment of the present disclosure changes the transistor whose first electrode or second electrode is electrically connected to the first node into at least two transistors connected in series, so as to reduce the leakage current of the first node and improve the stability of the driving circuit.

[0125] As shown in FIG. 1, on the basis of the embodiment of the driving circuit shown in FIG. 1, the driving circuit according to at least one embodiment of the present disclosure further includes a frame reset circuit 21. Figure 2 Figure 1 The frame reset circuit 21 is electrically connected to a frame reset line STV0, the first node PU and a second voltage line V2, and is configured to control the first node PU to be in communication or disconnected with the second voltage line V2 under the control of a frame reset signal provided by the frame reset line STV0.

[0126] The transistors included in the frame reset circuit 21 are arranged on a side of the transistors included in the first node reset circuit 13 away from the display area.

[0127] Optionally, the second voltage line can be a second low voltage line, but is not limited thereto.

[0128] In a specific implementation, the driving circuit according to at least one embodiment of the present disclosure can further include a frame reset circuit 21, which is configured to control the potential of the first node PU to be reset under the control of a frame reset signal in a blank time period between two frame display times; and the transistors included in the frame reset circuit 21 are arranged on a side of the transistors included in the first node reset circuit 13 away from the display area, so as to reasonably arrange the transistors included in each circuit and make good use of the horizontal space of the frame of the display substrate.

[0129] Optionally, the frame reset circuit includes at least two frame reset transistors connected in series with each other.

[0130] Optionally, the frame reset circuit includes at least two frame reset transistors connected in series with each other.

[0131] ​In at least one embodiment of this disclosure, the frame reset circuit may include at least two transistors whose gates are electrically connected to the frame reset line in series. In at least one embodiment of this disclosure, the transistor whose first or second terminal is electrically connected to the first node is replaced with at least two transistors in series to reduce the leakage current of the first node and improve the stability of the driving circuit.

[0132] In at least one embodiment of this disclosure, the transistors included in the control node control circuit are disposed on the side of the transistors included in the input circuit closer to the display area.

[0133] In a specific implementation, the transistors included in the control node control circuit can be arranged on the side of the transistors included in the input circuit closer to the display area, so as to reasonably arrange the transistors included in each circuit and make good use of the horizontal space of the display substrate frame.

[0134] Optionally, the control node control circuit includes a control transistor;

[0135] The gate of the control transistor is electrically connected to the first node, the first electrode of the control transistor is electrically connected to the third voltage line, and the second electrode of the control transistor is electrically connected to the control node.

[0136] The driving circuit described in at least one embodiment of this disclosure further includes a power-off reset circuit;

[0137] The power-off reset circuit is electrically connected to the fourth voltage line and the drive signal output terminal respectively, and is used to control the connection or disconnection between the drive signal output terminal and the fourth voltage line under the control of the fourth voltage signal provided by the fourth voltage line.

[0138] Optionally, the fourth voltage line can be the first low voltage line.

[0139] In a specific implementation, the driving circuit may further include a power-off reset circuit, which, under the control of the fourth voltage signal, controls the connection or disconnection between the driving signal output terminal and the fourth voltage line.

[0140] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the driving circuit shown, the driving circuit described in at least one embodiment of this disclosure further includes a power-off reset circuit 41;

[0141] The power-off reset circuit 41 is electrically connected to the fourth voltage line V4 and the drive signal output terminal GT, respectively, and is used to control the connection or disconnection between the drive signal output terminal GT and the fourth voltage line V4 under the control of the fourth voltage signal provided by the fourth voltage line V4.

[0142] In at least one embodiment of the present disclosure, when the transistor included in the power-off reset circuit 41 is an n-type transistor, a low voltage signal is provided by the fourth voltage line V4 when the display panel is normally displaying, and a high voltage signal is provided by the fourth voltage line V4 when the display panel is preparing to power off. The power-off reset circuit 41 controls the communication between the driving signal output end GT and the fourth voltage line V4 under the control of the fourth voltage signal, so that the driving signal output end GT outputs a high voltage signal, the residual charge in the pixel can be released, the opening ability of the driving signal output end GT can be effectively improved, and image sticking can be avoided.

[0143] In the related art, when the display panel is powered off, the voltage signal provided by each direct current voltage line is pulled high to a high level, and the fourth voltage line V4 inputs a high voltage signal to the AA area (active display area) through the output reset transistor included in the driving circuit to complete pixel discharge. However, after the reliability of the display product is ensured, the drift output ability of the output reset transistor decreases, which causes insufficient opening of the gate line and incomplete release of the pixel charge, resulting in image sticking. Based on this, in at least one embodiment of the present disclosure, the power-off reset circuit 41 controls the driving signal output end GT to output a high voltage signal under the control of the fourth voltage signal when the display panel is powered off, so as to release the residual charge in the pixel, effectively improve the opening ability of the driving signal output end GT, and avoid image sticking.

[0144] In at least one embodiment of the present disclosure, the transistor included in the power-off reset circuit is arranged on the side of the transistor included in the input circuit close to the display area.

[0145] In specific implementation, the transistor included in the power-off reset circuit is arranged on the side of the transistor included in the input circuit close to the display area, so as to reasonably arrange the transistors included in each circuit and make good use of the horizontal space of the frame of the display substrate.

[0146] Optionally, the power-off reset circuit includes a power-off reset transistor.

[0147] The gate of the power-off reset transistor and the first electrode of the power-off reset transistor are electrically connected with the fourth voltage line, and the second electrode of the power-off reset transistor is electrically connected with the driving signal output end.

[0148] Optionally, the input circuit includes a first input transistor and a second input transistor.

[0149] The gate of the first input transistor is electrically connected with the input control end, the first electrode of the first input transistor is electrically connected with the input end, and the second electrode of the first input transistor is electrically connected with the control node.

[0150] The gate of the second input transistor is electrically connected with the input control end, the first pole of the second input transistor is electrically connected with the control node, and the second pole of the second input transistor is electrically connected with the first node.

[0151] In at least one embodiment of the present disclosure, the input control end is a carry signal output end of an adjacent upper-level driving circuit, and the input end is a driving signal output end of the adjacent upper-level driving circuit.

[0152] The input control end and the input end are both carry signal output ends of an adjacent upper-level driving circuit.

[0153] In specific implementation, the input control end can be a carry signal output end of an adjacent upper-level driving circuit, the input end can be a driving signal output end of the adjacent upper-level driving circuit, or the input control end and the input end can both be carry signal output ends of the adjacent upper-level driving circuit.

[0154] Optionally, the reset circuit includes a first reset transistor and a second reset transistor.

[0155] The gate of the first reset transistor is electrically connected with the reset end, the first pole of the first reset transistor is electrically connected with the first node, and the second pole of the first reset transistor is electrically connected with the control node.

[0156] The gate of the second reset transistor is electrically connected with the reset end, the first pole of the second reset transistor is electrically connected with the control node, and the second pole of the second reset transistor is electrically connected with the first voltage line.

[0157] In at least one embodiment of the present disclosure, the control node control circuit includes a transistor with a channel width-length ratio smaller than that of the second reset transistor.

[0158] In specific implementation, the channel width-length ratio of the transistor included in the control node control circuit and the channel width-length ratio of the second reset transistor can be adjusted, so that when the reset signal provided by the reset end arrives, the competitiveness of the second reset transistor is improved, the potential of the control node and the potential of the first node are rapidly reduced to a low voltage, and it is ensured that the potential of the second node can be synchronously increased to a high voltage to start noise reduction.

[0159] For example, the channel width-length ratio of the transistor included in the control node control circuit can be 5 / 12, and the channel width-length ratio of the second reset transistor can be 5 / 6, but the present disclosure is not limited thereto.

[0160] Optionally, the first node reset circuit includes a first pull-down transistor and a second pull-down transistor.

[0161] The gate of the first pull-down transistor is electrically connected with the second node, the first pole of the first pull-down transistor is electrically connected with the first node, and the second pole of the first pull-down transistor is electrically connected with the control node.

[0162] The gate of the second pull-down transistor is electrically connected with the second node, the first pole of the second pull-down transistor is electrically connected with the control node, and the second pole of the second pull-down transistor is electrically connected with the first voltage line.

[0163] In at least one embodiment of the present disclosure, the ratio of the channel width-length ratio of the second pull-down transistor to the channel width-length ratio of the transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

[0164] In specific implementation, by adjusting the ratio of the channel width-length ratio of the second pull-down transistor to the channel width-length ratio of the transistor included in the control node control circuit, the noise of the control node can be prevented from being introduced into the first node through leakage, the stability of the driving circuit is improved, and multiple outputs are prevented.

[0165] Optionally, the channel width-length ratio of the transistor included in the control node control circuit can be 5 / 12, the channel width-length ratio of the second pull-down transistor can be 30 / 6, and the ratio between the channel width-length ratio of the transistor included in the control node control circuit and the channel width-length ratio of the second pull-down transistor is 1:12, but it is not limited thereto.

[0166] Optionally, the channel width-length ratio of the second pull-down transistor is greater than the channel width-length ratio of the first pull-down transistor.

[0167] In specific implementation, the channel width-length ratio of the second pull-down transistor can be greater than the channel width-length ratio of the first pull-down transistor, and by adjusting the channel width-length ratio of the first pull-down transistor and the channel width-length ratio of the second pull-down transistor, the noise of the control node can be prevented from being introduced into the first node through leakage, the stability of the driving circuit is improved, and multiple outputs are prevented.

[0168] For example, the channel width-length ratio of the first pull-down transistor can be 15 / 6, and the channel width-length ratio of the second pull-down transistor can be 30 / 6, but it is not limited thereto.

[0169] Optionally, the second node includes a first second node and a second second node.

[0170] The first node reset circuit includes a first pull-down transistor, a second pull-down transistor, a third pull-down transistor, and a fourth pull-down transistor.

[0171] The gate of the first pull-down transistor is electrically connected with the first second node, the first pole of the first pull-down transistor is electrically connected with the first node, and the second pole of the first pull-down transistor is electrically connected with the control node;

[0172] The gate of the second pull-down transistor is electrically connected with the first second node, the first pole of the second pull-down transistor is electrically connected with the control node, and the second pole of the second pull-down transistor is electrically connected with the first voltage line;

[0173] The gate of the third pull-down transistor is electrically connected with the second second node, the first pole of the third pull-down transistor is electrically connected with the first node, and the second pole of the third pull-down transistor is electrically connected with the control node;

[0174] The gate of the fourth pull-down transistor is electrically connected with the second second node, the first pole of the fourth pull-down transistor is electrically connected with the control node, and the second pole of the fourth pull-down transistor is electrically connected with the first voltage line.

[0175] In at least one embodiment of the present disclosure, the channel width-length ratio of the second pull-down transistor is greater than the channel width-length ratio of the first pull-down transistor, and the channel width-length ratio of the fourth pull-down transistor is greater than the channel width-length ratio of the third pull-down transistor.

[0176] In at least one embodiment of the present disclosure, the channel width-length ratio of the second pull-down transistor is greater than the channel width-length ratio of the first pull-down transistor, and the channel width-length ratio of the fourth pull-down transistor is greater than the channel width-length ratio of the third pull-down transistor.

[0177] In specific implementation, the channel width-length ratio of the second pull-down transistor can be greater than the channel width-length ratio of the first pull-down transistor, and the channel width-length ratio of the fourth pull-down transistor can be greater than the channel width-length ratio of the third pull-down transistor. By being configured as above, the noise of the control node can be prevented from being introduced into the first node through leakage, the stability of the driving circuit is improved, and multiple outputs are prevented.

[0178] For example, the channel width-length ratio of the first pull-down transistor and the channel width-length ratio of the third pull-down transistor can be 15 / 6, and the channel width-length ratio of the second pull-down transistor and the channel width-length ratio of the fourth pull-down transistor can be 30 / 6, but the present disclosure is not limited thereto.

[0179] Optionally, the ratio of the channel width-length ratio of the second pull-down transistor to the channel width-length ratio of the transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24;

[0180] The ratio of the channel width-length ratio of the fourth pull-down transistor to the channel width-length ratio of the control transistor is greater than or equal to 6 and less than or equal to 24.

[0181] In specific implementation, by adjusting the ratio of the channel width-length ratio of the second pull-down transistor and the channel width-length ratio of the transistor included in the control node control circuit, and adjusting the ratio of the channel width-length ratio of the fourth pull-down transistor and the channel width-length ratio of the transistor included in the control node control circuit, the noise of the control node is prevented from being introduced into the first node through leakage, the stability of the driving circuit is improved, and multiple outputs are prevented.

[0182] Optionally, the channel width-length ratio of the transistor included in the control node control circuit can be 5 / 12, the channel width-length ratio of the second pull-down transistor and the channel width-length ratio of the fourth pull-down transistor can be 30 / 6, the ratio between the channel width-length ratio of the transistor included in the control node control circuit and the channel width-length ratio of the second pull-down transistor is 1:12, and the ratio between the channel width-length ratio of the transistor included in the control node control circuit and the channel width-length ratio of the fourth pull-down transistor is 1:12, but the present disclosure is not limited thereto.

[0183] Optionally, the frame reset circuit includes a first frame reset transistor and a second frame reset transistor.

[0184] The gate of the first frame reset transistor is electrically connected with the frame reset line, the first pole of the first frame reset transistor is electrically connected with the first node, and the second pole of the first frame reset transistor is electrically connected with the control node.

[0185] The gate of the second frame reset transistor is electrically connected with the frame reset line, the first pole of the second frame reset transistor is electrically connected with the control node, and the second pole of the second frame reset transistor is electrically connected with the second voltage line.

[0186] In at least one embodiment of the present disclosure, the frame reset circuit electrically connected with the first node can be configured to include the first frame reset transistor and the second frame reset transistor connected in series with each other, so as to reduce the leakage of the first node.

[0187] The driving circuit in at least one embodiment of the present disclosure further includes a carry signal output circuit, a driving signal output circuit, and an energy storage circuit.

[0188] The carry signal output circuit is electrically connected with the first node, the second node, a carry signal output end, a clock signal end, and the second voltage line, respectively, for controlling the carry signal output end to be in communication or disconnected with the clock signal end under the control of the potential of the first node, and controlling the carry signal output end to be in communication or disconnected with the second voltage line under the control of the potential of the second node.

[0189] The drive signal output circuit is electrically connected with the first node, the second node, the drive signal output end, the clock signal end and the fourth voltage line respectively, and is configured to control the drive signal output end to be in communication or disconnected with the clock signal end under the control of the potential of the first node, and control the drive signal output end to be in communication or disconnected with the fourth voltage line under the control of the potential of the second node.

[0190] The energy storage circuit is electrically connected with the first node and the drive signal output end respectively, and is configured to store electric energy.

[0191] Optionally, the second voltage line can be a second low-voltage line, and the fourth voltage line can be a first low-voltage line.

[0192] In at least one embodiment of the present disclosure, the fourth voltage line is configured to provide a fourth voltage signal, and the second voltage line is configured to provide a second voltage signal.

[0193] The voltage value of the fourth voltage signal is equal to the voltage value of the second voltage signal, or the voltage value of the second voltage signal is less than the voltage value of the fourth voltage signal.

[0194] In specific implementation, the drive circuit can further include a carry signal output circuit and a drive signal output circuit. The carry signal output circuit controls the drive signal output end to be in communication or disconnected with the clock signal end under the control of the potential of the first node, and controls the drive signal output end to be in communication or disconnected with the third voltage line under the control of the potential of the second node. The drive signal output circuit controls the drive signal output end to be in communication or disconnected with the clock signal end under the control of the potential of the first node, and controls the drive signal output end to be in communication or disconnected with the third voltage line under the control of the potential of the second node.

[0195] In specific implementation, the voltage value of the second voltage signal can be less than the voltage value of the fourth voltage signal. When the input control end is a carry signal output end of an adjacent upper-level drive circuit, and the input end is a drive signal output end of the adjacent upper-level drive circuit, the gate-source voltage of a transistor for inputting is less than 0V, the working state of the transistor for inputting changes from a sub-threshold region to an off state, and the current leakage of the first node is reduced when the potential of the first node is lifted in the second order.

[0196] The drive circuit in at least one embodiment of the present disclosure further includes a second node control circuit.

[0197] The second node control circuit is electrically connected with the input control end, the first node, the second node and the second voltage line respectively, and is configured to control the second node to be connected or disconnected with the second voltage line under the control of an input control signal provided by the input control end, and control the potential of the second node under the control of the potential of the first node.

[0198] In a specific implementation, the driving circuit can include a second node control circuit configured to control the second node to be connected or disconnected with the fourth voltage line under the control of an input control signal, and control the potential of the second node under the control of the potential of the first node.

[0199] As shown in Figure 4 As shown in Figure 3 Based on at least one embodiment of the driving circuit shown in the figure, the driving circuit in at least one embodiment of the present disclosure includes a first second node PD1, a second second node PD2, a second node control circuit 43, an energy storage circuit 40, a carry signal output circuit 44 and a driving signal output circuit 45;

[0200] The first node reset circuit 13 is electrically connected with the first second node PD1, the second second node PD2, the first node PU and the first voltage line V1 respectively, and is configured to control the first node PU to be connected with the first voltage line V1 under the control of the potential of the first second node PD1, and control the first node PU to be connected with the first voltage line V1 under the control of the potential of the second second node PD2;

[0201] The second node control circuit 43 is electrically connected with the input control end IK1, the first node PU, the first second node PD1, the second second node PD2 and the second voltage line V2 respectively, and is configured to control the first second node PD1 to be connected with the second voltage line V2, control the second second node PD2 to be connected with the second voltage line V2, and control the potential of the first second node PD1 and the potential of the second second node PD2 under the control of the potential of the first node PU under the control of an input control signal provided by the input control end IK1;

[0202] The first end of the energy storage circuit 40 is electrically connected with the first node PU, and the second end of the energy storage circuit 40 is electrically connected with the driving signal output end GT. The energy storage circuit 40 is configured to store electric energy.

[0203] The carry signal output circuit 44 is electrically connected with the first node PU, the first second node PD1, the second second node PD2, the carry signal output end OC, the clock signal end CLK and the second voltage line V2 respectively, and is configured to control the communication between the carry signal output end OC and the clock signal end CLK under the control of the potential of the first node PU, control the communication between the carry signal output end OC and the second voltage line V2 under the control of the potential of the first second node PD1, and control the communication between the carry signal output end OC and the second voltage line V2 under the control of the potential of the second second node PD2.

[0204] The drive signal output circuit 45 is electrically connected with the first node PU, the first second node PD1, the second second node PD2, the drive signal output end GT, the clock signal end CLK and the fourth voltage line V4 respectively, and is configured to control the communication between the drive signal output end GT and the clock signal end CLK under the control of the potential of the first node PU, control the communication between the drive signal output end GT and the fourth voltage line V4 under the control of the potential of the first second node PD1, and control the communication between the drive signal output end GT and the fourth voltage line V4 under the control of the potential of the second second node PD2.

[0205] As shown in FIG. 1, the drive circuit includes a first input circuit 10, a second input circuit 20, a control node control circuit 30, a carry signal output circuit 44, a drive signal output circuit 45, a power supply circuit 50 and a power-off reset circuit 60. Figure 5 Figure 4 As shown in FIG. 1, the drive circuit includes a first input circuit 10, a second input circuit 20, a control node control circuit 30, a carry signal output circuit 44, a drive signal output circuit 45, a power supply circuit 50 and a power-off reset circuit 60.

[0206] The power-off reset circuit 60 includes a power-off reset transistor M14.

[0207] The gate of the power-off reset transistor M14 and the source of the power-off reset transistor M14 are electrically connected with the first low voltage line VGL, and the drain of the power-off reset transistor M14 is electrically connected with the drive signal output end GT.

[0208] The control node control circuit 30 includes a control transistor M0.

[0209] The gate of the control transistor M0 is electrically connected with the first node PU, the source of the control transistor M0 is electrically connected with the high voltage line VGH, and the drain of the control transistor M0 is electrically connected with the control node N0.

[0210] The input circuit includes a first input transistor M1A and a second input transistor M1B.

[0211] ​The gate of the first input transistor M1A is electrically connected with the input control end IK1, the source of the first input transistor M1A is electrically connected with the input end I0, and the drain of the first input transistor M1A is electrically connected with the control node N0;

[0212] The gate of the second input transistor M1B is electrically connected with the input control end IK1, the source of the second input transistor M1B is electrically connected with the control node N0, and the drain of the second input transistor M1B is electrically connected with the first node PU;

[0213] The reset circuit comprises a first reset transistor M2A and a second reset transistor M2B;

[0214] The gate of the first reset transistor M2A is electrically connected with the reset end R1, the source of the first reset transistor M2A is electrically connected with the first node PU, and the drain of the first reset transistor M2A is electrically connected with the control node N0;

[0215] The gate of the second reset transistor M2B is electrically connected with the reset end R1, the source of the second reset transistor M2B is electrically connected with the control node N0, and the drain of the second reset transistor M2B is electrically connected with the first low-voltage line VGL;

[0216] The first node reset circuit comprises a first pull-down transistor M8A, a second pull-down transistor M8C, a third pull-down transistor M8B and a fourth pull-down transistor M8D;

[0217] The gate of the first pull-down transistor M8A is electrically connected with the first second node PD1, the source of the first pull-down transistor M8A is electrically connected with the first node PU, and the drain of the first pull-down transistor M8A is electrically connected with the control node N0;

[0218] The gate of the second pull-down transistor M8C is electrically connected with the first second node PD1, the source of the second pull-down transistor M8C is electrically connected with the control node N0, and the drain of the second pull-down transistor M8C is electrically connected with the first low-voltage line VGL;

[0219] The gate of the third pull-down transistor M8B is electrically connected with the second second node PD2, the source of the third pull-down transistor M8B is electrically connected with the first node PU, and the drain of the third pull-down transistor M8B is electrically connected with the control node N0;

[0220] A gate of the fourth pull-down transistor M8D is electrically connected with the second node PD2, a source of the fourth pull-down transistor M8D is electrically connected with the control node N0, and a drain of the fourth pull-down transistor M8D is electrically connected with the first low voltage line VGL.

[0221] The frame reset circuit comprises a first frame reset transistor M15A and a second frame reset transistor M15B.

[0222] A gate of the first frame reset transistor M15A is electrically connected with the frame reset line STV0, a source of the first frame reset transistor M15A is electrically connected with the first node PU, and a drain of the first frame reset transistor M15A is electrically connected with the control node N0.

[0223] A gate of the second frame reset transistor M15B is electrically connected with the frame reset line STV0, a source of the second frame reset transistor M15B is electrically connected with the control node N0, and a drain of the second frame reset transistor M15B is electrically connected with the second low voltage line LVGL.

[0224] The second node control circuit comprises a first control transistor M5A, a second control transistor M6A, a third control transistor M16A, a fourth control transistor M5B, a fifth control transistor M6B and a sixth control transistor M16B.

[0225] A gate of the first control transistor M5A and a source of the first control transistor M5A are electrically connected with the first control voltage line VDDO, and a drain of the first control transistor M5A is electrically connected with the first node PD1.

[0226] A gate of the second control transistor M6A is electrically connected with the first node PU, a source of the second control transistor M6A is electrically connected with the first node PD1, and a drain of the second control transistor M6A is electrically connected with the second low voltage line LVGL.

[0227] A gate of the third control transistor M16A is electrically connected with the input control terminal IK1, a source of the third control transistor M16A is electrically connected with the first node PD1, and a drain of the third control transistor M16A is electrically connected with the second low voltage line LVGL.

[0228] A gate of the fourth control transistor M5B and a source of the second control transistor M5B are electrically connected with the second control voltage line VDDE, and a drain of the second control transistor M5B is electrically connected with the second node PD2.

[0229] The gate of the fifth control transistor M6B is electrically connected with the first node PU, the source of the fifth control transistor M6B is electrically connected with the second node PD2, and the drain of the fifth control transistor M6B is electrically connected with the second low voltage line LVGL;

[0230] The gate of the sixth control transistor M16B is electrically connected with the input control terminal IK1, the source of the sixth control transistor M16B is electrically connected with the second node PD2, and the drain of the sixth control transistor M16B is electrically connected with the second low voltage line LVGL;

[0231] The energy storage circuit comprises a storage capacitor C0;

[0232] The first plate of C0 is electrically connected with the first node PU, and the second plate of C0 is electrically connected with the driving signal output terminal GT;

[0233] The carry signal output circuit comprises a carry output transistor M11, a first carry reset transistor M12A and a second carry reset transistor M12B, and the driving signal output circuit comprises a driving output transistor M3, a first driving reset transistor M13A, a second driving reset transistor M13B and an output reset transistor M4;

[0234] The gate of the carry output transistor M11 is electrically connected with the first node PU, the source of the carry output transistor M11 is electrically connected with the clock signal terminal CLK, and the drain of the carry output transistor M11 is electrically connected with the carry signal output terminal OC;

[0235] The gate of the first carry reset transistor M12A is electrically connected with the first node PD1, the source of the first carry reset transistor M12A is electrically connected with the carry signal output terminal OC, and the drain of the first carry reset transistor M12A is electrically connected with the second low voltage line LVGL;

[0236] The gate of the second carry reset transistor M12B is electrically connected with the second node PD2, the source of the second carry reset transistor M12B is electrically connected with the carry signal output terminal OC, and the drain of the second carry reset transistor M12B is electrically connected with the second low voltage line LVGL;

[0237] The gate of the driving output transistor M3 is electrically connected with the first node PU, the source of the driving output transistor M3 is electrically connected with the clock signal terminal CLK, and the drain of the driving output transistor M3 is electrically connected with the driving signal output terminal GT;

[0238] The gate of the first driving reset transistor M13A is electrically connected with the first second node PD1, the source of the first driving reset transistor M13A is electrically connected with the driving signal output end GT, and the drain of the first driving reset transistor M13A is electrically connected with the first low voltage line VGL;

[0239] The gate of the second driving reset transistor M13B is electrically connected with the second second node PD2, the source of the second driving reset transistor M13B is electrically connected with the driving signal output end GT, and the drain of the second driving reset transistor M13B is electrically connected with the first low voltage line VGL;

[0240] The gate of the output reset transistor M4 is electrically connected with the reset control signal end R0, the source of the output reset transistor M4 is electrically connected with the driving signal output end GT, and the drain of the output reset transistor M4 is electrically connected with the first low voltage line VGL.

[0241] The input control end IK1 is the carry signal output end of the adjacent upper level driving circuit, and the input end I0 is the driving signal output end of the adjacent upper level driving circuit.

[0242] In at least one embodiment of the driving circuit shown in Figure 5 In at least one embodiment of the driving circuit shown in

[0243] In at least one embodiment of the driving circuit shown in Figure 5 In at least one embodiment of the driving circuit shown in

[0244] The drain of the first input transistor M1A is electrically connected with the control node N0; the source of the second input transistor M1B is electrically connected with the control node N0; the drain of the first reset transistor M2A is electrically connected with the control node N0; the source of the second reset transistor M2B is electrically connected with the control node N0; the drain of the first pull-down transistor M8A is electrically connected with the control node N0; the source of the second pull-down transistor M8C is electrically connected with the control node N0; the drain of the third pull-down transistor M8B is electrically connected with the control node N0; the source of the fourth pull-down transistor M8D is electrically connected with the control node N0; the drain of the first frame reset transistor M15A is electrically connected with the control node N0; the source of the second frame reset transistor M15B is electrically connected with the control node N0; at least one embodiment of the disclosure sets the transistor with the source or the drain electrically connected with the first node PU as two transistors in series to reduce the leakage current of the first node PU.

[0245] In Figure 5 In at least one embodiment of the driving circuit shown, M0, M2B, M8C, M8D, M15B, M16A and M16B jointly constitute a PU voltage ensuring unit; when I1 provides a high voltage signal to charge the first node PU of the current stage driving circuit, M16A and M16B are opened, at this time, the potential of PD1 and the potential of PD2 are quickly pulled down, M8A, M8B, M8C and M8D are closed, at the same time, the potential of PU climbs up, M0 is opened, the potential of N0 is charged to a high voltage, at this time, the leakage path of PU is PU-N0, the drain-source voltage of M1A, the drain-source voltage of M2A, the drain-source voltage of M8A, the drain-source voltage of M8B and the drain-source voltage of M15A are greatly reduced, close to 0V or equal to 0V, effectively preventing the leakage of the first node PU and improving the driving capability of the display product. At the same time, by adjusting the channel width-length ratio of M0 and the channel width-length ratio of M2B, the competitiveness of M2B is improved when the reset signal arrives, so that the potential of N0 and the voltage of the first node PU are quickly pulled down, ensuring that the potential of the pull-down node can be synchronously raised to a high voltage, and starting to reduce the noise of the driving signal and the carry signal. By adjusting the channel width-length ratio of M0, the channel width-length ratio of M8C and the channel width-length ratio of M8D, the ratio of the channel width-length ratio of M0 to the channel width-length ratio of M8C is 1 / 12, and the ratio of the channel width-length ratio of M0 to the channel width-length ratio of M8D is 1 / 12, by adjusting the channel width-length ratio of M8A, the channel width-length ratio of M8B, the channel width-length ratio of M8C and the channel width-length ratio of M8D, the ratio between the channel width-length ratio of M8A and the channel width-length ratio of M8C is set to 1 / 2, and the ratio between the channel width-length ratio of M8B and the channel width-length ratio of M8D is set to 1 / 2, preventing the noise of the control node N0 from being introduced into the first node PU through leakage, improving the stability of the driving circuit and preventing multiple outputs.

[0246] In Figure 5 In at least one embodiment of the drive circuit shown in FIG. 8, the channel width-length ratio of M0 can be 5 / 12, the channel width-length ratio of M2B can be 5 / 6, the channel width-length ratio of M8C can be 30 / 6, the channel width-length ratio of M8D can be 30 / 6, and the channel width-length ratio of M8A and the channel width-length ratio of M8B can be 15 / 6.

[0247] In Figure 5 In at least one embodiment of the drive circuit shown in FIG. 8, the drain of the first carry reset transistor M12A is electrically connected to the second low-voltage line LVGL, the drain of the second carry reset transistor M12B is electrically connected to the second low-voltage line LVGL, the drain of the first drive reset transistor M13A is electrically connected to the first low-voltage line VGL, and the drain of the second drive reset transistor M13B is electrically connected to the first low-voltage line VGL.

[0248] The first low-voltage line VGL is configured to provide a first low-voltage signal, and the second low-voltage line LVGL is configured to provide a second low-voltage signal. The voltage value of the second low-voltage signal can be less than the voltage value of the first low-voltage signal. When the input control terminal is a carry signal output terminal of an adjacent upper-stage drive circuit and the input terminal is a drive signal output terminal of the adjacent upper-stage drive circuit, the gate-source voltage of M1A and the voltage of M1B are less than 0V, the working state of M1A and the working state of M1B change from the sub-threshold region to the off state, and the leakage current of the second node PU is reduced when the potential of the first node PU is lifted in the second order.

[0249] In Figure 6 In at least one embodiment of the drive circuit shown in FIG. 8, the drain of M2B is electrically connected to the first low-voltage line VGL, the voltage value of the second low-voltage signal provided by the second low-voltage line is less than the voltage value of the first low-voltage signal provided by the first low-voltage line, the gate-source voltage of M2B, the gate-source voltage of M8C, and the gate-source voltage of M8D are all less than 0V, at this time, the working state of M2B, the working state of M8C, and the working state of M8D change from the sub-threshold region to the off state, and the leakage current is greatly reduced.

[0250] As Figure 5 As Figure 5 In at least one embodiment of the drive circuit shown in FIG. 8, when the drive circuit works in the touch scanning stage SC, the leakage current of the first node PU is small, and the potential of the first node PU can be maintained at a high voltage.

[0251] In Figure 7 In at least one embodiment of the drive circuit shown in FIG. 8, M14 is provided.

[0252] When the display panel is displaying normally, the first low voltage line VGL provides a low voltage signal. When the display panel is about to be turned off, the voltage signal provided by the first low voltage line LVGL is high, M14 is turned on, and the drive signal output terminal GT is controlled to output a high voltage signal, which can release the residual charge in the pixel and effectively improve the turn-on capability of the drive signal output terminal GT, avoiding image retention.

[0253] Figure 5 When in normal display mode, Figure 8 The simulated waveform of the potential of the first node PU when at least one embodiment of the driving circuit shown is in operation;

[0254] Figure 5 When in the touch stage, Figure 9 The simulated waveform of the potential of the first node PU during operation of at least one embodiment of the driving circuit shown; at this time, the highest potential of PU can be around 16.95V.

[0255] Figure 5 yes Figure 5 The timing diagram shows the operation of at least one embodiment of the driving circuit.

[0256] exist Figure 5 In at least one embodiment of the driving circuit shown, the channel width-to-length ratio of M14 can be selected according to the actual situation. The channel width-to-length ratio of M14 is usually close to that of M4, ensuring that the potential of the driving signal provided by GT can be pulled up to a high level quickly and sufficiently when the display panel is ready to be turned off.

[0257] This disclosure Figure 10 In at least one embodiment of the driving circuit shown, when in operation, the first control voltage provided by VDDO and the second control voltage provided by VDDE can be square wave signals, and the first control voltage and the second control voltage are out of phase with each other, so that PD1 and PD2 work alternately.

[0258] Figure 5 yes Figure 11 The diagram shows a layout of at least one embodiment of the driving circuit, which is disposed on a substrate.

[0259] Figure 10 yes Figure 12 Layout diagram of the gate metal layer in the middle. Figure 10 yes Figure 13 Layout diagram of the semiconductor layer in the middle. Figure 10 yes Figure 14 Layout diagram of the conductive layer in the middle. Figure 10 yes Figure 10 The layout diagram of the source and drain metal layers.

[0260] like Figures 10-14As shown, CLKA is the first clock signal line, CLKB is the second clock signal line, CLKC is the third clock signal line, CLKD is the fourth clock signal line, STV is the start voltage line, VDDO is the first control voltage line, VDDE is the second control voltage line, STV0 is the frame reset line, LVGL is the second low voltage line, VGL1 is the first low voltage line, VGL2 is the second low voltage line, and VGH is the high voltage line.

[0261] CLKA, CLKB, CLKC, CLKD, STV, VDDO, VDDE, STV0, LVGL, and VGL1 extend in the vertical direction;

[0262] CLKA, CLKB, CLKC, CLKD, STV, VDDO, VDDE, STV0, LVGL, and VGL1 are located on the side of the drive circuit away from the display area;

[0263] VGL2 and VGH extend in the vertical direction;

[0264] VGL2 and VGH are located on the side of the drive circuit closest to the display area.

[0265] like Figure 11 As shown, the transistors included in the input circuit, the transistors included in the reset circuit, and the transistors included in the first node reset circuit are arranged sequentially in a direction away from the display area.

[0266] M14 is located on the side of M0 furthest from the display area, and M0 is located on the side of M1A and M1B furthest from the display area.

[0267] The orthographic projections of the active pattern of M11, the first plate of C0, and the active pattern of M1A on the substrate are arranged sequentially along the vertical direction; the orthographic projections of the active pattern of M11, the first plate of C0, and the active pattern of M1B on the substrate are arranged sequentially along the vertical direction; this utilizes the vertical space layout of M11, C0, M1A, and M1B, which is beneficial for achieving a narrow bezel.

[0268] M1A and M1B are arranged side by side, with M1A and M1B arranged horizontally, and M1B is located on the side of M1A away from the display area;

[0269] M14 and M4 are arranged vertically in sequence to utilize the vertical space for layout, which is conducive to achieving a narrow bezel.

[0270] M3 and M0 are arranged in sequence along the vertical direction, so as to arrange M3 and M0 in the longitudinal space, and facilitate realization of narrow frame;

[0271] M3 is arranged between M14 and M11;

[0272] M2A and M2B are arranged side by side, and M2B and M2A are arranged along the horizontal direction;

[0273] M8D, M8B and M7A are arranged in sequence along the vertical direction, and M8D, M8B and M7B are arranged in sequence along the vertical direction, so as to arrange M8D, M8B, M7A and M7B in the longitudinal space, and facilitate realization of narrow frame;

[0274] M8C and M8A are arranged in sequence along the vertical direction, so as to arrange M8C and M8A in the longitudinal space, and facilitate realization of narrow frame;

[0275] M8D and M8C are arranged side by side, M8B and M8A are arranged side by side, M8C and M8D are arranged along the horizontal direction, M8A and M8B are arranged along the horizontal direction, M8D is arranged on the side of M8C away from the display area, and M8B is arranged on the side of M8A away from the display area;

[0276] M12B, M13B, M13A and M12A are arranged in sequence along the vertical direction, so as to arrange M12B, M13B, M13A and M12A in the vertical space, and facilitate realization of narrow frame;

[0277] M13B is arranged on the side of M8D away from the display area;

[0278] M6B, M15A and M16A are arranged in sequence along the vertical direction, and M6B, M15B and M16A are arranged in sequence along the vertical direction, so as to arrange M6B, M15A, M15B and M16A in the vertical space;

[0279] M15A and M15B are arranged side by side along the horizontal direction;

[0280] M6B is arranged on the side of M12B away from the display area;

[0281] M5B and M5A are arranged in sequence along the vertical direction, and M5A is arranged on the side of M6A away from the display area.

[0282] In Figure 12 , the label is CLKA1, which is the first clock signal line part included in CLKA; the label is CLKB1, which is the first clock signal line part included in CLKB; the label is CLKD1, which is the first clock signal line part included in CLKD; and the label is CLKD1, which is the first clock signal line part included in CLKD.

[0283] In Figure 14In the figure, the active pattern labeled as A8D is the active pattern of M8D, the active pattern labeled as A8C is the active pattern of M8C, the active pattern labeled as A8B is the active pattern of M8B, and the active pattern labeled as A8A is the active pattern of M8A.

[0284] In the figure, the active pattern labeled as A8D is the active pattern of M8D, the active pattern labeled as A8C is the active pattern of M8C, the active pattern labeled as A8B is the active pattern of M8B, and the active pattern labeled as A8A is the active pattern of M8A. Figure 15 In the figure, the active pattern labeled as A8D is the active pattern of M8D, the active pattern labeled as A8C is the active pattern of M8C, the active pattern labeled as A8B is the active pattern of M8B, and the active pattern labeled as A8A is the active pattern of M8A.

[0285] CLKA2 can be electrically connected with CLKA1, CLKB2 can be electrically connected with CLKB1, CLKC2 can be electrically connected with CLKC1, and CLKD2 can be electrically connected with CLKD1.

[0286] Figure 5 At least one embodiment of the driving circuit shown in the figure is different from at least one embodiment of the driving circuit shown in the figure in that: Figure 16

[0287] M0 and the control node N0 are not provided;

[0288] The drain of the first input transistor M1A is electrically connected with the source of the second input transistor M1B;

[0289] The drain of the first reset transistor M2A is electrically connected with the source of the second reset transistor M2B;

[0290] The drain of the first pull-down transistor M8A is electrically connected with the source of the second pull-down transistor M8C;

[0291] The drain of the third pull-down transistor M8B is electrically connected with the source of the fourth pull-down transistor M8D;

[0292] The drain of the first frame reset transistor M15A is electrically connected with the source of the second frame reset transistor M15B.

[0293] Figure 15 At least one embodiment of the driving circuit shown in the figure is different from at least one embodiment of the driving circuit shown in the figure in that: Figure 17

[0294] The gate of M1A and the gate of M1B are both electrically connected with I1;

[0295] The drain of M2B is electrically connected with the second low-voltage line LVGL, the drain of M8C is electrically connected with the second low-voltage line LVGL, and the drain of M8D is electrically connected with the second low-voltage line LVGL.

[0296] Figure 16 ​​At least one embodiment of the drive circuit shown is distinguished by Figure 18 At least one embodiment of the drive circuit shown is distinguished by:

[0297] The input circuit comprises an input transistor M1;

[0298] The gate of the input transistor M1 and the source of the input transistor M1 are electrically connected to the input terminal I0, and the drain of the input transistor M1 is electrically connected to the first node PU;

[0299] The reset circuit comprises a reset transistor M2;

[0300] The gate of the reset transistor M2 is electrically connected to the reset terminal R1, the source of the reset transistor M2 is electrically connected to the first node PU, and the drain of the reset transistor M2 is electrically connected to the first low-voltage line VGL;

[0301] The first node reset circuit comprises a first pull-down transistor M8A and a third pull-down transistor M8B;

[0302] The gate of the first pull-down transistor M8A is electrically connected to the first second node PD1, the source of the first pull-down transistor M8A is electrically connected to the first node PU, and the drain of the first pull-down transistor M8A is electrically connected to the second low-voltage line LVGL;

[0303] The gate of the third pull-down transistor M8B is electrically connected to the second second node PD2, the source of the third pull-down transistor M8B is electrically connected to the first node PU, and the drain of the third pull-down transistor M8B is electrically connected to the second low-voltage line LVGL;

[0304] The frame reset circuit comprises a frame reset transistor M15;

[0305] The gate of the frame reset transistor M15 is electrically connected to the frame reset line STV0, the source of the frame reset transistor M15 is electrically connected to the first node PU, and the drain of the frame reset transistor M15 is electrically connected to the second low-voltage line LVGL.

[0306] The display substrate disclosed in the embodiments of the present disclosure comprises a substrate and the above-mentioned drive circuit arranged on the substrate.

[0307] The display substrate disclosed in at least one embodiment of the present disclosure further comprises an electrostatic protection circuit arranged on the substrate;

[0308] The first end of the electrostatic protection circuit is electrically connected to the drive signal line, the second end of the electrostatic protection circuit is electrically connected to the common electrode voltage terminal through a short circuit line, and the electrostatic protection circuit is used for electrostatic protection;

[0309] The driving signal lines include a direct current voltage line, a clock signal line, a control voltage line, and a frame reset line.

[0310] In at least one embodiment of the present disclosure, the driving signal line is a metal line running through the entire display panel and is located at the edge of the display panel. When there is static electricity in the external environment, the driving signal line is easily burned by high voltage. Therefore, an electrostatic protection circuit is arranged between the signal line and the shorting bar to disperse the instantaneous voltage and prevent the driving signal line from being burned.

[0311] At least one embodiment of the present disclosure provides a specific structure of an electrostatic protection circuit. A mixed TFT (Thin Film Transistor) arrangement is adopted to reduce the current between signals and crosstalk while ensuring the electrostatic discharge performance. In addition, the size of the TFT is small, so the layout space is small.

[0312] Optionally, the electrostatic protection circuit includes a first protection transistor, a second protection transistor, and a third protection transistor.

[0313] The gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected to the driving signal line, and the second electrode of the first protection transistor is electrically connected to the gate of the second protection transistor.

[0314] The first electrode of the second protection transistor is electrically connected to the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected to the gate of the third protection transistor.

[0315] The gate of the third protection transistor and the first electrode of the third protection transistor are both electrically connected to the shorting bar, and the second electrode of the third protection transistor is electrically connected to the gate of the second protection transistor.

[0316] The channel width-length ratio of the first protection transistor is greater than the channel width-length ratio of the second protection transistor, and the channel width-length ratio of the third protection transistor is greater than the channel width-length ratio of the second protection transistor.

[0317] For example, the channel width-length ratio of the first protection transistor and the channel width-length ratio of the third protection transistor can be 3.5 / 8, and the channel width-length ratio of the second protection transistor can be 3.5 / 50, but not limited thereto.

[0318] In a specific implementation, the channel width-length ratio of the first protection transistor and the channel width-length ratio of the third protection transistor can be greater than or equal to 3.5 / 12 and less than or equal to 3.5 / 6, and the channel width-length ratio of the second protection transistor can be greater than or equal to 3.5 / 80 and less than or equal to 3.5 / 30, but not limited thereto.

[0319] Optionally, the electrostatic protection circuit comprises a first protection transistor, a second protection transistor, a third protection transistor, a fourth protection transistor and a fifth protection transistor;

[0320] The gate of the first protection transistor and the first pole of the first protection transistor are both electrically connected with the driving signal line, and the second pole of the first protection transistor is electrically connected with the gate of the second protection transistor.

[0321] The first pole of the second protection transistor is electrically connected with the gate of the first protection transistor, and the second pole of the second protection transistor is electrically connected with the gate of the third protection transistor.

[0322] The first pole of the third protection transistor is electrically connected with the gate of the second protection transistor, and the second pole of the third protection transistor is electrically connected with the gate of the fourth protection transistor.

[0323] The first pole of the fourth protection transistor is electrically connected with the gate of the third protection transistor, and the second pole of the fourth protection transistor is electrically connected with the gate of the fifth protection transistor.

[0324] The gate of the fifth protection transistor and the first pole of the fifth protection transistor are both electrically connected with the short circuit line, and the second pole of the fifth protection transistor is electrically connected with the gate of the fourth protection transistor.

[0325] The channel width-length ratio of the first protection transistor is greater than the channel width-length ratio of the second protection transistor, and the channel width-length ratio of the first protection transistor is greater than the channel width-length ratio of the fourth protection transistor.

[0326] The channel width-length ratio of the third protection transistor is greater than the channel width-length ratio of the second protection transistor, and the channel width-length ratio of the third protection transistor is greater than the channel width-length ratio of the fourth protection transistor.

[0327] The channel width-length ratio of the fifth protection transistor is greater than the channel width-length ratio of the second protection transistor, and the channel width-length ratio of the fifth protection transistor is greater than the channel width-length ratio of the fourth protection transistor.

[0328] For example, the channel width-length ratio of the first protection transistor, the channel width-length ratio of the third protection transistor and the channel width-length ratio of the fifth protection transistor can be 3.5 / 8, and the channel width-length ratio of the second protection transistor and the channel width-length ratio of the fourth protection transistor can be 3.5 / 50, but are not limited thereto.

[0329] In specific implementation, the channel width-length ratio of the first protection transistor, the channel width-length ratio of the third protection transistor, and the channel width-length ratio of the fifth protection transistor can be greater than or equal to 3.5 / 12 and less than or equal to 3.5 / 6, and the channel width-length ratio of the second protection transistor and the channel width-length ratio of the fourth protection transistor can be greater than or equal to 3.5 / 80 and less than or equal to 3.5 / 30, but the present application is not limited thereto.

[0330] As shown in FIG. 1, at least one embodiment of the electrostatic protection circuit can include a first protection transistor T1, a second protection transistor T2, a third protection transistor T3, a fourth protection transistor T4, and a fifth protection transistor T5. Figure 18 The gate of the first protection transistor T1 and the source of the first protection transistor T1 are electrically connected to a driving signal line QX, and the drain of the first protection transistor T1 is electrically connected to the gate of the second protection transistor T2.

[0331] The source of the second protection transistor T2 is electrically connected to the gate of the first protection transistor T1, and the drain of the second protection transistor T2 is electrically connected to the gate of the third protection transistor T3.

[0332] The source of the third protection transistor T3 is electrically connected to the gate of the second protection transistor T2, and the drain of the third protection transistor T3 is electrically connected to the gate of the fourth protection transistor T4.

[0333] The source of the fourth protection transistor T4 is electrically connected to the gate of the third protection transistor T3, and the drain of the fourth protection transistor T4 is electrically connected to the gate of the fifth protection transistor T5.

[0334] The gate of the fifth protection transistor T5 and the source of the fifth protection transistor T5 are electrically connected to a short circuit line SR, and the drain of the fifth protection transistor T5 is electrically connected to the gate of the fourth protection transistor T4. The gate of the fifth protection transistor T5 is electrically connected to a common electrode voltage terminal CM.

[0335] The channel width-length ratio of the first protection transistor T1 is greater than the channel width-length ratio of the second protection transistor T2, and the channel width-length ratio of the first protection transistor T1 is greater than the channel width-length ratio of the fourth protection transistor T4.

[0336] The channel width-length ratio of the third protection transistor T3 is greater than the channel width-length ratio of the second protection transistor T2, and the channel width-length ratio of the third protection transistor T3 is greater than the channel width-length ratio of the fourth protection transistor T4.

[0337] The channel width-length ratio of the third protection transistor T3 is greater than the channel width-length ratio of the second protection transistor T2, and the channel width-length ratio of the third protection transistor T3 is greater than the channel width-length ratio of the fourth protection transistor T4.

[0338] The channel width-to-length ratio of the fifth protection transistor T5 is greater than that of the second protection transistor T2, and the channel width-to-length ratio of the fifth protection transistor T5 is greater than that of the fourth protection transistor T4.

[0339] exist Figure 19 In at least one of the embodiments shown, the channel width-to-length ratio of the first protection transistor, the channel width-to-length ratio of the third protection transistor, and the channel width-to-length ratio of the fifth protection transistor can be greater than or equal to 3.5 / 12 and less than or equal to 3.5 / 6, and the channel width-to-length ratio of the second protection transistor and the channel width-to-length ratio of the fourth protection transistor can be greater than or equal to 3.5 / 80 and less than or equal to 3.5 / 30.

[0340] Figure 19 This is a layout diagram of at least one embodiment of an electrostatic discharge protection circuit.

[0341] exist Figure 19 In the diagram, CLKA is the first clock signal line, CLKB is the second clock signal line, CLKC is the third clock signal line, and CLKD is the fourth clock signal line; STV is the start voltage line, VDDO is the first control voltage line, VDDE is the second control voltage line, STV0 is the frame reset line, LVGL is the second low voltage line, and VGL is the first low voltage line.

[0342] The routes marked SR are the shortest routes;

[0343] The circuit labeled E1 is the first electrostatic discharge (ESD) protection circuit, E2 is the second ESD protection circuit, E3 is the third ESD protection circuit, E4 is the fourth ESD protection circuit, E5 is the fifth ESD protection circuit, E6 is the sixth ESD protection circuit, E7 is the seventh ESD protection circuit, E8 is the eighth ESD protection circuit, E9 is the ninth ESD protection circuit, and E10 is the tenth ESD protection circuit.

[0344] exist Figure 19 In the diagram, T1 is the first protection transistor in E5, T2 is the second protection transistor in E5, T3 is the third protection transistor in E5, T4 is the fourth protection transistor in E5, and T5 is the fifth protection transistor in E5.

[0345] like Figure 19 As shown, M2 and M4 are arranged side by side along the horizontal direction, and M1, M3 and M5 are arranged side by side along the horizontal direction.

[0346] exist Figure 20In the figure, the label CM is a common electrode voltage terminal.

[0347] As shown in Figure 21 at least one embodiment of the electrostatic protection circuit can include a first protection transistor T1 and a second protection transistor T2;

[0348] The gate of T1 and the source of T1 are electrically connected to the driving signal line QX, and the drain of T1 is electrically connected to the gate of T2;

[0349] The source of T2 is electrically connected to the gate of T1, and the gate of T1 is electrically connected to the common electrode voltage terminal CM.

[0350] The channel width-length ratio of T1 and the channel width-length ratio of T2 can be 3.5 / 180.

[0351] Figure 21 is a layout diagram of at least one embodiment of the electrostatic protection circuit.

[0352] In Figure 21 , the label CLKA is a first clock signal line, the label CLKB is a second clock signal line, the label CLKC is a third clock signal line, and the label CLKD is a fourth clock signal line; the label STV is a start voltage line, the label VDDO is a first control voltage line, the label VDDE is a second control voltage line, the label STV0 is a frame reset line, the label LVGL is a second low voltage line, and the label VGL is a first low voltage line;

[0353] The label SR is a short circuit line;

[0354] The label E1 is a first electrostatic protection circuit, the label E2 is a second electrostatic protection circuit, the label E3 is a third electrostatic protection circuit, the label E4 is a fourth electrostatic protection circuit, the label E5 is a fifth electrostatic protection circuit, the label E6 is a sixth electrostatic protection circuit, the label E7 is a seventh electrostatic protection circuit, the label E8 is an eighth electrostatic protection circuit, the label E9 is a ninth electrostatic protection circuit, and the label E10 is a tenth electrostatic protection circuit.

[0355] In Figure 21 , the label T1 is a first protection transistor in E5, and the label T2 is a second protection transistor in E5;

[0356] In ​ , the label CM is a common electrode voltage terminal.

[0357] The display device described in the embodiments of the present disclosure includes the display substrate described above.

[0358] The above are preferred embodiments of the present disclosure, and it should be pointed out that, for those skilled in the art, several improvements and refinements can be made without departing from the principles of the present disclosure, and these improvements and refinements should also be considered as the protection scope of the present disclosure.

Claims

1. A driving circuit comprising an input circuit, a reset circuit, a first node reset circuit and a control node control circuit; the input circuit is electrically connected with an input control terminal, an input terminal and a first node respectively, and is configured to control the input terminal to be in communication or disconnection with the first node under the control of an input control signal provided by the input control terminal; the reset circuit is electrically connected with a reset terminal, the first node and a first voltage line respectively, and is configured to control the first node to be in communication or disconnection with the first voltage line under the control of a reset signal provided by the reset terminal; the first node reset circuit is electrically connected with a second node, the first node and the first voltage line respectively, and is configured to control the first node to be in communication or disconnection with the first voltage line under the control of an electric potential of the second node; the control node control circuit is electrically connected with the first node, a third voltage line and a control node respectively, and is configured to control the control node to be in communication or disconnection with the third voltage line under the control of an electric potential of the first node; transistors included in the input circuit, transistors included in the reset circuit and transistors included in the first node reset circuit are arranged in sequence along a direction away from a display area; a ratio of a channel width-length ratio of a transistor included in the first node reset circuit and having a gate electrically connected with the second node to a channel width-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

2. The drive circuit of claim 1, wherein, a frame reset circuit is further included; the frame reset circuit is electrically connected with a frame reset line, the first node and a second voltage line respectively, and is configured to control the first node to be in communication or disconnection with the second voltage line under the control of a frame reset signal provided by the frame reset line; a transistor included in the frame reset circuit is arranged on a side of the transistor included in the first node reset circuit and away from the display area.

3. The drive circuit of claim 1, wherein, the input circuit includes at least two input transistors connected in series with each other, and the reset circuit includes at least two reset transistors connected in series with each other.

4. The drive circuit of claim 1, wherein, the first node reset circuit includes at least two transistors connected in series with each other and having gates electrically connected with the second node; or the second node includes a first second node and a second second node, and the first node reset circuit includes at least two transistors connected in series with each other and having gates electrically connected with the first second node, and at least two transistors connected in series with each other and having gates electrically connected with the second second node.

5. The drive circuit of claim 2, wherein, the frame reset circuit includes at least two frame reset transistors connected in series with each other.

6. The drive circuit of claim 1, wherein, a transistor included in the control node control circuit is arranged on a side of a transistor included in the input circuit and close to the display area.

7. The drive circuit of claim 1, wherein, the control node control circuit includes a control transistor; a gate of the control transistor is electrically connected with the first node, a first pole of the control transistor is electrically connected with the third voltage line, and a second pole of the control transistor is electrically connected with the control node.

8. The drive circuit according to any one of claims 1 to 7, wherein, a shutdown reset circuit is further included; The shutdown reset circuit is electrically connected with a fourth voltage line and a driving signal output terminal respectively, and is used for controlling the communication or disconnection between the driving signal output terminal and the fourth voltage line under the control of a fourth voltage signal provided by the fourth voltage line.

9. The drive circuit of claim 8, wherein, The transistor included in the shutdown reset circuit is arranged on one side of the transistor included in the input circuit close to the display area.

10. The drive circuit of claim 8, wherein, The shutdown reset circuit includes a shutdown reset transistor. The gate of the shutdown reset transistor and the first pole of the shutdown reset transistor are electrically connected with the fourth voltage line, and the second pole of the shutdown reset transistor is electrically connected with the driving signal output terminal.

11. The drive circuit of any one of claims 1 to 7, wherein, The input circuit includes a first input transistor and a second input transistor. The gate of the first input transistor is electrically connected with the input control terminal, the first pole of the first input transistor is electrically connected with the input terminal, and the second pole of the first input transistor is electrically connected with a control node. The gate of the second input transistor is electrically connected with the input control terminal, the first pole of the second input transistor is electrically connected with the control node, and the second pole of the second input transistor is electrically connected with the first node.

12. The drive circuit of claim 11, wherein, The input control terminal is a carry signal output terminal of an adjacent upper-level driving circuit, and the input terminal is a driving signal output terminal of the adjacent upper-level driving circuit. Alternatively, The input control terminal and the input terminal are both carry signal output terminals of the adjacent upper-level driving circuit.

13. The drive circuit of any one of claims 1 to 7, wherein, The reset circuit includes a first reset transistor and a second reset transistor. The gate of the first reset transistor is electrically connected with the reset terminal, the first pole of the first reset transistor is electrically connected with the first node, and the second pole of the first reset transistor is electrically connected with the control node. The gate of the second reset transistor is electrically connected with the reset terminal, the first pole of the second reset transistor is electrically connected with the control node, and the second pole of the second reset transistor is electrically connected with the first voltage line.

14. The drive circuit of claim 13, wherein, The channel width-length ratio of the transistor included in the control node control circuit is less than the channel width-length ratio of the second reset transistor.

15. The drive circuit of any one of claims 1 to 7, wherein, The first node reset circuit includes a first pull-down transistor and a second pull-down transistor. The gate of the first pull-down transistor is electrically connected with the second node, the first pole of the first pull-down transistor is electrically connected with the first node, and the second pole of the first pull-down transistor is electrically connected with the control node. The gate of the second pull-down transistor is electrically connected with the second node, the first pole of the second pull-down transistor is electrically connected with the control node, and the second pole of the second pull-down transistor is electrically connected with the first voltage line.

16. The drive circuit of claim 15, wherein, The ratio of the channel width-length ratio of the second pull-down transistor to the channel width-length ratio of the transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

17. The drive circuit of claim 15, wherein, The channel width-length ratio of the second pull-down transistor is greater than the channel width-length ratio of the first pull-down transistor.

18. The drive circuit of any one of claims 1 to 7, wherein, The second node includes a first second node and a second second node. The first node reset circuit includes a first pull-down transistor, a second pull-down transistor, a third pull-down transistor and a fourth pull-down transistor. A gate of the first pull-down transistor is electrically connected with the first second node, a first pole of the first pull-down transistor is electrically connected with the first node, and a second pole of the first pull-down transistor is electrically connected with the control node; A gate of the second pull-down transistor is electrically connected with the first second node, a first pole of the second pull-down transistor is electrically connected with the control node, and a second pole of the second pull-down transistor is electrically connected with the first voltage line; A gate of the third pull-down transistor is electrically connected with the second second node, a first pole of the third pull-down transistor is electrically connected with the first node, and a second pole of the third pull-down transistor is electrically connected with the control node; A gate of the fourth pull-down transistor is electrically connected with the second second node, a first pole of the fourth pull-down transistor is electrically connected with the control node, and a second pole of the fourth pull-down transistor is electrically connected with the first voltage line.

19. The drive circuit of claim 18, wherein, The channel width-length ratio of the second pull-down transistor is greater than the channel width-length ratio of the first pull-down transistor, and the channel width-length ratio of the fourth pull-down transistor is greater than the channel width-length ratio of the third pull-down transistor.

20. The driving circuit of claim 18, wherein, The ratio of the channel width-length ratio of the second pull-down transistor to the channel width-length ratio of the transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24; The ratio of the channel width-length ratio of the fourth pull-down transistor to the channel width-length ratio of the transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

21. The drive circuit of claim 2, wherein, The frame reset circuit includes a first frame reset transistor and a second frame reset transistor; A gate of the first frame reset transistor is electrically connected with the frame reset line, a first pole of the first frame reset transistor is electrically connected with the first node, and a second pole of the first frame reset transistor is electrically connected with the control node; A gate of the second frame reset transistor is electrically connected with the frame reset line, a first pole of the second frame reset transistor is electrically connected with the control node, and a second pole of the second frame reset transistor is electrically connected with the second voltage line.

22. The drive circuit of any one of claims 1 to 7, wherein, Further comprising a carry signal output circuit, a driving signal output circuit and an energy storage circuit; The carry signal output circuit is electrically connected with the first node, the second node, a carry signal output end, a clock signal end and the second voltage line respectively, and is configured to control the carry signal output end to be in communication or disconnected with the clock signal end under the control of the potential of the first node, and control the carry signal output end to be in communication or disconnected with the second voltage line under the control of the potential of the second node; The driving signal output circuit is electrically connected with the first node, the second node, a driving signal output end, the clock signal end and the fourth voltage line respectively, and is configured to control the driving signal output end to be in communication or disconnected with the clock signal end under the control of the potential of the first node, and control the driving signal output end to be in communication or disconnected with the fourth voltage line under the control of the potential of the second node; The energy storage circuit is electrically connected with the first node and the driving signal output end respectively, and is configured to store energy.

23. The drive circuit of claim 22, wherein, The fourth voltage line is configured to provide a fourth voltage signal, and the second voltage line is configured to provide a second voltage signal. The fourth voltage signal has a voltage value equal to that of the second voltage signal, or the voltage value of the second voltage signal is less than that of the fourth voltage signal.

24. The drive circuit of any one of claims 1 to 7, wherein, The second node control circuit is further configured to control the second node to be connected or disconnected with the second voltage line under the control of an input control signal provided by the input control terminal and to control the potential of the second node under the control of the potential of the first node. The second node control circuit is further configured to control the second node to be connected or disconnected with the second voltage line under the control of an input control signal provided by the input control terminal and to control the potential of the second node under the control of the potential of the first node.

25. A display substrate, comprising a substrate and a driving circuit according to any one of claims 1 to 24 disposed on the substrate.

26. The display substrate of claim 25, wherein, The electrostatic protection circuit is further configured to perform electrostatic protection. The driving signal line comprises a direct current voltage line, a clock signal line, a control voltage line and a frame reset line. The electrostatic protection circuit comprises a first protection transistor, a second protection transistor and a third protection transistor.

27. The display substrate of claim 26, wherein, The gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected with the driving signal line, and the second electrode of the first protection transistor is electrically connected with the gate of the second protection transistor. The first electrode of the second protection transistor is electrically connected with the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected with the gate of the third protection transistor. The gate of the third protection transistor and the first electrode of the third protection transistor are both electrically connected with the short circuit line, and the second electrode of the third protection transistor is electrically connected with the gate of the second protection transistor. The channel width-length ratio of the first protection transistor is greater than that of the second protection transistor, and the channel width-length ratio of the third protection transistor is greater than that of the second protection transistor. The electrostatic protection circuit comprises a first protection transistor, a second protection transistor, a third protection transistor, a fourth protection transistor and a fifth protection transistor.

28. The display substrate of claim 26, wherein, The gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected with the driving signal line, and the second electrode of the first protection transistor is electrically connected with the gate of the second protection transistor. The first electrode of the second protection transistor is electrically connected with the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected with the gate of the third protection transistor. The first electrode of the third protection transistor is electrically connected with the gate of the second protection transistor, and the second electrode of the third protection transistor is electrically connected with the gate of the fourth protection transistor. The first electrode of the fourth protection transistor is electrically connected with the gate of the third protection transistor, and the second electrode of the fourth protection transistor is electrically connected with the gate of the fifth protection transistor. ​ The gate of the fifth protection transistor and the first pole of the fifth protection transistor are electrically connected with the short circuit line, and the second pole of the fifth protection transistor is electrically connected with the gate of the fourth protection transistor; The channel width-length ratio of the first protection transistor is greater than the channel width-length ratio of the second protection transistor, and the channel width-length ratio of the first protection transistor is greater than the channel width-length ratio of the fourth protection transistor; The channel width-length ratio of the third protection transistor is greater than the channel width-length ratio of the second protection transistor, and the channel width-length ratio of the third protection transistor is greater than the channel width-length ratio of the fourth protection transistor; The channel width-length ratio of the fifth protection transistor is greater than the channel width-length ratio of the second protection transistor, and the channel width-length ratio of the fifth protection transistor is greater than the channel width-length ratio of the fourth protection transistor.

29. A display device comprising the display substrate according to any one of claims 25 to 28.

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