Method for manufacturing a nesting mother plate and the nesting mother plate

Abstract

This application belongs to the field of microfluidics technology, specifically relating to a method for fabricating a die-cutting motherboard and the die-cutting motherboard itself. The fabrication method includes providing a substrate; forming a first transistor, a first metal block, a second metal block, and a second transistor on the substrate; forming a first passivation layer, which has a first via and a second via; forming a protective layer and patterning it to obtain a first connecting block and a second connecting block; forming a semiconductor layer disposed on the first connecting block; forming a first pixel electrode, wherein the first pixel electrode in the display pixel area is connected to a first source electrode through the first connecting block, the first pixel electrode in the driving area is connected to a second source electrode through the second connecting block, and the first pixel electrode in the detection area corresponds to the second metal block; forming a second passivation layer, the second passivation layer exposing the first pixel electrode in the driving area; and forming a second pixel electrode, the second pixel electrode being connected to the first pixel electrode in the driving area. This application reduces manufacturing costs and improves the utilization rate of the motherboard.

Description

Technical Field

[0001] This application belongs to the field of microfluidics technology, specifically relating to a method for manufacturing a die-cutting master plate and the die-cutting master plate itself. Background Technology

[0002] Microfluidic technology is characterized by the manipulation of fluids at the micrometer scale. It integrates multiple steps in biological, chemical, and medical analysis processes onto a single micrometer-scale chip, automating the entire analytical process. Due to the powerful integration capabilities of microfluidic chips, they offer advantages such as high analysis speed, low loss, low material consumption, and minimal pollution during sample processing, demonstrating immense promise in numerous fields including biomedical research, drug synthesis and screening, environmental monitoring and protection, health quarantine, forensic identification, and the detection of biological reagents.

[0003] Microfluidic chips can automatically prepare and manipulate samples in droplet form, primarily utilizing the dielectric wetting effect to drive droplet movement. However, current microfluidic chips are still fabricated on a single substrate, resulting in low fabrication efficiency and the inability to fabricate them alongside the main product, thus increasing the cost of microfluidic chips. Summary of the Invention

[0004] The purpose of this application is to solve the technical problems in the prior art, such as the fact that microfluidic chips are still made on a single substrate, resulting in low manufacturing efficiency and the inability to be manufactured together with the main product, which increases the cost of microfluidic chips.

[0005] This application provides a method for manufacturing a die-cutting motherboard, comprising: providing a substrate, the substrate having at least a display area and a microfluidic area, the display area including a display pixel area, and the microfluidic area including a detection area and a driving area interconnected therewith; forming a first transistor in the display pixel area, sequentially forming a first metal block and a second metal block in the detection area, and forming a second transistor in the driving area, the first metal block being disposed on the side of the second metal block near the substrate; forming a first passivation layer on the substrate for covering the first transistor, the second metal block, and the second transistor, and providing a first via and a second via on the first passivation layer, the first via exposing a portion of the first source electrode in the first transistor, and the second via exposing a portion of the second source electrode in the second transistor; forming a protective layer on the first passivation layer, and patterning the protective layer to form a first connecting block in the display pixel area and a second connecting block in the driving area, the first connecting block being connected to the first source electrode through the first via, and the second connecting block being connected to the first source electrode through the first via. The second source electrode is connected through the second via; a semiconductor layer is formed on the display pixel area, and the semiconductor layer is connected to the first connecting block in the display pixel area; a first pixel electrode is formed on the display pixel area, the detection area, and the driving area, the first pixel electrode in the display pixel area is disposed on the side of the semiconductor layer away from the substrate and is connected to the semiconductor layer, the first pixel electrode in the detection area is electrically connected to the first pixel electrode in the driving area, and the first pixel electrode in the detection area is disposed on the side of the first passivation layer away from the substrate, the first pixel electrode in the driving area is connected to the first connecting block in the driving area; a second passivation layer is formed on the first passivation layer, and in the display pixel area, the second passivation layer covers the first pixel electrode and the semiconductor layer; in the detection area, the second passivation layer covers the first pixel electrode; in the driving area, the second passivation layer exposes the first pixel electrode; a second pixel electrode is formed in the detection area and the driving area, and the second pixel electrode is connected to the first pixel electrode located in the driving area.

[0006] In an exemplary embodiment of this application, the second transistor includes a second gate, a second active layer, and a second source and a second drain respectively connected to both ends of the second active layer. The second gate is disposed on the side of the second active layer near the substrate, and a gate insulating layer is provided between the second gate and the second active layer. When a protective layer is formed on the first passivation layer and the protective layer is patterned, the fabrication method further includes: forming a protective block in the driving region. The protective block is disposed on the side of the first passivation layer away from the substrate, and the orthographic projection of the protective block on the substrate overlaps with the orthographic projections of the second source and the second drain on the substrate.

[0007] In one exemplary embodiment of this application, the material of the protective layer includes one or more of metals and metal oxides.

[0008] In one exemplary embodiment of this application, before forming the second pixel electrode, the fabrication method further includes: forming a planarization layer on the second passivation layer, the planarization layer covering the second passivation layer, and forming a third via on the planarization layer for exposing the first pixel electrode located in the driving region, the second pixel electrode being electrically connected to the first pixel electrode through the third via.

[0009] In an exemplary embodiment of this application, the substrate is provided with a plurality of display areas and a plurality of microfluidic areas; after forming a planarization layer on the second passivation layer, the fabrication method further includes: forming a fourth via and a fifth via on the second passivation layer and the planarization layer respectively in the display pixel area, the fourth via and the fifth via corresponding to and communicating with each other, the fourth via and the fifth via being used to expose a portion of the first pixel electrode; forming a third metal layer on the planarization layer and patterning the third metal layer, forming a third metal block in the display pixel area of ​​at least a portion of the display area, the third metal block being connected to the first pixel electrode located in the display pixel area through the fourth via and the fifth via, forming a fourth metal block in the detection area of ​​at least a portion of the microfluidic area, the second pixel electrode covering the fourth metal block.

[0010] In an exemplary embodiment of this application, the first transistor includes a first gate, a first active layer, and a first source and a first drain respectively connected to both ends of the first active layer. The first gate is disposed on the side of the first active layer near the substrate, and a gate insulating layer is provided between the first gate and the first active layer. When a third metal layer is formed on the planarization layer and the third metal layer is patterned, the manufacturing method further includes: forming a fifth metal block in the display pixel area where the third metal block is formed, the fifth metal block being arranged at intervals from the third metal block, and the orthographic projection of the fifth metal block on the substrate having an overlapping area with the orthographic projections of the first source and the first drain on the substrate.

[0011] In one exemplary embodiment of this application, in the detection area, the orthographic projection of the second pixel electrode on the substrate and the orthographic projection of the second metal block on the substrate have an overlapping area.

[0012] In one exemplary embodiment of this application, in the detection area, the orthographic projection of the first pixel electrode on the substrate and the orthographic projection of the second metal block on the substrate have an overlapping area, and the voltage of the first pixel electrode and the second pixel electrode are the same.

[0013] In one exemplary embodiment of this application, the fabrication method further includes: forming a third passivation layer and a hydrophobic layer on the planarization layer, wherein the third passivation layer is disposed on the side of the hydrophobic layer close to the substrate, and the third passivation layer covers the second pixel electrode.

[0014] A second aspect of this application provides a die-cutting motherboard, including a die-cutting display substrate and a die-cutting microfluidic substrate manufactured using the manufacturing method described in any of the preceding claims.

[0015] The method for manufacturing the die-cutting mother plate and the die-cutting mother plate described in this application have the following beneficial effects:

[0016] The microfluidic substrate in this application is compatible with the number of film layers and photomask process of the microfluidic display substrate, enabling the fabrication of both the microfluidic display substrate and the microfluidic substrate on the same substrate. This allows for the microfluidic chip and the display substrate (main product) to be interlocked, reducing the manufacturing cost of both the microfluidic display substrate and the microfluidic substrate while also increasing the utilization rate of the motherboard.

[0017] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0020] Figure 1 A schematic diagram of the process for manufacturing the motherboard is shown.

[0021] Figure 2 A schematic diagram of the process for fabricating a first transistor, a first metal block, a second metal block, and a second transistor is shown.

[0022] Figure 3 A schematic diagram of a structure with multiple overlay display substrates and multiple overlay microfluidic substrates on a substrate is shown.

[0023] Figure 4 A schematic diagram of the cross-sectional structure of the display area and the microfluidic area is shown.

[0024] Figure 5 A schematic diagram of the cross-sectional structure of a microfluidic substrate is shown.

[0025] Figure 6 A schematic diagram of the cross-sectional structure of a cut display substrate is shown.

[0026] Figure 7 A cross-sectional schematic diagram of a first gate, a first metal block, and a first bonding metal layer formed on a substrate is shown.

[0027] Figure 8 A schematic diagram of a cross-sectional structure in which a gate insulating layer is formed on a substrate is shown.

[0028] Figure 9 A schematic cross-sectional structure diagram showing the formation of a first active layer and a second active layer on a gate insulating layer is shown.

[0029] Figure 10 A schematic cross-sectional structure showing a first source, a first drain, a second source, and a second drain formed on a gate insulating layer is shown.

[0030] Figure 11 A schematic cross-sectional view of a first passivation layer disposed on a gate insulating layer is shown.

[0031] Figure 12 A cross-sectional structural diagram showing the formation of a first connecting block, a second connecting block, and a protective block on a substrate is shown.

[0032] Figure 13A schematic diagram of a cross-sectional structure showing a semiconductor layer formed on a substrate is shown.

[0033] Figure 14 A schematic diagram of the cross-sectional structure of the first pixel electrode formed on the substrate is shown.

[0034] Figure 15 A schematic diagram of the cross-sectional structure of the second passivation layer formed on the substrate is shown.

[0035] Figure 16 A schematic diagram of the cross-sectional structure of a flat layer formed on a substrate is shown.

[0036] Figure 17 A schematic diagram of the cross-sectional structure of the third, fourth and fifth metal blocks formed on the substrate is shown.

[0037] Figure 18 A schematic diagram of the cross-sectional structure of the second pixel electrode formed on the substrate is shown.

[0038] Explanation of reference numerals in the attached figures:

[0039] 100. Cutting the motherboard; 100a. Cutting the display substrate; 100b. Cutting the microfluidic substrate;

[0040] 110, Substrate; 120, Display area; 120a, Display pixel area; 120b, First binding area; 130, Microfluidic area; 130a, Detection area; 130b, Driving area; 130c, Second binding area;

[0041] 140, First transistor; 141, First gate; 142, First active layer; 143, First source; 144, First drain; 150, First metal block; 160, Second metal block; 170, Second transistor; 171, Second gate; 172, Second active layer; 173, Second source; 174, Second drain; 180, First bonding metal layer; 190, Gate insulating layer; 191, First via;

[0042] 1100, Second bonding metal layer; 1200, First passivation layer; 1210, First via; 1220, Second via; 1230, Second through-hole; 1310, First connector block; 1320, Second connector block; 1330, Protective block; 1400, Third bonding metal layer; 1500, Semiconductor layer; 1600, First pixel electrode; 1700, First bonding pixel electrode; 1800, Second passivation layer; 1810, Fourth via; 1900, Planarization layer; 1910, Fifth via;

[0043] 11110, Third metal block; 11120, Fourth metal block; 11130, Fifth metal block; 11200, Fourth bonding metal layer; 11300, Second pixel electrode; 11400, Second bonding pixel electrode; 11500, Third passivation layer; 11600, Hydrophobic layer. Detailed Implementation

[0044] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0045] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0046] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0047] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0048] Example 1

[0049] Figure 1 A schematic diagram of the manufacturing process of the master die provided in the embodiment of this application is shown. Figure 2 A schematic diagram of the process for fabricating a first transistor, a first metal block, a second metal block, and a second transistor, provided in an embodiment of this application, is shown.

[0050] See Figure 1 and Figure 2 As shown, Embodiment 1 of this application provides a method for manufacturing a cutting mother plate 100, which includes the following steps:

[0051] S100 provides a substrate 110.

[0052] The substrate 110 can be a rigid substrate made of glass, but is not limited to it. It can also be a flexible substrate made of materials such as polyimide (abbreviated as polyimide). In other words, the overlay display panel of this application is not limited to a rigid, inflexible panel, but can also be a flexible, bendable panel.

[0053] It should be noted that the substrate 110 may include at least a display area 120 and a microfluidic area 130. The display area 120 is used to fabricate a display substrate for a display device, and the microfluidic area 130 is used to fabricate a microfluidic substrate for a microfluidic chip.

[0054] Figure 3 A schematic diagram of a structure with multiple overlay display substrates and multiple overlay microfluidic substrates on a substrate is shown. Figure 4 A schematic diagram of the cross-sectional structure of the display area and the microfluidic area is shown. Figure 5 A schematic diagram of the cross-sectional structure of a microfluidic substrate is shown. Figure 6 A schematic diagram of the cross-sectional structure of a cut display substrate is shown.

[0055] In addition, see Figure 2 , Figure 5 and Figure 6 As shown, the substrate 110 may include multiple display areas 120 and multiple microfluidic areas 130, so as to simultaneously produce multiple overlay display substrates 100a and multiple overlay microfluidic substrates 100b, thereby increasing production quantity and reducing production costs.

[0056] In some embodiments of this application, the substrate 110 also includes a cutting alignment line (not shown in the figure) located between the display area 120 and the microfluidic area 130. A cutting tool is used to cut at the cutting alignment line to achieve overlay cutting, so as to form overlay-cut display substrate 100a and overlay-cut microfluidic substrate 100b respectively.

[0057] It should be noted that, see Figure 4 As shown, the display area 120 may include a display pixel area 120a and a first bonding area 120b. The first bonding area 120b is located on one side of the display pixel area 120a and connected to it. It is understood that this first bonding area 120b can be used to connect to a flexible circuit board for signal transmission.

[0058] Furthermore, the microfluidic region 130 may include a detection region 130a for detecting droplets, a driving region 130b for driving droplet movement, and a second bonding region 130c for electrical connection with the flexible circuit board. The detection region 130a is connected to the second bonding region 130c via the driving region 130b. The driving region 130b can drive the droplet to move along the movement path, and the detection region 130a can observe the position of the droplet. The second bonding region 130c is electrically connected to the flexible circuit board to transmit electrical signals to the driving region 130b and the detection region 130a, thereby enabling the driving and observation of the droplet.

[0059] S200, a first transistor 140 is formed in the display pixel area 120a, a first metal block 150 and a second metal block 160 are formed sequentially in the detection area 130a, and a second transistor 170 is formed in the driving area 130b.

[0060] It should be noted that, while forming the first transistor 140 in the display pixel area 120a, the first metal block 150 and the second metal block 160 in the detection area 130a and the second transistor 170 in the driving area 130b are formed together. This allows the first transistor 140, the first metal block 150, the second metal block 160 and the second transistor 170 to be fabricated simultaneously under the same process technology, thereby reducing production costs.

[0061] Among them, see Figure 2 As shown, the first transistor 140 includes a first gate 141, a first active layer 142, a first source 143, and a first drain 144; the second transistor 170 includes a second gate 171, a second active layer 172, a second source 173, and a second drain 174.

[0062] Figure 7 A cross-sectional schematic diagram of a first gate, a first metal block, and a first bonding metal layer formed on a substrate is shown. Figure 8 A schematic diagram of a cross-sectional structure in which a gate insulating layer is formed on a substrate is shown.

[0063] Figure 9 A schematic cross-sectional structure diagram showing the formation of a first active layer and a second active layer on a gate insulating layer is shown.

[0064] Figure 10 A schematic cross-sectional structure showing a first source, a first drain, a second source, and a second drain formed on a gate insulating layer is shown.

[0065] See Figures 7 to 10 As shown, the method for fabricating a first transistor 140 in the display pixel area 120a, a first metal block 150 and a second metal block 160 sequentially formed in the detection area 130a, and a second transistor 170 formed in the driving area 130b includes at least the following steps:

[0066] S210, a first metal layer is formed on the substrate 110 and the first metal layer is patterned to form a first gate 141 in the display pixel area 120a, a first metal block 150 in the detection area 130a, and a second gate 171 in the driving area 130b.

[0067] In other words, such as Figure 7 As shown, the first metal block 150, the first gate 141, and the second gate 171 are arranged on the same layer and spaced apart.

[0068] It should be noted that the first metal layer can be made of metallic materials, such as molybdenum, aluminum and titanium, to ensure good conductivity, but it is not limited to these and can also be made of other materials with good conductivity.

[0069] It is worth mentioning that, see Figure 7 As shown, after the first metal layer is patterned, a first bonding metal layer 180 is formed in both the first bonding region 120b and the second bonding region 130c, and the first bonding metal layer 180 is spaced apart from the first gate 141 and the second gate 171.

[0070] S220, a gate insulating layer 190 is formed on the substrate 110, the gate insulating layer 190 covering the first gate 141, the first metal block 150, and the second gate 171, as shown. Figure 8 As shown.

[0071] The gate insulating layer 190 is made of one or more of silicon oxide (SiOx) and silicon nitride (SiNx).

[0072] It should be noted that, see Figure 9 As shown, in the second bonding area 130c: the above-mentioned gate insulating layer 190 is formed in the second bonding area 130c, and after the gate insulating layer 190 is formed, a first through hole 191 is opened above the gate insulating layer 190. The first through hole 191 exposes a portion of the first bonding metal layer 180 so that the metal material in the subsequent second metal layer can be filled into the first through hole 191 and connected to the first bonding metal layer 180.

[0073] S230, a first inorganic silicon layer is formed on the gate insulating layer 190, and the first inorganic silicon layer is patterned to form a first active layer 142 in the display pixel area 120a and a second active layer 172 in the driving area 130b, as shown. Figure 9 As shown.

[0074] The orthographic projection of the first active layer 142 onto the substrate 110 covers the orthographic projection of the first gate 141 onto the substrate 110. The orthographic projection of the second active layer 172 onto the substrate 110 covers the orthographic projection of the second gate 171 onto the substrate 110.

[0075] Understandably, the material of the first inorganic silicon layer may include one or more of amorphous silicon and polycrystalline silicon.

[0076] S240, a second metal layer is formed on the gate insulating layer 190, and the second metal layer is patterned to form a first source 143 and a first drain 144 in the display pixel area 120a, a second metal block 160 in the detection area 130a, and a second source 173 and a second drain 174 in the driving area 130b, as shown. Figure 10 As shown.

[0077] In other words, the first source 143, the first drain 144, the second metal block 160, the second source 173, and the second drain 174 are arranged on the same layer and at intervals.

[0078] The first source 143 and the first drain 144 are respectively disposed at opposite ends of the first active layer 142 and are spaced apart from each other. The second source 173 and the second drain 174 are respectively disposed at opposite ends of the second active layer 172 and are spaced apart from each other. The second metal block 160 is disposed on the side of the gate insulating layer 190 away from the substrate 110, and the orthographic projection of the second metal block 160 on the substrate 110 overlaps with the orthographic projection of the first metal block 150 on the substrate 110.

[0079] In addition, such as Figure 10 As shown, when the second metal layer is formed on the gate insulating layer 190, a second bonding metal layer 1100 is formed at the second bonding region 130c, which is spaced apart from the second source 173 or the second drain 174. The metal material in the second bonding metal layer 1100 fills the first through hole 191, so that the second bonding metal layer 1100 is connected to the first bonding metal layer 180.

[0080] That is, through the above steps, a first transistor 140 is formed in the display pixel area 120a on the substrate 110, a first metal block 150 and a second metal block 160 are formed in the detection area 130a, and a second transistor 170 is formed in the driving area 130b.

[0081] Figure 11 A schematic cross-sectional view of a first passivation layer disposed on a gate insulating layer is shown.

[0082] S300, a first passivation layer 1200 is formed on the substrate 110, and a first via 1210 and a second via 1220 are provided on the first passivation layer 1200, such as Figure 11 As shown.

[0083] It should be noted that the first passivation layer 1200 can cover the first transistor 140, the second metal block 160, and the second transistor 170.

[0084] In addition, the first via 1210 is used to expose a portion of the first source 143 in the first transistor 140, and the second via 1220 is used to expose a portion of the second source 173 in the second transistor 170.

[0085] The first passivation layer 1200 is formed on the side of the gate insulating layer 190 away from the substrate 110, and the first passivation layer 1200 covers the first source 143, the first drain 144, the first active layer 142, the second active layer 172, the second source 173, the second drain 174, and the second metal block 160.

[0086] In some embodiments of this application, see Figure 11 As shown, a first passivation layer 1200 may also be formed in the second bonding area 130c. After the first passivation layer 1200 is formed, a second through hole 1230 is opened on the first passivation layer 1200 to expose a portion of the second bonding metal layer 1100 for connection with the third bonding metal layer 1400 described later.

[0087] Figure 12 A cross-sectional structural diagram of the first connecting block, the second connecting block, and the protective block is shown.

[0088] S400, a protective layer is formed on the first passivation layer 1200, and the protective layer is patterned to form a first connecting block 1310 in the display pixel area 120a and a second connecting block 1320 in the driving area 130b, as shown. Figure 12 As shown.

[0089] The first connecting block 1310 is connected to the first source 143 through the first via 1210, and the second connecting block 1320 is connected to the second source 173 through the second via 1220.

[0090] In some embodiments of this application, the material of the protective layer is filled into the first via 1210 and the second via 1220, such that a portion of the first connecting block 1310 overlaps with the first source 143 exposed at the first via 1210, and the second connecting block 1320 is connected to the second source 173 for signal transmission.

[0091] It should be noted that in the drive area 130b, the second connecting block 1320 completely fills the second via 1220.

[0092] The protective layer can be made of one or more metals and metal oxides, such as molybdenum, aluminum, titanium, indium tin oxide, etc.

[0093] For example, the protective layer is made of metal and is in a floating state. It does not receive signals, but it can transmit electrical signals.

[0094] It is worth mentioning that, in the patterning process of the protective layer, the manufacturing method also includes forming a protective block 1330 within the driving area 130b, such as... Figure 12 As shown. The protective block 1330 is disposed on the side of the first passivation layer 1200 away from the substrate 110, and the orthographic projection of the protective block 1330 on the substrate 110 overlaps with the orthographic projections of the second source 173 and the second drain 174 on the substrate 110.

[0095] In other words, the protection block 1330 can shield the channel region of the second transistor 170 so that the channel region of the second transistor 170 will not be affected by the plasma shock waves of subsequent processes such as deposition and dry etching, thereby improving the stability of the second transistor 170.

[0096] In addition, such as Figure 12 As shown, when the protective layer is patterned, a third bonding metal layer 1400 is also formed in the second bonding area 130c, which is spaced apart from the second connecting block 1320. The material of the third bonding metal layer 1400 is filled into the second through hole 1230 so that the third bonding metal layer 1400 is connected to the second bonding metal layer 1100.

[0097] Figure 13 A schematic diagram of the cross-sectional structure forming the semiconductor layer is shown.

[0098] S500, a semiconductor layer 1500 is formed within the display pixel area 120a, and the semiconductor layer 1500 is electrically connected to the first connecting block 1310 in the display pixel area 120a, such as... Figure 13 As shown.

[0099] The semiconductor layer 1500 is made of one or more of silicon oxide (SiOx) and silicon nitride (SiNx).

[0100] The semiconductor layer 1500 can convert the received light signals into electrical signals to enable display.

[0101] In other words, this display area 120 can be used as a substrate for an X-ray sensing screen or an X-ray detector, or as a substrate for other photoelectric sensing display devices.

[0102] Figure 14 A schematic diagram of the cross-sectional structure forming the first pixel electrode is shown.

[0103] S600, a first pixel electrode 1600 is formed on the display pixel area 120a, the detection area 130a, and the driving area 130b, such as Figure 14 As shown.

[0104] The first pixel electrode 1600 in the display pixel area 120a is disposed on the side of the semiconductor layer 1500 away from the substrate 110 and is electrically connected to the semiconductor layer 1500, so that the data signal on the first source 143 can be transmitted to the first pixel electrode 1600 through the first connection block 1310 and the semiconductor layer 1500.

[0105] The first pixel electrode 1600 in the detection area 130a is disposed on the side of the first passivation layer 1200 away from the substrate 110. The first pixel electrode 1600 in the detection area 130a is connected to the first pixel electrode 1600 in the driving area 130b to transmit the same electrical signal. The orthographic projection of the first pixel electrode 1600 in the detection area 130a on the substrate 110 overlaps with the orthographic projection of the second metal block 160 on the substrate 110, so as to form a storage capacitor between the first pixel electrode 160 and the second metal block 160.

[0106] The first pixel electrode 1600 in the driving region 130b is connected to the second connection block 1320 in the driving region 130b, so that the electrical signal on the second source 173 is transmitted to the first pixel electrode 1600 through the second connection block 1320.

[0107] The first pixel electrode 1600 and the first bonded pixel electrode 1700 described below can be made of transparent conductive materials, such as ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), etc.

[0108] In some embodiments of this application, the second binding region 130c is further provided with a first binding pixel electrode 1700 that is on the same layer as the first pixel electrode 1600 and spaced apart from it. The first binding pixel electrode 1700 is connected to the third binding metal layer 1400.

[0109] Figure 15 A schematic diagram of the cross-sectional structure for forming the second passivation layer is shown.

[0110] S700, a second passivation layer 1800 is formed on the first passivation layer 1200, such as Figure 15 As shown.

[0111] In the display pixel area 120a, the second passivation layer 1800 covers the first pixel electrode 1600 and the semiconductor layer 1500. In the detection area 130a, the second passivation layer 1800 covers the first pixel electrode 1600. In the driving area 130b, the first pixel electrode 1600 is exposed on the second passivation layer 1800, meaning that in the driving area 130b, the thickness of the second passivation layer 1800 at the location where the first pixel electrode 1600 is disposed is zero.

[0112] It should be noted that the second passivation layer 1800 can be made of the same material as the first passivation layer 1200, such as silicon oxide or silicon nitride.

[0113] In addition, a second passivation layer 1800 is also provided in the second bonding area 130c, and the second passivation layer 1800 exposes the first bonded pixel electrode 1700 in the second bonding area 130c, that is, the film thickness at the location where the first bonded pixel electrode 1700 is provided in the second passivation layer 1800 is zero.

[0114] Figure 16 A schematic diagram of the cross-sectional structure forming the flat layer is shown.

[0115] S800, a planarization layer 1900 is formed on the second passivation layer 1800, such as Figure 16 As shown.

[0116] In this process, the planarization layer 1900 in the display pixel area 120a and the detection area 130a covers the second passivation layer 1800. When the planarization layer 1900 is formed on the second passivation layer 1800, a third via is formed on the planarization layer 1900 in the driving area 130b to expose the first pixel electrode 1600 located in the driving area 130b.

[0117] It is worth mentioning that the planarization layer 1900 can be made of soluble polytetrafluoroethylene material.

[0118] In some embodiments of this application, the substrate 110 is provided with a plurality of display areas 120 and a plurality of microfluidic areas 130. An opaque material can be added to at least a portion of the microfluidic areas 130 to allow for more intuitive observation of the droplets. Furthermore, an opaque material can also be added to a portion of the display areas 120 to cover the channel region of the first transistor 140, preventing light from damaging the first transistor 140.

[0119] Figure 17 A schematic diagram of the cross-sectional structure forming the third, fourth, and fifth metal blocks is shown.

[0120] After the planarization layer 1900 is formed, the manufacturing method may also include:

[0121] S900, a third metal layer is prepared on the planarization layer 1900, and the third metal layer is patterned to form a third metal block 11110 in at least a portion of the display pixel area 120a of the display area 120, and a fourth metal block 11120 is formed in at least a portion of the detection area 130a of the microfluidic region 130, as shown. Figure 17 As shown.

[0122] It is understandable that forming an opaque fourth metal block 11120 in at least part of the detection area 130a of the microfluidic region 130 can provide an opaque background for more intuitive observation of the droplet's movement. Furthermore, the area without the fourth metal block 11120 remains transparent. By setting or not setting the fourth metal block 11120 in different microfluidic regions 130, different observation needs can be met, improving the adaptability of the microfluidic substrate 100b.

[0123] It is worth mentioning that in the display pixel area 120a with the third metal block 11110, a fourth via 1810 needs to be opened on the second passivation layer 1800 and a fifth via 1910 needs to be opened on the planarization layer 1900 to expose a portion of the first pixel electrode 1600 in the display pixel area 120a, so that the material in the third metal layer overlaps with the portion of the first pixel electrode 1600 in the display pixel area 120a, so that the third metal block 11110 is electrically connected to the first pixel electrode 1600 for signal transmission.

[0124] It should be understood that the fourth via 1810 can be formed simultaneously with the formation of the second passivation layer 1800, and the fifth via 1910 can be formed simultaneously with the formation of the planarization layer 1900. Alternatively, the fourth via 1810 and the fifth via 1910 can be formed after the formation of the second passivation layer 1800 and the planarization layer 1900, depending on the specific design of different embodiments.

[0125] In some embodiments of this application, when fabricating a third metal layer on the planarization layer 1900, the fabrication method further includes patterning the third metal layer:

[0126] like Figure 17 As shown, a fifth metal block 11130 is formed in the display pixel area 120a where the third metal block 11110 is formed.

[0127] The fifth metal block 11130 and the third metal block 11110 are arranged at intervals, and the orthographic projection of the fifth metal block 11130 on the substrate 110 overlaps with the orthographic projections of the first source 143 and the first drain 144 on the substrate 110, so that the fifth metal block 11130 can shield the channel region of the first transistor 140 and prevent light from damaging the first transistor 140.

[0128] Furthermore, during the preparation of the third metal layer, a fourth bonding metal layer 11200 is formed above the first bonding metal layer 180 in the first bonding region 120b.

[0129] Figure 18 A schematic diagram of the cross-sectional structure forming the second pixel electrode is shown.

[0130] S1000, a second pixel electrode 11300 is formed in the detection area 130a and the driving area 130b, and the second pixel electrode 11300 is electrically connected to the first pixel electrode 1600 located in the driving area 130b, such as Figure 18 As shown.

[0131] The second pixel electrode 11300 is disposed on the side of the planarization layer 1900 away from the substrate 110. The orthographic projection of the second pixel electrode 11300 on the substrate 110 in the detection area 130a overlaps with the orthographic projection of the second metal block 160 on the substrate 110, so as to ensure that a storage capacitor is formed between the second pixel electrode 11300 and the second metal block 160.

[0132] It should be noted that a connection hole (not shown in the figure) is provided on the planarization layer 1900. The material of the second pixel electrode 11300 is filled in this connection hole to connect the second pixel electrode 11300 with the first pixel electrode 1600. The second pixel electrode 11300 in the driving region 130b is connected to the second source electrode 173 through the first pixel electrode 1600 and the second connection block 1320, so that the first pixel electrode 1600 and the second pixel electrode 11300 in the driving region 130b can receive the same electrical signal. Since the first pixel electrode 1600 in the detection region 130a is connected to the first pixel electrode 1600 in the driving region 130b, and the second pixel electrode 11300 in the detection region 130a is also connected to the second pixel electrode 11300 in the driving region 130b, the electrical signals of the first pixel electrode 1600 and the second pixel electrode 11300 in the detection region 130a are the same, that is, the first pixel electrode 1600 and the second pixel electrode 11300 will not generate capacitance.

[0133] In other words, the storage capacitance of the entire microfluidic substrate can be increased by adding the first pixel electrode 1600.

[0134] Furthermore, the movement of the droplet can be controlled by supplying an electrical signal to the second pixel electrode 11300.

[0135] It is worth mentioning that, since a planarization layer 1900 is added between the second pixel electrode 11300 and the second source electrode 173 and the second drain electrode 174, the distance between the second pixel electrode 11300 and the second source electrode 173 / second drain electrode 174 in the driving region 130b is increased, which reduces the parasitic capacitance between the second pixel electrode 11300 and the second source electrode 173 / second drain electrode 174 in the driving region 130b and improves the stability of the output voltage of the second pixel electrode 11300.

[0136] In some embodiments of this application, such as Figure 18 As shown, when forming the second pixel electrode 11300, a second bonding pixel electrode 11400 can also be formed in both the first bonding region 120b and the second bonding region 130c. The second bonding pixel electrode 11400 in the first bonding region 120b is connected to the fourth bonding metal layer 11200, and the second bonding pixel electrode 11400 in the second bonding region 130c is connected to the first bonding pixel electrode 1700 and is spaced apart from the second pixel electrode 11300 in the driving region 130b.

[0137] The second pixel electrode 11300 and the second bonded pixel electrode 11400 can both be made of transparent conductive materials, such as ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), etc.

[0138] S1100, a third passivation layer 11500 and a hydrophobic layer 11600 are formed on the planarization layer 1900, such as Figure 4 As shown.

[0139] The third passivation layer 11500 is disposed on the side of the hydrophobic layer 11600 near the substrate 110. The third passivation layer 11500 covers the second pixel electrode 11300, the fifth metal block 11130 and the third metal block 11110. The third passivation layer 11500 can be made of the same material as the first passivation layer 1200 and the second passivation layer 1800, such as silicon oxide or silicon nitride.

[0140] The hydrophobic layer 11600 can be made of polytetrafluoroethylene, silane-modified materials, etc.

[0141] It is understandable that the hydrophobic layer 11600 in the detection area 130a and the hydrophobic layer 11600 in the driving area 130b can be located at the same height to ensure that the droplet can slide smoothly in the driving area 130b and the detection area 130a without loss.

[0142] Through the above method of fabricating the overlay motherboard 100, it can be seen that by changing the process film layer and photomask sequence of the overlay microfluidic substrate 100b, the overlay microfluidic substrate 100b can be adapted to the overlay display substrate, so that the film layers and photomask processes used in the display area 120 and the microfluidic area 130 are similar. The overlay microfluidic substrate 100b can be compatible with the number of film layers and photomask processes of the overlay display substrate 100a, so that the overlay display substrate 100a and the overlay microfluidic substrate 100b can be fabricated on the same substrate 110, so that the microfluidic chip and the display substrate (main product) can be overlaid. This reduces the manufacturing cost of the overlay display substrate 100a and the overlay microfluidic substrate 100b, while also improving the utilization rate of the motherboard.

[0143] Example 2

[0144] Embodiment 2 of this application provides a cut-out motherboard 100, which includes a cut-out display substrate 100a and a cut-out microfluidic substrate 100b prepared by the manufacturing method in Embodiment 1. The cut-out display substrate 100a can be used as a substrate for photoelectric sensing display devices, and the cut-out microfluidic substrate 100b can be used in microfluidic chips.

[0145] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0146] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A method for manufacturing a mother plate for die cutting, characterized in that, include: A substrate is provided, the substrate having at least a display area and a microfluidic area, the display area including a display pixel area, and the microfluidic area including an interconnected detection area and a driving area; A first transistor is formed in the display pixel area, a first metal block and a second metal block are sequentially formed in the detection area, and a second transistor is formed in the driving area. The first metal block is disposed on the side of the second metal block close to the substrate. A first passivation layer is formed on the substrate to cover the first transistor, the second metal block, and the second transistor. A first via and a second via are provided on the first passivation layer. The first via is used to expose a portion of the first source electrode in the first transistor, and the second via is used to expose a portion of the second source electrode in the second transistor. A protective layer is formed on the first passivation layer, and the protective layer is patterned to form a first connecting block in the display pixel area and a second connecting block in the driving area. The first connecting block is connected to the first source through the first via, and the second connecting block is connected to the second source through the second via. A semiconductor layer is formed on the display pixel area, and the semiconductor layer is connected to a first connection block in the display pixel area; A first pixel electrode is formed on the display pixel area, the detection area, and the driving area. The first pixel electrode in the display pixel area is disposed on the side of the semiconductor layer away from the substrate and is connected to the semiconductor layer. The first pixel electrode in the detection area is electrically connected to the first pixel electrode in the driving area, and the first pixel electrode in the detection area is disposed on the side of the first passivation layer away from the substrate. The first pixel electrode in the driving area is connected to the second connecting block in the driving area. A second passivation layer is formed on the first passivation layer, and within the display pixel area, the second passivation layer covers the first pixel electrode and the semiconductor layer; In the detection area, the second passivation layer covers the first pixel electrode; In the driving region, the second passivation layer exposes the first pixel electrode; A second pixel electrode is formed in the detection area and the driving area, and the second pixel electrode is connected to the first pixel electrode located in the driving area.

2. The manufacturing method according to claim 1, characterized in that, The second transistor includes a second gate, a second active layer, and a second source and a second drain respectively connected to both ends of the second active layer. The second gate is disposed on the side of the second active layer close to the substrate, and a gate insulating layer is provided between the second gate and the second active layer. When forming a protective layer on the first passivation layer and patterning the protective layer, the manufacturing method further includes: A protective block is formed within the driving region. The protective block is located on the side of the first passivation layer away from the substrate, and the orthographic projection of the protective block on the substrate overlaps with the orthographic projections of the second source and the second drain on the substrate.

3. The manufacturing method according to claim 2, characterized in that, The material of the protective layer includes one or more of metals and metal oxides.

4. The manufacturing method according to claim 1, characterized in that, Before forming the second pixel electrode, the fabrication method further includes: A planarization layer is formed on the second passivation layer, the planarization layer covers the second passivation layer, and a third via is formed on the planarization layer to expose the first pixel electrode located in the driving region, the second pixel electrode being electrically connected to the first pixel electrode through the third via.

5. The manufacturing method according to claim 4, characterized in that, The substrate is provided with multiple display areas and multiple microfluidic areas; After forming a planarization layer on the second passivation layer, the fabrication method further includes: In the display pixel area, a fourth via and a fifth via are respectively formed on the second passivation layer and the planarization layer. The fourth via and the fifth via correspond to and are connected. The fourth via and the fifth via are used to expose the portion of the first pixel electrode. A third metal layer is formed on the planarization layer and the third metal layer is patterned. A third metal block is formed in the display pixel area of ​​at least a portion of the display area. The third metal block is connected to the first pixel electrode located in the display pixel area through the fourth via and the fifth via. A fourth metal block is formed in the detection area of ​​at least a portion of the microfluidic area. The second pixel electrode covers the fourth metal block.

6. The manufacturing method according to claim 5, characterized in that, The first transistor includes a first gate, a first active layer, and a first source and a first drain respectively connected to both ends of the first active layer. The first gate is disposed on the side of the first active layer close to the substrate, and a gate insulating layer is provided between the first gate and the first active layer. When forming a third metal layer on the planar layer and patterning the third metal layer, the fabrication method further includes: A fifth metal block is formed in the display pixel area where the third metal block is formed. The fifth metal block is arranged at intervals from the third metal block. The orthographic projection of the fifth metal block on the substrate overlaps with the orthographic projections of the first source and the first drain on the substrate.

7. The manufacturing method according to claim 1, characterized in that, In the detection area, the orthographic projection of the second pixel electrode on the substrate and the orthographic projection of the second metal block on the substrate have an overlapping area.

8. The manufacturing method according to claim 7, characterized in that, In the detection area, the orthographic projection of the first pixel electrode on the substrate and the orthographic projection of the second metal block on the substrate have an overlapping area, and the voltage of the first pixel electrode and the second pixel electrode are the same.

9. The manufacturing method according to claim 4, characterized in that, The manufacturing method further includes: A third passivation layer and a hydrophobic layer are formed on the planar layer. The third passivation layer is disposed on the side of the hydrophobic layer close to the substrate, and the third passivation layer covers the second pixel electrode.

10. A type of die-cutting mother plate, characterized in that, This includes overlay-cut display substrates and overlay-cut microfluidic substrates manufactured using the manufacturing method described in any one of claims 1 to 9.

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