Wafer test probe card structure and test method

Abstract

The invention discloses a wafer test probe card structure and a test method, the probe card structure comprises a plurality of probes, a soft board, a first capacitor, a second capacitor, a copper foil, a needle fixing ring and a PCB, the probes, the soft board and the needle fixing ring are respectively arranged on the PCB, the first capacitor and the second capacitor are arranged on the soft board, and the copper foil is arranged on the PCB. The probe is connected with the first capacitor and the second capacitor through the flexible board, and the copper foil is arranged on the PCB, welded to the periphery of the probe fixing ring and connected with the GND. On the basis of an existing probe card structure, the flexible board, the first capacitor, the second capacitor and the copper foil are additionally arranged, shielding of power clutter is facilitated by designing the flexible board and the copper foil, meanwhile, the probes are connected with the first capacitor and the second capacitor through the flexible board, the capacitors can be made to be closer to a chip in layout, the filtering effect is improved, and the service life is prolonged. Therefore, the accuracy of test data is further improved, the test effect is better, the overall structure is simple, the design is ingenious, and the device is suitable for industrial popularization and application.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a wafer testing probe card structure and a testing method. Background Art

[0002] During the semiconductor wafer testing stage, probe cards are usually used to test unpackaged chips on the wafer. However, the testing effect of existing probe cards still has a lot of room for improvement. How to further improve the filtering effect and increase the accuracy of test data has become a major difficulty in the industry.

[0003] Therefore, the present invention discloses a wafer testing probe card structure and a testing method. Summary of the invention

[0004] In order to solve the technical problems existing in the prior art, the object of the present invention is to provide a wafer test probe card structure and a test method.

[0005] In order to achieve the above purpose and the above technical effect, the technical solution adopted by the present invention is:

[0006] A wafer test probe card structure comprises a probe, a soft board, a capacitor, a copper foil, a fixed needle ring and a PCB board, wherein a plurality of probes are provided, and the probes, the soft board and the fixed needle ring are respectively provided on the PCB board, the capacitor is provided on the soft board, the probe is connected to the capacitor through the soft board, the copper foil is provided on the PCB board and is located outside the fixed needle ring, and the copper foil is connected to GND.

[0007] Furthermore, the capacitor includes a plurality of first capacitors and second capacitors, the first capacitors and the second capacitors are respectively arranged on the flexible board, one end of the first capacitor and the second capacitor is respectively connected to GND, and the other end of the first capacitor and the second capacitor is respectively connected to the power supply.

[0008] Furthermore, the first capacitor is located on the inner side of the flexible board, close to the chip position, and the second capacitor is located on the outer side of the flexible board, close to the pogo position of the PCB board.

[0009] Furthermore, the first capacitor and the second capacitor have different capacities, and the capacity of the first capacitor is smaller than the capacity of the second capacitor.

[0010] Furthermore, the capacity of the first capacitor is not greater than 0.1UF.

[0011] Furthermore, the capacity of the first capacitor is 0.1UF or 0.01UF.

[0012] Furthermore, the capacity of the second capacitor is not greater than 10UF.

[0013] Furthermore, the capacity of the second capacitor is 4.7UF or 10UF.

[0014] Furthermore, the copper foil is laid flat on the periphery of the pin fixing ring, that is, the soldering pin area, and the copper foil is connected to GND through an electric wire.

[0015] The present invention also discloses a wafer testing method, which uses the wafer testing probe card structure as described above to test the wafer.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The present invention discloses a wafer test probe card structure and a test method. On the basis of the existing probe card structure, a soft board, a first capacitor, a second capacitor and a copper foil are additionally provided. The soft board and the copper foil are designed to be beneficial for shielding power supply noise. Meanwhile, the probe is connected to the first capacitor and the second capacitor through the soft board, so that the capacitor can be closer to the chip in layout, and the filtering effect is improved, thereby facilitating further improving the accuracy of test data and achieving better test effect. The overall structure is simple and the design is ingenious, so the device is suitable for industrial promotion and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural schematic diagram of the present invention;

[0019] Figure 2 For the present invention Figure 1 A partial enlarged view of point A in the figure. DETAILED DESCRIPTION

[0020] The present invention is described in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0021] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or critical elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0022] like Figure 1-2As shown, the present invention discloses a wafer test probe card structure, including a probe 1, a soft board 2, a capacitor 3, a copper foil 4, a fixed needle ring 5 and a PCB board 6, wherein a plurality of probes 1 are provided. On the basis of the existing probe card structure, the present invention adds a soft board 2, a capacitor 3 and a copper foil 4, and respectively arranges the probe 1, the soft board 2 and the fixed needle ring 5 on the PCB board 6. By designing the soft board 2 and the copper foil 4, it is beneficial to shield power supply clutter and reduce voltage drop. The capacitor 3 is arranged on the soft board 2, so that the probe 1 is connected to the capacitor 3 through the soft board 2, so that the capacitor 3 can be closer to the chip in layout, and the filtering effect is improved, which is beneficial to improve the accuracy of the test data. The copper foil 4 is spread as a whole on the periphery of the fixed needle ring 5, that is, the area of ​​the welding pin, and the copper foil 4 is connected to the GND through an electric wire, which also plays a good shielding effect and can further improve the accuracy of the test data.

[0023] In some implementations, the inner layer of the flexible board 2 is designed with a signal channel, and the outer layer is GND, and a conductive material such as metal is used.

[0024] In some embodiments, the capacitor 3 includes a plurality of first capacitors 31 and second capacitors 32 connected in parallel, the first capacitors 31 and the second capacitors 32 are respectively arranged on the flexible board 2, one end of the first capacitor 31 and the second capacitor 32 are respectively connected to GND, and the other ends of the first capacitor 31 and the second capacitor 32 are respectively connected to a power supply, and the power supply is arranged on the PCB board 6.

[0025] In some specific implementations, the first capacitor 31 is located on the inner side of the flexible board 2 , close to the chip position, and the second capacitor 32 is located on the outer side of the flexible board 2 , close to the pogo position of the PCB board 6 .

[0026] In some embodiments, the first capacitor 31 and the second capacitor 32 have different capacities, and the capacity of the first capacitor 31 is smaller than the capacity of the second capacitor 32 .

[0027] In some implementations, the capacity of the first capacitor 31 is not greater than 0.1 UF.

[0028] In some specific implementations, the capacity of the first capacitor 31 is 0.1UF or 0.01UF.

[0029] In some embodiments, the capacity of the second capacitor 32 is not greater than 10 UF.

[0030] In some specific implementations, the capacity of the second capacitor 32 is 4.7UF or 10UF.

[0031] In some implementations, a plurality of first capacitors 31 are connected in parallel with each other and with the second capacitor 32 .

[0032] The present invention Figure 2The Power in the figure is the power supply, and the Power Bar is the copper foil 4 for soldering the Power.

[0033] The present invention also discloses a wafer testing method, which uses the wafer testing probe card structure as described above to test the wafer.

[0034] Example 1

[0035] like Figure 1-2 As shown, a wafer test probe card structure includes a probe 1, a soft board 2, a capacitor 3, a copper foil 4, a fixed needle ring 5 and a PCB board 6, wherein a plurality of probes 1 are provided. In this embodiment, on the basis of the existing probe card structure, a soft board 2, a capacitor 3 and a copper foil 4 are additionally provided, and the probe 1, the soft board 2 and the fixed needle ring 5 are respectively arranged on the PCB board 6. By designing the soft board 2 and the copper foil 4, it is beneficial to shield power supply clutter and reduce voltage drop, thereby reducing IO interference. The soft board 2 is about 0.5 cm away from the copper foil. The capacitor 3 is arranged on the soft board 2, so that the probe 1 is connected to the capacitor 3 through the soft board 2, so that the capacitor 3 can be closer to the chip in layout, thereby improving the filtering effect, which is beneficial to improving the accuracy of the test data. The copper foil 4 is spread as a whole on the periphery of the fixed needle ring 5, that is, the area of ​​the welding pin, and the copper foil 4 is connected to the GND through an electric wire, which also plays a certain shielding role and can further improve the accuracy of the test data.

[0036] In this embodiment, the inner layer of the flexible board 2 is designed with a signal channel, and the outer layer is GND, and copper conductive material is used.

[0037] In this embodiment, the capacitor 3 includes three first capacitors 31 and one second capacitor 32. The first capacitors 31 are connected in parallel with each other and in parallel with the second capacitor 32. The first capacitors 31 and the second capacitors 32 are respectively arranged on the soft board 2. Specifically, the first capacitor 31 is located on the inner side of the soft board 2, close to the chip position, and the second capacitor 32 is located on the outer side of the soft board 2, close to the pogo position of the PCB board 6. One end of the first capacitor 31 and the second capacitor 32 are respectively connected to GND, and the other ends of the first capacitor 31 and the second capacitor 32 are respectively connected to the power supply, and the power supply is arranged on the PCB board 6.

[0038] In this embodiment, the first capacitor 31 and the second capacitor 32 have different capacities. The capacity of the first capacitor 31 is 0.1 UF, and the capacity of the second capacitor 32 is 4.7 UF.

[0039] This embodiment also discloses a wafer testing method, which uses the wafer testing probe card structure as described above to test the wafer.

[0040] Parts or structures not specifically described in the present invention may adopt existing technologies or existing products and will not be described in detail here.

[0041] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A wafer test probe card structure, characterized in that: It includes a probe, a soft board, a capacitor, a copper foil, a fixed needle ring and a PCB board. There are several probes, and the probe, the soft board and the fixed needle ring are respectively arranged on the PCB board. The capacitor is arranged on the soft board, and the probe is connected to the capacitor through the soft board. The copper foil is arranged on the PCB board and is located outside the fixed needle ring, and the copper foil is connected to GND.

2. A wafer test probe card structure according to claim 1, characterized in that: The capacitor includes a plurality of first capacitors and second capacitors, wherein the first capacitors and the second capacitors are respectively arranged on the flexible board, one end of the first capacitors and the second capacitors are respectively connected to GND, and the other ends of the first capacitors and the second capacitors are respectively connected to the power supply.

3. A wafer test probe card structure according to claim 2, characterized in that: The first capacitor is located on the inner side of the flexible board, close to the chip position, and the second capacitor is located on the outer side of the flexible board, close to the pogo position of the PCB board.

4. The wafer test probe card structure according to claim 2, characterized in that: The first capacitor and the second capacitor have different capacities, and the capacity of the first capacitor is smaller than the capacity of the second capacitor.

5. The wafer test probe card structure according to claim 4, characterized in that: The capacity of the first capacitor is not greater than 0.1UF.

6. The wafer test probe card structure according to claim 5, characterized in that: The capacity of the first capacitor is 0.1UF or 0.01UF.

7. The wafer test probe card structure according to claim 4, characterized in that: The capacity of the second capacitor is not greater than 10UF.

8. The wafer test probe card structure according to claim 7, characterized in that: The capacity of the second capacitor is 4.7UF or 10UF.

9. The wafer test probe card structure according to claim 1, characterized in that: The copper foil is laid flat on the periphery of the fixed needle ring as a whole, and the copper foil is connected to the GND through an electric wire.

10. A wafer testing method, characterized in that: A wafer test probe card structure according to any one of claims 1 to 9 is used to test a wafer.

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