Method for realizing TSV failure verification of 3D chip product

Abstract

The invention discloses a method for realizing TSV failure verification of a 3D chip product, and the method comprises the steps: enabling the upper end of a TSV group to be connected to an upper chip in a 3D chip, enabling the lower end of the TSV group to be connected to a bottom chip in the 3D chip, and screening and positioning a suspected TSV structure in the TSV group through a chip testing technology; grinding the upper chip and the bottom chip to expose the metal layers at the top and the bottom of each TSV structure, and establishing electrical interconnection of each TSV structure on the bottom metal layer; and based on the electrical interconnection of the metal layers, performing an electrical test on the suspected TSV structure and the contrast TSV structure in the TSV group, and determining whether the suspected TSV structure is abnormal or not according to comparison information of an electrical test result. According to the scheme of the invention, non-destructive TSV electrical testing is realized.

Description

Technical Field

[0001] The present application relates to the technical field of chip failure verification, and in particular to a method for implementing TSV failure verification of 3D chip products. Background Art

[0002] In 3D-oriented IC chips, the adoption of TSV structure is an important difference from 2D to 3D. TSV, also known as Through Silicon Via technology, realizes vertical electrical interconnection of through silicon vias by making vertical conductions between chips and between wafers. Therefore, after 2D chips are stacked, multiple sets of TSV tests are required to test the functional status of chips before and after bonding, as well as faulty TSV screening. Bonding is an advanced integrated circuit packaging technology used to achieve high-density, high-performance interconnection between different chips. It replaces traditional bump or solder ball interconnection with direct copper-to-copper connection, thereby enabling ultra-fine pitch stacking and packaging in a very small space.

[0003] There are a lot of related technologies for TSV test logic development, but after TSV failure, physical failure analysis (PFA) is mostly done by directly observing the TSV section through physical slicing. However, due to the large overall structure of TSV, with a diameter of several microns and a depth of tens of microns, coupled with the structure of 3D chips, the risks of physical slicing are much more complex and difficult than traditional 2D. Summary of the invention

[0004] In view of this, the present application provides a method for realizing TSV failure verification of 3D chip products, aiming to combine the process characteristics of 3D stacking itself, through physical metal interconnection modification, without destroying the original structure of TSV, through electrical resistance testing, VC (voltage contrast imaging) and other non-destructive means, to help verify and confirm the existence of faults in the target TSV.

[0005] In a first aspect, the present application provides a method for implementing TSV failure verification of a 3D chip product, comprising:

[0006] Connecting the upper end of the TSV group to the upper chip in the 3D chip, and the lower end to the bottom chip in the 3D chip, and screening and locating the suspected TSV structure in the TSV group through a chip testing process;

[0007] Grinding the upper chip and the bottom chip to expose the metal layers at the top and bottom of each TSV structure, and establishing electrical interconnection between each TSV structure at the bottom metal layer;

[0008] Based on the electrical interconnection of the metal layer, an electrical test is performed on the suspected TSV structure and a control TSV structure in the TSV group, and it is determined whether the suspected TSV structure is abnormal based on comparison information of the electrical test results.

[0009] Preferably, the screening and locating the suspected TSV structure in the TSV group by a chip testing process further comprises:

[0010] Through the chip test WS test program, the electrical function test is performed on the TSV structure in the TSV group to determine the suspected TSV structure.

[0011] Preferably, after determining the suspected TSV structure, the method further includes:

[0012] A suspect TSV structure with a single signal failure is selected from the suspect TSV structures, and the coordinates are marked.

[0013] Preferably, the metal layers at the top and bottom of the TSV structure are respectively an upper interconnect layer in the upper chip and a lower interconnect layer in the bottom chip.

[0014] Preferably, the establishing of electrical interconnection of the bottom metal layer further comprises:

[0015] The bottom interconnect layer is opened with a FIB insulating passivation layer, and the bottom metal interconnection of each TSV structure is realized by using a metal plating layer in the insulating passivation layer opening.

[0016] Preferably, the bottom metal layer is other layers in the bottom chip except the lower interconnect layer.

[0017] Preferably, the electrical testing of the suspected TSV structure and the control TSV structure in the TSV group further comprises:

[0018] Connecting the first control TSV structure and the second control TSV structure in series to perform an IV test to obtain a standard resistance value;

[0019] Connecting the second control TSV structure and the suspected TSV structure in series to perform an IV test to obtain a verification resistance value;

[0020] By comparing the standard resistance value with the verification resistance value, it is determined whether there is a resistance abnormality.

[0021] Preferably, comparing the standard resistance value with the verification resistance value to determine whether there is a resistance abnormality further includes:

[0022] When the resistance ratio of the standard resistance value to the verification resistance value is greater than 2 or less than 0.5, it is determined that the resistance value is abnormal.

[0023] Preferably, the electrical test is performed on the suspected TSV structure and the control TSV structure in the TSV group, and determining whether the suspected TSV structure is abnormal according to comparison information of the electrical test results, further comprising:

[0024] The metal layer on the top of all parallel structures was observed by SEM VC electron microscopy, and the electrical connectivity was determined based on the difference in brightness between the observed TSV area and the control area.

[0025] Preferably, if the brightness difference between the suspected TSV structure region and the control TSV structure is greater than a preset threshold, it is determined that the suspected TSV structure is abnormal.

[0026] It can be seen that the method for implementing TSV failure verification of 3D chip products in the present application provides a non-destructive TSV electrical testing and fault identification method, which implements single-sided TSV electrical testing by interconnecting the bottom metal layer between TSVs, and implements fault identification by comparing the suspected TSV with the electrical resistance of the surrounding TSVs or the brightness observed under an electron microscope. Electrical interconnection modification is achieved by modifying the metal layer between TSV groups. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments or technologies of the present application, the drawings required for use in the embodiments or technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 A schematic diagram of a physical failure analysis verification process according to related technology is shown.

[0029] Figure 2 A flow chart of a method for implementing TSV failure verification of a 3D chip product according to the present application is shown.

[0030] Figure 3 An example diagram comparing the advantages and disadvantages of the TSV structure according to the present application is shown.

[0031] Figure 4 A flow chart of electrical interconnect modification of metal layers according to the present application is shown.

[0032] Figure 5 A schematic diagram of TSV bottom metal interconnection according to the present application is shown.

[0033] Figure 6 A schematic diagram of SEM VC electron microscope observation according to the present application is shown. DETAILED DESCRIPTION

[0034] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0035] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. In order to more clearly illustrate the present application, many technical details are described in the following specific embodiments. Those skilled in the art should understand that the present application can also be implemented without some of the details. In addition, in order to highlight the invention of the present application, some methods, means, components and their applications well known to those skilled in the art are not described in detail, but this does not affect the implementation of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application.

[0036] After the upper and lower chips are bonded, the verification of their connectivity has always been the most important. However, the current electronic design automation (EDA) tools for 3D IC verification are not yet mature. Therefore, the industry's EDA tools often have difficulty in designing and verifying 3D stacked chips. The current industry's EDA design process mainly treats TSV and hybrid bonding as a whole, sets the hierarchical structure at both ends as two independent endpoints and marks them for design, and then performs electrical connection and physical hierarchy inspection according to the real physical hierarchy. Therefore, in the entire TSV interconnection structure inspection, check whether the TSV structure has connectivity.

[0037] When a TSV failure is detected, the traditional test solution needs to physically slice the faulty TSV structure to confirm the type and status of the TSV structural failure. Specifically, it involves chip delayering, followed by focused ion beam (FIB) hole digging, and then transmission electron microscopy (TEM) and scanning electron microscopy (SEM) observation to confirm the TSV failure. The specific flow chart is as follows Figure 1 As shown in the figure, the above verification methods are mostly physical destructive slice verification. However, when facing 2D to 3D structures, the difficulty of physical failure analysis (PFA) will increase dramatically. And the entire PFA must destroy the TSV structure for verification, which is difficult to operate and time-consuming.

[0038] In order to solve the above problems or other problems, the present application provides a method for implementing TSV failure verification of 3D chip products. By modifying the metal layer and cooperating with an electrical testing solution, it is possible to determine whether the TSV structure itself has failed without the need for overall TSV slicing, thereby simplifying the physical slicing verification process when TSV fails in 3D chip products.

[0039] See also Figure 2 The flowchart of the method for implementing TSV failure verification of 3D chip products shown in the figure includes the following specific steps:

[0040] Step S101 , connecting the upper end of the TSV group to the upper chip in the 3D chip, and the lower end to the bottom chip in the 3D chip, and screening and locating the suspected TSV structure in the TSV group through a chip testing process.

[0041] by Figure 3 Taking the simplest stacked 3D die shown as an example, the upper chip is Top Die and the bottom chip is Bottom Die. First, a rough TSV structure is defined. The TSV connects the upper interconnect layer (TM layer, Top Die) and the lower interconnect layer (TLM layer, Bottom Die) respectively.

[0042] The 3D chip first uses the chip test WS test program to perform electrical function tests on all TSV structures involved to find out whether there is a TSV structure fault. For example, signal receiving ports can be designed on both sides of the TSV. Channel test is performed on the TSV. When the data signal is injected into one end, the signal is received at the other end. The data at the receiving end is compared with the data at the input end to determine whether there is a fault. After the suspected TSV is identified, the TSV structure with a single signal failure is selected from the suspected TSV structure and the coordinates are marked. Before further FA physical verification, the following process is used for fault verification and identification.

[0043] Step S102 , grinding the upper chip and the bottom chip to expose the metal layers at the top and bottom of each TSV structure, and establishing electrical interconnection between each TSV structure at the bottom metal layer.

[0044] Next, metal interconnect modification is performed. Figure 4 Flow chart, when a TSV test failure occurs, the failed TSV area is firstly subjected to delay grinding until the metal layer TM on the top of each TSV is exposed.

[0045] After determining other control TSV locations near the failed TSV, the Bottom Dielayer is polished until the bottom interconnect layer is exposed.

[0046] like Figure 5 As shown in the figure, the bottom metal interconnection of each TSV is achieved by opening holes in the FIB insulating passivation layer and setting a metal plating layer in the bottom interconnection layer. The bottom metal layer of the suspected TSV is interconnected, the bottom metal layer of the TSV is exposed by grinding, and then the insulating layer is evaporated on the area that does not need to be interconnected through a mask. After completion, platinum or aluminum is evaporated on the area that needs to be interconnected to achieve metal electrical interconnection.

[0047] Optionally, in the modification of the bottom interconnect metal, the layer can be the TLM layer, or any suitable layer can be operated. For example, the modification can be operated within the metal layer layer 2 layers below, and the spacing between metal layers is less than or equal to 300um. Smaller layer spacing facilitates subsequent interconnect modification operations.

[0048] Step S103 , based on the electrical interconnection of the metal layer, electrical testing is performed on the suspected TSV structure and the control TSV structure in the TSV group, and it is determined whether the suspected TSV structure is abnormal according to comparison information of the electrical test results.

[0049] After obtaining the coordinates of the suspected TSV, the solution of this application aligns the layout interconnection structure for analysis. Because other TSV structures are generally distributed around the TSV, other TSV structure paths are used to perform electrical resistance tests or VC comparisons to determine faults. In order to achieve non-destructive analysis of suspected TSVs, one of the following strategies is adopted.

[0050] Strategy 1: Current-voltage (IV) test: Screen and confirm suspected TSVs by testing good and bad TSVs in series.

[0051] By interconnecting the TLMs near the suspected TSV, and then through series testing, the needles or leads on one side of the chip can be inserted for resistance testing.

[0052] Connect TSV2 and TSV1 in series for IV testing to obtain the standard resistance R1. Connect TSV2 and TSV3 in series for IV testing to obtain the verification resistance R2. By comparing R2 with R1, it is determined whether the resistance is abnormal, and whether TSV3 is abnormal. In a specific embodiment, it can be set that when the resistance ratio R1 / R2>2 or R1 / R2<0.5, it is determined that the resistance is abnormal, otherwise it is determined that the resistance is normal.

[0053] Strategy 2: SEM VC electron microscope observation: Once the bottom TLM interconnects are connected, SEM VC is used to perform TSV comparison observation to determine which TSVs are open.

[0054] In a specific embodiment, the upper part of the TSV is first delayed to the top interconnect metal layer during electron microscope observation. After grinding, multiple TSV top interconnect layers around the suspected TSV are exposed at the same time for easy comparison and observation. All parallel TSV TM layers are observed by SEM VC, and the electrical connectivity is determined based on the brightness of the TSV area. Bright areas have good connectivity, and dark areas have poor connectivity.

[0055] Exemplarily, if the brightness difference between the suspected TSV and the control TSV is greater than a preset threshold, or the brightness of the suspected TSV is lower than a certain brightness threshold, it is determined that the suspected TSV is abnormal.

[0056] See also Figure 6 If the color of TSV-3 is significantly darker, it is judged that the electrical connection is poor and abnormal.

[0057] It can be seen that the method for implementing TSV failure verification of 3D chip products provided by this application has the following advantages compared with related technologies: it provides a non-destructive TSV electrical test and fault identification method, realizes single-sided TSV electrical testing by interconnecting the bottom metal layer between TSVs, realizes fault identification by comparing the suspected TSV with the electrical resistance value of the surrounding TSVs or the brightness observed by an electron microscope, and realizes electrical interconnection modification by modifying the metal layer between TSV groups. It determines whether the TSV structure itself has a fault without the need for overall TSV slicing, thereby simplifying the physical slicing verification process when TSV fails in 3D chip products.

[0058] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0059] Although the embodiments of the present application are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for implementing TSV failure verification of 3D chip products, characterized in that: include: Connecting the upper end of the TSV group to the upper chip in the 3D chip, and the lower end to the bottom chip in the 3D chip, and screening and locating the suspected TSV structure in the TSV group through a chip testing process; Grinding the upper chip and the bottom chip to expose the metal layers at the top and bottom of each TSV structure, and establishing electrical interconnection between each TSV structure at the bottom metal layer; Based on the electrical interconnection of the metal layer, an electrical test is performed on the suspected TSV structure and a control TSV structure in the TSV group, and it is determined whether the suspected TSV structure is abnormal based on comparison information of the electrical test results.

2. The method for implementing TSV failure verification of 3D chip products according to claim 1, characterized in that: The screening and locating of the suspected TSV structure in the TSV group by a chip testing process further includes: Through the chip test WS test program, the electrical function test is performed on the TSV structure in the TSV group to determine the suspected TSV structure.

3. The method for implementing TSV failure verification of 3D chip products according to claim 2, characterized in that: After the suspected TSV structure is determined, the following steps are also required: A suspect TSV structure with a single signal failure is selected from the suspect TSV structures, and the coordinates are marked.

4. The method for implementing TSV failure verification of 3D chip products according to claim 1, characterized in that: The metal layers at the top and bottom of the TSV structure are respectively an upper interconnect layer in the upper chip and a lower interconnect layer in the bottom chip.

5. The method for implementing TSV failure verification of 3D chip products according to claim 4, characterized in that: The establishing of the bottom metal layer electrical interconnection further comprises: The bottom interconnect layer is opened with a FIB insulating passivation layer, and the bottom metal interconnection of each TSV structure is realized by using a metal plating layer in the insulating passivation layer opening.

6. The method for implementing TSV failure verification of 3D chip products according to claim 1, characterized in that: The bottom metal layer is the other layer in the bottom chip except the lower interconnection layer.

7. The method for implementing TSV failure verification of 3D chip products according to claim 1, characterized in that: The performing electrical testing on the suspected TSV structure and the control TSV structure in the TSV group, and determining whether the suspected TSV structure is abnormal according to comparison information of the electrical testing results, further includes: Connecting the first control TSV structure and the second control TSV structure in series to perform an IV test to obtain a standard resistance value; Connecting the second control TSV structure and the suspected TSV structure in series to perform an IV test to obtain a verification resistance value; By comparing the standard resistance value with the verification resistance value, it is determined whether there is a resistance abnormality.

8. The method for implementing TSV failure verification of 3D chip products according to claim 7, characterized in that: The comparing the standard resistance value with the verification resistance value to determine whether there is a resistance abnormality further includes: When the resistance ratio of the standard resistance value to the verification resistance value is greater than 2 or less than 0.5, it is determined that the resistance value is abnormal.

9. The method for implementing TSV failure verification of 3D chip products according to claim 1, characterized in that: The performing electrical testing on the suspected TSV structure and the control TSV structure in the TSV group, and determining whether the suspected TSV structure is abnormal according to comparison information of the electrical testing results, further includes: The metal layer on the top of all parallel structures was observed by SEM VC electron microscopy, and the electrical connectivity was determined based on the difference in brightness between the observed TSV area and the control area.

10. The method for implementing TSV failure verification of 3D chip products according to claim 9, characterized in that: Determining electrical connectivity based on a difference in brightness between the observed TSV region and the control region further includes: If the brightness difference between the suspected TSV structure region and the control TSV structure is greater than a preset threshold, it is determined that the suspected TSV structure is abnormal.

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