Microsecond multi-channel separation synchronization test device and method based on STM32 chip

Abstract

The application belongs to the technical field of aerospace, and particularly relates to a microsecond multi-channel separation synchronization test device and method based on an STM32 chip, which comprises an STM32 chip, a plurality of separation monitoring channels based on the STM32 chip, a switch module, a power-on control interface, a communication chip and a communication interface. The microsecond multi-channel separation synchronization test device and method based on the STM32 chip improve the automation degree and time monitoring precision of the test device, can realize closed-loop control of experiments, and can display experimental results in real time. In a low-cost manner, the microsecond multi-channel separation synchronization test is realized.

Description

Technical Field

[0001] This invention belongs to the field of aerospace technology, specifically relating to a multi-point synchronous separation test method, and more particularly to a microsecond-level multi-channel separation synchronization test device and method based on an STM32 chip. Background Technology

[0002] Currently, non-pyrotechnic connection and separation mechanisms driven by shape memory alloys (SMA) are widely used in various fields, such as connection and separation mechanisms in the aerospace field. These mechanisms can realize the connection and separation between the entire aircraft and its components, as well as between components, and have important research significance.

[0003] Generally, connection and separation mechanisms can be used not only as single-point connections but also in combination to meet different target requirements. For example, high-load separation requirements such as interstage separation of rockets or separation of satellites from rockets often require the combined use of multiple connection and separation mechanisms or a single connection and separation mechanism combined with a linkage mechanism. For instance, in the rigid strap separation of a satellite and rocket, a single connection and separation mechanism triggers the connection, while a linkage mechanism unlocks it. During use, ensuring the successful separation process is crucial for the synchronization of multiple separation points. Poor synchronization can cause uneven force distribution, leading to deflection of the connecting parts and continued movement due to inertia, posing a risk of accidental collisions with other components and affecting the reliability of the separation mission. Therefore, testing the separation synchronization of multiple separation points is an indispensable part of multi-point synchronous separation missions.

[0004] In the use of non-pyrotechnic connection and separation mechanisms driven by shape memory alloys, it is also important to note that although SMAs can be reused, they are sensitive to temperature. When the temperature exceeds their specific phase transition temperature range, the microstructure of the SMA will undergo an irreversible phase transition, or even lose its shape memory effect. Therefore, the energizing process of the SMA filament must be strictly controlled.

[0005] Currently, there are two main testing methods for multi-point synchronization separation:

[0006] (a) The two ends of the on / off signal adapter are connected to the separation test point and the four channels of the oscilloscope respectively. At the same time as the power is output, the oscilloscope is externally triggered. After separation, the separation time is read by the oscilloscope with an accuracy of 0.01ms.

[0007] (b) The entire separation process is captured by a high-speed camera with hundreds of thousands of frames per second. The images are then processed to determine the separation time at each point with an accuracy of 0.01ms.

[0008] However, both of the above solutions have certain drawbacks:

[0009] In the above scheme (a), on the one hand, the control logic is in an open-loop state, which means that after the separation action occurs, the system cannot effectively provide feedback and control to the power output. Since the SMA wire has strict requirements on the energizing time and current magnitude, excessive energizing may lead to performance degradation or even damage. Therefore, this lack of feedback mechanism is prone to over-energizing the SMA wire, thereby affecting its service life. On the other hand, the number of separation measurement points that scheme (a) can monitor simultaneously is limited. It cannot connect and monitor enough separation measurement points at the same time, thus limiting its application in multi-point synchronous separation testing.

[0010] In scheme (b) described above, firstly, the system lacks direct information feedback. At the moment of separation, scheme (b) cannot immediately provide feedback on the power output, which may cause the SMA filament to continue to be energized, resulting in over-energization. Over-energization will affect the performance and lifespan of the SMA filament, and may even cause it to be damaged. Secondly, after the experiment, scheme (b) cannot immediately provide experimental results, requiring a significant amount of time for manual image processing and analysis. This not only prolongs the experimental cycle but also increases the uncertainty of the experiment. Furthermore, although high-speed cameras can provide high frame rate images, their shooting angle has blind spots. Scheme (b) cannot effectively monitor separation measurement points located in the shooting angle blind spots, thus limiting its application in complex separation scenarios. Moreover, high-speed cameras cost hundreds of thousands or even millions of dollars, and the expensive equipment significantly increases the overall cost of the experiment. For research institutions or enterprises with limited budgets, adopting scheme (b) may face considerable economic pressure. Therefore, although high-speed cameras can provide high frame rate images and more intuitively demonstrate the separation process, they also have significant limitations in terms of cost and applicability.

[0011] Therefore, providing a microsecond-level multi-channel separation synchronization test device and method that is simple in structure, low in cost, high in precision, easy to implement, and widely applicable, and can prevent SMA filament overcharging, is of great significance for promoting the development of multi-point synchronous separation test technology. Summary of the Invention

[0012] The purpose of this invention is to address the aforementioned technical problems by providing a microsecond-level multi-channel separation synchronization test device and method based on an STM32 chip.

[0013] In view of this, the present invention provides a microsecond-level multi-channel separation synchronization test device based on an STM32 chip, characterized in that it comprises:

[0014] STM32 chip;

[0015] Multiple separation monitoring channels based on STM32 chips are provided. Each separation monitoring channel includes a charging power supply VDD, a resistor R, and a capacitor C connected in series. The other end of the capacitor C is grounded. A GPIO interface is provided between the resistor R and the capacitor C. The GPIO interface is connected to the external interrupt pin of the STM32 chip. One part of the separation monitoring point in the separation body is connected between the resistor R and the capacitor C, and the other part is connected between the capacitor C and the ground point of the capacitor C. It is ensured that the two parts of the separation monitoring point in the separation body can conduct. During the separation process, the test device can obtain the total time from power-on to separation of the two parts of the separation monitoring point in the separation body according to the voltage change of the capacitor C.

[0016] A switching module, which is connected to the power input interface of the device under test;

[0017] The power control interface can control the switching module to turn the circuit on or off;

[0018] In addition, a communication chip and a communication interface are provided. The STM32 chip, the communication chip, and the communication interface are connected in sequence. The communication interface can communicate with the computer host via a USB interface to receive instructions from the computer host or send information to the computer host.

[0019] The STM32 chip is also connected to the power control interface and the switch module. The STM32 chip can control the power-on status of the separation monitoring points in the separation body during the test and acquire the power-on status parameters.

[0020] Furthermore, when the two parts of the separation monitoring point in the connecting separator are in a connected state, the voltage of the capacitor C is 0;

[0021] After the two parts of the separation monitoring point in the connecting separation body are separated, the circuit is broken, and the capacitor C is charged under the action of the charging power supply VDD and the resistor R, and the voltage gradually increases.

[0022] When the voltage of the capacitor C rises to the trigger voltage of the external interrupt of the STM32 chip, the STM32 chip automatically executes the external interrupt program. In the external interrupt program, the controller of the STM32 chip reads the current time and calculates the total time taken from power-on to separation of the two parts of the separation monitoring point in the connected separation body by calculating the interval between the current time and the power-on start time.

[0023] Furthermore, the microsecond-level multi-channel separation synchronization test device also includes:

[0024] The programming interface is an interface led out from the program download pin of the STM32 chip. Before use, an existing program needs to be programmed into the test device through the programming interface.

[0025] The system restart interface is an interface led out from the restart pin of the STM32 chip. The system restart interface is connected to an external mechanical restart button. Pressing the mechanical restart button will restart the system.

[0026] Furthermore, the microsecond-level multi-channel separation synchronization test device also includes:

[0027] Each test may use some or all of the multiple separate monitoring channels. Before use, connect some or all of the channels used in the separate monitoring channels to the corresponding separate monitoring points.

[0028] A microsecond-level multi-channel separation synchronization test method is provided, the test method being used in the aforementioned microsecond-level multi-channel separation synchronization test device, the test method comprising the following steps:

[0029] S1, During the test, if a certain separation monitoring channel is interrupted, step S2 is executed;

[0030] S2, the STM32 chip automatically enters the interrupt function of this channel. At the same time, after the test device delays for a set time t1, it determines whether the separation monitoring point has been separated. The determination is based on the following: if the corresponding separation monitoring point has been separated, then capacitor C is at a high level; otherwise, capacitor C is at a low level.

[0031] S3. If the corresponding separation monitoring point has been separated, obtain the current time and execute step S4; otherwise, end the monitoring of this channel.

[0032] S4, change the separation flag of the separation monitoring channel to indicate that the separation monitoring channel has been completed and end the monitoring of the channel.

[0033] Furthermore, when the tested connection / disconnection is a connection / disconnection that is unlocked using a release mechanism and through mechanical linkage, the test method further includes step S3 located between steps S3 and S4. + Step S3 + include:

[0034] S3 + If the corresponding separation monitoring point has been separated, determine whether the separation monitoring channel is the main channel. The main channel refers to the channel connected to the micro switch inside the unlocker. If it is, control the switch module to disconnect the current output. If not, treat the separation monitoring channel as a normal monitoring channel, obtain the current time, change the separation flag, and then end.

[0035] Furthermore, the testing method also includes:

[0036] Upon receiving experimental data from the user, the program burned into the STM32 chip automatically determines the format of the experimental data. Once the information format is correct, a power-on message is sent to the switch module to initiate power-on and perform a separation synchronization test.

[0037] Furthermore, the test method also includes: after the separation synchronization test begins, the controller of the STM32 chip periodically sends the channel numbers that have not yet been separated according to a set cycle.

[0038] Furthermore, the test method also includes: after the separation synchronization test begins, the controller of the STM32 chip monitors the test time, and after all the separation monitoring channels used by the user have completed separation, or after the maximum test time set by the system is reached, the system automatically ends and sends the separation results of each channel.

[0039] Furthermore, the testing method also includes:

[0040] After the unlocker completes the separation action by being powered on, the controller of the STM32 chip sends a command to stop power supply to the switching module, and the switching module cuts off the current output.

[0041] The beneficial effects of this invention are:

[0042] The microsecond-level multi-channel separation synchronization test device and method based on STM32 chip provided by this invention integrates automated experimental control and multi-channel separation time monitoring functions, and has the following advantages:

[0043] (1) The present invention realizes the automated control of the connection and separation mechanism experiment. Unlocking immediately cuts off the power, which can effectively prevent the overcharging of SAM wire and extend its service life.

[0044] (2) The present invention achieves high time accuracy monitoring of a single connection separation point with a measurement error of less than 10 μs, which has the advantage of high accuracy;

[0045] (3) This invention integrates multi-channel separation synchronization monitoring, realizing separation synchronization monitoring of multiple separation points, and the synchronization error in actual use is less than 2µs;

[0046] In summary, the microsecond-level multi-channel separation synchronization test device and method based on STM32 chip described in this invention improves the automation level and time monitoring accuracy of the test system, enables closed-loop control of the experiment, and can display the experimental results in real time, thus realizing microsecond-level multi-channel separation synchronization test in a low-cost manner. Attached Figure Description

[0047] Figure 1 This is an overall structural diagram of the separation synchronization test device described in this invention;

[0048] Figure 2 This is a circuit diagram of the separate monitoring channel described in this invention;

[0049] Figure 3 This is a schematic diagram illustrating the principle of the interrupt function;

[0050] Figure 4 This is a flowchart illustrating the process after an interruption is detected in the separation synchronization test method described in this invention.

[0051] Figure 5 This is the main flowchart of the separation synchronization test method described in this invention;

[0052] Figure 6 This is an example graph of the fitting curve of the test data obtained by the present invention;

[0053] Figure 7 This is the first result of the separation synchronization test obtained from an embodiment of the present invention;

[0054] Figure 8 This is the second result of the separation synchronization test obtained from the embodiment of the present invention;

[0055] The markings in the diagram are as follows:

[0056] 1. Communication interface; 2. Programming interface; 3. Separate monitoring channel; 4. System restart interface; 5. Power-on control interface; 6. Switch module; 61. Control interface; 62. Power output interface; 63. Power input interface; 7. Communication chip; 8. STM32 chip. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0058] In the description of this application, it should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. For ease of description, techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0059] It should be noted that the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0060] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0061] like Figure 1 As shown, a microsecond-level multi-channel separation synchronization test device based on an STM32 chip includes:

[0062] STM32 chip 8;

[0063] Multiple separate monitoring channels 3 based on STM32 chip 8, such as Figure 2 As shown, the separation monitoring channel 3 includes a charging power supply VDD, a resistor R, and a capacitor C connected in series. The other end of the capacitor C is grounded. A GPIO interface is set between the resistor R and the capacitor C. The GPIO interface is connected to the external interrupt pin of the STM32 chip 8. One part of the separation monitoring point in the separation body is connected between the resistor R and the capacitor C, and the other part is connected between the capacitor C and the ground point of the capacitor C. It is ensured that the two parts of the separation monitoring point in the separation body can be connected. During the separation process, the test device can obtain the total time from power-on to separation of the two parts of the separation monitoring point in the separation body according to the voltage change of the capacitor C.

[0064] The power-on control interface 5 includes two pins for connecting to the switch module 6: a signal transmission pin and a GND pin. The signal transmission pin is used to send a control signal to the switch module 6, which triggers the switch module 6 to perform corresponding actions, such as turning the circuit on or off. The GND pin is the reference zero potential point in the circuit, used to ensure that the control signal output by the signal transmission pin has a stable reference potential, thereby ensuring the accuracy and reliability of the control signal.

[0065] The switch module 6 includes a control interface 61, a power input interface 63, and a power output interface 62. The control interface 61 is connected to the signal transmission pin in the power-on control interface 5. The power input interface 63 and the power output interface 62 are connected. The power input interface 63 is connected to an external constant current power supply. The power output interface 62 is connected to the power input interface of the device under test. The control interface 61 receives control signals sent by the signal transmission pin to determine whether to open or close the circuit path between the power input interface 63 and the power output interface 62, thereby controlling the power supply on and off through the switch module 6.

[0066] In addition, the communication chip 7 and the communication interface 1 are connected in sequence. The STM32 chip 8, the communication chip 7 and the communication interface 1 are connected in sequence. The communication interface 1 can communicate with the computer host via the USB interface through serial port, receive instructions from the computer host or send information to the computer host.

[0067] In addition, the STM32 chip 8 is also connected to the power control interface 5 and the switch module 6. The STM32 chip 8 can control the power-on status of the separation monitoring points in the separation body during the test, and acquire power-on status parameters, such as power-on and power-off time.

[0068] As some examples of the present invention, the communication interface 1 is a serial communication module built using the CP2102 chip.

[0069] Generally, the STM32 chip 8 contains multiple external interrupt pins, and the multiple separate monitoring channels 3 can be connected to different external interrupt pins to form a multi-channel, such as an 8-channel separation synchronization test device.

[0070] As some examples of the present invention, the STM32 chip 8 can be an STM32 series chip, such as the STM32F103C8T6 chip, the STM32F103RCT6 chip, etc.

[0071] Preferably, the STM32 chip 8 is an STM32F103C8T6 chip, which can reduce costs while meeting performance requirements.

[0072] The working process and principle of the separation monitoring channel 3 are illustrated below with examples:

[0073] like Figures 1-2 As shown, the two input ports in the separation monitoring channel 3 are respectively connected to the two parts Part1 and Part2 of the separation monitoring point in the object to be separated, and it is ensured that the two parts Part1 and Part2 can be connected. The GPIO (General-Purpose Input / Output) interface is connected to the external interrupt pin of the STM32 chip.

[0074] Based on this, the process of obtaining the total time from energization to separation in this invention is as follows: When the two parts of the separation monitoring point in the receiving separation body are in a connected state, the voltage of capacitor C between the two inlets connected to Part1 and Part2 is 0. After the two parts of the separation monitoring point in the receiving separation body are separated, the circuit is broken, and capacitor C is charged under the action of charging power supply VDD and resistor R. The voltage gradually increases, and the increase process satisfies the RC charging law, that is, the voltage of capacitor C V=V0*(1-e (-t / RC) ), where V is the voltage of capacitor C at time t, V0 is the voltage of charging power supply VDD, which is the stable voltage value of capacitor C after charging is completed. In this invention, the value of V0 is preferably 5V, e is the base of the natural logarithm, t is time, t represents the time elapsed from the start of charging to the current time, and RC is the time constant of the circuit, which is determined by the product of resistance R and capacitor C.

[0075] When the voltage of capacitor C rises to the trigger voltage of the external interrupt of STM32 chip 8 (typically 0.7 times V0; when V0 = 3.3V, the trigger voltage is 2.31V), STM32 chip 8 automatically executes the external interrupt program. In the external interrupt program, the controller of STM32 chip 8 reads the current time and calculates the total time taken from power-on to separation of the two parts of the separation monitoring point in the connected separation body by calculating the interval between the current time and the power-on start time.

[0076] Furthermore, the microsecond-level multi-channel separation synchronization test device also includes:

[0077] Programming interface 2 is an interface led out from the program download pin of the STM32 chip 8. Generally, a common ST-Link programmer can be used for code programming.

[0078] Furthermore, the microsecond-level eight-channel separation synchronization test device also includes:

[0079] System restart interface 4 is an interface led out from the restart pin of STM32 chip 8. System restart interface 4 is connected to an external mechanical restart button. Pressing the mechanical restart button will restart the system.

[0080] Furthermore, in the switch module 6, the control interface 61 includes two pins, namely a signal receiving pin and a GND pin; the power input interface 63 includes two pins, which are respectively connected to the positive and negative terminals of an external constant current power supply; the power output interface 62 includes two pins, which are respectively connected to the positive and negative terminals of an external load.

[0081] As some examples of the present invention, the switch module 6 can use commercially available switch modules, which control the opening and closing of the circuit through optocouplers and MOSFETs. After the control interface 61 receives the open signal sent by the power-on control interface 5, the switch opens and the external load is powered by the power supply. After receiving the close signal sent by the power-on control interface 5, the switch closes and the external load is disconnected from the power supply.

[0082] Furthermore, before use, connect the communication interface 1 to the USB interface on the computer host, connect the system restart interface 4 to the external mechanical restart button, connect the power control interface 5 to the control interface 61 of the switch module 6, connect the power input interface 63 to the external constant current source, connect the power output interface 62 to the power input interface of the external connection separation mechanism, and connect some or all of the channels used in the separation monitoring channel 3 to the separation monitoring point.

[0083] Furthermore, each detection allows the use of some or all of the multiple separation monitoring channels 3. Before use, some or all of the channels used in the separation monitoring channels 3 are respectively connected to the corresponding separation monitoring points.

[0084] It should be noted that before use, an existing program needs to be programmed into the test device through the program programming interface 2. This process only needs to be done once and does not need to be repeated in subsequent uses.

[0085] As some examples of the present invention, the STM32 chip 8 further includes:

[0086] Memory, which is used to store computer programs;

[0087] When the processor executes the program stored in the memory, it implements the microsecond-level multi-channel separation synchronization test method based on the STM32 chip provided by this invention.

[0088] The external interrupt principle involved in the STM32 chip 8 described in this invention is as follows: Figure 3 As shown, during the execution of the main function of the STM32 chip 8, the external interrupt pin captures the separation signal, triggers an interrupt, pauses the execution of the main function, maintains the current state, executes the interrupt function content, and then continues the execution of the main function after the interrupt function is completed.

[0089] Furthermore, this invention also provides a microsecond-level multi-channel separation synchronization test method based on an STM32 chip. This test method is used in the aforementioned microsecond-level multi-channel separation synchronization test device based on an STM32 chip, such as... Figure 4 As shown, the microsecond-level multi-channel separation synchronization test method based on the STM32 chip includes the following steps:

[0090] S1, During the test, when a certain separation monitoring channel 3 is interrupted, step S2 is executed;

[0091] S2, the STM32 chip automatically enters the interrupt function of this channel. Simultaneously, after a set delay t1 (preferably 1-10µs), the test device determines whether the separation monitoring point has separated. The determination is based on the following: if the corresponding separation monitoring point has separated, capacitor C is at a high level; otherwise, capacitor C is at a low level. This is done because the present invention uses a capacitor integrating circuit, which, although capable of absorbing voltage fluctuations during the separation process, may still trigger false triggers. By delaying and then determining the level, if it is a false trigger, the level is low; if separation has occurred, the level is high, resulting in higher accuracy.

[0092] S3. If the corresponding separation monitoring point has been separated, obtain the current time and execute step S4; otherwise, end the monitoring of this channel.

[0093] S4, change the separation flag of the separation monitoring channel 3 to indicate that the separation monitoring channel 3 has been completed and end the monitoring of the channel.

[0094] Generally, in step S2, the high and low levels for the capacitor C are set according to specific circumstances or experiments.

[0095] As some examples of the present invention, in step S2, when the supply voltage is 3.3V, for the capacitor C, capacitor C with a voltage of 0.7*3.3V or higher is at a high level, and capacitor C with a voltage of 0.3*3.3V or lower is at a low level.

[0096] Furthermore, for connected and separated entities that use an unlocker and are unlocked through a mechanical linkage, the microsecond-level multi-channel separation synchronization test method based on the STM32 chip includes step S3 located between steps S3 and S4. + Step S3 + include:

[0097] S3 + If the corresponding separation monitoring point has been separated, then determine whether the separation monitoring channel 3 is the main channel. The main channel refers to the channel connected to the micro switch inside the unlocker. If it is, then control the switch module 6 to disconnect the current output. If not, then treat the separation monitoring channel as a normal monitoring channel, obtain the current time, change the separation flag, and then end.

[0098] Furthermore, the microsecond-level multi-channel separation synchronization test method based on the STM32 chip also includes:

[0099] Upon receiving experimental data from the user, the program burned into the STM32 chip 8 automatically determines the format of the experimental data. Once the information format is correct, a power-on message is sent to the switch module 6 to start powering on and perform a separation synchronization test.

[0100] Furthermore, after the separation synchronization test begins, the controller of the STM32 chip 8 periodically sends the channel numbers that have not yet been separated according to a set cycle. The duration of the cycle can be set according to actual needs, such as several milliseconds or several seconds. By periodically sending the channel numbers that have not yet been separated, the test progress can be understood in a timely manner.

[0101] Furthermore, after the separation synchronization test begins, the controller of the STM32 chip 8 monitors the test time. Once all separation monitoring channels 3 used by the user have completed separation, or once the maximum test time set by the system is reached, the system automatically terminates and sends the separation results for each channel: separation time or no separation. Then the next experiment can begin.

[0102] As examples of this invention, when inputting experimental parameters to the device via a serial port host computer on the computer, the first parameter is the number of channels used, the second parameter is the main channel number, and the following numbers are the numbers of other channels used, the quantity of which must correspond to the first parameter. One of the last two parameters is the maximum power-on time, measured in milliseconds. The maximum power-on time specifies the maximum permissible power-on time in the event that the microswitch fails to trigger due to an accident in the connection / separation mechanism. Setting the maximum power-on time prevents over-powering problems caused by accidents. The other of the last two parameters is the maximum test time, measured in seconds. The maximum test time specifies the maximum waiting time if all separation test points are not completely separated. If all separations have occurred, the waiting period automatically ends.

[0103] In this invention, for a connection and separation body that uses an unlocker and is unlocked by mechanical linkage, the channel connected to the micro switch inside the unlocker is defined as the main channel, and the monitoring channels of other separation points are defined as other channels. In actual operation, the separation points can be set freely by the user. It is only necessary to ensure that the two inputs of each channel in the separation monitoring channel 3 can be connected and conductive when connected, and can be disconnected simultaneously after separation.

[0104] The following example illustrates the microsecond-level multi-channel separation synchronization test method based on the STM32 chip described in this invention, using the task of separating the satellite and rocket by combining a single connection and separation mechanism with a linkage mechanism as an example:

[0105] This example uses an unlocker to lock the connection of the entire connecting and separating body through mechanical linkage. When the unlocker is powered on, it unlocks, and the internal micro switch changes its switching state accordingly. The device begins to move linearly or rotate under the action of the spring, which actuates the entire device to achieve separation. The separation area is large, and the separation status of multiple measurement points needs to be monitored simultaneously.

[0106] After testing according to the above-described microsecond-level multi-channel separation synchronization test device and method based on STM32 chip, the results are as follows: Figures 7-8 As shown:

[0107] The testing device uses eight external interrupt channels of the STM32F103C8T6 chip to achieve synchronous monitoring of eight separation monitoring points. After each separation monitoring channel 3 is triggered, two steps are performed: waiting for the separation signal to stabilize and obtaining the separation time. This process takes about 7us. If other channels are triggered at this time, they will be suspended and wait. This is the main source of error in this invention.

[0108] Analysis of the actual test results yielded the following: Figure 7As shown, when the separation interval between the two channels is in the tens of microseconds, the separation synchronization measurement error is only 0.4 microseconds (wherein, the oscilloscope shows a separation time difference of 91.6 microseconds between the two channels, and the test device described in this invention shows a separation time difference of 92 microseconds between the two channels); in addition, as Figure 8 As shown, when the separation interval between the two channels is 10µs, the separation synchronization measurement error is approximately 1.2µs (wherein, the oscilloscope shows a separation time difference of 9.8µs between the two channels, and the test device described in this invention shows a separation time difference of 11µs between the two channels).

[0109] In the most extreme case, if all eight channels trigger simultaneously, the maximum time interval between the first and last triggered channel would be approximately 7 × 7 = 49 µs. For a 300 ms separation experiment, this 49 µs error represents about 1 / 6,000 of the total separation time. However, in actual separation experiments, due to factors such as manufacturing errors and insufficient part consistency, the separation time interval between different channels is much greater than 10 µs. Common synchronization requirements are in the millisecond range. Therefore, the measurement error for separation synchronization can be reduced to within 2 µs.

[0110] Furthermore, in this invention, the STM32 chip 8 used in the testing device operates at a frequency of 72MHz and has a timing accuracy of 1µs. The use of pull-up resistors R combined with integrating capacitors C can absorb voltage jumps caused by multiple contacts during separation, preventing misjudgments. The device can respond within 10µs of the separation monitoring point completing the separation and record the separation time, such as... Figure 6 As shown, the measurement error of separation time increases linearly with the extension of test time. By measuring the change of error with test time in advance and compensating for the measurement results, the separation time monitoring error can be reduced to less than 10µs.

[0111] After the separation action is completed by powering on the connection and separation body, the main channel monitoring its separation status transmits the information to the controller of the STM32 chip 8. The controller sends a command to stop the power supply to the switch module 6, and the switch module 6 cuts off the current output. The entire process takes less than 100us and is carried out automatically, which can effectively prevent over-powering and extend the service life of the connection and separation mechanism.

[0112] In summary, the microsecond-level multi-channel separation synchronization test device and method based on the STM32 chip integrates automated experimental control and multi-channel separation time monitoring functions, and has the following advantages:

[0113] (3) The present invention realizes the automated control of the connection and separation mechanism experiment. Unlocking immediately cuts off the power, which can effectively prevent the overcharging of SAM wire and extend its service life.

[0114] (4) The present invention achieves high time accuracy monitoring of a single connection separation point with a measurement error of less than 10 μs, which has the advantage of high accuracy;

[0115] (3) This invention integrates multi-channel separation synchronization monitoring, realizing separation synchronization monitoring of multiple separation points, and the synchronization error in actual use is less than 2µs;

[0116] In summary, the microsecond-level multi-channel separation synchronization test device and method based on STM32 chip described in this invention improves the automation level and time monitoring accuracy of the test system, enables closed-loop control of the experiment, and can display the experimental results in real time, thus realizing microsecond-level multi-channel separation synchronization test in a low-cost manner.

[0117] The embodiments of this application have been described above with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. This application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A microsecond multi-channel separation synchronization test device based on an STM32 chip, characterized in that, It comprises: an STM32 chip (8); a plurality of separation monitoring channels (3) based on the STM32 chip (8), each of which comprises a charging power supply VDD, a resistor R and a capacitor C connected in series, the other end of the capacitor C being grounded, a GPIO interface being arranged between the resistor R and the capacitor C, the GPIO interface being connected to an external interrupt pin of the STM32 chip (8), one part of a separation monitoring point in a connection separation body being connected between the resistor R and the capacitor C, and the other part of the separation monitoring point being connected between the capacitor C and the ground of the capacitor C, and the two parts of the separation monitoring point being ensured to be conductive, and in the separation process, the total time from power-on to separation of the two parts of the separation monitoring point in the connection separation body can be obtained according to the voltage change of the capacitor C; a switch module (6) connected to a power input interface of the connection separation body to be tested; a power-on control interface (5) capable of controlling the switch module (6) to turn on or off the circuit; a communication chip (7) and a communication interface (1), the STM32 chip (8), the communication chip (7) and the communication interface (1) being connected in series, and the communication interface (1) being capable of performing serial communication with a computer host through a USB interface to receive instructions from the computer host or send information to the computer host; the STM32 chip (8) is further connected to the power-on control interface (5) and the switch module (6), and the STM32 chip (8) is capable of controlling the power-on state of the separation monitoring point in the connection separation body in the test process and obtaining the power-on state parameters.

2. The microsecond-level multi-channel separation synchronization test device according to claim 1, wherein when the two parts of the separation monitoring point in the connection separation body are in a connected state, the voltage of the capacitor C is 0; after the two parts of the separation monitoring point in the connection separation body are separated, the circuit is disconnected, the capacitor C is charged under the action of the charging power supply VDD and the resistor R, and the voltage gradually rises; when the voltage of the capacitor C rises to the trigger voltage of the external interrupt of the STM32 chip (8), the STM32 chip (8) automatically executes the external interrupt program, in which the controller of the STM32 chip (8) reads the current time and obtains the total time from power-on to separation of the two parts of the separation monitoring point in the connection separation body by calculating the interval between the current time and the power-on start time.

3. The microsecond-level multi-channel separation synchronization test device according to claim 1, wherein, The microsecond-level multi-channel separation synchronization test device further comprises: a program burning interface (2) connected to a program download pin of the STM32 chip (8), and before use, the test device needs to be pre-burned with an existing program through the program burning interface (2); a system restart interface (4) connected to a restart pin of the STM32 chip (8), and the system restart interface (4) is externally connected to a mechanical restart button, and the system can be restarted by pressing the mechanical restart button.

4. The microsecond-level multi-channel separation synchronization test device according to claim 1, wherein, The microsecond-level multi-channel separation synchronization test device further comprises: Each detection allows using part or all of the plurality of separation monitoring channels (3), and before use, part or all of the separation monitoring channels (3) used are respectively connected with the corresponding separation monitoring points.

5. A microsecond multi-channel separation synchronization test method, characterized in that, The test method is used for the microsecond multi-channel separation synchronization test device in any one of the above claims 1-4, and the test method comprises the steps of: S1, during the test, when the interruption of a separation monitoring channel is triggered, step S2 is performed; S2, the STM32 chip automatically enters the interruption function of the channel, and at the same time, the test device delays for a set time t1, and then judges whether the separation monitoring point has been separated or not, and the judgment basis is that if the corresponding separation monitoring point has been separated, the capacitor C is high level, otherwise the capacitor C is low level; S3, if the corresponding separation monitoring point has been separated, the current time is obtained, and step S4 is performed; if not, the monitoring of the channel is ended; S4, the separation flag of the separation monitoring channel is changed to indicate that the separation monitoring channel has completed separation, and the monitoring of the channel is ended.

6. The microsecond-level multi-channel separation synchronization test method according to claim 5, characterized in that, When the connection separator to be tested is a connection separator unlocked by mechanical structural linkage using an unlocker, the test method further comprises a step S3 between steps S3 and S4 + , the step S3 + comprises: S3 + If the corresponding separation monitoring point has been separated, it is determined whether the separation monitoring channel is a main channel, wherein the main channel refers to a channel connected with a micro switch inside the unlocking device. If yes, the switch module is controlled to disconnect the current output. If no, the separation monitoring channel is regarded as a common monitoring channel, and the current time is obtained, the separation flag is changed, and the process ends.

7. The microsecond-level multi-channel separation synchronization test method according to claim 5, characterized in that, The test method further comprises: When receiving the experimental data sent by the user, the program burned in the STM32 chip automatically judges the format of the experimental data, and after the information format is correct, sends the information of starting power-on to the switch module, starts power-on, and performs separation synchronization test.

8. The microsecond-level multi-channel separation synchronization test method according to claim 7, characterized in that, The test method further comprises: after starting the separation synchronization test, the controller of the STM32 chip regularly sends the channel numbers that have not been separated according to the set period.

9. The microsecond-level multi-channel separation synchronization test method according to claim 7, characterized in that, The test method further comprises: after starting the separation synchronization test, the controller of the STM32 chip monitors the test time, and after all the separation monitoring channels used by the user are separated, or after the maximum test time set by the system is reached, the system automatically ends and sends the separation results of each channel.

10. The microsecond-level multi-channel separation synchronization test method according to claim 5, wherein, The test method further comprises: After the unlocking device is powered on and the separation action is completed, the STM32 chip sends a stop power supply instruction to the switch module, and the switch module cuts off the current output.

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