Method for continuously outputting test signals of digital signal tester
By designing an internal controller in a digital signal tester to quickly diagnose the test results and using multi-threaded cycles to send the test signal, the problem that traditional tester signals cannot be continuously output is solved, and efficient continuous output of test signals and low resource usage is achieved.
Patent Information
- Application Number
- CN202510273213.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2025-05-13
AI Technical Summary
When traditional digital signal testers conduct the stability and repetition test of the chip being tested, the test signal cannot achieve continuous and uninterrupted output, resulting in inefficient testing. The software consumes a lot of time and occupies a lot of CPU resources.
Design a method for continuous output of digital signal testers. The internal controller quickly diagnoses the test result status and uses multi-threaded loops to send the test signal to avoid being occupied by the main thread and realizes continuous output of the signal.
It realizes uninterrupted continuous output of test signals, shortens the test interval time, improves test efficiency, and reduces the use of system resources.
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Figure CN119986331A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of digital signal testers, and in particular relates to a method for testing continuous output of a signal by a digital signal tester. Background Art
[0002] Digital signal tester is the core equipment in digital, mixed analog and microwave integrated circuit test system, providing test environment for digital and mixed signal integrated circuit (IC) design, verification and production. Digital signal tester mainly generates digital test vector signals, or digital stimulus signals, composed of 0 (low level), 1 (high level), X (not driven), L (expected low level), H (expected high level), etc. On the one hand, it can provide multi-channel dynamic digital test vector signals for the tested integrated circuit, and on the other hand, it can collect the response signal of the tested integrated circuit to determine whether the integrated circuit has faults.
[0003] In the actual applications of integrated circuit testing systems such as chip design, chip manufacturing and chip testing, digital signal testers need to continuously and repeatedly send digital excitation signals, and the chip under test repeatedly receives the digital excitation signals to perform a large number of repetitive indicator tests, and judge whether the chip functions and indicators are normal based on the test results of each test.
[0004] In the traditional method of stability testing of the chip under test, after each time the digital signal tester sends a test vector signal, it determines whether the test result is correct, and determines whether to continue to send the test signal repeatedly based on the test result. The test interval between each test signal is long, and the test signal cannot be output continuously and uninterruptedly, which cannot meet the requirements of stability and repeatability testing of the chip under test. Moreover, the traditional method uses software to judge the status of the test result. The process of software reading the test result consumes a lot of time, resulting in a long interval between each cycle of sending the signal, which is inefficient. When using traditional testing methods, it is necessary to constantly poll whether the test result is correct, which consumes a lot of CPU resources and occupies a lot of system resources. Summary of the invention
[0005] In view of the various shortcomings of the prior art, the inventors have researched and designed a method for continuous output of test signals of a digital signal tester through long-term practice. The method does not require host computer software to query the test results, can achieve uninterrupted continuous output of test signals, and the internal controller can quickly diagnose the test result status, avoiding the consumption of a large amount of CPU resources and occupying less system resources.
[0006] A method for testing continuous output of a signal by a digital signal tester of the present invention is as follows:
[0007] Step 1: Set the digital signal tester to signal continuous output mode.
[0008] Step 2: Set the test signal continuous output mode to any of the three modes: stop loop upon test success, stop loop upon test failure, or stop loop upon receipt of stop signal.
[0009] Step 3: In the test success stop cycle and test failure stop cycle mode, after the signal is sent once, the internal controller of the digital signal tester determines whether the test result is correct. According to the test result and the selected test signal continuous output mode, it decides to continue to send the test signal repeatedly; or trigger an interrupt signal to stop the continuous output of the test signal.
[0010] In the stop cycle mode, after the signal is sent, the test result is not judged and the signal is sent repeatedly. After receiving the external stop signal, the interrupt signal is triggered and the test signal stops continuous output.
[0011] A multi-threaded method is used to send test signals in a loop, and the signal sending, waiting for interrupt signals, signal stopping, etc. in the digital signal sending process are placed in a new thread to avoid causing the main thread to be unable to respond to other operations.
[0012] Furthermore, in the test success stop cycle mode, the method for continuously outputting the test signal comprises the following sub-steps:
[0013] Sub-step 3.1.1: Select the loop mode as Stop loop after successful test, set the maximum number of loops according to the test requirements, and force stop the loop when the maximum number of loops is reached.
[0014] Sub-step 3.1.2: Send the test vector signal once and wait for the test vector signal to be sent. When the test vector executes to the test vector where the halt vector opcode is located, the signal sending ends and the test vector remains in the state of the last test vector. The halt vector opcode indicates that the test vector will no longer send the test vector when it is executed to this position and will maintain the current vector state.
[0015] Sub-step 3.1.3: After the single transmission of the test vector signal is completed, the internal controller determines whether the current number of cycles has reached the maximum number of cycles. If the maximum number of cycles has been reached, the continuous output of the signal ends; if the maximum number of cycles has not been reached, a determination is made as to whether the test is successful;
[0016] Sub-step 3.1.4: The internal controller of the digital signal tester reads the status of the test result status flag to quickly diagnose whether the test is successful. If the test fails, the test data is not saved and processed to reduce the time consumption of processing the test result information. The internal controller jumps to the signal sending instruction and resends the test vector signal; if the test is successful and the conditions for stopping the continuous output of the test vector signal are met, the internal controller saves and further processes the test data.
[0017] Sub-step 3.1.5: After the test is successful, the internal controller triggers an interrupt signal. After the host computer software receives the interrupt signal, the signal continuous output ends. The host computer reads the test result information stored in the digital signal tester to further analyze the repeatability and stability of the tested device.
[0018] Furthermore, in the test failure stop cycle mode, the method for continuously outputting the test signal comprises the following sub-steps:
[0019] Sub-step 3.2.1: Select the loop mode as Stop loop on test failure, set the maximum number of loops according to the test requirements, and force the loop to stop when the maximum number of loops is reached.
[0020] Sub-step 3.2.2: Send the test vector signal once and wait for the test vector signal to be sent. When the test vector executes the test vector where the halt vector opcode is located, the signal sending ends and the test vector remains in the state of the last test vector.
[0021] Sub-step 3.2.3: After the single transmission of the test vector signal is completed, determine whether the current number of cycles has reached the maximum number of cycles. If the maximum number of cycles has been reached, directly jump to the end of the continuous output of the signal; if the maximum number of cycles has not been reached, determine whether the test is successful.
[0022] Sub-step 3.2.4: The internal controller of the digital signal tester reads the status of the test result status flag and quickly diagnoses whether the test is successful. If the test is successful, the test data is not saved and processed to reduce the time consumption of processing the test result information, and the internal controller resends the test vector signal. If the test fails and the conditions for stopping the continuous output of the test vector signal are met, the internal controller saves and further processes the test data.
[0023] Sub-step 3.2.5: After the test fails, the internal controller triggers an interrupt signal. After the host computer software receives the interrupt signal, the host computer reads the detailed test result information stored in the digital signal tester, and the signal continuous output ends. The host computer reads the test result information stored in the digital signal tester to further analyze the repeatability and stability of the DUT.
[0024] Further, in the stop cycle mode when a stop signal is received, the method for continuously outputting the test signal comprises the following sub-steps:
[0025] Sub-step 3.3.1: Select the loop mode to stop the loop upon receiving the stop signal and send the test vector signal once.
[0026] Sub-step 3.3.2: The internal controller of the digital signal tester monitors in real time whether an external forced stop signal is received. If no forced stop signal is received, after the test vector signal is sent, the test result diagnosis is not performed and the test vector signal is sent repeatedly. If a forced stop signal is received, wait for the test vector signal to be executed.
[0027] Sub-step 3.3.3: After the execution of the test vector signal is completed, the internal controller triggers an interrupt signal. After the host computer software receives the interrupt signal, the host computer obtains whether the test is successful, reads the test result information stored in the digital signal tester, and the signal continuous output ends.
[0028] The beneficial effects of the present invention are:
[0029] 1) Continuous signal output: No need for host computer software to query test results, the test signal can be output continuously without interruption.
[0030] 2) Short test intervals and high test efficiency: According to the set operating mode, the internal controller quickly diagnoses the test result status without the need for host computer software intervention, saving the time consumed by software to determine the test result status.
[0031] 3) Occupies less system resources: The internal controller quickly diagnoses the test result status and performs corresponding operations according to the set mode, avoiding the problem of the host computer software constantly polling whether the test results are correct and consuming a lot of CPU resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 The present invention discloses a flow chart of the continuous output of signals of a digital signal tester.
[0033] Figure 2 It is a flowchart of the signal continuous output process in the test success stop cycle mode of the present invention.
[0034] Figure 3 It is a flowchart of the signal continuous output process in the test failure stop cycle mode of the present invention.
[0035] Figure 4 It is a flowchart of the continuous signal output in the cyclic mode when a stop signal is received by the present invention. DETAILED DESCRIPTION
[0036] The present invention will be further described in detail below in conjunction with the accompanying drawings and implementation examples. These implementation examples are described in sufficient detail so that those skilled in the art can understand and practice the present invention. Without departing from the spirit and scope of the present invention, logical, achievable and other changes may be made to the implementation. Therefore, the following detailed description should not be construed as limiting, and the scope of the present invention is limited only by the claims.
[0037] See also Figure 1 The present invention proposes a method for testing the continuous output of a signal by a digital signal tester, and the specific steps are as follows:
[0038] Step 1: Set the digital signal tester to signal continuous output mode.
[0039] Step 2: Set the test signal continuous output mode to any of the three modes: stop loop upon test success, stop loop upon test failure, or stop loop upon receipt of stop signal.
[0040] Step 3: In the test success stop cycle and test failure stop cycle mode, after the signal is sent once, the internal controller of the digital signal tester determines whether the test result is correct. According to the test result and the selected test signal continuous output mode, it decides to continue to send the test signal repeatedly; or trigger an interrupt signal to stop the continuous output of the test signal.
[0041] In the stop cycle mode, after the signal is sent, the test result is not judged and the signal is sent repeatedly. After receiving the external stop signal, the interrupt signal is triggered and the test signal stops continuous output.
[0042] Based on the state of the test result status flag bit read by the internal controller of the digital signal tester, the test result can be quickly diagnosed, thus avoiding the time consumption caused by the query and judgment of the host computer.
[0043] A multi-threaded method is used to send test signals in a loop, and the signal sending, waiting for interrupt signals, signal stopping, etc. in the digital signal sending process are placed in a new thread to avoid causing the main thread to be unable to respond to other operations.
[0044] See also Figure 2 , in the test success stop cycle mode, the method of continuous output of the test signal, the specific steps are as follows:
[0045] Sub-step 3.1.1: Select the loop mode as Stop loop after successful test, set the maximum number of loops according to the test requirements, and force stop the loop when the maximum number of loops is reached.
[0046] Sub-step 3.1.2: Send the test vector signal once and wait for the test vector signal to be sent. When the test vector executes to the test vector where the halt vector opcode is located, the signal sending ends and the test vector remains in the state of the last test vector. The halt vector opcode indicates that the test vector will no longer send the test vector when it is executed to this position and will maintain the current vector state.
[0047] Sub-step 3.1.3: After the test vector signal is sent once, the internal controller determines whether the current number of cycles has reached the maximum number of cycles. If the maximum number of cycles has been reached, the continuous output of the signal ends; if the maximum number of cycles has not been reached, a determination is made as to whether the test is successful.
[0048] Sub-step 3.1.4: The internal controller of the digital signal tester reads the status of the test result status flag to quickly diagnose whether the test is successful. If the test fails, the test data is not saved and processed to reduce the time consumption of processing the test result information. The internal controller jumps to the signal sending instruction and resends the test vector signal; if the test is successful and the conditions for stopping the continuous output of the test vector signal are met, the internal controller saves and further processes the test data.
[0049] Sub-step 3.1.5: After the test is successful, the internal controller triggers an interrupt signal. After the host computer software receives the interrupt signal, the signal continuous output ends. The host computer reads the test result information stored in the digital signal tester to further analyze the repeatability and stability of the tested device.
[0050] See also Figure 3 , in the test failure stop loop mode, the method of continuous output of the test signal, the specific steps are as follows:
[0051] Sub-step 3.2.1: Select the loop mode as Stop loop on test failure, set the maximum number of loops according to the test requirements, and force the loop to stop when the maximum number of loops is reached.
[0052] Sub-step 3.2.2: Send the test vector signal once and wait for the test vector signal to be sent. When the test vector executes the test vector where the halt vector opcode is located, the signal sending ends and the test vector remains in the state of the last test vector.
[0053] Sub-step 3.2.3: After the single transmission of the test vector signal is completed, determine whether the current number of cycles has reached the maximum number of cycles. If the maximum number of cycles has been reached, directly jump to the end of the continuous output of the signal; if the maximum number of cycles has not been reached, determine whether the test is successful.
[0054] Sub-step 3.2.4: The internal controller of the digital signal tester reads the status of the test result status flag to quickly diagnose whether the test is successful. If the test is successful, the test data is not saved and processed to reduce the time consumption of processing the test result information. The internal controller resends the test vector signal; if the test fails, the conditions for stopping the continuous output of the test vector signal are met, and the internal controller saves and further processes the test data.
[0055] Sub-step 3.2.5: After the test fails, the internal controller triggers an interrupt signal. After the host computer software receives the interrupt signal, the host computer reads the detailed test result information stored in the digital signal tester, and the signal continuous output ends. The host computer reads the test result information stored in the digital signal tester to further analyze the repeatability and stability of the DUT.
[0056] See also Figure 4 , in the stop signal stop cycle mode, the method of testing the continuous output of the signal, the specific steps are as follows:
[0057] Sub-step 3.3.1: Select the loop mode to stop the loop upon receiving the stop signal and send the test vector signal once.
[0058] Sub-step 3.3.2: The internal controller of the digital signal tester monitors in real time whether an external forced stop signal is received. If no forced stop signal is received, after the test vector signal is sent, the test result diagnosis is not performed and the test vector signal is sent repeatedly; if a forced stop signal is received, wait for the test vector signal to be executed.
[0059] Sub-step 3.3.3: After the execution of the test vector signal is completed, the internal controller triggers an interrupt signal. After the host computer software receives the interrupt signal, the host computer obtains whether the test is successful, reads the test result information stored in the digital signal tester, and the signal continuous output ends.
[0060] It is not possible to describe all possible combinations of components or methods for the purpose of describing the above-described embodiments, but it should be recognized by those skilled in the art that the various embodiments may be further combined and arranged. Therefore, the embodiments described herein are intended to cover all such changes, modifications and variations that fall within the scope of protection of the appended claims. In addition, with respect to the term "comprising" used in the specification or claims, the word is encompassed in a manner similar to the term "including," as explained by "including," used as a transitional word in the claims. In addition, any term "or" used in the specification of the claims is intended to mean "non-exclusive or."
Claims
1. A method for testing continuous output of a signal by a digital signal tester, characterized in that: The specific method is as follows: Step 1: Set the digital signal tester to signal continuous output mode; Step 2: Set the test signal continuous output mode to any of the three modes: stop loop after test success, stop loop after test failure, or stop loop after receiving stop signal; Step 3: In the test success stop cycle and test failure stop cycle modes, after the signal is sent once, the internal controller of the digital signal tester determines whether the test result is correct; based on the test result and the selected test signal continuous output mode, it decides to continue to send the test signal repeatedly, or trigger an interrupt signal to stop the continuous output of the test signal; In the stop cycle mode, after the signal is sent, the test result is not judged and the signal is sent repeatedly. After receiving the external stop signal, the interrupt signal is triggered and the test signal stops continuous output.
2. The method according to claim 1, characterized in that: The method for continuously outputting a test signal in the test success stop cycle mode comprises the following sub-steps: Sub-step 3.1.1: Select the loop mode as "Stop loop after successful test", set the maximum number of loops according to the test requirements, and force the loop to stop when the maximum number of loops is reached; Sub-step 3.1.2: Send the test vector signal once and wait for the test vector signal to be sent. When the test vector executes the test vector where the halt vector opcode is located, the signal sending is completed and the test vector remains in the state of the last test vector. The halt vector opcode indicates that the test vector will not be sent further after the test vector is executed to this position, and the current vector state will be maintained; Sub-step 3.1.3: After the single transmission of the test vector signal is completed, the internal controller determines whether the current number of cycles has reached the maximum number of cycles. If the maximum number of cycles has been reached, the continuous output of the signal ends; if the maximum number of cycles has not been reached, a determination is made as to whether the test is successful; Sub-step 3.1.4: The internal controller of the digital signal tester reads the status of the test result status flag bit to quickly diagnose whether the test is successful; if the test fails, the test data is not saved and processed to reduce the time consumption of processing the test result information, and the internal controller jumps to the signal sending instruction and resends the test vector signal; if the test is successful and the conditions for stopping the continuous output of the test vector signal are met, the internal controller saves and further processes the test data; Sub-step 3.1.5: After the test is successful, the internal controller triggers an interrupt signal. After the host computer software receives the interrupt signal, the signal continuous output ends; the host computer reads the test result information stored in the digital signal tester to further analyze the repeatability and stability of the device under test.
3. The method according to claim 1, characterized in that In the test failure stop cycle mode, the method for continuously outputting the test signal comprises the following sub-steps: Sub-step 3.2.1: Select the loop mode as Stop loop on test failure, set the maximum number of loops according to the test requirements, and force the loop to stop when the maximum number of loops is reached; Sub-step 3.2.2: Send the test vector signal once and wait for the test vector signal to be sent. When the test vector executes the test vector where the halt vector opcode is located, the signal sending is completed and the test vector remains in the state of the last test vector. Sub-step 3.2.3: After the single transmission of the test vector signal is completed, determine whether the current number of cycles has reached the maximum number of cycles; If the maximum number of cycles is reached, it will jump directly to the end of the continuous output of the signal; If the maximum number of cycles is not reached, determine whether the test is successful; Sub-step 3.2.4: The internal controller of the digital signal tester reads the status of the test result status flag bit to quickly diagnose whether the test is successful; if the test is successful, the test data is not saved and processed to reduce the time consumption of processing the test result information, and the internal controller resends the test vector signal; if the test fails and the conditions for stopping the continuous output of the test vector signal are met, the internal controller saves and further processes the test data; Sub-step 3.2.5: After the test fails, the internal controller triggers an interrupt signal. After the host computer software receives the interrupt signal, the host computer reads the detailed test result information stored in the digital signal tester, and the continuous output of the signal ends; the host computer reads the test result information stored in the digital signal tester to further analyze the repeatability and stability of the device under test.
4. The method according to claim 1, characterized in that: The method for continuously outputting a test signal in the stop cycle mode upon receiving a stop signal comprises the following sub-steps: Sub-step 3.3.1: Select the loop mode to stop the loop upon receiving the stop signal and send the test vector signal once; Sub-step 3.3.2: The internal controller of the digital signal tester monitors in real time whether an external forced stop signal is received; if no forced stop signal is received, after the test vector signal is sent, the test result diagnosis is not performed and the test vector signal is directly sent repeatedly; if a forced stop signal is received, the execution of the test vector signal is waited for to be completed; Sub-step 3.3.3: After the execution of the test vector signal is completed, the internal controller triggers an interrupt signal. After the host computer software receives the interrupt signal, the host computer obtains whether the test is successful, reads the test result information stored in the digital signal tester, and the signal continuous output ends.