Radar signal processing method

Abstract

The invention relates to signal processing, in particular to a radar signal processing method, which comprises the following steps that: a radar generates time sequences with different pulse widths according to the detection distance; for the short pulse time sequence, the radar adaptively adopts time domain pulse compression for processing to obtain pulse compression data of the short pulse; for a long pulse time sequence, the radar adaptively adopts frequency domain pulse compression for processing to obtain pulse compression data of a long pulse; splicing the pulse compression data of the short pulse and the pulse compression data of the long pulse together to obtain a group of combined pulse compression data aiming at the distance of the detection distance; according to the technical scheme provided by the invention, the defect that radar signals are difficult to process efficiently in the prior art can be effectively overcome.

Description

Technical Field

[0001] The invention relates to signal processing, and in particular to a radar signal processing method. Background Art

[0002] Digital pulse compression refers to the calculation process in which the radar transmits a wide pulse signal through the transmitter and obtains a narrow pulse after processing the received signal. It effectively solves the contradiction between the radar's detection range and distance resolution, and can improve the radar's distance resolution without reducing the radar's effectiveness.

[0003] Digital pulse compression uses digital signal processing methods to complete the relevant matched filtering, and has two implementation methods: time domain processing and frequency domain processing. Time domain processing is to directly perform convolution operations on the radar echo signal, while frequency domain processing is to first use FFT to calculate the spectrum of the radar echo signal, then multiply it with the frequency domain response of the matched filter, and finally perform IFFT operations to obtain the pulse compression results. For short pulse signals at close range, due to their short time width, the amount of calculation for processing using time domain pulse compression is relatively small, and there is no need for complex frequency domain transformation and inverse Fourier transform, and the real-time advantage is more obvious; for long pulse signals at long distances, the use of time domain pulse compression requires a large number of convolution operations in the time domain, which consumes a lot of hardware resources, while the use of frequency domain pulse compression converts the signal to the frequency domain through FFT, performs multiplication operations in the frequency domain, and then converts it back to the time domain through IFFT, which greatly reduces the amount of calculation.

[0004] In the invention patent application with application publication number CN106093942A, a high-resolution spaceborne SAR pulse compression method considering the squint effect is disclosed; in the invention patent application with application publication number CN110308427A, a frequency domain pulse compression processing method of LFM pulse radar based on FPGA is disclosed; in the invention patent application with application publication number CN102353940A, a pulse compression optimization method based on FPGA is disclosed. In the above patents, frequency domain pulse compression technology is adopted, and time domain pulse compression technology is not considered for short pulse signals, resulting in a large amount of calculation and difficulty in meeting real-time requirements. Summary of the invention

[0005] 1. Technical issues to be resolved

[0006] In view of the above-mentioned shortcomings of the prior art, the present invention provides a radar signal processing method, which can effectively overcome the defect of the prior art that it is difficult to efficiently process radar signals.

[0007] (II) Technical solution

[0008] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0009] A radar signal processing method comprises the following steps:

[0010] S1. The radar generates different pulse width timings according to the detection distance;

[0011] S2. For short pulse timing, the radar adaptively uses time domain pulse compression to process and obtain pulse compression data of short pulses;

[0012] S3. For long pulse timing, the radar adaptively uses frequency domain pulse compression to process and obtain pulse compression data of long pulses;

[0013] S4. The pulse compression data of the short pulse and the pulse compression data of the long pulse are spliced ​​together to obtain a set of combined pulse compression data for the detection distance.

[0014] Preferably, the radar in S1 generates a timing sequence of different pulse widths according to the detection distance, including:

[0015] S11, ADC collects the linear frequency modulated time domain signal x(t) with the intermediate frequency, and sends it to FPGA, removes the intermediate frequency in the linear frequency modulated time domain signal x(t) through digital down-conversion, and obtains the zero intermediate frequency baseband signal SS_DATA(t);

[0016] S12, FPGA generates different pulse width timings according to the detection distance, and processes the zero intermediate frequency baseband signal SS_DATA(t) accordingly according to the timings of different pulse widths;

[0017] Among them, the radar generates a short pulse width timing for short distances, and the short pulse widths include 1μs and 2μs; the radar generates a long pulse width timing for long distances, and the long pulse widths include 10μs and 20μs.

[0018] Preferably, in S11, removing the intermediate frequency in the linear frequency modulation time domain signal x(t) by digital down-conversion to obtain a zero intermediate frequency baseband signal SS_DATA(t) includes:

[0019] S111, after the digital down converter receives the linear frequency modulation time domain signal x(t), the numerically controlled oscillator NCO forms a cosine signal hi and a sine signal hq for mixing;

[0020] Among them, the expression of the linear frequency modulation time domain signal x(t) is:

[0021]

[0022] The expression of the cosine signal hi formed by the numerically controlled oscillator NCO for mixing is:

[0023] hi=cos(2πf0t)=cos(2πf0NT S );

[0024] The expression of the sinusoidal signal hq formed by the numerically controlled oscillator NCO for mixing is:

[0025] hq=-sin(2πf0t)=-sin(2πf0NT s );

[0026] t is time, T is pulse width, f0 is carrier frequency, K is frequency modulation slope, B is the bandwidth of the linear frequency modulation time domain signal, B = 20MHz, N is the number of sampling points in a pulse repetition period, a pulse repetition period is 100μs or 200μs, T s is the inverse of the sampling frequency;

[0027] S112, multiplying the linear frequency modulation time domain signal x(t) by the cosine signal hi, performing mixing, and obtaining the real component Xi(t) of the linear frequency modulation time domain signal x(t) after orthogonal demodulation; multiplying the linear frequency modulation time domain signal x(t) by the sine signal hq, performing mixing, and obtaining the imaginary component Xq(t) of the linear frequency modulation time domain signal x(t) after orthogonal demodulation;

[0028] Among them, the expression of the real component Xi(t) of the linear frequency modulation time domain signal x(t) after orthogonal demodulation is:

[0029]

[0030] The expression of the imaginary component Xq(t) of the linear frequency modulation time domain signal x(t) after orthogonal demodulation is:

[0031]

[0032] S113, low-pass filtering is performed on the real component Xi(t) and the imaginary component Xq(t) of the linear frequency modulation time domain signal x(t) obtained after orthogonal demodulation to obtain the real component SI(t) and the imaginary component SQ(t) of the zero intermediate frequency baseband signal SS_DATA(t), respectively, and then the zero intermediate frequency baseband signal SS_DATA(t) is obtained;

[0033] Among them, the expression of the real component SI(t) of the zero intermediate frequency baseband signal SS_DATA(t) is:

[0034]

[0035] The expression of the imaginary component SQ(t) of the zero intermediate frequency baseband signal SS_DATA(t) is:

[0036]

[0037] The expression of zero intermediate frequency baseband signal SS_DATA(t) is:

[0038]

[0039] Preferably, in S2, for the short pulse sequence, the radar adaptively uses time domain pulse compression for processing to obtain pulse compression data of the short pulse, including:

[0040] S21, convolve the real component SI(t) and imaginary component SQ(t) of the zero intermediate frequency baseband signal SS_DATA(t) with the real component HI(t) and imaginary component HQ(t) of the matched filter time domain response signal HH_DATA(t), and obtain 4-way convolution results, namely SI_HI(t), SQ_HQ(t), SI_HQ(t), and SQ_HI(t);

[0041] Among them, the matched filter time domain response signal HH_DATA(t) is the time-inverted complex conjugate of the zero intermediate frequency baseband signal SS_DATA(t), and the expression of the matched filter time domain response signal HH_DATA(t) is:

[0042]

[0043] S22, subtract the two-way convolution results SI_HI(t) and SQ_HQ(t) to obtain the real part MI(t) of the pulse compression data DM_DATA(t) of the short pulse; sum the two-way convolution results SI_HQ(t) and SQ_HI(t) to obtain the imaginary part MQ(t) of the pulse compression data DM_DATA(t) of the short pulse, and then obtain the pulse compression data DM_DATA(t) of the short pulse;

[0044] The expression of the pulse compression data DM_DATA(t) of the short pulse is:

[0045]

[0046] The summation and difference operations are implemented by using Adder and Subtracter of the IP core Fixed_to_float that comes with the FPGA, respectively. Adder and Subtracter are instantiated as adders and subtractors, respectively.

[0047] Preferably, 8-way FIR Comlier cores are instantiated to form a matched filter, wherein 4-way FIR Comlier cores include a matched filter time domain response signal of a 1 μs short pulse, 2 of the 4-way FIR Comlier cores include a real component of the matched filter time domain response signal of a 1 μs short pulse, and the other 2 include an imaginary component of the matched filter time domain response signal of a 1 μs short pulse;

[0048] Another 4 FIR Comlier cores include the matched filter time domain response signal of the 2μs short pulse, 2 of which include the real component of the matched filter time domain response signal of the 2μs short pulse, and the other 2 include the imaginary component of the matched filter time domain response signal of the 2μs short pulse.

[0049] Preferably, in S3, for the long pulse sequence, the radar adaptively uses frequency domain pulse compression for processing to obtain pulse compression data of the long pulse, including:

[0050] S31, preprocessing the zero intermediate frequency baseband signal SS_DATA(t), and performing fast Fourier transform FFT to obtain an echo frequency domain signal FS_DATA(t);

[0051] S32, read the matched filter frequency domain response signal HS_DATA(t) pre-stored in the BRAM core inside the FPGA, and multiply it with the echo frequency domain signal FS_DATA(t) to obtain the filtered frequency domain signal FH_DATA(t);

[0052] S33, performing inverse fast Fourier transform IFFT on the filtered frequency domain signal FH_DATA(t) to obtain long pulse pulse compression data CM_DATA(t);

[0053] Among them, the expression of the pulse compression data CM_DATA(t) of the long pulse is:

[0054]

[0055] Preferably, the zero intermediate frequency baseband signal SS_DATA(t) is preprocessed in S31, including:

[0056] The 16-bit fixed-point number sampled by AD is converted into a 32-bit floating-point number using the IP core Fixed_to_float of the FPGA, so as to convert the zero intermediate frequency baseband signal SS_DATA(t) into a floating-point number.

[0057] Among them, the clock is consistent with the AD sampling clock, which is 250MHz. The fixed-point number is converted to a floating-point number while AD sampling. The floating-point number is delayed by two clock rising edges than the sampled fixed-point number.

[0058] Preferably, the IP core FastFourierTransform core of the FPGA, that is, the FFT core, is used to perform fast Fourier transform FFT and inverse fast Fourier transform IFFT. When the parameter s_axis_config_tdata of the FFT core is set to 1, the FFT core is used to perform fast Fourier transform FFT; when the parameter s_axis_config_tdata of the FFT core is set to 0, the FFT core is used to perform inverse fast Fourier transform IFFT.

[0059] When the long pulse width is 10 μs, the input data length of the FFT core is configured to be 2048, the input data width is 32 bits, and the input data format is floating point;

[0060] When the long pulse width is 20 μs, the input data length of the FFT core is configured to be 4096, the input data width is 32 bits, and the input data format is a floating point number.

[0061] Preferably, in S32, the matched filter frequency domain response signal HS_DATA(t) pre-stored in the BRAM core inside the FPGA is read, and multiplied with the echo frequency domain signal FS_DATA(t) to obtain the filtered frequency domain signal FH_DATA(t), including:

[0062] S321, multiplying the matched filter time domain response signal HH_DATA(t) by the window function data point, and performing a 2048-point fast Fourier transform FFT to obtain a matched filter frequency domain response signal HS_DATA(t);

[0063] S322, converting the matched filter frequency domain response signal HS_DATA(t) into a floating point number, and storing it in a coe file, and then storing the coe file in the BRAM core;

[0064] S323, reading the pre-stored matched filter frequency domain response signal HS_DATA(t) from the BRAM core, and performing complex multiplication with the echo frequency domain signal FS_DATA(t) to obtain a filtered frequency domain signal FH_DATA(t);

[0065] Among them, the expression of the filtered frequency domain signal FH_DATA(t) is:

[0066]

[0067] H i , H q are the real and imaginary components of the frequency domain response signal HS_DATA(t) of the matched filter, S i , S qare the real and imaginary components of the echo frequency domain signal FS_DATA(t) respectively;

[0068] The multiplication, summation and difference operations are implemented by using Multiply, Adder and Subtracter of the IP core Fixed_to_float of the FPGA, and Multiply, Adder and Subtracter are instantiated as multiplier, adder and subtractor respectively.

[0069] Preferably, in S4, the pulse compression data of the short pulse and the pulse compression data of the long pulse are spliced ​​together to obtain a set of combined pulse compression data for the detection distance, including:

[0070] S41, storing the pulse compression data DM_DATA(t) of the short pulse into the write buffer FIFO_DM, and storing the pulse compression data CM_DATA(t) of the long pulse into the write buffer FIFO_CM;

[0071] Among them, the write buffers FIFO_DM and FIFO_CM are the IP core FIFO Generator core that comes with the FPGA, that is, the FIFO core. The write clock of the FIFO core write data is set to be consistent with the pulse compression clock, and the read clock of the FIFO core read data is set to be consistent with the write clock. The data depth of the write buffer FIFO_DM is set to 512, and the read and write data widths are both 64 bits; the data depth of the write buffer FIFO_CM is set to 4096, and the read and write data widths are both 64 bits;

[0072] S42. When the write buffers FIFO_DM and FIFO_CM complete writing data, the trigger timing first reads the pulse compression data DM_DATA(t) of the short pulse written in the buffer FIFO_DM in sequence, and then reads the pulse compression data CM_DATA(t) of the long pulse written in the buffer FIFO_CM in sequence, thereby splicing the pulse compression data DM_DATA(t) of the short pulse and the pulse compression data CM_DATA(t) of the long pulse together to obtain a set of combined pulse compression data for the detection distance from near to far.

[0073] (III) Beneficial effects

[0074] Compared with the prior art, the radar signal processing method provided by the present invention adopts different pulse compression methods for timing adaptiveness of different pulse widths, greatly improves the computing efficiency without increasing hardware resources, realizes efficient processing of radar signals, and can better meet the real-time requirements of radar signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0076] Figure 1 It is a schematic diagram of the process of the present invention;

[0077] Figure 2 It is a schematic diagram of a process of obtaining a zero intermediate frequency baseband signal SS_DATA(t) by digital down-conversion in the present invention;

[0078] Figure 3 It is a schematic diagram of a process of obtaining pulse compression data of a short pulse by time-domain pulse compression in the present invention;

[0079] Figure 4 It is a schematic diagram of the process of obtaining pulse compression data of a long pulse by frequency domain pulse compression in the present invention. DETAILED DESCRIPTION

[0080] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0081] A radar signal processing method, such as Figure 1 As shown in S1, the radar generates different pulse width timings according to the detection distance, specifically including:

[0082] S11, ADC collects the linear frequency modulated time domain signal x(t) with the intermediate frequency, and sends it to FPGA, removes the intermediate frequency in the linear frequency modulated time domain signal x(t) through digital down-conversion, and obtains the zero intermediate frequency baseband signal SS_DATA(t);

[0083] S12, FPGA generates different pulse width timings according to the detection distance, and processes the zero intermediate frequency baseband signal SS_DATA(t) accordingly according to the timings of different pulse widths;

[0084] Among them, the radar generates a short pulse width timing for short distances, and the short pulse widths include 1μs and 2μs; the radar generates a long pulse width timing for long distances, and the long pulse widths include 10μs and 20μs.

[0085] Specifically, in S11, the intermediate frequency in the linear frequency modulation time domain signal x(t) is removed by digital down-conversion to obtain a zero intermediate frequency baseband signal SS_DATA(t), such as Figure 2 As shown, including:

[0086] S111, after the digital down converter receives the linear frequency modulation time domain signal x(t), the numerically controlled oscillator NCO forms a cosine signal hi and a sine signal hq for mixing;

[0087] Among them, the expression of the linear frequency modulation time domain signal x(t) is:

[0088]

[0089] The expression of the cosine signal hi formed by the numerically controlled oscillator NCO for mixing is:

[0090] hi=cos(2πf0t)=cos(2πf0NT S );

[0091] The expression of the sinusoidal signal hq formed by the numerically controlled oscillator NCO for mixing is:

[0092] hq=-sin(2πf0t)=-sin(2πf0NT s );

[0093] t is time, T is pulse width, f0 is carrier frequency, K is frequency modulation slope, B is the bandwidth of the linear frequency modulation time domain signal, B = 20MHz, N is the number of sampling points in a pulse repetition period, a pulse repetition period is 100μs or 200μs, T s is the inverse of the sampling frequency;

[0094] S112, multiplying the linear frequency modulation time domain signal x(t) by the cosine signal hi, performing mixing, and obtaining the real component Xi(t) of the linear frequency modulation time domain signal x(t) after orthogonal demodulation; multiplying the linear frequency modulation time domain signal x(t) by the sine signal hq, performing mixing, and obtaining the imaginary component Xq(t) of the linear frequency modulation time domain signal x(t) after orthogonal demodulation;

[0095] Among them, the expression of the real component Xi(t) of the linear frequency modulation time domain signal x(t) after orthogonal demodulation is:

[0096]

[0097] The expression of the imaginary component Xq(t) of the linear frequency modulation time domain signal x(t) after orthogonal demodulation is:

[0098]

[0099] S113, low-pass filtering is performed on the real component Xi(t) and the imaginary component Xq(t) of the linear frequency modulation time domain signal x(t) obtained after orthogonal demodulation to obtain the real component SI(t) and the imaginary component SQ(t) of the zero intermediate frequency baseband signal SS_DATA(t), respectively, and then the zero intermediate frequency baseband signal SS_DATA(t) is obtained;

[0100] Among them, the expression of the real component SI(t) of the zero intermediate frequency baseband signal SS_DATA(t) is:

[0101]

[0102] The expression of the imaginary component SQ(t) of the zero intermediate frequency baseband signal SS_DATA(t) is:

[0103]

[0104] The expression of zero intermediate frequency baseband signal SS_DATA(t) is:

[0105]

[0106] In the technical solution of this application, the FPGA adopts kintex-7 from Xilinx, and the analog-to-digital converter ADC adopts AD9467 from Analog Devices. AD9467 is a 16-bit, single-chip, intermediate frequency (IF) sampling analog-to-digital converter with a sampling rate of 250MHz.

[0107] S2. For short pulse timing, radar adaptively uses time domain pulse compression to obtain pulse compression data of short pulses, such as Figure 3 As shown, specifically including:

[0108] S21, convolve the real component SI(t) and imaginary component SQ(t) of the zero intermediate frequency baseband signal SS_DATA(t) with the real component HI(t) and imaginary component HQ(t) of the matched filter time domain response signal HH_DATA(t), and obtain 4-way convolution results, namely SI_HI(t), SQ_HQ(t), SI_HQ(t), and SQ_HI(t);

[0109] Among them, the matched filter time domain response signal HH_DATA(t) is the time-inverted complex conjugate of the zero intermediate frequency baseband signal SS_DATA(t), and the expression of the matched filter time domain response signal HH_DATA(t) is:

[0110]

[0111] S22, subtract the two-way convolution results SI_HI(t) and SQ_HQ(t) to obtain the real part MI(t) of the pulse compression data DM_DATA(t) of the short pulse; sum the two-way convolution results SI_HQ(t) and SQ_HI(t) to obtain the imaginary part MQ(t) of the pulse compression data DM_DATA(t) of the short pulse, and then obtain the pulse compression data DM_DATA(t) of the short pulse;

[0112] The expression of the pulse compression data DM_DATA(t) of the short pulse is:

[0113]

[0114] The summation and difference operations are implemented by using Adder and Subtracter of the IP core Fixed_to_float that comes with the FPGA, respectively. Adder and Subtracter are instantiated as adders and subtractors, respectively.

[0115] In the technical solution of the present application, 8 FIR Comlier cores are instantiated to form a matched filter, wherein 4 FIR Comlier cores include a matched filter time domain response signal of a 1 μs short pulse, 2 of the 4 FIR Comlier cores include a real component of the matched filter time domain response signal of a 1 μs short pulse, and the other 2 include an imaginary component of the matched filter time domain response signal of a 1 μs short pulse;

[0116] Another 4 FIR Comlier cores include the matched filter time domain response signal of the 2μs short pulse, 2 of which include the real component of the matched filter time domain response signal of the 2μs short pulse, and the other 2 include the imaginary component of the matched filter time domain response signal of the 2μs short pulse.

[0117] S3. For long pulse timing, radar adaptively uses frequency domain pulse compression to obtain pulse compression data of long pulses, such as Figure 4 As shown, specifically including:

[0118] S31, preprocessing the zero intermediate frequency baseband signal SS_DATA(t), and performing fast Fourier transform FFT to obtain an echo frequency domain signal FS_DATA(t);

[0119] S32, read the matched filter frequency domain response signal HS_DATA(t) pre-stored in the BRAM core inside the FPGA, and multiply it with the echo frequency domain signal FS_DATA(t) to obtain the filtered frequency domain signal FH_DATA(t);

[0120] S33, performing inverse fast Fourier transform IFFT on the filtered frequency domain signal FH_DATA(t) to obtain long pulse pulse compression data CM_DATA(t);

[0121] Among them, the expression of the pulse compression data CM_DATA(t) of the long pulse is:

[0122]

[0123] Specifically, in S31, the zero intermediate frequency baseband signal SS_DATA(t) is preprocessed, including:

[0124] The 16-bit fixed-point number sampled by AD is converted into a 32-bit floating-point number using the IP core Fixed_to_float of the FPGA, so as to convert the zero intermediate frequency baseband signal SS_DATA(t) into a floating-point number.

[0125] Among them, the clock is consistent with the AD sampling clock, which is 250MHz. The fixed-point number is converted to a floating-point number while AD sampling. The floating-point number is delayed by two clock rising edges than the sampled fixed-point number.

[0126] Specifically, in S32, the matched filter frequency domain response signal HS_DATA(t) pre-stored in the BRAM core inside the FPGA is read, and multiplied with the echo frequency domain signal FS_DATA(t) to obtain the filtered frequency domain signal FH_DATA(t), including:

[0127] S321, multiplying the matched filter time domain response signal HH_DATA(t) by the window function data point, and performing a 2048-point fast Fourier transform FFT to obtain a matched filter frequency domain response signal HS_DATA(t);

[0128] S322, converting the matched filter frequency domain response signal HS_DATA(t) into a floating point number, and storing it in a coe file, and then storing the coe file in the BRAM core;

[0129] S323, reading the pre-stored matched filter frequency domain response signal HS_DATA(t) from the BRAM core, and performing complex multiplication with the echo frequency domain signal FS_DATA(t) to obtain a filtered frequency domain signal FH_DATA(t);

[0130] Among them, the expression of the filtered frequency domain signal FH_DATA(t) is:

[0131]

[0132] H i , H qare the real and imaginary components of the frequency domain response signal HS_DATA(t) of the matched filter, S i , S q are the real and imaginary components of the echo frequency domain signal FS_DATA(t) respectively;

[0133] The multiplication, summation and difference operations are implemented by using Multiply, Adder and Subtracter of the IP core Fixed_to_float of the FPGA, and Multiply, Adder and Subtracter are instantiated as multiplier, adder and subtractor respectively.

[0134] In the technical solution of the present application, the IP core FastFourierTransform core of FPGA, that is, the FFT core, is used to perform fast Fourier transform FFT and inverse fast Fourier transform IFFT. When the parameter s_axis_config_tdata of the FFT core is set to 1, the FFT core is used to perform fast Fourier transform FFT; when the parameter s_axis_config_tdata of the FFT core is set to 0, the FFT core is used to perform inverse fast Fourier transform IFFT;

[0135] When the long pulse width is 10 μs, the input data length of the FFT core is configured to be 2048, the input data width is 32 bits, and the input data format is floating point;

[0136] When the long pulse width is 20 μs, the input data length of the FFT core is configured to be 4096, the input data width is 32 bits, and the input data format is a floating point number.

[0137] The BRAM core inside the FPGA is the SinglePortROM of the FPGA's built-in IP core Block Memory Generator, that is, the ROM core. The read and write data width of the BRAM core is set to 64 bits. The matched filter frequency domain response signal HS_DATA(t) in the BRAM core is generated by MATLAB.

[0138] S4. The pulse compression data of the short pulse and the pulse compression data of the long pulse are spliced ​​together to obtain a set of combined pulse compression data for the detection distance, specifically including:

[0139] S41, storing the pulse compression data DM_DATA(t) of the short pulse into the write buffer FIFO_DM, and storing the pulse compression data CM_DATA(t) of the long pulse into the write buffer FIFO_CM;

[0140] Among them, the write buffers FIFO_DM and FIFO_CM are the IP core FIFO Generator core that comes with the FPGA, that is, the FIFO core. The write clock of the FIFO core write data is set to be consistent with the pulse compression clock, and the read clock of the FIFO core read data is set to be consistent with the write clock. The data depth of the write buffer FIFO_DM is set to 512, and the read and write data widths are both 64 bits; the data depth of the write buffer FIFO_CM is set to 4096, and the read and write data widths are both 64 bits;

[0141] S42. When the write buffers FIFO_DM and FIFO_CM complete writing data, the trigger timing first reads the pulse compression data DM_DATA(t) of the short pulse written in the buffer FIFO_DM in sequence, and then reads the pulse compression data CM_DATA(t) of the long pulse written in the buffer FIFO_CM in sequence, thereby splicing the pulse compression data DM_DATA(t) of the short pulse and the pulse compression data CM_DATA(t) of the long pulse together to obtain a set of combined pulse compression data for the detection distance from near to far.

[0142] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A radar signal processing method, characterized in that: The following steps are involved: S1. The radar generates different pulse width timings according to the detection distance; S2. For short pulse timing, the radar adaptively uses time domain pulse compression to process and obtain pulse compression data of short pulses; S3. For long pulse timing, the radar adaptively uses frequency domain pulse compression to process and obtain pulse compression data of long pulses; S4. The pulse compression data of the short pulse and the pulse compression data of the long pulse are spliced ​​together to obtain a set of combined pulse compression data for the detection distance.

2. The radar signal processing method according to claim 1, characterized in that: The radar in S1 generates different pulse width timings according to the detection distance, including: S11, ADC collects the linear frequency modulated time domain signal x(t) with the intermediate frequency, and sends it to FPGA, removes the intermediate frequency in the linear frequency modulated time domain signal x(t) through digital down-conversion, and obtains the zero intermediate frequency baseband signal SS_DATA(t); S12, FPGA generates different pulse width timings according to the detection distance, and processes the zero intermediate frequency baseband signal SS_DATA(t) accordingly according to the timings of different pulse widths; Among them, the radar generates a short pulse width timing for short distances, and the short pulse widths include 1μs and 2μs; the radar generates a long pulse width timing for long distances, and the long pulse widths include 10μs and 20μs.

3. The radar signal processing method according to claim 2, characterized in that: In S11, the intermediate frequency in the linear frequency modulation time domain signal x(t) is removed by digital down-conversion to obtain a zero intermediate frequency baseband signal SS_DATA(t), including: S111, after the digital down converter receives the linear frequency modulation time domain signal x(t), the numerically controlled oscillator NCO forms a cosine signal hi and a sine signal hq for mixing; Among them, the expression of the linear frequency modulation time domain signal x(t) is: The expression of the cosine signal hi formed by the numerically controlled oscillator NCO for mixing is: hi=cos(2πf0t)=cos(2πf0NT S ); The expression of the sinusoidal signal hq formed by the numerically controlled oscillator NCO for mixing is: <h2 style=";text-align:left;direction:ltr">hq = - sin(2πf0t) = - sin(2πf0NT<h2 style=";text-align:left;direction:ltr"> s <h2 style=";text-align:left;direction:ltr"> ); t is time, T is pulse width, f0 is carrier frequency, K is frequency modulation slope, B is the bandwidth of the linear frequency modulation time domain signal, B = 20MHz, N is the number of sampling points in a pulse repetition period, a pulse repetition period is 100μs or 200μs, T s is the inverse of the sampling frequency; S112, multiplying the linear frequency modulation time domain signal x(t) by the cosine signal hi, performing mixing, and obtaining the real component Xi(t) of the linear frequency modulation time domain signal x(t) after orthogonal demodulation; multiplying the linear frequency modulation time domain signal x(t) by the sine signal hq, performing mixing, and obtaining the imaginary component Xq(t) of the linear frequency modulation time domain signal x(t) after orthogonal demodulation; Among them, the expression of the real component Xi(t) of the linear frequency modulation time domain signal x(t) after orthogonal demodulation is: The expression of the imaginary component Xq(t) of the linear frequency modulation time domain signal x(t) after orthogonal demodulation is: S113, low-pass filtering is performed on the real component Xi(t) and the imaginary component Xq(t) of the linear frequency modulation time domain signal x(t) obtained after orthogonal demodulation to obtain the real component SI(t) and the imaginary component SQ(t) of the zero intermediate frequency baseband signal SS_DATA(t), respectively, and then the zero intermediate frequency baseband signal SS_DATA(t) is obtained; Among them, the expression of the real component SI(t) of the zero intermediate frequency baseband signal SS_DATA(t) is: The expression of the imaginary component SQ(t) of the zero intermediate frequency baseband signal SS_DATA(t) is: The expression of zero intermediate frequency baseband signal SS_DATA(t) is:

4. The radar signal processing method according to claim 1, characterized in that: In S2, for the short pulse sequence, the radar adaptively uses time domain pulse compression to process and obtain the pulse compression data of the short pulse, including: S21, convolve the real component SI(t) and imaginary component SQ(t) of the zero intermediate frequency baseband signal SS_DATA(t) with the real component HI(t) and imaginary component HQ(t) of the matched filter time domain response signal HH_DATA(t), and obtain 4-way convolution results, namely SI_HI(t), SQ_HQ(t), SI_HQ(t), and SQ_HI(t); Among them, the matched filter time domain response signal HH_DATA(t) is the time-inverted complex conjugate of the zero intermediate frequency baseband signal SS_DATA(t), and the expression of the matched filter time domain response signal HH_DATA(t) is: S22, subtract the two-way convolution results SI_HI(t) and SQ_HQ(t) to obtain the real part MI(t) of the pulse compression data DM_DATA(t) of the short pulse; sum the two-way convolution results SI_HQ(t) and SQ_HI(t) to obtain the imaginary part MQ(t) of the pulse compression data DM_DATA(t) of the short pulse, and then obtain the pulse compression data DM_DATA(t) of the short pulse; The expression of the pulse compression data DM_DATA(t) of the short pulse is: The summation and difference operations are implemented by using Adder and Subtracter of the IP core Fixed_to_float that comes with the FPGA, respectively. Adder and Subtracter are instantiated as adders and subtractors, respectively.

5. The radar signal processing method according to claim 4, characterized in that: Instantiate 8-way FIR Comlier cores to form a matched filter, wherein 4-way FIR Comlier cores include a matched filter time domain response signal of a 1μs short pulse, 2 of the 4-way FIR Comlier cores include a real component of the matched filter time domain response signal of a 1μs short pulse, and the other 2 include an imaginary component of the matched filter time domain response signal of a 1μs short pulse; Another 4 FIR Comlier cores include the matched filter time domain response signal of the 2μs short pulse, 2 of which include the real component of the matched filter time domain response signal of the 2μs short pulse, and the other 2 include the imaginary component of the matched filter time domain response signal of the 2μs short pulse.

6. The radar signal processing method according to claim 1, characterized in that: In S3, for long pulse timing, the radar adaptively uses frequency domain pulse compression to process and obtain the pulse compression data of the long pulse, including: S31, preprocessing the zero intermediate frequency baseband signal SS_DATA(t), and performing fast Fourier transform FFT to obtain an echo frequency domain signal FS_DATA(t); S32, read the matched filter frequency domain response signal HS_DATA(t) pre-stored in the BRAM core inside the FPGA, and multiply it with the echo frequency domain signal FS_DATA(t) to obtain the filtered frequency domain signal FH_DATA(t); S33, performing inverse fast Fourier transform IFFT on the filtered frequency domain signal FH_DATA(t) to obtain long pulse pulse compression data CM_DATA(t); Among them, the expression of the pulse compression data CM_DATA(t) of the long pulse is:

7. The radar signal processing method according to claim 6, characterized in that: In S31, the zero intermediate frequency baseband signal SS_DATA(t) is preprocessed, including: The 16-bit fixed-point number sampled by AD is converted into a 32-bit floating-point number using the IP core Fixed_to_float of the FPGA, so as to convert the zero intermediate frequency baseband signal SS_DATA(t) into a floating-point number. Among them, the clock is consistent with the AD sampling clock, which is 250MHz. The fixed-point number is converted to a floating-point number while AD sampling. The floating-point number is delayed by two clock rising edges than the sampled fixed-point number.

8. The radar signal processing method according to claim 6, characterized in that: Use the IP core FastFourierTransform core of FPGA, that is, FFT core, to perform fast Fourier transform FFT and inverse fast Fourier transform IFFT. When the parameter s_axis_config_tdata of the FFT core is set to 1, the FFT core is used to perform fast Fourier transform FFT; when the parameter s_axis_config_tdata of the FFT core is set to 0, the FFT core is used to perform inverse fast Fourier transform IFFT. When the long pulse width is 10 μs, the input data length of the FFT core is configured to be 2048, the input data width is 32 bits, and the input data format is floating point; When the long pulse width is 20 μs, the input data length of the FFT core is configured to be 4096, the input data width is 32 bits, and the input data format is a floating point number.

9. The radar signal processing method according to claim 6, characterized in that: In S32, the matched filter frequency domain response signal HS_DATA(t) pre-stored in the BRAM core inside the FPGA is read, and multiplied with the echo frequency domain signal FS_DATA(t) to obtain the filtered frequency domain signal FH_DATA(t), including: S321, multiplying the matched filter time domain response signal HH_DATA(t) by the window function data point, and performing a 2048-point fast Fourier transform FFT to obtain a matched filter frequency domain response signal HS_DATA(t); S322, converting the matched filter frequency domain response signal HS_DATA(t) into a floating point number and storing it in a coe file, and then storing the coe file in the BRAM core; S323, reading the pre-stored matched filter frequency domain response signal HS_DATA(t) from the BRAM core, and performing complex multiplication with the echo frequency domain signal FS_DATA(t) to obtain a filtered frequency domain signal FH_DATA(t); Among them, the expression of the filtered frequency domain signal FH_DATA(t) is: H i , H q are the real and imaginary components of the frequency domain response signal HS_DATA(t) of the matched filter, S i , S q are the real and imaginary components of the echo frequency domain signal FS_DATA(t) respectively; The multiplication, summation and difference operations are implemented by using Multiply, Adder and Subtracter of the IP core Fixed_to_float of the FPGA, and Multiply, Adder and Subtracter are instantiated as multiplier, adder and subtractor respectively.

10. The radar signal processing method according to claim 1, characterized in that: In S4, the pulse compression data of the short pulse and the pulse compression data of the long pulse are spliced ​​together to obtain a set of combined pulse compression data for the detection distance, including: S41, storing the pulse compression data DM_DATA(t) of the short pulse into the write buffer FIFO_DM, and storing the pulse compression data CM_DATA(t) of the long pulse into the write buffer FIFO_CM; Among them, the write buffers FIFO_DM and FIFO_CM are the IP core FIFO Generator core that comes with the FPGA, that is, the FIFO core. The write clock of the FIFO core write data is set to be consistent with the pulse compression clock, and the read clock of the FIFO core read data is set to be consistent with the write clock. The data depth of the write buffer FIFO_DM is set to 512, and the read and write data widths are both 64 bits; the data depth of the write buffer FIFO_CM is set to 4096, and the read and write data widths are both 64 bits; S42. When the write buffers FIFO_DM and FIFO_CM complete writing data, the trigger timing first reads the pulse compression data DM_DATA(t) of the short pulse written in the buffer FIFO_DM in sequence, and then reads the pulse compression data CM_DATA(t) of the long pulse written in the buffer FIFO_CM in sequence, thereby splicing the pulse compression data DM_DATA(t) of the short pulse and the pulse compression data CM_DATA(t) of the long pulse together to obtain a set of combined pulse compression data for the detection distance from near to far.

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