V / I source system with wide voltage and current range

Abstract

The invention discloses a V / I source system with a wide voltage and current range. The V / I source system comprises a power amplifier U1, a parameter measuring unit, a compensating circuit, a current sampling circuit, a voltage sampling circuit, a positive power supply module, a clamping circuit and a mode selector, the positive power supply module is connected with the positive power supply end of the power amplifier U1; the parameter measuring unit is provided with a plurality of channels for respectively setting the output voltage / output current of the power amplifier U1 and the clamping voltage / clamping current of the clamping circuit and adjusting the output voltage of the positive power supply module; the compensation circuit can adapt to different capacitive loads so as to be used for adjusting the establishment time of the output voltage / output current of the power amplifier U1, and the output end of the power amplifier U1 supplies power to the DUT; the method is excellent in performance, the test quality can be improved, and the test cost is reduced.

Description

Technical Field

[0001] The invention relates to the technical field of V / I source, in particular to a V / I source system with a wide voltage and current range. Background Art

[0002] V / I source is a programmable voltage / current source, one of the most basic and important equipment of ATE (Automatic Test Equipment). It mainly provides voltage / current (FV / FI) to DUT (Device Under Test) and can measure the current / voltage (MI / MV) of the corresponding pin. Ordinary voltage / current stabilization sources usually can only work in one quadrant, while V / I source can work in four quadrants, that is, when providing positive / negative voltage to DUT (FV mode), the current can be positive (flowing to DUT) or negative (flowing to V / I source); when providing positive / negative current (FI mode), the voltage can be positive or negative. To ensure the safety of the DUT, the V / I source will also integrate a clamping circuit. The upper / lower limit of the clamping current can be set in FV. If the DUT has an overcurrent anomaly, the VI source will keep the current constant at the upper / lower limit value; the upper / lower limit of the clamping voltage can be set in FI. If the DUT has an overvoltage anomaly, the VI source will keep the voltage constant at the upper / lower limit value. In terms of dynamic performance, settling time and stability are the two most important indicators of the V / I source. On the one hand, the test cost requires the test time to be as short as possible, so the output stabilization time of the V / I source needs to be as small as possible, usually at the level of tens or hundreds of us; on the other hand, the test quality requires that the chip test results are stable and reliable, which requires the V / I source to be stable enough. For the V / I source, a short settling time may cause overshoot and ringing, especially in the scenario of driving a large capacitive load. Therefore, settling time and stability are also the "spear" and "shield" of the V / I source. A V / I source used for chip mass production testing usually compromises these two aspects.

[0003] In recent years, digital-analog hybrid power management chips have flourished. Such chips integrate both digital circuits and analog circuits, as well as high-power devices. During mass production testing, the power supply provided by ATE is required to have a wide range of voltages and currents. For example, when testing digital circuit modules, it is necessary to apply low-voltage and high-precision voltages, and when testing power modules, it is necessary to provide high-voltage and high-current power. Currently, there are very few ATE boards that can meet such requirements at the same time. In the test plan, it is often necessary to combine multiple boards to power the chip under test, which increases the complexity of chip testing and also increases the testing cost. Figure 1This is an existing test solution, which uses a pulsed high-voltage and high-current board, a high-voltage and low-current board, and a low-voltage and low-current board to power the digital-analog hybrid power management chip. The pulsed high-voltage and high-current board mainly provides high-power power and load. For example, when testing the power module, this board needs to provide +30V voltage and ±3A current; the measurement of the leakage current of the chip high-voltage pin is realized by the high-voltage and low-current board. For example, the board provides +48V to the chip to be tested and measures a leakage current of about 100uA; because the current capacity of the low-voltage board is usually only 1A, multiple channels need to be connected in parallel to power the chip. Three boards of different specifications are required to realize the test of the digital-analog hybrid power management chip, which is relatively complex and has high testing costs. Summary of the invention

[0004] The purpose of the present invention is to solve at least one of the technical problems existing in the prior art and to provide a wide voltage and current range V / I source system that reduces test complexity and cost.

[0005] The wide voltage and current range V / I source system according to the embodiment of the present invention comprises: a power amplifier U1, a parameter measurement unit, a compensation circuit, a current sampling circuit, a voltage sampling circuit, a positive power supply module, a clamping circuit and a mode selector; the positive power supply module is connected to the positive power supply terminal of the power amplifier U1; the parameter measurement unit has a plurality of channels to respectively set the output voltage / output current of the power amplifier U1, the clamping voltage / clamping current of the clamping circuit and adjust the output voltage of the positive power supply module; the compensation circuit can adapt to different capacitive loads to adjust the output voltage / output current of the power amplifier U1. At the stand-alone time, the output end of the power amplifier U1 supplies power to the DUT; the current sampling circuit is used to collect the output current of the power amplifier U1, and feed back the current sampling signal to the mode selector; the voltage sampling circuit is used to collect the output voltage of the power amplifier U1, and feed back the voltage sampling signal to the mode selector; in the FV mode, the mode selector selects the voltage sampling signal to be fed back to the power amplifier U1, and selects the current sampling signal to be fed back to the clamping circuit; in the FI mode, the mode selector selects the current sampling signal to be fed back to the power amplifier U1, and selects the voltage sampling signal to be fed back to the clamping circuit.

[0006] According to some embodiments of the present invention, a negative power supply module is further included, and the negative power supply module is connected to the negative power supply terminal of the power amplifier U1.

[0007] According to some embodiments of the present invention, the parameter measurement unit adopts a PMU chip, a DPS or a DAC chip, and the parameter measurement unit includes channel 0, channel 1, channel 2 and channel 3. Channel 0 of the parameter measurement unit is connected to the input end of the power amplifier U1, channel 1 of the parameter measurement unit is connected to the negative input end of the clamping circuit, channel 2 of the parameter measurement unit is connected to the positive input end of the clamping circuit, and channel 3 of the parameter measurement unit is connected to the input end of the positive power supply module.

[0008] According to some embodiments of the present invention, the mode selector includes a voltage / current drive mode selector M1, the input end of the voltage / current drive mode selector M1 is respectively connected to the output end of the current sampling circuit and the output end of the voltage sampling circuit, the output end of the voltage / current drive mode selector M1 is connected to the input end of the power amplifier U1, in the FV mode, the voltage / current drive mode selector M1 selects the voltage acquisition signal to be fed back to the power amplifier U1, and in the FI mode, the voltage / current drive mode selector M1 selects the current acquisition signal to be fed back to the power amplifier U1.

[0009] According to some embodiments of the present invention, the mode selector includes a current / voltage clamping mode selector M2, the input end of the current / voltage clamping mode selector M2 is respectively connected to the output end of the current sampling circuit and the output end of the voltage sampling circuit, the output end of the current / voltage clamping mode selector M2 is connected to the input end of the power amplifier U1, in the FV mode, the current / voltage clamping mode selector M2 selects the current acquisition signal to be fed back to the clamping circuit, and in the FI mode, the current / voltage clamping mode selector M2 selects the voltage acquisition signal to be fed back to the clamping circuit.

[0010] According to some embodiments of the present invention, the compensation circuit includes a resistor R3, multiple capacitors and a compensation capacitor selector M3, the input end of the compensation capacitor selector M3 is respectively connected to one end of the multiple capacitors, the output end of the compensation capacitor selector M3 is respectively connected to the resistor R3 and the inverting input end of the power amplifier U1, the other ends of the multiple capacitors are respectively connected to the output end of the power amplifier U1, and different capacitive loads are adapted by switching the corresponding capacitors through the compensation capacitor selector M3.

[0011] According to some embodiments of the present invention, the current sampling circuit includes a sampling resistor Rsense and an operational amplifier U2, the positive end of the sampling resistor Rsense is respectively connected to the output end of the power amplifier U1 and the in-phase input end of the operational amplifier U2, the negative end of the sampling resistor Rsense is connected to the inverting input end of the operational amplifier U2, and the output end of the operational amplifier U2 is connected to the input end of the mode selector.

[0012] According to some embodiments of the present invention, the current sampling circuit also includes an operational amplifier U21, a resistor R21 and a resistor R22, the output end of the operational amplifier U2 is connected to the non-inverting input end of the operational amplifier U21, the inverting input end of the operational amplifier U21 is grounded via the series resistor R21, one end of the resistor R22 is connected to the inverting input end of the operational amplifier U21, and the other end of the resistor R22 is respectively connected to the output end of the operational amplifier U21 and the input end of the mode selector.

[0013] According to some embodiments of the present invention, the voltage sampling circuit includes an op amp U3, an op amp U31, an op amp U32, a resistor R31, a resistor R32, and a resistor R33. The non-inverting input of the op amp U31 is connected to the power input of the DUT, the inverting input of the op amp U31 is connected to its output, the output of the op amp U31 is connected to the non-inverting input of the op amp U3 via a series resistor R1, the non-inverting input of the op amp U32 is connected to the ground of the DUT, the inverting input of the op amp U32 is connected to its output, the output of the op amp U32 is respectively connected to the inverting input of the op amp U3 and one end of the resistor R33 via a series resistor R32, and the other end of the resistor R33 is respectively connected to the output of the op amp U3 and the input of the mode selector.

[0014] According to some embodiments of the present invention, the mode selector is an analog switch.

[0015] The wide voltage and current range V / I source system according to the embodiment of the present invention has at least the following beneficial effects:

[0016] 1. Use a multi-channel parameter measurement unit as a voltage regulator. Only one parameter measurement unit is needed to complete the output setting of the V / I source, the clamp setting, and the setting of the output voltage of the positive power module. By adjusting the output voltage of the positive power module, a wide range of voltage and current can be obtained to test the digital-analog hybrid power management chip. There is no need for voltage and current boards of various specifications. The integration is high, which effectively reduces the complexity and cost of testing.

[0017] 2. The compensation circuit is used to adjust the output voltage / output current settling time and can adapt to different capacitive loads, so it is suitable for scenarios that require fast response and reduce chip testing time;

[0018] 3. The current sampling circuit, the voltage sampling circuit, the mode selector and the clamping circuit constitute a feedback network, which is connected to the inverting input and output of the power amplifier U1, and forms an inverting summing circuit with the power amplifier U1; the compensation circuit constitutes another feedback network, which is connected to the inverting input and output of the power amplifier U1, and forms an integrating circuit with the power amplifier U1. This circuit works in FV mode (driving voltage mode) or FI mode (driving current mode). In FV mode, the output voltage of the V / I source returns to the input end of the power amplifier U1 through the feedback network, and the output current of the V / I source returns to the input end of the clamp circuit through the feedback network, serving as the trigger source of the clamp circuit; in FI mode, the output current of the V / I source returns to the input end of the power amplifier U1 through the feedback network, and the output voltage of the V / I source returns to the input end of the clamp circuit through the feedback network, serving as the trigger source of the clamp circuit; the present invention uses the power amplifier U1 as the output drive of the V / I source system, and at the same time uses the power amplifier U1 as the main amplifier of the negative feedback system to perform the "summing" operation. In addition, the power amplifier U1 is also the main amplifier of the integration circuit. That is, a power amplifier U1 is used to realize the circuit functions of summing, integration, and driving. In the conventional scheme, the summing, integration, and driving circuits each require an operational amplifier. Therefore, the present invention has a high degree of integration and significantly reduces the testing cost.

[0019] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings;

[0021] Figure 1 This is the existing mass production test schematic of the digital-analog hybrid power management chip;

[0022] Figure 2 is a circuit block diagram of the V / I source system of the present invention;

[0023] Figure 3 is a circuit schematic diagram of the V / I source system of the present invention;

[0024] Figure 4 It is the circuit schematic diagram of the parameter measurement unit (PMU module);

[0025] Figure 5 This is the circuit schematic diagram of the positive power module;

[0026] Figure 6 This is the circuit schematic diagram of the negative power module;

[0027] Figure 7 It is the schematic diagram of the current sampling circuit;

[0028] Figure 8 This is the schematic diagram of the voltage sampling circuit. DETAILED DESCRIPTION

[0029] This section will describe in detail the specific embodiments of the present invention. The preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the accompanying drawings is to supplement the description of the text part of the specification with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of the present invention, but it cannot be understood as a limitation on the scope of protection of the present invention.

[0030] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0031] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0032] Reference Figures 1 to 8The present invention provides a wide voltage and current range V / I source system, comprising: a power amplifier U1, a parameter measurement unit 10, a compensation circuit 20, a current sampling circuit 31, a voltage sampling circuit 32, a positive power module 41, a negative power module 42, a clamping circuit 50 and a mode selector 60; the positive power module 41 is connected to the positive power module 41 end of the power amplifier U1, and the negative power module 42 is connected to the negative power module 42 end of the power amplifier U1; the parameter measurement unit 10 has a plurality of channels to respectively set the output voltage / output current of the power amplifier U1, the clamping voltage / clamping current of the clamping circuit 50 and adjust the output voltage of the positive power module 41; the compensation circuit 20 can adapt to different capacitive loads , which is used to adjust the output voltage / output current establishment time of the power amplifier U1. The output end of the power amplifier U1 supplies power to the DUT; the current sampling circuit 31 is used to collect the output current of the power amplifier U1, and feed back the current collection signal to the mode selector 60; the voltage sampling circuit 32 is used to collect the output voltage of the power amplifier U1, and feed back the voltage collection signal to the mode selector 60; in the FV mode, the mode selector 60 selects the voltage collection signal to be fed back to the power amplifier U1, and selects the current collection signal to be fed back to the clamping circuit 50; in the FI mode, the mode selector 60 selects the current collection signal to be fed back to the power amplifier U1, and selects the voltage collection signal to be fed back to the clamping circuit 50. The current sampling circuit 31, the voltage sampling circuit 32, the mode selector 60 and the clamping circuit 50 constitute a feedback network, which is connected to the inverting input and output of the power amplifier U1, and forms an inverting summing circuit with the power amplifier U1; the compensation circuit 20 constitutes another feedback network, which is connected to the inverting input and output of the power amplifier U1, and forms an integrating circuit with the power amplifier U1. This circuit works in FV mode (driving voltage mode) or FI mode (driving current mode). In FV mode, the output voltage of the V / I source returns to the input end of the power amplifier U1 through the feedback network, and the output current of the V / I source returns to the input end of the clamp circuit 50 through the feedback network, serving as the trigger source of the clamp circuit 50; in FI mode, the output current of the V / I source returns to the input end of the power amplifier U1 through the feedback network, and the output voltage of the V / I source returns to the input end of the clamp circuit 50 through the feedback network, serving as the trigger source of the clamp circuit 50; the present invention uses the power amplifier U1 as the output drive of the V / I source system, and at the same time uses the power amplifier U1 as the main amplifier of the negative feedback system to perform the "summing" operation. In addition, the power amplifier U1 is also the main amplifier of the integration circuit. That is, one power amplifier U1 is used to realize the circuit functions of summing, integration, and driving. In conventional schemes, the summing, integration, and driving circuits each require an operational amplifier. Therefore, the present invention has a high degree of integration and significantly reduces the testing cost.

[0033] In certain embodiments, such as Figure 2and Figure 3 As shown, the mode selector 60 includes a voltage / current driving mode selector M1 and a current / voltage clamping mode selector M2. The input end of the voltage / current driving mode selector M1 is respectively connected to the output end of the current sampling circuit 31 and the output end of the voltage sampling circuit 32. The output end of the voltage / current driving mode selector M1 is connected to the input end of the power amplifier U1. In the FV mode, the voltage / current driving mode selector M1 selects the voltage acquisition signal to be fed back to the power amplifier U1. In the FI mode, the voltage / current driving mode selector M1 selects the current acquisition signal to be fed back to the power amplifier U1. The input end of the current / voltage clamping mode selector M2 is connected to the output end of the current sampling circuit 31 and the output end of the voltage sampling circuit 32 respectively, and the output end of the current / voltage clamping mode selector M2 is connected to the input end of the power amplifier U1. In the FV mode, the current / voltage clamping mode selector M2 selects the current acquisition signal to be fed back to the clamping circuit 50, and in the FI mode, the current / voltage clamping mode selector M2 selects the voltage acquisition signal to be fed back to the clamping circuit 50. In this example, the voltage / current driving mode selector M1 and the current / voltage clamping mode selector M2 respectively use ADG1419. ADG1419 is an analog switch produced by ADI, with an on-resistance of 2.1Ω and a power supply voltage support of ±15V.

[0034] In certain embodiments, such as Figure 3 As shown, the compensation circuit 20 includes a resistor R3, a plurality of capacitors C1-C4 and a compensation capacitor selector M3, the input end of the compensation capacitor selector M3 is respectively connected to one end of the plurality of capacitors C1-C4, the output end of the compensation capacitor selector M3 is respectively connected to the resistor R3 and the inverting input end of the power amplifier U1, the other ends of the plurality of capacitors C1-C4 are respectively connected to the output end of the power amplifier U1, and the corresponding capacitors are switched by the compensation capacitor selector M3 to adapt to different capacitive loads. The specific number of the plurality of capacitors is not limited here and can be set according to the specific load capacitance.

[0035] like Figure 3 In the circuit, four resistors R1 to R4 are connected to a common node respectively, the other end of resistor R1 is connected to channel 0 of the PMU chip, the other end of resistor R2 is connected to the output end of the voltage / current drive mode selector M1, and the other end of resistor R4 is electrically connected to the clamping circuit. Assume that the currents flowing through R1, R2, R3 and R4 are Ir1, Ir2, Ir3 and Ir4 respectively, the current at the inverting input end of the power amplifier U1 is In, and the current of the compensation circuit 20 data selector is Im3. From the current equation, we can get

[0036] Ir1+Ir2+Ir3+Ir4=0 (1)

[0037] Ir3=In+Im3 (2)

[0038] Assume that the voltage of channel 0 of parameter measurement unit 10 is Vpmu_ch0, and the voltage of the common node of resistors R1, R2, R3 and R4 is Vnode, then

[0039]

[0040] Assume that the output voltage of the voltage / current drive mode selector M1 is Vm1, then

[0041]

[0042] Assume that the output voltage of the V / I source is Vforce, the output current is Iforce, the output voltage of the voltage sampling circuit 32 is Vsense, the sampling current of the circuit sampling circuit is Isense, and the sampling resistor is Rsense. For the convenience of explaining the principle, the influence of line loss is not considered for the time being, and it is assumed that there is no voltage drop on the AGND plane, then

[0043] Vforce=Vsense (5)

[0044] Iforce=Isense (6) When the V / I source system reaches equilibrium, the integrator no longer integrates, and the current flowing through the integrating capacitor is 0, that is,

[0045] Im3=0 (7)

[0046] Assume that the voltage at the inverting input terminal of the power amplifier U1 is Vn, and the voltage at the non-inverting input terminal is Vp. From the virtual disconnection and virtual disconnection, we can get

[0047] In=0 (8)

[0048] Vn=Vp=0 (9)

[0049]

[0050] When the output current / voltage does not exceed the clamping range, the output of the clamping circuit 50 is high impedance, so

[0051] Ir4=0 (11)

[0052] Assuming that the gain of the voltage sampling circuit 32 is Gain_V, in the FV mode, the voltage / current driving mode selector M1 outputs the voltage of the voltage sampling circuit 32, that is,

[0053] Vm1=[Vsense**Gain_V (12)

[0054] Assuming that the gain of the current sampling circuit 31 is Gain_I, in the FI mode, the voltage / current driving mode selector M1 outputs the voltage of the current sampling circuit 31, that is,

[0055] Vm1=[sense*Resnse*Gain_I (13)

[0056] Combining equations (1) to (12), we can get

[0057]

[0058] Combining equations (1) to (11) and (13), we can obtain

[0059]

[0060] It can be seen from formula (14) that in FV mode, when the output current does not exceed the clamping range, the output voltage of the V / I source is in opposite phase to the voltage of PMU channel 0, and the magnitude is R2 / (R1*Gain_V) times the voltage of channel 0. It can be seen from formula (15) that in FI mode, when the output voltage does not exceed the clamping range, the output current of the V / I source is in opposite phase to the voltage of channel 0, and the magnitude is R2 / (R1*Rsense*Gain_I) times the voltage of channel 0 of parameter measurement unit 10.

[0061] Assume that the output voltage of power amplifier U1 is Vpa, then

[0062]

[0063] The relationship between the output voltage, resistor R3 and capacitor can be obtained by sorting out

[0064]

[0065] It can be seen from formula (35) that the output voltage of the power amplifier U1 is inversely proportional to the integration time constant R3C. The larger the integration time constant, the slower the output voltage of the power amplifier U1 changes.

[0066] Generally speaking, the larger the capacitive load, the larger the integral time constant is to prevent the V / I source from overshooting and ringing. In order to drive a larger range of capacitive loads while reducing the output stabilization time, this embodiment sets four capacitors (capacitors C1 to C4), and switches the corresponding capacitors through the compensation capacitor selector M3 to adapt to different capacitive loads, so as to be suitable for scenarios that require fast response and reduce chip testing time. The compensation capacitor selector of this embodiment uses ADG5401.

[0067] The capacitance of the compensation capacitor needs to be determined by combining the frequency domain and time domain simulation results. From the frequency domain perspective, a negative feedback system must be able to achieve stable output, and the phase margin of its loop gain must be greater than 45°, otherwise oscillation or ringing effects are likely to occur. This V / I source system is a negative feedback system and needs to follow this principle. The loop gain AC parameters of this V / I source system are simulated using software. This test circuit uses a two-port network method to ground the input end (PMU channel 0), disconnect the connection between the output end of the power amplifier U1 and the feedback loop, and connect an AC voltage source at the point where the feedback loop is disconnected. In order to measure the loop more accurately, this test considers the load effect, that is, "copy" the feedback loop one more time and connect it to the output of the power amplifier U1 as its load. This test circuit sets the V / I source to drive a 100uF capacitive load. By adjusting the capacitance of the compensation capacitor C1, when the loop gain is 0dB, the phase is -135°. At this time, C1 is the minimum capacitor that meets the phase margin. The capacitance of C1 obtained by this test circuit is 215pF. That is to say, if this V / I source circuit is to drive a 100uF capacitive load, the compensation capacitor needs to be greater than 215pF.

[0068] The frequency domain analysis obtains the minimum value of the compensation capacitor, which only ensures that the V / I source circuit does not oscillate within the bandwidth range. The circuit may also have overshoot and ringing. In order to reduce the ringing effect, it is necessary to combine the time domain waveform, especially the step response result to adjust the size of the compensation capacitor. The software is used to perform time domain step simulation on this V / I source. This test circuit inputs a 250Hz square wave with a high level of 0V and a low level of -2.5V, and outputs a square wave with a low level of 0V and a high level of 50V. By adjusting the capacitance of the compensation capacitor C1, the ringing effect of the output current Isense of the power amplifier U1 and the output voltage Vout of the V / I source is reduced. When C1 is greater than 3nF, the ringing effect can be almost ignored. Combining the frequency domain and time domain simulation results and the minimum stabilization time requirements, when this V / I source drives a 100uF capacitive load, the compensation capacitor takes 3nF. Based on the above-mentioned method of combining frequency domain and time domain simulation, the corresponding relationship between the compensation capacitor and the load capacitor of this embodiment can be obtained, as shown in Table 1.

[0069]

[0070]

[0071] Table 1 Compensation capacitance and load capacitance correspondence table

[0072] In some embodiments, the parameter measurement unit 10 uses a PMU chip, which can provide functions such as voltage drive (FV), current drive (FI), voltage measurement (MV) and current measurement (MI). The PMU chip used in this embodiment is AD5522 of ADI. The chip integrates a 16-bit DAC, supports Kelvin connection, and provides 4 independent output channels (channel 0, channel 1, channel 2 and channel 3). Channel 0 of the parameter measurement unit 10 is connected to the input end of the power amplifier U1, channel 1 of the parameter measurement unit 10 is connected to the negative input end of the clamp circuit 50, channel 2 of the parameter measurement unit 10 is connected to the positive input end of the clamp circuit 50, and channel 3 of the parameter measurement unit 10 is connected to the input end of the positive power module 41. That is, when a multi-channel parameter measurement unit 10 is used as a voltage regulator, only one parameter measurement unit 10 is needed to complete the output setting, clamp setting and output voltage setting of the V / I source and the positive power module 41; by adjusting the output voltage of the positive power module 41, a wide range of voltage and current can be obtained to realize the testing of the digital-analog hybrid power management chip, without the need for voltage and current boards of various specifications, with high integration, effectively reducing the test complexity and cost.

[0073] Figure 4 This is the schematic diagram of the PMU chip in this embodiment. Since the internal sampling resistor of AD5522 only supports a maximum current of 2mA, in order to improve the versatility of the circuit, this system uses an external sampling resistor. The external sampling resistors R82 / R85 / R83 / R84 of the four channels are all 20Ω, and the PMU can provide a maximum current of 50mA. The discrete DAC output end usually has only one wire, while the PMU output channel supports Kelvin connection, that is, it provides two wires, FORCE and SENSE. This structure can improve the accuracy and consistency of the V / I source system. Taking channel 0 as an example, when the system reaches equilibrium, the voltage on the right end of resistor R1 is 0V. Assuming that the impedance on the PCB trace is Rwire, the voltage on the left end of resistor R1 is

[0074]

[0075] It can be seen from formula (16) that due to the influence of line resistance, the voltage of resistor R1 will be lower than the output voltage of PMU. When designing PCB, the sense line of PMU channel 0 is connected to the pad at the left end of resistor R1. The sense line feeds back the voltage at the left end of R1 to the inside of the PMU chip in real time to adjust the output of PMU so that the voltage reaching the left end of R1 is the preset voltage. In summary, using a PMU chip that supports Kelvin output can improve the accuracy and consistency of the system. In addition, since PMU chips usually integrate multiple channels, the integration of the system can be improved. It should be noted that in addition to using PMU chips, the parameter measurement unit 10 can also use high-precision multi-channel DPS or DAC chips that support Kelvin output.

[0076] The positive power module 41 can use a positive power DC-DC converter (DCDC+) to provide a positive power supply for the power amplifier U1. Figure 5 This is the schematic diagram of the positive power supply DC-DC converter of this embodiment. The circuit is mainly composed of the LM5118 chip, inductor, diode, MOSFET, resistor and capacitor. Since the output voltage range of the power amplifier U1 in this system is relatively wide, when the power supply voltage is fixed, the large voltage difference between the power supply end and the output end will lead to low output efficiency and limited output current range. In order to improve the output current and efficiency of the power amplifier U1, this system uses channel 3 of the PMU chip to adjust the output voltage of the positive power supply DC-DC converter so that the output voltage of the positive power supply DC-DC converter and the output voltage of the power amplifier U1 maintain a small voltage difference. Assuming that the output voltage of the positive power supply DC-DC converter is Vout, the FB pin voltage is Vfb, and the voltage of PMU chip channel 3 is Vpmu3, then

[0077]

[0078] Where Vfb = 1.23V, R51 = 10K, R52 = 5.1K, R53 = 2K, then we can get

[0079] Vout=9.79-5*Vpmu3

[0080] The output voltage of the PMU chip is ±11.25 V, and the maximum output voltage of the positive power DC-DC converter is 66.04 V. Therefore, the output voltage of the positive power DC-DC converter can be adjusted according to the output requirements of the power amplifier U1, and a wide range of voltage and current can be obtained, while improving the efficiency of the V / I source system.

[0081] The negative power module 42 may use a negative power DC-DC converter (DCDC-). Figure 6 The negative power supply DC-DC converter schematic diagram of this embodiment is shown in FIG. The circuit is mainly composed of a TPS54360 chip, an inductor, a diode, and a resistor and capacitor.

[0082] In some embodiments, the current sampling circuit 31 includes a sampling resistor Rsense, an operational amplifier U2, such as Figure 3 As shown, the positive end of the sampling resistor Rsense is connected to the output end of the power amplifier U1 and the non-inverting input end of the operational amplifier U2 respectively, the negative end of the sampling resistor Rsense is connected to the inverting input end of the operational amplifier U2, and the output end of the operational amplifier U2 is connected to the input end of the mode selector 60.

[0083] In certain embodiments, such as Figure 7As shown, the current sampling circuit 31 also includes an operational amplifier U21, a resistor R21 and a resistor R22. The output end of the operational amplifier U2 is connected to the non-inverting input end of the operational amplifier U21, the inverting input end of the operational amplifier U21 is grounded via the series resistor R21, one end of the resistor R22 is connected to the inverting input end of the operational amplifier U21, and the other end of the resistor R22 is respectively connected to the output end of the operational amplifier U21 and the input end of the mode selector 60.

[0084] In certain embodiments, such as Figure 8 As shown, the voltage sampling circuit 32 includes an amplifier U3, an amplifier U31, an amplifier U32, a resistor R31, a resistor R32, and a resistor R33. The in-phase input of the amplifier U31 is connected to the power input of the DUT, the inverting input of the amplifier U31 is connected to its output, the output of the amplifier U31 is connected to the in-phase input of the amplifier U3 through a series resistor R1, the in-phase input of the amplifier U32 is connected to the ground of the DUT, the inverting input of the amplifier U32 is connected to its output, the output of the amplifier U32 is connected to the inverting input of the amplifier U3 and one end of the resistor R33 through a series resistor R32, and the other end of the resistor R33 is connected to the output of the amplifier U3 and the input of the mode selector 60. The amplifier U31 is a high-voltage amplifier, and its function is to collect the power supply voltage at the DUT end. Its inverting input is connected to the output, forming a buffer with a gain of 1. Since the DUT is connected to the in-phase input terminal, the input impedance of this path is very high, and the voltage of the DUT is almost unaffected. The high-voltage amplifier used in this example is LTC6090. The operational amplifier U32 is a low-voltage amplifier, and its function is to collect the ground voltage at the DUT end. Its inverting input terminal is connected to the output terminal to form a buffer with a gain of 1. Since the DUT is connected to the in-phase input terminal, the input impedance of this path is very high, and the voltage of the DUT is almost unaffected. The low-voltage amplifier in this embodiment uses the OPA141 chip. The operational amplifier U3 is a low-voltage amplifier, which forms a differential amplifier with resistors R31, R32, and R3, and its function is to make a difference between the DUT voltages collected by the operational amplifiers U31 and U32, so as to feed back the "absolute" differential voltage at the DUT end to the power amplifier U1 or the clamping circuit 50. The operational amplifier U3 in this embodiment uses the OPA141 chip.

[0085] The power amplifier U1 is the core of this V / I source. It is not only an amplifier for summing and integrating operations, but also a driver for the voltage and current output of the V / I source. The power amplifier U1 of this embodiment adopts the OPA541 chip produced by TI. In this embodiment, the in-phase input terminal of OPA541 is grounded, and the inverting input terminal is connected to the right end of resistor R3 and the output terminal of compensation capacitor selector M3. The output terminal of OPA541 is connected to the right end of four compensation capacitors C1~C4, and to the left end of the sampling resistor Rsense. Overall, the PMU chip channel 0, the current sampling circuit 31, the voltage sampling circuit 32, the mode selector 60 and the clamping circuit 50 form a feedback network, which connects the inverting input terminal and the output terminal of the power amplifier U1, and forms an inverting summing circuit with the power amplifier U1. The input and output relationship is shown in equations (14) and (15). Locally, the OPA541 and the compensation circuit 20 form an integration circuit that can adjust the output settling time of the V / I source to adapt to different capacitive loads.

[0086] Therefore, the present invention builds a V / I source system with a wide voltage and current range based on the PMU chip + power amplifier U1 + DC-DC converter architecture, which has the following advantages:

[0087] 1. The present invention has excellent performance and can improve the test quality while reducing the test cost: (1) The voltage and current range is wide. In this embodiment, the voltage can reach -20V to +50V, and the current can reach -5A to +5A. By changing the positive power supply DC-DC converter conditions, or replacing the power amplifier U1, etc., a wider range of voltage and current can be obtained. (2) The output stabilization time is short. As can be seen from Table 1, when driving a 10uF load capacitor, the stabilization time for the output 50V voltage is only 200us; when driving a 1uF load capacitor, the stabilization time is only 15us; it can be applied to scenarios that require fast response, and can also reduce the chip test time.

[0088] 2. The present invention has a high degree of integration and can reduce the testing cost: (1) An integrated high-power power amplifier U1 and a DC-DC converter chip are used as the driving source of the system. Compared with the discrete power amplifier U1 and DCDC solution, the present invention requires fewer devices. (2) A power amplifier U1 is used to realize circuit functions such as summation, integration, and driving. The present invention uses the power amplifier U1 as the output driver of the V / I source system, and at the same time uses the power amplifier U1 as the main amplifier of the negative feedback system to perform the "summation" operation. In addition, the power amplifier U1 is also the main amplifier of the integration circuit. In the conventional solution, the summation, integration, and driving circuits each require an operational amplifier. (3) A multi-channel PMU chip is used as a voltage regulator. Only one PMU chip is needed to complete the VI source output setting, clamp setting, and DCDC voltage setting.

[0089] It is easy for those skilled in the art to understand that the above preferred embodiments can be freely combined and superimposed without conflict.

[0090] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or directly or indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A wide voltage and current range V / I source system, characterized in that: include: A power amplifier U1, a parameter measurement unit (10), a compensation circuit (20), a current sampling circuit (31), a voltage sampling circuit (32), a positive power supply module (41), a clamping circuit (50) and a mode selector (60); the positive power supply module (41) is connected to the positive power supply terminal of the power amplifier U1; the parameter measurement unit (10) has a plurality of channels for respectively setting the output voltage / output current of the power amplifier U1, the clamping voltage / clamping current of the clamping circuit (50) and adjusting the output voltage of the positive power supply module (41); the compensation circuit (20) can adapt to different capacitive loads to adjust the establishment time of the output voltage / output current of the power amplifier U1, The output end of the power amplifier U1 supplies power to the DUT; the current sampling circuit (31) is used to collect the output current of the power amplifier U1, and feed back the current collection signal to the mode selector (60); the voltage sampling circuit (32) is used to collect the output voltage of the power amplifier U1, and feed back the voltage collection signal to the mode selector (60); in the FV mode, the mode selector (60) selects the voltage collection signal to be fed back to the power amplifier U1, and selects the current collection signal to be fed back to the clamping circuit (50); in the FI mode, the mode selector (60) selects the current collection signal to be fed back to the power amplifier U1, and selects the voltage collection signal to be fed back to the clamping circuit (50).

2. The wide voltage and current range V / I source system according to claim 1, characterized in that: It also includes a negative power supply module (42), and the negative power supply module (42) is connected to the negative power supply terminal of the power amplifier U1.

3. The wide voltage and current range V / I source system according to claim 1, characterized in that: The parameter measurement unit (10) adopts a PMU chip, a DPS or a DAC chip. The parameter measurement unit (10) comprises a channel 0, a channel 1, a channel 2 and a channel 3. The channel 0 of the parameter measurement unit (10) is connected to the input end of the power amplifier U1, the channel 1 of the parameter measurement unit (10) is connected to the negative input end of the clamping circuit (50), the channel 2 of the parameter measurement unit (10) is connected to the positive input end of the clamping circuit (50), and the channel 3 of the parameter measurement unit (10) is connected to the input end of the positive power supply module (41).

4. The wide voltage and current range V / I source system according to claim 1, characterized in that: The mode selector (60) comprises a voltage / current drive mode selector M1, the input end of the voltage / current drive mode selector M1 is respectively connected to the output end of the current sampling circuit (31) and the output end of the voltage sampling circuit (32), the output end of the voltage / current drive mode selector M1 is connected to the input end of the power amplifier U1, in the FV mode, the voltage / current drive mode selector M1 selects the voltage acquisition signal to be fed back to the power amplifier U1, and in the FI mode, the voltage / current drive mode selector M1 selects the current acquisition signal to be fed back to the power amplifier U1.

5. The wide voltage and current range V / I source system according to claim 1, characterized in that: The mode selector (60) comprises a current / voltage clamping mode selector M2, the input end of the current / voltage clamping mode selector M2 being respectively connected to the output end of the current sampling circuit (31) and the output end of the voltage sampling circuit (32), the output end of the current / voltage clamping mode selector M2 being connected to the input end of the power amplifier U1, and in the FV mode, the current / voltage clamping mode selector M2 selecting a current sampling signal to be fed back to the clamping circuit (50), and in the FI mode, the current / voltage clamping mode selector M2 selecting a voltage sampling signal to be fed back to the clamping circuit (50).

6. The wide voltage and current range V / I source system according to claim 1, characterized in that: The compensation circuit (20) comprises a resistor R3, a plurality of capacitors and a compensation capacitor selector M3, wherein the input end of the compensation capacitor selector M3 is respectively connected to one end of the plurality of capacitors, the output end of the compensation capacitor selector M3 is respectively connected to the resistor R3 and the inverting input end of the power amplifier U1, and the other ends of the plurality of capacitors are respectively connected to the output end of the power amplifier U1, and different capacitive loads are adapted by switching corresponding capacitors through the compensation capacitor selector M3.

7. The wide voltage and current range V / I source system according to claim 1, characterized in that: The current sampling circuit (31) comprises a sampling resistor Rsense and an operational amplifier U2, wherein the positive end of the sampling resistor Rsense is respectively connected to the output end of the power amplifier U1 and the in-phase input end of the operational amplifier U2, the negative end of the sampling resistor Rsense is connected to the inverting input end of the operational amplifier U2, and the output end of the operational amplifier U2 is connected to the input end of the mode selector (60).

8. The wide voltage and current range V / I source system according to claim 1, characterized in that: The current sampling circuit (31) also includes an operational amplifier U21, a resistor R21 and a resistor R22, the output end of the operational amplifier U2 is connected to the non-inverting input end of the operational amplifier U21, the inverting input end of the operational amplifier U21 is grounded via the series resistor R21, one end of the resistor R22 is connected to the inverting input end of the operational amplifier U21, and the other end of the resistor R22 is respectively connected to the output end of the operational amplifier U21 and the input end of the mode selector (60).

9. The wide voltage and current range V / I source system according to claim 1, characterized in that: The voltage sampling circuit (32) comprises an operational amplifier U3, an operational amplifier U31, an operational amplifier U32, a resistor R31, a resistor R32, and a resistor R33. The in-phase input terminal of the operational amplifier U31 is connected to the power input terminal of the DUT, the inverting input terminal of the operational amplifier U31 is connected to its output terminal, the output terminal of the operational amplifier U31 is connected to the in-phase input terminal of the operational amplifier U3 via a series resistor R1, the in-phase input terminal of the operational amplifier U32 is connected to the ground terminal of the DUT, the inverting input terminal of the operational amplifier U32 is connected to its output terminal, the output terminal of the operational amplifier U32 is respectively connected to the inverting input terminal of the operational amplifier U3 and one end of the resistor R33 via a series resistor R32, and the other end of the resistor R33 is respectively connected to the output terminal of the operational amplifier U3 and the input terminal of the mode selector (60).

10. The wide voltage and current range V / I source system according to claim 1, characterized in that: The mode selector (60) adopts an analog switch.

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