A curvature-compensated bandgap reference circuit with high power supply rejection ratio

Abstract

This invention discloses a curvature-compensated bandgap reference circuit with high power supply rejection ratio, characterized by comprising: a pseudo-power supply circuit, a startup circuit, and a main circuit; the pseudo-power supply circuit is connected to the startup circuit, and the startup circuit is connected to the main circuit; compared with traditional bandgap reference circuits, this invention improves the power supply rejection ratio of the bandgap reference voltage source by using pseudo-power supply circuit technology, enabling the reference voltage source to remain stable when the power supply voltage changes; and by reducing the influence of the linear and nonlinear components of the temperature coefficient on the reference voltage through the main circuit, the bandgap reference has a low temperature drift coefficient over a wide temperature range, which is crucial for maintaining the stability of the reference voltage; and without increasing the size of the circuit, it can effectively improve the stability and reliability of the power supply and enhance the overall performance of the power supply.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a curvature-compensated bandgap reference circuit with high power supply rejection ratio. Background Technology

[0002] A bandgap reference source circuit is a widely used voltage reference source in integrated circuits. It possesses excellent temperature stability and is commonly used for high-precision voltage references. Bandgap reference sources are widely used in analog devices such as motor drives, dynamic storage, and flash memory, serving as a voltage reference and outputting a temperature-independent reference voltage. The working principle of a traditional bandgap reference circuit is based on the weighted addition of a positive temperature coefficient voltage and a negative temperature coefficient voltage to obtain a voltage quantity that hardly changes with temperature. However, the voltage quantity with a positive temperature coefficient is not first-order but has certain higher-order temperature characteristics. Therefore, traditional bandgap reference voltage sources have poor temperature characteristics, making it difficult to meet the requirements of high-performance analog circuits. This shortcoming can be calibrated using higher-order compensation methods.

[0003] The bandgap reference source circuit proposed in the patent "Low-Voltage Adjustable Bandgap Reference Source Circuit" has two shortcomings. Firstly, its power supply rejection ratio may not be ideal, and power supply noise has a significant impact on the reference voltage. Secondly, during circuit operation, although the first-order linear component of the temperature coefficient is eliminated through transistors and current mirrors, the temperature drift coefficient of the reference voltage is still relatively large, which may not meet the accuracy requirements of some circuits. The bandgap reference circuit proposed in the patent "A Bandgap Reference Circuit Using Current Subtraction Technology" employs current subtraction technology. It includes two negative temperature coefficient current generation circuits and a current subtraction circuit. In the two negative temperature coefficient current generation circuits, the emitter area of ​​Q2 is N times that of Q1. It converts the base-emitter voltage of a transistor with a negative temperature coefficient into a negative temperature coefficient current, and then subtracts negative temperature coefficient currents with the same temperature coefficient but different amplitudes to obtain the reference current. The reference current is multiplied by the resistor to obtain the reference voltage. However, this circuit has certain drawbacks, including significant susceptibility to power supply noise and a relatively low power supply rejection ratio. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a curvature-compensated bandgap reference circuit with a high power supply rejection ratio.

[0005] The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, the present invention provides a curvature-compensated bandgap reference circuit with high power supply rejection ratio, comprising: a pseudo power supply circuit, a startup circuit, and a main circuit; wherein the pseudo power supply circuit is connected to the startup circuit, and the startup circuit is connected to the main circuit.

[0007] The pseudo power supply circuit is used to output a pseudo power supply output voltage to the startup circuit in order to improve the power supply rejection ratio.

[0008] The startup circuit is used to output a startup current to the main circuit according to the pseudo power supply output voltage, so as to start the main circuit.

[0009] The main circuit is used to generate a positive temperature coefficient current I after starting according to the starting current. PTAT and negative temperature coefficient current I CTAT1 And according to the positive temperature coefficient current I PTAT and the negative temperature coefficient current I CTAT1 Obtain the first-order compensated current I CON Then, based on the first-order compensated current I... CON Obtain the initial reference voltage V REF It is also used to eliminate nonlinear and linear components in the initial reference voltage to obtain the final reference voltage V. REF '.

[0010] Optionally, the pseudo-power supply circuit includes: transistor P M1 transistor P M2 transistor P M3 transistor N M1 transistor N M2 transistor N M3 transistor N M4 Resistors R1, R2, and R3; operational amplifier OP1 and capacitor C1; transistor P M1 The source of transistor P is connected to the power supply voltage VCC. M1 The drain of the transistor N M1 The drain of the transistor P M1 The gate and the transistor P M2 The gate connection of the transistor P; M2 The source of the transistor is connected to the power supply voltage VCC, and the transistor P M2 The drain of the transistor N M2 The drain of the transistor N M1 Gate and the transistor N M2 The gate connection of the transistor P; M3 The source terminal of the transistor P is connected to the power supply voltage VCC. M3 The drain terminal of the transistor is connected to the lower plate of the capacitor C1 and the first terminal of the resistor R2. M3 The gate of the transistor is connected to the upper plate of the capacitor C1 and the output terminal of the operational amplifier OP1; the transistor NM1 The source of the transistor N M3 The drain connection; the transistor N M2 The source of the transistor is connected to the negative input terminal of the operational amplifier OP1, the first terminal of the resistor R1, and the transistor N. M4 The gate connection of the transistor N; M3 The source of the transistor N is connected to GND. M3 The drain of the transistor N M1 The source connection of the transistor N M3 The gate of the transistor and the second terminal of the resistor R1 and the transistor N M4 The drain connection; the transistor N M4 The source of the transistor is connected to GND, and the transistor N M4 The gate of the transistor is connected to the first terminal of the resistor R1, the negative input terminal of the operational amplifier OP1, and the transistor N. M2 The source terminal is connected; the second terminal of the resistor R2 is connected to the positive input terminal of the operational amplifier OP1 and the first terminal of the resistor R3; the second terminal of the resistor R3 is connected to GND.

[0011] Optionally, the startup circuit includes: transistor P M4 transistor P M5 With capacitor C2; the transistor P M4 The source and pseudo-power supply output voltage V REG Connection, the transistor P M4 The drain of the capacitor C2 and the upper plate of the capacitor C2 and the transistor P M5 The gate connection of the transistor P M4 The gate of the transistor is connected to GND; the transistor P M5 The source of the pseudo power supply output voltage V REG Connection, the transistor P M5 The gate of the transistor P, the upper plate of the capacitor C2, and the transistor P M4 The drain connection.

[0012] Optionally, the main circuit includes transistor P. M6 transistor P M7 transistor P M8 transistor P M9 transistor P M10 transistor P M11 transistor P M12 Transistor Q1, transistor Q2, transistor Q3, operational amplifier OP2, operational amplifier OP3, operational amplifier OP4, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, and transistor N. M5 The transistor PM6 The source of the pseudo power supply output voltage V REG Connection, the transistor P M6 The drain of transistor P is connected to the positive input terminal of operational amplifier OP2 and the first terminal of resistor R4. M6 The gate of the transistor is connected to the output terminal of the operational amplifier OP2 and the transistor P. M5 The drain of the transistor P M7 The gate of the transistor P M8 The gate and the transistor P M12 The gate connection of the transistor P; M7 The source of the pseudo power supply output voltage V REG Connection, the transistor P M7 The drain of transistor P is connected to the negative input terminal of operational amplifier OP2, the negative input terminal of operational amplifier OP3, and the emitter of transistor Q2; M8 The source of the pseudo power supply output voltage V REG Connection, the transistor P M8 The drain of the transistor P M9 The drain of the transistor is connected to the positive input terminal of the operational amplifier OP4 and the emitter of the transistor Q3; the transistor P M9 The source of the pseudo power supply output voltage V REG Connection, the transistor P M9 The gate of the transistor is connected to the output terminal of the operational amplifier OP3 and the transistor P. M10 The gate and the transistor P M11 The gate connection of the transistor P; M10 The source of the pseudo power supply output voltage V REG Connection, the transistor P M10 The drain of the transistor is connected to the positive input terminal of the operational amplifier OP3 and the first terminal of the resistor R5; the transistor P M11 The source of the pseudo power supply output voltage V REG Connection, the transistor P M11 The drain of the transistor N M5 The drain of the transistor P is connected to the first terminal of the resistor R7; M12 The source of the pseudo power supply output voltage V REG Connection, the transistor P M12 The drain of the transistor is connected to the second terminal of resistor R7 and the first terminal of resistor R8; the transistor N M5 The source of transistor N is connected to the negative input terminal of operational amplifier OP4 and the first terminal of resistor R6. M5 The drain of the transistor PM11 The drain of the transistor N is connected to the first terminal of the resistor R7. M5 The gate of the transistor is connected to the output terminal of the operational amplifier OP4; the lower plate of the capacitor C2 is connected to GND; the second end of the resistor R4 is connected to the emitter of the transistor Q1; the second end of the resistor R5 is connected to GND; the second end of the resistor R6 is connected to GND; the second end of the resistor R8 is connected to GND; the base and collector of the transistor Q1 are both connected to GND; the base and collector of the transistor Q2 are both connected to GND; and the base and collector of the transistor Q3 are both connected to GND.

[0013] Optionally, the positive temperature coefficient current I PTAT It is expressed as follows:

[0014]

[0015] Among them, I PTAT The positive temperature coefficient current I represents PTAT k is Boltzmann's constant, T is the absolute temperature, N1 represents the ratio of the emitter areas of transistor Q1 and transistor Q2, q is the electron charge, and R4 represents the resistance of resistor R4.

[0016] Optionally, the negative temperature coefficient current I CTAT1 It is expressed as follows:

[0017]

[0018] Among them, I CTAT1 The negative temperature coefficient current I represents CTAT1 V BE2 R1 is the base-emitter voltage of transistor Q2, and R5 is the resistance value of resistor R5.

[0019] Optionally, the base-emitter voltage V of the transistor Q2 BE2 It is expressed as follows:

[0020]

[0021] Among them, V BE2 (T) represents the base-emitter voltage V of transistor Q2 at temperature T. BE2 V g0 This represents the bandgap voltage of silicon at 0K, in V. BE2 (T r ) indicates that the temperature is T r The base-emitter voltage V of the transistor Q2 at that time BE2 η is the temperature constant, T rThis is a reference temperature.

[0022] Optionally, the initial reference voltage V REF It is expressed as follows:

[0023] V REF =I NPTAP ×(R7+R8)+I PTAT ×R8;

[0024] Among them, V REF The initial reference voltage V represents REF I NPTAP According to the negative temperature coefficient current I CTAT1 The obtained characteristic current, I PTAT The positive temperature coefficient current I PTAT R7 is the resistance value of resistor R7, and R8 is the resistance value of resistor R8.

[0025] Optionally, the final reference voltage V REF ' is represented as follows:

[0026]

[0027] Among them, V REF ' is the final reference voltage V REF R6 is the resistance value of the resistor R6.

[0028] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects:

[0029] In the above technical solution, compared with the traditional bandgap reference circuit, the present invention improves the power supply rejection ratio of the bandgap reference voltage source by using pseudo power supply circuit technology, so that the reference voltage source can remain stable when the power supply voltage changes; and reduces the influence of the linear and nonlinear components of the temperature coefficient in the circuit on the reference voltage by reducing the main circuit, so that the bandgap reference has a low temperature drift coefficient over a wide temperature range, which is crucial for maintaining the stability of the reference voltage; and effectively improves the stability and reliability of the power supply and enhances the overall performance of the power supply without increasing the scale of the circuit.

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a curvature-compensated bandgap reference circuit with high power supply rejection ratio provided in an embodiment of the present invention. Detailed Implementation

[0032] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0033] Figure 1 This is a schematic diagram of a curvature-compensated bandgap reference circuit with high power supply rejection ratio provided in an embodiment of the present invention, as shown below. Figure 1 As shown, it includes: a pseudo-power supply circuit, a startup circuit, and a main circuit; the pseudo-power supply circuit is connected to the startup circuit, and the startup circuit is connected to the main circuit; as shown... Figure 1 As shown, the part within the green dashed box is the pseudo power supply circuit, the part within the purple dashed box is the startup circuit, and the part within the red dashed box is the main circuit.

[0034] like Figure 1 As shown, the pseudo power supply circuit includes: transistor P M1 transistor P M2 transistor P M3 transistor N M1 transistor N M2 transistor N M3 transistor N M4 Resistors R1, R2, and R3; operational amplifier OP1 and capacitor C1; transistor P M1 The source of transistor P is connected to the power supply voltage VCC. M1 The drain of the transistor N M1 The drain of the transistor P M1 The gate and the transistor P M2 The gate connection of the transistor P; M2 The source of the transistor is connected to the power supply voltage VCC, and the transistor P M2 The drain of the transistor N M2 The drain of the transistor N M1 Gate and the transistor N M2 The gate connection of the transistor P; M3 The source terminal of the transistor P is connected to the power supply voltage VCC. M3 The drain terminal of the transistor is connected to the lower plate of the capacitor C1 and the first terminal of the resistor R2. M3 The gate of the transistor is connected to the upper plate of the capacitor C1 and the output terminal of the operational amplifier OP1; the transistor N M1 The source of the transistor N M3 The drain connection; the transistor N M2 The source of the transistor is connected to the negative input terminal of the operational amplifier OP1, the first terminal of the resistor R1, and the transistor N. M4 The gate connection of the transistor N; M3 The source of the transistor N is connected to GND.M3 The drain of the transistor N M1 The source connection of the transistor N M3 The gate of the transistor and the second terminal of the resistor R1 and the transistor N M4 The drain connection; the transistor N M4 The source of the transistor is connected to GND, and the transistor N M4 The gate of the transistor is connected to the first terminal of the resistor R1, the negative input terminal of the operational amplifier OP1, and the transistor N. M2 The source terminal is connected; the second terminal of the resistor R2 is connected to the positive input terminal of the operational amplifier OP1 and the first terminal of the resistor R3; the second terminal of the resistor R3 is connected to GND.

[0035] like Figure 1 As shown, the startup circuit includes: transistor P M4 transistor P M5 With capacitor C2; the transistor P M4 The source and pseudo-power supply output voltage V REG Connection, the transistor P M4 The drain of the capacitor C2 and the upper plate of the capacitor C2 and the transistor P M5 The gate connection of the transistor P M4 The gate of the transistor is connected to GND; the transistor P M5 The source of the pseudo power supply output voltage V REG Connection, the transistor P M5 The gate of the transistor P, the upper plate of the capacitor C2, and the transistor P M4 The drain connection.

[0036] like Figure 1 As shown, the main circuit includes transistor P M6 transistor P M7 transistor P M8 transistor P M9 transistor P M10 transistor P M11 transistor P M12 Transistor Q1, transistor Q2, transistor Q3, operational amplifier OP2, operational amplifier OP3, operational amplifier OP4, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, and transistor N. M5 The transistor P M6 The source of the pseudo power supply output voltage V REG Connection, the transistor P M6 The drain of transistor P is connected to the positive input terminal of operational amplifier OP2 and the first terminal of resistor R4. M6The gate of the transistor is connected to the output terminal of the operational amplifier OP2 and the transistor P. M5 The drain of the transistor P M7 The gate of the transistor P M8 The gate and the transistor P M12 The gate connection of the transistor P; M7 The source of the pseudo power supply output voltage V REG Connection, the transistor P M7 The drain of transistor P is connected to the negative input terminal of operational amplifier OP2, the negative input terminal of operational amplifier OP3, and the emitter of transistor Q2; M8 The source of the pseudo power supply output voltage V REG Connection, the transistor P M8 The drain of the transistor P M9 The drain of the transistor is connected to the positive input terminal of the operational amplifier OP4 and the emitter of the transistor Q3; the transistor P M9 The source of the pseudo power supply output voltage V REG Connection, the transistor P M9 The gate of the transistor is connected to the output terminal of the operational amplifier OP3 and the transistor P. M10 The gate and the transistor P M11 The gate connection of the transistor P; M10 The source of the pseudo power supply output voltage V REG Connection, the transistor P M10 The drain of the transistor is connected to the positive input terminal of the operational amplifier OP3 and the first terminal of the resistor R5; the transistor P M11 The source of the pseudo power supply output voltage V REG Connection, the transistor P M11 The drain of the transistor N M5 The drain of the transistor P is connected to the first terminal of the resistor R7; M12 The source of the pseudo power supply output voltage V REG Connection, the transistor P M12 The drain of the transistor is connected to the second terminal of resistor R7 and the first terminal of resistor R8; the transistor N M5 The source of transistor N is connected to the negative input terminal of operational amplifier OP4 and the first terminal of resistor R6. M5 The drain of the transistor P M11 The drain of the transistor N is connected to the first terminal of the resistor R7. M5The gate of the transistor is connected to the output terminal of the operational amplifier OP4; the lower plate of the capacitor C2 is connected to GND; the second end of the resistor R4 is connected to the emitter of the transistor Q1; the second end of the resistor R5 is connected to GND; the second end of the resistor R6 is connected to GND; the second end of the resistor R8 is connected to GND; the base and collector of the transistor Q1 are both connected to GND; the base and collector of the transistor Q2 are both connected to GND; and the base and collector of the transistor Q3 are both connected to GND.

[0037] The pseudo power supply circuit is used to output a pseudo power supply output voltage to the startup circuit in order to improve the power supply rejection ratio.

[0038] It is understandable that the two PMOS transistors P in the pseudo power supply circuit M1 P M2 and four NMOS transistors N M1 N M2 N M3 N M4 It forms an auxiliary bandgap and can provide bias for the operational amplifier. The pseudo-power supply technology can improve the power supply rejection ratio of the bandgap reference by nearly A1 times, where A1 is the gain of the operational amplifier OP1 in the pseudo-power supply circuit.

[0039] The startup circuit is used to output a startup current to the main circuit according to the pseudo power supply output voltage, so as to start the main circuit.

[0040] Understandably, transistor P M4 transistor P M5 The transistor P, along with capacitor C2, forms the current-mode bandgap startup section; at the initial power-on, transistor P... M4 When the transistor P is turned on, it begins to charge capacitor C2. M5 The gate of transistor P is at a low level, therefore transistor P M5 When the capacitor is fully charged, transistor P is turned on, outputting a startup current to the output node of operational amplifier OP2. M5 When the gate is high, transistor P... M5 The shutdown and startup circuits ensure the stability and reliability of the overall circuit.

[0041] The main circuit is used to generate a positive temperature coefficient current I after starting according to the starting current. PTAT and negative temperature coefficient current I CTAT1 And according to the positive temperature coefficient current I PTAT and the negative temperature coefficient current I CTAT1 Obtain the first-order compensated current I CON Then, based on the first-order compensated current I... CONObtain the initial reference voltage V REF It is also used to eliminate nonlinear and linear components in the initial reference voltage to obtain the final reference voltage V. REF '.

[0042] It is understandable that, such as Figure 1 As shown, the positive temperature coefficient current I is achieved through the clamping effect of operational amplifiers OP2, OP3, and OP4, and the temperature characteristics of transistors Q1, Q2, and Q3. PTAT and negative temperature coefficient current I CTAT1 The generation of the positive temperature coefficient current I is achieved by adding two currents with opposite temperature coefficients at point C, and by setting the resistance values ​​of resistors R4 and R5. PTAT With negative temperature coefficient current I CTAT1 The first-order compensated current I is obtained by superposition. CON .

[0043] Optionally, the positive temperature coefficient current I PTAT It is expressed as follows:

[0044]

[0045] Among them, I PTAT The positive temperature coefficient current I represents PTAT k is Boltzmann's constant, T is the absolute temperature, N1 represents the ratio of the emitter areas of transistor Q1 and transistor Q2, q is the electron charge, and R4 represents the resistance of resistor R4.

[0046] Negative temperature coefficient current I CTAT1 It is expressed as follows:

[0047]

[0048] Among them, I CTAT1 The negative temperature coefficient current I represents CTAT1 V BE2 R1 is the base-emitter voltage of transistor Q2, and R5 is the resistance value of resistor R5.

[0049] The base-emitter voltage V of transistor Q2 BE2 It is expressed as follows:

[0050]

[0051] Among them, V BE2 (T) represents the base-emitter voltage V of transistor Q2 at temperature T. BE2 V g0 This represents the bandgap voltage of silicon at 0K, in V. BE2 (Tr ) indicates that the temperature is T r The base-emitter voltage V of the transistor Q2 at that time BE2 η is the temperature constant, T r This is a reference temperature.

[0052] Because the base-emitter voltage V of transistor Q3 BE3 It is the current I injected into the emitter of transistor Q3. CON Therefore, the base-emitter voltage of transistor Q3 can be expressed as follows:

[0053]

[0054] Among them, V BE3 (T) represents the base-emitter voltage V of transistor Q3 at temperature T. BE3 V BE3 (T r ) indicates that the temperature is T r The base-emitter voltage V of transistor Q3 at that time BE3 .

[0055] Figure 1 The second negative temperature coefficient current I in CTAT2 It is expressed as follows:

[0056]

[0057] Where R6 is the resistance value of resistor R6.

[0058] According to Kirchhoff's current law, the characteristic current I... NPTAT The expression is as follows:

[0059] I NPTAP =I CTAT1 -I CTAT2 ;

[0060] The characteristic current I can be obtained from the above formula. NPTAT The expression is as follows:

[0061]

[0062] Due to the initial reference voltage V REF It is expressed as follows:

[0063] V REF =I NPTAP ×(R7+R8)+I PTAT ×R8;

[0064] Among them, V REF The initial reference voltage V represents REF I NPTAPAccording to the negative temperature coefficient current I CTAT1 The obtained characteristic current, I PTAT The positive temperature coefficient current I PTAT R7 is the resistance value of resistor R7, and R8 is the resistance value of resistor R8.

[0065] The positive temperature coefficient current I PTAT and characteristic current I NPTAT Substituting the formula into it, we obtain the initial reference voltage V. REF Further explanation:

[0066]

[0067] If the nonlinear component representing temperature in the above equation is made... If the value is equal to 0, the nonlinear component in the equation can be eliminated, and the initial reference voltage V after eliminating the nonlinear component is obtained. REF The expression is as follows:

[0068]

[0069] make This is equivalent to eliminating the linear component in the equation, resulting in a stable final reference voltage V that is unaffected by temperature. REF ' is represented as follows:

[0070]

[0071] Among them, V REF ' is the final reference voltage V REF R6 is the resistance value of the resistor R6.

[0072] In the above technical solution, compared with the traditional bandgap reference circuit, the present invention improves the power supply rejection ratio of the bandgap reference voltage source by using pseudo power supply circuit technology, so that the reference voltage source can remain stable when the power supply voltage changes; and reduces the influence of the linear and nonlinear components of the temperature coefficient in the circuit on the reference voltage by reducing the main circuit, so that the bandgap reference has a low temperature drift coefficient over a wide temperature range, which is crucial for maintaining the stability of the reference voltage; and effectively improves the stability and reliability of the power supply and enhances the overall performance of the power supply without increasing the scale of the circuit.

[0073] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0074] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0075] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0076] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A curvature-compensated bandgap reference circuit with high power supply rejection ratio, characterized in that, include: Pseudo-power supply circuit, startup circuit, main circuit; The pseudo-power supply circuit is connected to the startup circuit, and the startup circuit is connected to the main circuit; the main circuit includes a transistor P. M6 transistor P M7 transistor P M8 transistor P M9 transistor P M10 transistor P M11 transistor P M12 Transistor Q1, transistor Q2, transistor Q3, operational amplifier OP2, operational amplifier OP3, operational amplifier OP4, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, and transistor N. M5 The transistor P M6 The source and pseudo-power supply output voltage V REG Connection, the transistor P M6 The drain of transistor P is connected to the positive input terminal of operational amplifier OP2 and the first terminal of resistor R4. M6 The gate of the transistor is connected to the output terminal of the operational amplifier OP2, the port of the startup circuit, and the transistor P. M7 The gate of the transistor P M8 The gate and the transistor P M12 The gate connection of the transistor P; M7 The source and pseudo-power supply output voltage V REG Connection, the transistor P M7 The drain of transistor P is connected to the negative input terminal of operational amplifier OP2, the negative input terminal of operational amplifier OP3, and the emitter of transistor Q2; M8 The source and pseudo-power supply output voltage V REG Connection, the transistor P M8 The drain of the transistor P M9 The drain of the transistor is connected to the positive input terminal of the operational amplifier OP4 and the emitter of the transistor Q3; the transistor P M9 The source and pseudo-power supply output voltage V REG Connection, the transistor P M9 The gate of the transistor is connected to the output terminal of the operational amplifier OP3 and the transistor P. M10 The gate and the transistor P M11 The gate connection of the transistor P; M10 The source and pseudo-power supply output voltage V REG Connection, the transistor P M10 The drain of the transistor is connected to the positive input terminal of the operational amplifier OP3 and the first terminal of the resistor R5; the transistor P M11 The source and pseudo-power supply output voltage V REG Connection, the transistor P M11 The drain of the transistor N M5 The drain of the transistor P is connected to the first terminal of the resistor R7; M12 The source and pseudo-power supply output voltage V REG Connection, the transistor P M12 The drain of the transistor is connected to the second terminal of resistor R7 and the first terminal of resistor R8; the transistor N M5 The source of transistor N is connected to the negative input terminal of operational amplifier OP4 and the first terminal of resistor R6. M5 The drain of the transistor P M11 The drain of the transistor N is connected to the first terminal of the resistor R7. M5 The gate of the transistor is connected to the output terminal of the operational amplifier OP4; the second terminal of the resistor R4 is connected to the emitter of the transistor Q1; the second terminal of the resistor R5 is connected to GND; the second terminal of the resistor R6 is connected to GND; the second terminal of the resistor R8 is connected to GND; the base and collector of the transistor Q1 are both connected to GND; the base and collector of the transistor Q2 are both connected to GND; and the base and collector of the transistor Q3 are both connected to GND. The pseudo-power supply circuit is used to output a pseudo-power supply output voltage V to the startup circuit. REG To improve the power supply rejection ratio; The startup circuit is used to determine the output voltage V of the pseudo power supply. REG Output a starting current to the main circuit so that the main circuit starts up; The main circuit is used to generate a positive temperature coefficient current I after starting according to the starting current. PTAT and negative temperature coefficient current I CTAT1 And according to the positive temperature coefficient current I PTAT and the negative temperature coefficient current I CTAT1 Obtain the first-order compensated current I CON Then, based on the first-order compensated current I... CON Obtain the initial reference voltage V REF It is also used to eliminate nonlinear and linear components in the initial reference voltage to obtain the final reference voltage V. REF '.

2. The high power supply rejection ratio curvature-compensated bandgap reference circuit according to claim 1, characterized in that, The pseudo power supply circuit includes: transistor P M1 transistor P M2 transistor P M3 transistor N M1 transistor N M2 transistor N M3 transistor N M4 Resistors R1, R2, and R3; operational amplifier OP1 and capacitor C1; transistor P M1 The source of transistor P is connected to the power supply voltage VCC. M1 The drain of the transistor N M1 The drain of the transistor P M1 The gate and the transistor P M2 The gate connection of the transistor P; M2 The source of the transistor is connected to the power supply voltage VCC, and the transistor P M2 The drain of the transistor N M2 The drain of the transistor N M1 Gate and the transistor N M2 The gate connection of the transistor P; M3 The source terminal of the transistor P is connected to the power supply voltage VCC. M3 The drain terminal of the transistor is connected to the lower plate of the capacitor C1 and the first terminal of the resistor R2. M3 The gate of the transistor is connected to the upper plate of the capacitor C1 and the output terminal of the operational amplifier OP1; the transistor N M1 The source of the transistor N M3 The drain connection; the transistor N M2 The source of the transistor is connected to the negative input terminal of the operational amplifier OP1, the first terminal of the resistor R1, and the transistor N. M4 The gate connection of the transistor N; M3 The source of the transistor N is connected to GND. M3 The drain of the transistor N M1 The source connection of the transistor N M3 The gate of the transistor and the second terminal of the resistor R1 and the transistor N M4 The drain connection; the transistor N M4 The source of the transistor is connected to GND, and the transistor N M4 The gate of the transistor is connected to the first terminal of the resistor R1, the negative input terminal of the operational amplifier OP1, and the transistor N. M2 The source terminal is connected; the second terminal of the resistor R2 is connected to the positive input terminal of the operational amplifier OP1 and the first terminal of the resistor R3; the second terminal of the resistor R3 is connected to GND.

3. The high power supply rejection ratio curvature-compensated bandgap reference circuit according to claim 1, characterized in that, The startup circuit includes: transistor P M4 transistor P M5 With capacitor C2; the transistor P M4 The source and pseudo-power supply output voltage V REG Connection, the transistor P M4 The drain of the capacitor C2 and the upper plate of the capacitor C2 and the transistor P M5 The gate connection of the transistor P M4 The gate of the transistor is connected to GND; the transistor P M5 The source of the pseudo power supply output voltage V REG Connection, the transistor P M5 The gate of the transistor P, the upper plate of the capacitor C2, and the transistor P M4 The drain of capacitor C2 is connected; the lower plate of capacitor C2 is connected to GND.

4. The high power supply rejection ratio curvature-compensated bandgap reference circuit according to claim 1, characterized in that, The positive temperature coefficient current I PTAT It is expressed as follows: ； in, The positive temperature coefficient current I represents PTAT , Boltzmann's constant, Absolute temperature This represents the ratio of the emitter areas of transistor Q1 and transistor Q2. The amount of electron charge. This indicates the resistance value of resistor R4.

5. The high power supply rejection ratio curvature-compensated bandgap reference circuit according to claim 4, characterized in that, The negative temperature coefficient current I CTAT1 It is expressed as follows: ； in, The negative temperature coefficient current I represents CTAT1 , This is the base-emitter voltage of the transistor Q2. Let R5 be the resistance value.

6. The high power supply rejection ratio curvature-compensated bandgap reference circuit according to claim 5, characterized in that, The base-emitter voltage V of the transistor Q2 BE2 It is expressed as follows: ； in, Indicates temperature as The base-emitter voltage V of the transistor Q2 at that time BE2 , This represents the bandgap voltage of silicon at a temperature of 0K. Indicates temperature as The base-emitter voltage V of the transistor Q2 at that time BE2 , It is a temperature constant. This is a reference temperature.

7. The high power supply rejection ratio curvature-compensated bandgap reference circuit according to claim 5, characterized in that, The initial reference voltage V REF It is expressed as follows: ； in, The initial reference voltage V represents REF , According to the negative temperature coefficient current I CTAT1 The obtained characteristic current, The positive temperature coefficient current I PTAT , Let R7 be the resistance value. Let R8 be the resistance value.

8. The high power supply rejection ratio curvature-compensated bandgap reference circuit according to claim 7, characterized in that, The final reference voltage V REF ' is represented as follows: ； in, The final reference voltage V REF ', Let R6 be the resistance value.

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