Semiconductor device related to command generation

Abstract

The invention relates to a semiconductor device related to command generation. The semiconductor device includes: a clock division circuit configured to generate a divided clock from a clock signal based on a division enable signal, the division enable signal being activated based on a chip selection signal; and a valid time determination circuit configured to generate a valid signal for setting a generation time of the command based on the chip selection signal and the divided clock.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0156638, filed on November 13, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure generally relate to a semiconductor device, and more particularly, to a semiconductor device related to command generation. Background Art

[0004] As the miniaturization of semiconductor devices develops, high efficiency of pads connected to semiconductor devices is required. Semiconductor devices receive command addresses through pads and generate internal commands and internal addresses to perform internal operations. Therefore, it is necessary to minimize the number of pads used in semiconductor devices to shrink semiconductor devices.

[0005] In addition, since the semiconductor device uses a high-frequency external clock to perform high-speed operation, the semiconductor device controls internal operation using a divided clock generated by dividing the external clock to achieve stable internal operation. Summary of the invention

[0006] According to an embodiment of the present disclosure, a semiconductor device may include: a clock division circuit, configured to receive a division enable signal to generate a divided clock from a clock signal when the division enable signal is activated based on a chip selection signal; and a valid time determination circuit, configured to generate a valid signal for setting a generation time of a command based on the chip selection signal and the divided clock.

[0007] In addition, according to an embodiment of the present disclosure, the semiconductor device may include: a frequency division enable signal generating circuit, configured to: generate an activated frequency division enable signal when a chip selection signal set to a preset logic level after leaving a power down period is received synchronously with a clock signal; and a valid time determination circuit, configured to generate a valid signal for setting a generation time of a command based on a frequency division clock, the frequency division clock being generated based on the frequency division enable signal and the chip selection signal.

[0008] In addition, according to an embodiment of the present disclosure, a semiconductor device may include: a clock division circuit, configured to receive a division enable signal to generate a divided clock from a clock signal when the division enable signal is activated based on a chip selection signal; and a valid time determination circuit, configured to generate a first valid signal and a second valid signal for setting a generation time of a command based on the chip selection signal and the divided clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2 It is shown Figure 1 FIG. 2 is a timing diagram of a command generation operation of a semiconductor device shown in FIG.

[0011] Figure 3 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 4 It is shown Figure 3 FIG. 2 is a timing diagram of a command generation operation of a semiconductor device shown in FIG.

[0013] Figure 5 is a block diagram showing a configuration of a semiconductor system according to an embodiment of the present disclosure.

[0014] Figure 6 is a block diagram showing a configuration of an electronic system according to an embodiment of the present disclosure.

[0015] Figure 7 is a block diagram illustrating a configuration of an electronic system according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] In the description of the following embodiments, when a parameter is referred to as "predetermined", it may be intended to indicate that the value of the parameter is predetermined when the parameter is used in a process or algorithm. The value of the parameter may be set at the beginning of the process or algorithm, or may be set during the period in which the process or algorithm is executed. In the following description of the embodiments, when a parameter is referred to as "preset", it may be intended to indicate that the value of the parameter is predetermined when the parameter is used in a process or algorithm. The value of the parameter may be set at the beginning of the process or algorithm, or may be set during the execution of the process or algorithm. For example, the term "preset" used herein for parameters such as preset logic levels, delay periods or states means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0017] It should be understood that although the terms "first", "second", "third", etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element and are not intended to imply the order or quantity of the elements. Therefore, the first element in some embodiments can be called the second element in other embodiments without departing from the teachings of the present disclosure.

[0018] In addition, it should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0019] Logical "high" levels and logical "low" levels can be used to describe the logical levels of electrical signals. A signal with a logical "high" level can be distinguished from a signal with a logical "low" level. For example, when a signal with a first voltage corresponds to a signal with a logical "high" level, a signal with a second voltage corresponds to a signal with a logical "low" level. In an embodiment, the logical "high" level can be set to a voltage level higher than the voltage level of the logical "low" level. In addition, the logical level of the signal can be set to be different or opposite according to the embodiment. For example, a signal with a logical "high" level in one embodiment can be set to have a logical "low" level in another embodiment.

[0020] The term "logical bit group" may mean a combination of logic levels of bits included in a signal. When the logic level of each bit included in the signal changes, the logic bit group of the signal may be set differently. For example, if the signal includes two bits, when the logic level of each of the two bits included in the signal is "logic low level, logic low level", the logic bit group of the signal may be set to a first logic bit group, and when the logic level of each of the two bits included in the signal is "logic low level and logic high level", the logic bit group of the signal may be set to a second logic bit group.

[0021] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments described herein are only for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0022] Figure 1 1 is a block diagram showing the configuration of a semiconductor device 10 according to an embodiment of the present disclosure. Figure 1As shown, the semiconductor device 10 may include pads 100_1, 100_2, 100_3, 100_4 and 100_5, receivers (RX) 101_1, 101_2, 101_3 and 101_4, setup hold delay units (SHD) 103_1, 103_2, 103_3 and 103_4, a distribution enable signal generating circuit (DIV_EN GEN) 105, a clock dividing circuit (CLK DIV) 107, a valid time determining circuit (VALID DET) 109, a command address latch circuit 111, a command address decoder (CA DEC) 113, and a latency shift circuit (i.e., a write latency shift circuit (WL SFT) 115 and / or a read latency shift circuit (RL SFT) 117).

[0023] The receiver 101_1 may receive the clocks CLK_T and CLK_C through the pads 100_1 and 100_2. The clocks CLK_T and CLK_C may be received from a controller (eg, Figure 5 31) is applied. The clock CLK_T and the clock CLK_C may be set to have opposite phases to each other, but this is only an example and the present disclosure is not limited thereto. The setup and hold delay unit 103_1 may delay the clocks CLK_T and CLK_C received by the receiver 101_1 to control the setup time and hold time of each of the clocks CLK_T and CLK_C. The delay period during which the clocks CLK_T and CLK_C are delayed in the setup and hold delay unit 103_1 may be set in various ways according to the embodiment.

[0024] The receiver 101_2 may receive a chip selection signal CS through the pad 100_3. The chip selection signal CS may be received from a controller (eg, Figure 5 31) is applied, and can be used to determine whether to exit the power-down mode and generate a valid command. The setup and hold delay unit 103_2 can delay the chip selection signal CS received by the receiver 101_2 to control the setup time and hold time of the chip selection signal CS. The delay period during which the chip selection signal CS is delayed in the setup and hold delay unit 103_2 can be set in various ways according to the embodiment.

[0025] The receiver 101_3 may receive the first command address CAx through the pad 100_4. The first command address CAx may be received from a controller (eg, Figure 531) in, and may include commands and addresses for internal operations. The setup and hold delay unit 103_3 may delay the first command address CAx received by the receiver 101_3 to control the setup time and hold time of the first command address CAx. The delay period during which the first command address CAx is delayed in the setup and hold delay unit 103_3 may be set in various ways according to the embodiment.

[0026] The receiver 101_4 may receive the second command address CAy through the pad 100_5. The second command address CAy may be received from a controller (eg, Figure 5 31) in, and may include commands and addresses for internal operations. The setup and hold delay unit 103_4 may delay the second command address CAy received by the receiver 101_4 to control the setup time and hold time of the second command address CAy. The delay period during which the second command address CAy is delayed in the setup and hold delay unit 103_4 may be set in a variety of ways according to the embodiment. The second command address CAy may be applied at a different time from the first command address CAx, but may be implemented to be applied simultaneously with the first command address CAx according to the embodiment.

[0027] The frequency division enable signal generating circuit 105 may be electrically connected to the setup hold delay unit 103_2 to receive the chip selection signal CS from the setup hold delay unit 103_2. The frequency division enable signal generating circuit 105 may generate the frequency division enable signal DIV_EN based on the chip selection signal CS. When the chip selection signal CS is received in a preset state after leaving the power-off period, the frequency division enable signal generating circuit 105 may generate the activated frequency division enable signal DIV_EN. As an example, when the chip selection signal CS set to a logic "high" level is received after leaving the power-off period, the frequency division enable signal generating circuit 105 may generate the activated frequency division enable signal DIV_EN.

[0028] The clock frequency division circuit 107 may be electrically connected to the setup hold delay unit 103_1 and the frequency division enable signal generation circuit 105 to receive the clocks CLK_T and CLK_C from the setup hold delay unit 103_1, and receive the frequency division enable signal DIV_EN from the frequency division enable signal generation circuit 105. The clock frequency division circuit 107 may generate frequency division clocks ICLK, QCLK, IBCLK, and QBCLK from the frequency division enable signal DIV_EN and the clocks CLK_T and CLK_C. When the frequency division enable signal DIV_EN is activated, the clock frequency division circuit 107 may divide the clocks CLK_T and CLK_C to generate frequency division clocks ICLK, QCLK, IBCLK, and QBCLK. Each of the frequency division clocks ICLK, QCLK, IBCLK, and QBCLK may be set as a two-division signal of the clocks CLK_T and CLK_C, but this is only an example and the present disclosure is not limited thereto.

[0029] The valid time determination circuit 109 may be electrically connected to the setup hold delay unit 103_2 and the clock frequency division circuit 107 to receive the chip selection signal CS from the setup hold delay unit 103_2 and the divided clock IBCLK from the clock frequency division circuit 107. The valid time determination circuit 109 may detect the logic level of the chip selection signal CS in synchronization with the divided clock IBCLK to generate a valid signal VCS. As an example, when the detection condition of receiving the chip selection signal CS set to a logic "high" level in synchronization with the rising edge (defined as the part that transitions from a logic "low" level to a logic "high" level) of the divided clock IBCLK is met, the valid time determination circuit 109 may generate an activated valid signal VCS at the valid command generation time. Here, the valid command generation time may be set to the time when the detection condition is met or the time after a preset delay period from the time when the detection condition is met. As another example, when the detection condition of receiving the chip select signal CS set to a logic "high" level synchronously with the rising edge of the divided clock IBCLK "N" times or more is met, the effective time determination circuit 109 can generate an activated valid signal VCS at the effective command generation time. Here, "N" can be set to a natural number of 2 or more. As another example, when the detection condition of receiving the chip select signal CS set to a logic "high" level synchronously with the rising and falling edges (defined as the part that transitions from a logic "high" level to a logic "low" level) of the divided clock IBCLK is met, the effective time determination circuit 109 can generate an activated valid signal VCS at the effective command generation time. In addition, according to an embodiment, the effective time determination circuit 109 can be implemented to detect the logic level of the chip select signal CS synchronously with one of the divided clocks ICLK, QCLK, and QBCLK to generate a valid signal VCS.

[0030] The command address latch circuit 111 may be electrically connected to the clock frequency division circuit 107, the setup and hold delay unit 103_3, and the setup and hold delay unit 103_4 to receive the divided clocks ICLK, QCLK, IBCLK, and QBCLK from the clock frequency division circuit 107, receive the first command address CAx from the setup and hold delay unit 103_3, and receive the second command address CAy from the setup and hold delay unit 103_4. The command address latch circuit 111 may latch the first command address CAx and the second command address CAy in synchronization with the divided clocks ICLK, QCLK, IBCLK, and QBCLK to generate a first latched command address CA_R1. <x>、CA_F1 <x>、CA_R2 <x>and CA_F2 <x>And the second latch command address CA_R1 <y>、CA_F1 <y>、CA_R2 <y>and CA_F2 <y>More specifically, the command address latch circuit 111 may latch the first command address CAx and the second command address CAy in synchronization with the divided clock IBCLK to generate a first latched command address CA_R1. <x>and the second latch command address CA_R1 <y>The command address latch circuit 111 may latch the first command address CAx and the second command address CAy in synchronization with the divided clock QBCLK to generate a first latched command address CA_F1. <x>and the second latch command address CA_F1 <y>The command address latch circuit 111 can latch the first command address CAx and the second command address CAy in synchronization with the divided clock ICLK to generate a first latched command address CA_R2 <x>And the second latch command address CA_R2 <y>The command address latch circuit 111 may latch the first command address CAx and the second command address CAy in synchronization with the divided clock QCLK to generate a first latched command address CA_F2 <x>and the second latch command address CA_F2 <y>In an embodiment, the command address latch circuit 111 may include flip-flops (FF) 111_1 to 111_8 coupled to the semiconductor device 10, such as Figure 1 shown.

[0031] The command address decoder 113 may be electrically connected to the valid time determination circuit 109 and the command address latch circuit 111 to receive the valid signal VCS from the valid time determination circuit 109 and receive the first latch command address CA_R1. <x>、CA_F1 <x>、CA_R2 <x>and CA_F2 <x>And the second latch command address CA_R1 <y>、CA_F1 <y>、CA_R2 <y>and CA_F2 <y>When the valid signal VCS is activated at the valid command generation time, the command address decoder 113 may latch the first command address CA_R1 <x>、CA_F1 <x>、CA_R2 <x>and CA_F2 <x>And the second latch command address CA_R1 <y>、CA_F1 <y>、CA_R2 <y>and CA_F2 <y>The internal commands ACT, WR, RD, PRE and REF and the internal addresses RADD and CADD are decoded to generate the internal commands ACT, WR, RD, PRE and REF and the internal addresses RADD and CADD. The internal commands ACT, WR, RD, PRE and REF may include an activation command ACT generated for an activation operation, a write command WR generated for a write operation, a read command RD generated for a read operation, a precharge command PRE generated for a precharge operation, and a refresh command REF generated for a refresh operation. The internal addresses RADD and CADD may include a row address RADD for selecting a word line (not shown) in a row operation and a column address CADD for selecting an input / output switch (not shown) in a column operation.

[0032] The write delay shift circuit 115 may be electrically connected to the clock frequency division circuit 107 and the command address decoder 113 to receive the divided clock IBCLK from the clock frequency division circuit 107 and the write command WR from the command address decoder 113. The write delay shift circuit 115 may shift the write command WR based on the divided clock IBCLK to generate a shift command (i.e., a shift write command IWR). According to an embodiment, the write delay shift circuit 115 may be implemented to shift the write command WR based on one of the divided clocks ICLK, QCLK, and QBCLK.

[0033] The read delay shift circuit 117 may be electrically connected to the clock frequency division circuit 107 and the command address decoder 113 to receive the divided clock IBCLK from the clock frequency division circuit 107 and the read command RD from the command address decoder 113. The read delay shift circuit 117 may shift the read command RD based on the divided clock IBCLK to generate a shift command (i.e., a shifted read command IRD). According to an embodiment, the read delay shift circuit 117 may be implemented to shift the read command RD based on one of the divided clocks ICLK, QCLK, and QBCLK.

[0034] In an embodiment, the semiconductor device 10 configured as described above can set the command generation time according to the chip selection signal CS without using a separate control signal, thereby minimizing the number of control signals required to generate a command and improving pad usage efficiency. In an embodiment, the semiconductor device 10 can latch the command addresses CAx and CAy using the divided clock IBCLK and perform the shift operation required for the write operation and the read operation, thereby stably performing internal operations even when the high-frequency clocks CLK_T and CLK_C are input.

[0035] Figure 2 It is shown Figure 1 The timing diagram of the command generation operation of the semiconductor device 10 shown in FIG. Figure 1 and Figure 2 The command generation operation of the semiconductor device 10 is described in more detail.

[0036] First, at time T11, the semiconductor device 10 in the power-down mode can receive a chip selection signal CS of a logic "high" level in synchronization with the rising edge of the clock CLK_T to exit the power-down mode. Next, at time T12, the frequency division enable signal generation circuit 105 can receive a chip selection signal CS of a logic "high" level after exiting the power-down mode to generate an activated frequency division enable signal DIV_EN, and the clock frequency division circuit 107 can generate frequency division clocks ICLK, QCLK, IBCLK and QBCLK according to the frequency division enable signal DIV_EN. The voltage level fluctuation range of the chip selection signal CS can be set differently before and after exiting the power-down mode according to various reasons (such as whether termination is performed), but this is only an example and the present disclosure is not limited thereto. Next, after time T13, the command address latch circuit 111 can sequentially latch the first command address CAx in synchronization with the frequency division clocks ICLK, QCLK, IBCLK and QBCLK to generate the first latched command address CA_R1 <x>、CA_F1 <x>、CA_R2 <x>and CA_F2 <x>In addition, since the detection condition of receiving the chip selection signal CS set to a logic "high" level in synchronization with the rising edge of the divided clock IBCLK at time T13 is satisfied, the valid time determination circuit 109 can generate an activated valid signal VCS at the valid command generation time (i.e., time T15). During the period in which the valid signal VCS is activated after time T15, the command address decoder 113 can latch the first command address CA_R1. <x>、CA_F1 <x>、CA_R2 <x>and CA_F2 <x>The decoding is performed to generate at least one of the internal commands ACT, WR, RD, PRE, and REF and the internal addresses RADD and CADD.

[0037] Figure 3 2 is a block diagram showing the configuration of a semiconductor device 20 according to an embodiment of the present disclosure. Figure 3 As shown, the semiconductor device 20 may include pads 200_1, 200_2, 200_3, 200_4 and 200_5, receivers (Rx) 201_1, 201_2, 201_3 and 201_4, set up hold delay units (SHD) 203_1, 203_2, 203_3, 203_4, a division enable signal generating circuit (DIV_EN GEN) 205, a clock division circuit (CLK DIV) 207, a valid time determining circuit (VALID DET) 209, a command address latch circuit 211, a command address decoder (CA DEC) 213, a write delay shift circuit (WL SFT) 215 and a read delay shift circuit (RL SFT) 217.

[0038] The receiver 201_1 may receive the clocks CLK_T and CLK_C through the pads 200_1 and 200_2. The setup and hold delay unit 203_1 may delay the clocks CLK_T and CLK_C received by the receiver 201_1 to control the setup time and hold time of each of the clocks CLK_T and CLK_C. The delay period during which the clocks CLK_T and CLK_C are delayed in the setup and hold delay unit 203_1 may be set in various ways according to embodiments.

[0039] The receiver 201_2 may receive the chip selection signal CS through the pad 200_3. The setup and hold delay unit 203_2 may delay the chip selection signal CS received by the receiver 201_2 to control the setup time and hold time of the chip selection signal CS. The delay period during which the chip selection signal CS is delayed in the setup and hold delay unit 203_2 may be set in various ways according to the embodiment.

[0040] The receiver 201_3 may receive the first command address CAx through the pad 200_4. The setup and hold delay unit 203_3 may delay the first command address CAx received by the receiver 201_3 to control the setup time and hold time of the first command address CAx. The delay period during which the first command address CAx is delayed in the setup and hold delay unit 203_3 may be set in various ways according to the embodiment.

[0041] The receiver 201_4 may receive the second command address CAy through the pad 200_5. The setup and hold delay unit 203_4 may delay the second command address CAy received through the receiver 201_4 to control the setup time and hold time of the second command address CAy. The delay period during which the second command address CAy is delayed in the setup and hold delay unit 203_4 may be set in various ways according to the embodiment. The second command address CAy may be applied at a different time from the first command address CAx, but may be implemented to be applied simultaneously with the first command address CAx according to the embodiment.

[0042] The frequency division enable signal generation circuit 205 may be electrically connected to the setup hold delay unit 203_2 to receive the chip selection signal CS from the setup hold delay unit 203_2. The frequency division enable signal generation circuit 205 may generate the frequency division enable signal DIV_EN based on the chip selection signal CS. When the chip selection signal CS is received in a preset state after leaving the power-off period, the frequency division enable signal generation circuit 205 may generate the activated frequency division enable signal DIV_EN.

[0043] The clock frequency division circuit 207 may be electrically connected to the setup hold delay unit 203_1 and the frequency division enable signal generation circuit 205 to receive the clocks CLK_T and CLK_C from the setup hold delay unit 203_1 and the frequency division enable signal DIV_EN from the frequency division enable signal generation circuit 205. The clock frequency division circuit 207 may generate frequency division clocks ICLK, QCLK, IBCLK, and QBCLK from the frequency division enable signal DIV_EN and the clocks CLK_T and CLK_C. When the frequency division enable signal DIV_EN is activated, the clock frequency division circuit 207 may divide the clocks CLK_T and CLK_C to generate the frequency division clocks ICLK, QCLK, IBCLK, and QBCLK.

[0044] The valid time determination circuit 209 may be electrically connected to the setup hold delay unit 203_2 and the clock frequency division circuit 207 to receive the chip selection signal CS from the setup hold delay unit 203_2 and the frequency division clock IBCLK from the clock frequency division circuit 207. The valid time determination circuit 209 may detect the logic level of the chip selection signal CS in synchronization with the frequency division clock IBCLK to generate a first valid signal VCS1 and a second valid signal VCS2. As an example, when the detection condition of receiving the chip selection signal CS set to a logic "high" level in synchronization with the rising edge of the frequency division clock IBCLK is met, the valid time determination circuit 209 may generate a first valid signal VCS1 activated at a first valid command generation time and a second valid signal VCS2 activated at a second valid command generation time. Here, the first valid command generation time may be set to a time when the detection condition is met or a time when a preset delay period has passed from a time when the detection condition is met, and the second valid command generation time may be set to a time after the first valid command generation time. As another example, when a detection condition of receiving the chip selection signal CS set to a logic "high" level in synchronization with the rising edge of the divided clock IBCLK "N" times or more is satisfied, the valid time determination circuit 209 may generate a first valid signal VCS1 activated at a first valid command generation time and a second valid signal VCS2 activated at a second valid command generation time. As another example, when a detection condition of receiving the chip selection signal CS set to a logic "high" level in synchronization with the rising and falling edges of the divided clock IBCLK is satisfied, the valid time determination circuit 209 may generate a first valid signal VCS1 activated at a first valid command generation time and a second valid signal VCS2 activated at a second valid command generation time. In addition, depending on the embodiment, the valid time determination circuit 209 may be implemented to detect the logic level of the chip selection signal CS in synchronization with one of the divided clocks ICLK, QCLK, and QBCLK to generate the first valid signal VCS1 and the second valid signal VCS2.

[0045] The command address latch circuit 211 may be electrically connected to the clock frequency division circuit 207, the setup and hold delay unit 203_3, and the setup and hold delay unit 203_4 to receive the divided clocks ICLK, QCLK, IBCLK, and QBCLK from the clock frequency division circuit 207, receive the first command address CAx from the setup and hold delay unit 203_3, and receive the second command address CAy from the setup and hold delay unit 203_4. The command address latch circuit 211 may latch the first command address CAx and the second command address CAy in synchronization with the divided clocks ICLK, QCLK, IBCLK, and QBCLK to generate a first latched command address CA_R1. <x>、CA_F1 <x>、CA_R2 <x>and CA_F2 <x>And the second latch command address CA_R1 <y>、CA_F1 <y>、CA_R2 <y>and CA_F2 <y>More specifically, the command address latch circuit 211 may latch the first command address CAx and the second command address CAy in synchronization with the divided clock IBCLK to generate a first latched command address CA_R1. <x>and the second latch command address CA_R1 <y>The command address latch circuit 211 may latch the first command address CAx and the second command address CAy in synchronization with the divided clock QBCLK to generate a first latched command address CA_F1. <x>and the second latch command address CA_F1 <y>The command address latch circuit 211 may latch the first command address CAx and the second command address CAy in synchronization with the divided clock ICLK to generate a first latched command address CA_R2 <x>And the second latch command address CA_R2 <y>The command address latch circuit 211 may latch the first command address CAx and the second command address CAy in synchronization with the divided clock QCLK to generate a first latched command address CA_F2 <x>and the second latch command address CA_F2 <y>.

[0046] The command address decoder 213 may be electrically connected to the valid time determination circuit 209 and the command address latch circuit 211 to receive the first valid signal VCS1 and the second valid signal VCS2 from the valid time determination circuit 209 and receive the first latch command address CA_R1 from the command address latch circuit 211. <x>、CA_F1 <x>、CA_R2 <x>and CA_F2 <x>And the second latch command address CA_R1 <y>、CA_F1 <y>、CA_R2 <y>and CA_F2 <y>When the first valid signal VCS1 is activated at the first valid command generation time, the command address decoder 213 may latch the first command address CA_R1. <x>、CA_F1 <x>、CA_R2 <x>and CA_F2 <x>And the second latch command address CA_R1 <y>、CA_F1 <y>、CA_R2 <y>and CA_F2 <y>The command address decoder 213 can decode the first latch command address CA_R1 to generate the internal commands ACT, WR, RD, PRE and REF and the internal addresses RADD and CADD. <x>、CA_F1 <x>、CA_R2 <x>and CA_F2 <x>And the second latch command address CA_R1 <y>、CA_F1 <y>、CA_R2 <y>and CA_F2 <y>Decodes to generate internal commands ACT, WR, RD, PRE, and REF and internal addresses RADD and CADD.

[0047] The write delay shift circuit 215 may be electrically connected to the clock frequency division circuit 207 and the command address decoder 213 to receive the divided clock IBCLK from the clock frequency division circuit 207 and the write command WR from the command address decoder 213. The write delay shift circuit 215 may shift the write command WR based on the divided clock IBCLK to generate a shifted write command IWR.

[0048] The read delay shift circuit 217 may be electrically connected to the clock frequency division circuit 207 and the command address decoder 213 to receive the divided clock IBCLK from the clock frequency division circuit 207 and the read command RD from the command address decoder 213. The read delay shift circuit 217 may shift the read command RD based on the divided clock IBCLK to generate a shifted read command IRD.

[0049] In an embodiment, the semiconductor device 20 configured as described above can set the command generation time according to the chip selection signal CS without using a separate control signal, thereby minimizing the number of control signals required to generate a command and improving pad usage efficiency. In addition, in an embodiment, the semiconductor device 20 can use the divided clock IBCLK to latch the command addresses CAx and CAy and perform the shift operation required for the write operation and the read operation, thereby stably performing internal operations even when the high-frequency clocks CLK_T and CLK_C are input.

[0050] Figure 4 It is shown Figure 3 The timing diagram of the command generation operation of the semiconductor device 20 shown in FIG. Figure 3 and Figure 4 The command generation operation of the semiconductor device 20 is described in more detail.

[0051] First, at time T21, the semiconductor device 20 in the power-down mode can receive the chip selection signal CS of the logic "high" level in synchronization with the rising edge of the clock CLK_T to exit the power-down mode. Next, at time T22, after exiting the power-down mode, the frequency division enable signal generation circuit 205 can receive the chip selection signal CS of the logic "high" level to generate an activated frequency division enable signal DIV_EN, and the clock frequency division circuit 207 can generate the frequency division clocks ICLK, QCLK, IBCLK and QBCLK according to the frequency division enable signal DIV_EN. Next, after time T23, the command address latch circuit 211 can sequentially latch the first command address CAx in synchronization with the frequency division clocks ICLK, QCLK, IBCLK and QBCLK to generate the first latched command address CA_R1. <x>、CA_F1 <x>、CA_R2 <x>and CA_F2 <x>In addition, at time T23, the detection condition of receiving the chip selection signal CS set to a logic "high" level in synchronization with the rising edge of the divided clock IBCLK is satisfied, so that the valid time determination circuit 209 can generate the activated first valid signal VCS1 at the first valid command generation time (that is, at time T25). During the period in which the first valid signal VCS1 is activated after time T25, the command address decoder 213 can latch the first command address CA_R1. <x>、CA_F1 <x>、CA_R2 <x>and CA_F2 <x>The command address decoder 213 may decode to generate at least one of the internal commands ACT, WR, RD, PRE, and REF and the internal addresses RADD and CADD. In addition, the valid time determination circuit 209 may generate the second valid signal VCS2 activated at the second valid command generation time (i.e., time T26). During the period in which the second valid signal VCS2 is activated after time T26, the command address decoder 213 may latch the first command address CA_R1 <x>、CA_F1 <x>、CA_R2 <x>and CA_F2 <x>The decoded data is decoded to generate at least one of the internal commands ACT, WR, RD, PRE, and REF and the internal addresses RADD and CADD.

[0052] Figure 5 is a block diagram showing the configuration of a semiconductor system 3 according to an embodiment of the present disclosure. Figure 5 As shown, the semiconductor system 3 may include a controller 31 and a semiconductor device 33 .

[0053] The controller 31 may include a first control pin 31_1, a second control pin 31_3, and a third control pin 31_5. The semiconductor device 33 may include a first device pin 33_1, a second device pin 33_3, and a third device pin 33_5. The controller 31 may transmit the clocks CLK_T and CLK_C to the semiconductor device 33 through a first transmission line 32_1 connected between the first control pin 31_1 and the first device pin 33_1. The first control pin 31_1, the first transmission line 32_1, and the first device pin 33_1 may be provided for each of the clocks CLK_T and CLK_C. The controller 31 may apply a chip select signal CS to the semiconductor device 33 through a second transmission line 32_3 connected between the second control pin 31_3 and the second device pin 33_3. The controller 31 may transmit a first command address CAx and a second command address Cay to the semiconductor device 33 through a third transmission line 32_5 connected between the third control pin 31_5 and the third device pin 33_5. The third control pin 31_5 , the third transmission line 32_5 , and the third device pin 33_5 may be provided for each of the first command address CAx and the second command address CAy.

[0054] The semiconductor device 33 can set the command generation time according to the chip selection signal CS without using a separate control signal, thereby minimizing the number of control signals required to generate a command and improving pin usage efficiency.

[0055] Previous references Figure 1 The semiconductor device 10 described and the reference Figure 3 The semiconductor device 20 described can be applied to electronic systems including memory systems, graphics systems, computing systems, and mobile systems. Figure 6 , which is a block diagram illustrating a configuration of an electronic system 1000 according to an embodiment of the present disclosure, the electronic system 1000 may include a data storage unit 1001 , a memory controller 1002 , a buffer memory 1003 , and an input / output interface 1004 .

[0056] The data storage unit 1001 may store data (not shown) applied from the memory controller 1002 according to a control signal from the memory controller 1002, and may read out the stored data (not shown) to output the data to the memory controller 1002. In addition, the data storage unit 1001 may include a non-volatile memory device that can continuously store data without losing the data even when power is off. The non-volatile memory device may include a flash memory device (NOR flash memory device, NAND flash memory device), a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a spin transfer torque random access memory (STTRAM) device, or a magnetic random access memory (MRAM) device.

[0057] The memory controller 1002 can decode a command applied from an external device (host device) through the I / O interface 1004, and can control data input and output for the data storage unit 1001 and the buffer memory 1003 according to the decoding result. Figure 6 1002 is shown as one block, but the controller for controlling the data storage unit 1001 and the controller for controlling the buffer memory 1003 as a volatile memory device may be independently configured in the memory controller 1002. The memory controller 1002 may include the above reference Figure 5 The controller 31 is described.

[0058] The buffer memory 1003 may store data to be processed by the memory controller 1002, that is, data (not shown) input or output to or from the data storage unit 1001. The buffer memory 1003 may store data (not shown) applied from the memory controller 1002 according to a control signal. The buffer memory 1003 may include the above-referenced Figure 1 The semiconductor device 10 described above or the semiconductor device 10 described above Figure 3 The semiconductor device 20 described above. The buffer memory 1003 may read out the stored data to output the data to the memory controller 1002. The buffer memory 1003 may include a volatile memory device such as a dynamic random access memory (DRAM) device, a mobile DRAM device, or a static random access memory (SRAM) device.

[0059] The I / O interface 1004 may provide a physical connection between the memory controller 1002 and an external device (host device) to allow the memory controller 1002 to receive control signals for data input / output from the external device and to exchange data with the external device. The I / O interface 1004 may include one of a variety of interface protocols, such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI, and IDE.

[0060] The electronic system 1000 may be used as an auxiliary storage device or an external storage device of a host device. The electronic system 1000 may include a solid state disk (SSD), a universal serial bus (USB) memory, a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC), a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded multimedia card (eMMC), and a compact flash (CF) card, etc.

[0061] Figure 7 2 is a block diagram showing a configuration of an electronic system 2000 according to another embodiment of the present disclosure. Figure 7 As shown, the electronic system 2000 may include a host 2100 and a semiconductor system 2200 .

[0062] The host 2100 and the semiconductor system 2200 may use an interface protocol to transmit signals to each other. The interface protocol used between the host 2100 and the semiconductor system 2200 may include a multimedia card (MMC), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a peripheral component interconnect express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a serial attached SCSI (SAS), and a universal serial bus (USB), etc.

[0063] The semiconductor system 2200 may include a controller 2300 and semiconductor devices 2400 (1:K). The controller 2300 may apply a voltage code V_CD, a code input control signal CICNT, and a fuse selection address FS_ADD to each semiconductor device 2400 (1:K). Each semiconductor device 2400 (1:K) may receive the voltage code V_CD, the code input control signal CICNT, and the fuse selection address FS_ADD to control the voltage level of the internal voltage VINT.

[0064] Each semiconductor device 1400 (1:K) may include the above reference Figure 1 The semiconductor device 10 or the semiconductor device 10 described above Figure 3 The semiconductor device 20. Each semiconductor device 1400 (1:K) can be implemented by one of a dynamic random access memory (DRAM) device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device.

[0065] Concepts have been disclosed in conjunction with some of the embodiments described above. Those skilled in the art will appreciate that multiple modifications, additions and / or substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered restrictive, but exemplary. The scope of the concept is not limited to the above description, but is defined by the appended claims, and all different features within the equivalent range should be interpreted as being included in the concept.< / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / y> < / y> < / y> < / y> < / x> < / x> < / x> < / x> < / y> < / y> < / y> < / y> < / x> < / x> < / x> < / x> < / y> < / y> < / y> < / y> < / x> < / x> < / x> < / x> < / y> < / x> < / y> < / x> < / y> < / x> < / y> < / x> < / y> < / y> < / y> < / y> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / y> < / y> < / y> < / y> < / x> < / x> < / x> < / x> < / y> < / y> < / y> < / y> < / x> < / x> < / x> < / x> < / y> < / x> < / y> < / x> < / y> < / x> < / y> < / x> < / y> < / y> < / y> < / y> < / x> < / x> < / x> < / x>

Claims

1. A semiconductor device, comprising: a clock frequency division circuit that: when the frequency division enable signal is activated based on the chip selection signal, receives the frequency division enable signal to generate a frequency division clock from the clock signal; and A valid time determination circuit generates a valid signal for setting a generation time of a command based on the chip selection signal and the divided clock.

2. The semiconductor device according to claim 1, wherein The clock frequency division circuit generates the divided clock when the chip selection signal is received in a preset state and the frequency division enable signal is activated after leaving the power-down period.

3. The semiconductor device according to claim 1, wherein The clock frequency division circuit generates the divided clock when the chip selection signal set to a preset logic level is received in synchronization with the clock signal and the frequency division enable signal is activated after leaving the power-down period.

4. The semiconductor device according to claim 1, wherein: The valid time determination circuit detects a logic level of the chip selection signal in synchronization with one of the divided clocks to generate the valid signal.

5. The semiconductor device according to claim 4, wherein: The valid time determination circuit generates the valid signal activated at a valid command generation time when a detection condition of receiving the chip selection signal set to a preset logic level in synchronization with one of the divided clocks is satisfied.

6. The semiconductor device according to claim 5, wherein: The effective command generation time is set to a time when the detection condition is satisfied, or a time when a preset delay period elapses from a time when the detection condition is satisfied.

7. The semiconductor device according to claim 4, wherein: The valid time determination circuit generates the valid signal activated at a valid command generation time when a detection condition of receiving the chip selection signal set to a preset logic level at least twice in synchronization with one of the divided clocks is satisfied.

8. The semiconductor device according to claim 4, wherein: The valid time determination circuit generates the valid signal activated at a valid command generation time when the detection condition of receiving the chip selection signal set to a preset logic level in synchronization with one of the divided clocks is satisfied.

9. The semiconductor device according to claim 1, further comprising: a command address latch circuit that latches a command address in synchronization with the divided clock to generate a latched command address; as well as A command address decoder is configured to decode the latched command address based on the valid signal to generate an internal command and an internal address. 10 . The semiconductor device according to claim 1 , further comprising a delay shift circuit that shifts an internal command in synchronization with one of the divided clocks to generate a shift command.

11. A semiconductor device comprising: A frequency division enable signal generating circuit that generates an activated frequency division enable signal when a chip selection signal set to have a preset logic level after leaving a power-down period is received in synchronization with a clock signal; and A valid time determination circuit generates a valid signal for setting a generation time of a command based on a frequency-divided clock generated based on the frequency-divided enable signal and the chip select signal.

12. The semiconductor device according to claim 11, wherein The valid time determination circuit generates the valid signal activated at a valid command generation time when a detection condition of receiving the chip selection signal set to a preset logic level in synchronization with one of the divided clocks is satisfied.

13. The semiconductor device according to claim 12, wherein: The effective command generation time is set to a time when the detection condition is satisfied, or a time when a preset delay period elapses from a time when the detection condition is satisfied.

14. The semiconductor device according to claim 11, wherein The valid time determination circuit generates the valid signal activated at a valid command generation time when the detection condition of receiving the chip selection signal set to a preset logic level in synchronization with the rising edge and the falling edge of one of the divided clocks is satisfied.

15. The semiconductor device according to claim 11, further comprising: a command address latch circuit that latches a command address in synchronization with the divided clock to generate a latched command address; A command address decoder, which: decodes the latched command address based on the valid signal to generate an internal command and an internal address; as well as A time-delay shift circuit shifts the internal command in synchronization with one of the divided frequency clocks to generate a shift command.

16. A semiconductor device comprising: a clock frequency division circuit, which: receives the frequency division enable signal to generate a frequency-divided clock from the clock signal when the frequency division enable signal is activated based on the chip selection signal; and A valid time determination circuit generates a first valid signal and a second valid signal for setting a generation time of a command based on the chip selection signal and the divided clock.

17. The semiconductor device according to claim 16, wherein: The effective time determination circuit generates the first effective signal activated at a first effective command generation time and generates the second effective signal activated at a second effective command generation time when a detection condition of receiving the chip selection signal set to a preset logic level in synchronization with one of the divided clocks is met.

18. The semiconductor device according to claim 17, wherein: The first effective command generation time is set to a time when the detection condition is satisfied, or a time when a preset delay period elapses from a time when the detection condition is satisfied.

19. The semiconductor device according to claim 18, wherein: The second valid command generation time is set to a time after the first valid command generation time.

20. The semiconductor device according to claim 16, wherein The effective time determination circuit generates the first effective signal activated at a first effective command generation time and generates the second effective signal activated at a second effective command generation time when a detection condition of receiving the chip selection signal set to a preset logic level at least twice in synchronization with one of the divided clocks is met.

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