Data writing method and memory controller

Abstract

The invention provides a data writing method and a memory controller, which are suitable for a rewritable nonvolatile memory module with a plurality of memory units. The method comprises the following steps: firstly, obtaining original data from a host system; then, a plurality of randomization operations are performed on the original data to obtain a plurality of write-in data. Next, based on a plurality of directions of a three-dimensional circuit architecture of the rewritable nonvolatile memory module, a randomization verification operation is performed on each write data to obtain a target write data among the plurality of write data, where the randomization quality of the target write data is determined to be qualified. Finally, the target write data is stored in a plurality of target memory cells of the plurality of memory cells. Through multiple randomization operations and verification processes, the randomness and reliability of data storage are effectively improved, so that the overall performance and data security of a storage system are enhanced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor storage technology, and in particular to a data writing method for a rewritable non-volatile memory module and a memory controller using the method. Background Art

[0002] With the rapid development of information technology, non-volatile storage devices are increasingly used in various electronic products. In particular, three-dimensional NAND flash memory has become the mainstream of current non-volatile storage technology due to its high storage density, low cost and excellent performance. However, with the continuous improvement of storage density, data reliability and interference between storage units have become more and more prominent.

[0003] In order to improve the reliability of data storage and reduce the interference between cells, data randomization technology is widely used in NAND flash memory. Traditional data randomization methods usually use a single randomization algorithm, such as a simple XOR operation or a fixed permutation table. Although this method improves data distribution to a certain extent, its effect is often unsatisfactory in the face of increasingly complex three-dimensional NAND flash memory structures.

[0004] In addition, the prior art generally lacks an effective verification mechanism for randomization results. Directly writing data without verifying the quality of randomization may result in some data patterns being unevenly distributed in the memory, thus affecting storage performance and reliability. Especially in high-density storage scenarios, improper data distribution may lead to problems such as read interference and write interference, thereby shortening the service life of the storage device. Summary of the invention

[0005] The purpose of the present invention is to solve the above problems, to be able to perform multiple randomization operations and effectively verify the randomization quality to ensure that the data written into the memory has good random distribution characteristics, thereby improving the reliability and performance of the storage.

[0006] One or more embodiments of the present invention provide a data writing method for a rewritable non-volatile memory module having a plurality of storage units. The method comprises: obtaining original data from a host system; performing a plurality of randomization operations on the original data to obtain a plurality of write data; performing a randomization verification operation on each write data based on a plurality of directions of a three-dimensional circuit architecture of the rewritable non-volatile memory module to obtain target write data among the plurality of write data, wherein the randomization quality of the target write data is determined to be qualified; and storing the target write data into a plurality of target storage units among the plurality of storage units.

[0007] In one or more embodiments of the present invention, each randomization operation uses a different randomization algorithm to process the original data, wherein the different randomization algorithms include at least one of the following: an exclusive OR (XOR) operation, performing an exclusive OR operation on the original data with a predefined plurality of different random sequences; a shift operation, performing a different plurality of cyclic shifts or logical shifts on the original data; a permutation operation, changing the order of bits in the original data according to a predefined plurality of different permutation tables; a dynamic random seed operation, generating a different plurality of random seeds based on system time, data address or other system variables, and using the plurality of random seeds and the original data to generate the plurality of write data; and a grouping operation, dividing the original data into a plurality of sub-blocks, and applying different exclusive OR operations, shift operations, permutation operations, and dynamic random seed operations to the plurality of sub-blocks.

[0008] In one or more embodiments of the present invention, the step of performing the randomization verification operation on each write data based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module includes: obtaining M bit value groups corresponding to a first direction of the multiple directions of the write data, the multiple bit values ​​in each bit value group corresponding to multiple storage units in the first direction of the rewritable non-volatile memory module, and each bit value corresponds to one of N bit states, where N is 2X, and X is the number of bits that can be stored in each storage unit; according to the multiple bit values ​​of each bit value group, obtaining N state proportions corresponding to the N bit states of each bit value group; according to the N state proportions, obtaining the randomization quality of the write data corresponding to the first direction.

[0009] In one or more embodiments of the present invention, the step of performing the randomization verification operation on each write data based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module also includes: obtaining a benchmark proportion value based on the N bit states; and obtaining the quality of the randomization of the write data corresponding to the first direction based on the N state proportions and the benchmark proportion value.

[0010] In one or more embodiments of the present invention, the step of performing the randomization verification operation on each write data based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module also includes: based on each bit value group, obtaining N deviation values ​​between the N state proportions of each bit value group and the reference proportion value; according to the M deviation values ​​corresponding to the same bit state of the M bit value groups, taking the maximum of the M deviation values ​​as the maximum deviation value corresponding to the same bit state, thereby obtaining N maximum deviation values ​​corresponding to the N bit states; if the N maximum deviation values ​​are all not greater than a preset threshold, determining that the quality of the randomization of the write data corresponding to the first direction is qualified; if one of the N maximum deviation values ​​is greater than the preset threshold, determining that the quality of the randomization of the write data corresponding to the first direction is unqualified.

[0011] In one or more embodiments of the present invention, the multiple directions include the first direction, the second direction, and the third direction. Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each write data also includes: obtaining P bit value groups corresponding to the second direction of the write data and N maximum deviation values ​​corresponding to the N bit states of the P bit value groups to obtain the quality of the randomization of the write data corresponding to the second direction; obtaining Q bit value groups corresponding to the third direction of the write data and N maximum deviation values ​​corresponding to the N bit states of the Q bit value groups to obtain the quality of the randomization of the write data corresponding to the third direction; and if the quality of the randomization of the write data corresponding to the first direction, the second direction, and the third direction are all qualified, determining that the quality of the randomization of the write data is qualified.

[0012] In one or more embodiments of the present invention, after determining that the quality of the randomization corresponding to the first direction of the written data is unqualified, the method further includes: obtaining one or more abnormal maximum deviation values ​​greater than the preset threshold among the N maximum deviation values ​​and one or more abnormal bit states corresponding to the one or more abnormal maximum deviation values ​​among the N bit states; and recording the first direction and the one or more abnormal bit states corresponding to the first direction.

[0013] In one or more embodiments of the present invention, if the quality of the randomization of the multiple write data is unqualified, the method further includes: adjusting the multiple randomization operations according to the one or more abnormal bit states and the corresponding directions to regenerate new multiple write data; and performing the randomization verification operation on each new write data again to attempt to obtain the target write data, and then storing the target write data to the multiple target storage units.

[0014] One or more embodiments of the present invention provide a memory controller suitable for a storage device configured with a rewritable non-volatile memory module, wherein the storage device is electrically connected to a host system. The memory controller includes: a memory interface control circuit for electrically connecting to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of storage units; and a processor electrically connected to the memory interface control circuit. The processor is configured to: obtain original data from the host system; perform a plurality of randomization operations on the original data to obtain a plurality of write data; perform a randomization verification operation on each write data based on a plurality of directions of a three-dimensional circuit architecture of the rewritable non-volatile memory module to obtain a target write data among the plurality of write data, wherein the quality of the randomization of the target write data is determined to be qualified; and store the target write data in a plurality of target storage units among the plurality of storage units.

[0015] Based on the above, the data writing method and randomized verification operation proposed by the present invention have obvious technical effects in a three-dimensional non-volatile memory. By performing multiple randomization operations on the written data and executing the verification process based on multiple directions of the three-dimensional circuit architecture, the method can effectively improve the uniformity of data distribution in the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0017] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention;

[0018] Figure 2 is a flow chart of a data writing method according to an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of a randomization operation according to an embodiment of the present invention;

[0020] Figure 4is a schematic diagram of a three-dimensional circuit architecture of a plurality of storage units of a rewritable non-volatile memory module according to an embodiment of the present invention;

[0021] Figure 5 FIG. 4 is a flow chart of a randomized verification operation according to an embodiment of the present invention.

[0022] Description of Figure Numbers

[0023] 10: Host system

[0024] 20: Storage device

[0025] 211: First processor

[0026] 110: Second processor

[0027] 120: Host memory

[0028] 130: Data transmission interface circuit

[0029] 210: Memory Controller

[0030] 212: Data management circuit

[0031] 213: Memory interface control circuit

[0032] 214: Buffer memory

[0033] 220: Rewritable non-volatile memory module

[0034] 230: Connecting interface circuit

[0035] S210~S240: Process steps of memory testing method

[0036] OD1, OD2: original data

[0037] WD1~WD4: write data

[0038] A31~A34: Arrow

[0039] WL0~WL3:Word lines

[0040] BL0~BL2: bit lines

[0041] CSTR: Cell string

[0042] SL0~SL2:Sequential wiring

[0043] SSL: Source Select Line

[0044] GSL: Ground Select Line

[0045] CSL: Common Source Line

[0046] MCT: Memory Cell Transistor

[0047] SST: Source Select Transistor

[0048] GST: Ground Select Transistor

[0049] S510~S580: Process steps of randomized verification operation DETAILED DESCRIPTION

[0050] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0051] Figure 1 FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention. Figure 1 , the host system 10 is, for example, a personal computer, a notebook computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other using a system bus. In this embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on a motherboard of the host system 10. In this embodiment, the original data is, for example, user data transmitted from the host system 10 to the storage device 20, or data that has not yet been subjected to a randomization operation.

[0052] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also called a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0053] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0054] In this embodiment, the number of the data transmission interface circuit 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless manner. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD) or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device or a low power consumption Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. through a system bus.

[0055] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the high-speed peripheral component interconnect interface (Peripheral Component Interconnect Express, PCI Express) standard. In addition, the data transmission interface circuit 130 and the connection interface circuit 230 use the fast non-volatile memory interface standard (Non-Volatile Memory express, NVMe) communication protocol to transmit data.

[0056] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0057] In the present embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in the present embodiment, the host memory 120 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, it should be understood that the present invention is not limited thereto, and the host memory 120 may also be other suitable memories.

[0058] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to instructions of the host system 10 .

[0059] In more detail, the processor 211 in the memory controller 210 is hardware with computing capabilities, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control instructions / program codes, and when the storage device 20 operates, these control instructions / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in this embodiment, the control instructions / program codes can be further executed to perform data writing operations, randomization verification operations or randomization operations to implement the data writing method provided by the present invention. The control instructions / program codes corresponding to the data writing method can be further implemented as a circuit unit in the form of hardware to implement the data writing method provided by the present invention.

[0060] It is worth mentioning that in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, but the present invention is not limited thereto.

[0061] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 can also be regarded as the operations performed by the memory controller 210.

[0062] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., the write operation is performed according to the write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (the data can be read from one or more storage units in the one or more physical units), and the read data is written to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., the read operation is performed according to the read instruction from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0063] The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform a write (also called programming) operation, a read operation or an erase operation on the rewritable non-volatile memory module 220 .

[0064] In addition, the data to be written to the rewritable non-volatile memory module 220 will be converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will transmit a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in the read instruction sequence, information such as the read identification code, memory address, and physical address will be included.

[0065] In addition, the memory controller 210 establishes a logical to physical address mapping table (Logical To Physical address mapping table) and a physical to logical address mapping table (Physical To Logical address mapping table) to record the mapping relationship between the logical address of the logical unit (e.g., logical block, logical page) configured for the rewritable non-volatile memory module 220 and the physical address (physical address) of the physical unit (e.g., physical erase unit / physical block, physical page). In other words, the memory controller 210 can search for the physical unit mapped by a logical unit (e.g., search for the physical page mapped by a logical page; search for the physical address mapped by a logical address) through the logical to physical address mapping table (also called the logical to physical mapping table), and the memory controller 210 can search for the logical unit mapped by a physical unit (e.g., search for the logical page mapped by a physical page; search for the logical address mapped by a physical address) through the physical to logical address mapping table (also called the physical to logical mapping table).

[0066] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data for managing the storage device 20 (e.g., various mapping tables, index tables, various information or data related to randomization operations and randomization verification operations), so that the processor 211 can quickly access the data, instructions or system data from the buffer memory 216. In one embodiment, the memory controller 210 can establish one or more write mapping tables in the buffer memory 214 to indicate the target physical address for writing valid data. It should be noted that in other embodiments, the buffer memory 214 can also be configured outside the memory controller 210. Alternatively, the buffer memory 214 can be configured inside and outside the memory controller 210.

[0067] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213 ) and is used to store user data sent by the host system 10 .

[0068] In the present embodiment, each memory grain (chip) of the multiple memory grains of the rewritable non-volatile memory module 220 has multiple planes, and each plane has multiple physical blocks. Each physical block includes multiple physical programming units (also called physical pages). Each physical page has multiple storage groups (also called physical bytes or bytes), and each storage group corresponds to a physical address. The physical address is used to record the physical location of the data stored in the storage group. It should be noted that the present invention is not limited to the size of each physical page and logical page.

[0069] Figure 2 FIG. 4 is a flow chart of a data writing method according to an embodiment of the present invention.

[0070] Please refer to Figure 2 In step S210, the memory controller 210 (processor 211) obtains original data from the host system 10. Next, in step S220, the processor 211 performs multiple randomization operations on the original data to obtain multiple write data.

[0071] In one embodiment, the processor 211 performs a randomization operation on the original data to obtain write data, wherein the randomization operation is used to change the distribution mode of the first bit value and the second bit value in the original data, so that the arrangement of the first bit value and the second bit value in the write data presents a random distribution characteristic, wherein the first bit value and the second bit value correspond to "0" and "1" in binary data, respectively. After performing the randomization operation, the processor 211 stores the corresponding write data obtained into the buffer memory 214.

[0072] Figure 3 FIG. 1 is a schematic diagram of a randomization operation according to an embodiment of the present invention. For example, the randomization operation of the present invention can be further described by a specific example. Figure 3 As shown in FIG. 1 , the process of performing randomization operation on the original data is shown in FIG. 1 . In this example, two groups of original data OD1 and OD2 are considered, each group containing 8 bits.

[0073] OD1 consists of 8 consecutive "1"s (11111111), while OD2 consists of 8 consecutive "0"s (00000000). These two sets of data represent non-random distribution in extreme cases, where the distribution of the first bit value ("0") and the second bit value ("1") is highly concentrated. The original data is, for example, user data that the host system 10 wants to store in the storage device 20.

[0074] By performing the randomization operation, the corresponding write data WD1, WD2, WD3 and WD4 are obtained. Specifically:

[0075] After the (first) randomization operation A31, OD1 generates WD1 (01010101).

[0076] After another (second) randomization operation A32, OD1 generates WD2 (10101010).

[0077] After the (third) randomization operation A33, OD2 generates WD3 (10101010).

[0078] After another (fourth) randomization operation A34, OD2 generates WD4 (01010101).

[0079] From the results, it can be seen that no matter whether the original data is all "1" or all "0", the written data obtained after the randomization operation presents a pattern of "0" and "1" appearing evenly alternately. This pattern significantly changes the original distribution of the first bit value and the second bit value in the original data, making the arrangement of "0" and "1" in the written data present a more random distribution characteristic.

[0080] It is worth noting that although the written data in this example presents a regular alternating pattern, this is only for the purpose of simplifying the description. In practical applications, the result of the randomization operation usually produces a more complex and irregular bit distribution to ensure the security of data stored in the storage device.

[0081] Through this example, we can clearly see how the randomization operation effectively changes the distribution pattern of the bit values ​​in the original data, thereby achieving the purpose of data randomization. This randomization can not only improve the uniformity of data storage, so that the storage unit will not cause write interference due to the uneven distribution of data bit values, but also enhance data security.

[0082] More specifically, in one embodiment, the process of performing multiple randomization operations on the original data may use different randomization algorithms to process the original data, wherein the different randomization algorithms include at least one of the following:

[0083] (1) XOR operation: The system (e.g., processor 211) predefines multiple sets of random sequences of different lengths and stores them in a lookup table. A random sequence of appropriate length is selected based on the size of the original data. If the length of the original data exceeds the random sequence, the random sequence is used cyclically. When performing the XOR operation, each bit of the original data is XORed with the corresponding bit of the random sequence to generate the first type of write data.

[0084] (2) Shift operation: The system maintains a shift pool containing different circular shift and logical shift values. When performing a shift operation on the original data, a value is selected from the shift pool and the entire data block is shifted. For large data blocks, they can be split into fixed-size segments, each using a different shift amount, and then reassembled to generate the second type of written data.

[0085] (3) Permutation operation: The system predefines multiple permutation tables, each of which defines a different way of reordering bits. Select a permutation table and rearrange the bits in the original data in the order defined in the table. For large data blocks, they can be divided into fixed-size blocks, each using a different permutation table, and then reassembled to generate a third type of written data.

[0086] (4) Dynamic random seed operation: The system collects a variety of system variables as inputs for random seeds, including but not limited to: system time (including local time of the host system 10 or storage device 20), data address, temperature sensor reading, power supply voltage fluctuation value, operating frequency of the memory controller 210, number of recent data read and write operations, unique identifier of the storage device 20, process ID or thread ID of the host system 10, MAC address of the network interface (if available), remaining capacity of the current storage device 20, running time since the last boot, value of the internal error counter of the storage device 20, etc. The system can select one of the variables as a seed, or combine multiple variables to generate a more complex seed. For example, the system time, temperature reading, and error counter value can be combined by bit operations to generate a composite seed. Use this seed to initialize a pseudo-random number generator (such as a linear congruential generator or a Mersenne twister algorithm) to generate a random sequence. Then, use this random sequence to transform the original data (such as an XOR operation or bitwise addition) to generate the fourth type of write data.

[0087] (5) Grouping operation: The original data is divided into multiple sub-blocks. The size of each sub-block can be fixed (such as 4KB) or dynamically determined (such as based on the entropy value of the data). For each sub-block, the system selects one or more of the above four operations for combined application. For example:

[0088] The first sub-block may first be subjected to an XOR operation and then to a bit shift operation.

[0089] The second sub-block can be permuted first and then operated using a dynamic random seed.

[0090] The third sub-block can only perform dynamic random seed operations.

[0091] After all sub-blocks are processed, they are reassembled to form the fifth type of written data.

[0092] Through these five different randomization operations, the system generates five different write data. This diverse randomization strategy increases the randomness of the data, making the distribution of the bit states of the bit values ​​of the final generated write data more uniform.

[0093] Please go back Figure 2 Next, in step S230, the processor 211 performs a randomization verification operation on each write data based on multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module to obtain target write data from the multiple write data, wherein the randomization quality of the target write data is determined to be qualified.

[0094] Before describing the details of the randomized verification operation, a three-dimensional circuit architecture of a plurality of memory cells of the rewritable non-volatile memory module 220 is described first, wherein the plurality of memory cells are considered to be arranged at the intersection of m first reference lines corresponding to the X direction (also called the first direction), p second reference lines corresponding to the Y direction (also called the second direction), and q third reference lines corresponding to the Z direction (also called the third direction).

[0095] Figure 4 The schematic diagram of the three-dimensional circuit architecture of multiple storage units of a rewritable non-volatile memory module according to an embodiment of the present invention is shown. The structure includes multiple key components to form a complex three-dimensional storage array. Taking a NAND type rewritable non-volatile memory module as an example, the specific structure is as follows:

[0096] Word Line (WL): WL0, WL1, WL2 and WL3 are marked in the figure and arranged horizontally along the x-axis. There are multiple parallel word lines on each plane, which are used to select the memory cells of a specific layer. The word line can be regarded as the first reference line corresponding to the x-direction (also called the first direction).

[0097] Bit Line (BL): In the figure, it is marked as BL0, BL1, BL2, etc., and is arranged vertically along the y-axis direction. The word line can be regarded as the second reference line corresponding to the Y direction (also called the second direction).

[0098] Cell String (CSTR): is a physical structure that contains a series of vertically stacked memory cells with SST at the top and GST at the bottom. It represents a complete vertical NAND string in a three-dimensional memory array and is the basic building block in a memory array.

[0099] String Line (SL): Marked as SL0, SL1, SL2, etc. in the figure, arranged vertically along the z-axis direction. Each string line contains a series of vertically stacked memory cells to form a NAND string structure. The string line can be regarded as the third reference line corresponding to the Z direction (also known as the third direction). The CSTR (Cell String) in the present invention refers to a complete vertical structure including a series of vertically stacked memory cells and a top SST and a bottom GST. Among them, the vertical memory cell stack part inside the CSTR can be called a string line (String Line).

[0100] Source Select Line (SSL): Located at the top of the NAND string and used to control the source select transistor (SST).

[0101] Ground Select Line (GSL): Located at the bottom of the NAND string, it is used to control the ground select transistor (GST).

[0102] Common Source Line (CSL): Located at the bottom, it provides a common source connection for all NAND strings.

[0103] Memory Cell Transistor (MCT): Marked as MCT in the figure, it is the unit that actually stores data.

[0104] Source Select Transistor (SST): Located at the top of each NAND string and controlled by SSL.

[0105] Ground Select Transistor (GST): Located at the bottom of each NAND string and controlled by the GSL.

[0106] Simply put, in this three-dimensional structure, the benchmarks in three directions are:

[0107] X direction: word line (WL), first reference line;

[0108] Y direction: bit line (BL), second reference line;

[0109] Z direction: string line (SL); third reference line.

[0110] The intersection of these three baselines is set as a memory cell, also known as a memory cell (marked as "Cell" in the figure). Each memory cell is located at the intersection of a specific WL, BL and SL, and can independently store and access data. This three-dimensional structure significantly improves the storage density, allowing more memory cells to be accommodated in the same chip area. It should be noted that these three directions are perpendicular to each other.

[0111] In one embodiment, the processor 211 obtains multiple bit values ​​of each written data, and each of the multiple bit values ​​is one of the preset N bit states. In the present invention, the storage unit of the non-volatile storage device can be configured to store different numbers of bit data. The number of bits that each storage unit can store can vary according to specific application requirements and technical implementations, and can range from 1 bit to multiple bits. It is divided into multiple types: SLC (Single-Level Cell), single-layer cell; MLC (Multi-Level Cell), multi-layer cell; TLC (Triple-Level Cell), three-layer cell; QLC (Quad-Level Cell), four-layer cell; PLC (Penta-Level Cell), five-layer cell.

[0112] Specifically, a single memory cell can be programmed to have 2 X different threshold voltage states, where X represents the number of bits that the memory cell can store. For example, when X=1, the memory cell has two bit states and can store 1 bit of data (SLC); when X=2, the memory cell has four bit states (MLC) and can store 2 bits of data; when X=3, the memory cell has eight bit states and can store 3 bits of data (TLC); when X=4, the memory cell has 16 bit states and can store 4 bits of data (QLC); when X=5, the memory cell has 32 bit states and can store 5 bits of data (PLC). And so on. This approach allows storage devices to achieve different storage densities under the same physical structure, thereby achieving a balance between capacity, performance, and reliability.

[0113] Taking TLC (Triple-Level Cell) flash memory as an example, each storage cell can store 3 bits of information / data, corresponding to 8 bit states (N=8), usually recorded as S0, S1, S2, S3, S4, S5, S6 and S7. The processor 211 reads the voltage level of each storage cell and converts it into the corresponding bit state. For example, the voltage level of a storage cell may correspond to state S3.

[0114] On the other hand, it is worth mentioning that the processor 211 can identify the specific positions of the multiple storage units for storing the multiple bit values ​​in the three-dimensional circuit architecture of the rewritable non-volatile memory module according to the multiple physical addresses for storing the multiple bit values ​​of the write data, so that the processor 211 can obtain the M groups of first bit values ​​stored on the M first reference lines corresponding to the first direction (e.g., the M bit groups corresponding to the first direction respectively include multiple first bit values), obtain the P groups of second bit values ​​stored on the P second reference lines corresponding to the second direction (e.g., the P bit groups corresponding to the second direction respectively include multiple second bit values) among the multiple bit values ​​in the write data according to these specific positions, and obtain the Q groups of third bit values ​​stored on the Q third reference lines corresponding to the third direction (e.g., the Q bit groups corresponding to the third direction respectively include multiple Qth bit values). In other words, the multiple bit values ​​in the write data can be presented by the M bit groups corresponding to the first direction, the P bit groups corresponding to the second direction, or the Q bit groups corresponding to the third direction.

[0115] It should be noted that the randomized verification operation provided by the present invention can be checked from one of the first direction to the third direction first, and then the other directions. The present invention is not limited to the order in which the directions are checked. On the other hand, the first direction is not limited to the X direction, and the first direction can be the X direction, the Y direction, or the Z direction; and the second direction and the third direction are directions other than the first direction.

[0116] The following uses multiple embodiments to illustrate the implementation of the randomized verification operation of the present invention.

[0117] Embodiment 1: According to the multiple bit values ​​of each bit value group, N state proportions corresponding to the N bit states of each bit value group are obtained.

[0118] For example, in one embodiment, assuming that the storage unit is SLC, that is, X=1, N=2 1 =2. The processor 211 obtains a plurality of bit value groups of the write data in the first direction. Assume that there are 4 bit value groups (M=4) in the first direction, corresponding to 4 first reference lines respectively, and each group contains 8 bits, as follows:

[0119] The first bit value group: "10110101" (8 bits);

[0120] The second bit value group: "11001100" (8 bits);

[0121] The third bit value group: "10101010" (8 bits);

[0122] The 4th bit value group: "11110000" (8 bits).

[0123] Next, the processor 211 obtains the state proportions of the N bit states of each bit value group respectively. In this example, N=2, indicating that there are two states (S0=0 and S1=1).

[0124] For the first group of bit values:

[0125] The number of S0 is 3, and the state proportion is: 3 / 8=37.5%;

[0126] The number of S1 is 5, and the status ratio is: 5 / 8=62.5%.

[0127] For the second group of bit values:

[0128] The number of S0 is 4, and the state proportion is: 4 / 8=50.0%;

[0129] The number of S1 is 4, and the status ratio is: 4 / 8=50.0%.

[0130] For the third group of bit values:

[0131] The number of S0 is 4, and the state proportion is: 4 / 8=50.0%;

[0132] The number of S1 is 4, and the status ratio is: 4 / 8=50.0%.

[0133] For the 4th group of bit values:

[0134] The number of S0 is 4, and the state proportion is: 4 / 8=50.0%;

[0135] The number of S1 is 4, and the status ratio is: 4 / 8=50.0%.

[0136] In this way, the processor 211 obtains the N state proportions of the M bit value groups in the first direction, and these state proportion data will be used for subsequent random verification operations.

[0137] In this simple embodiment, the processor 211 can preliminarily determine the randomization quality by comparing the proportions of the two states. If the proportions of the two bit states are not much different, the randomization quality is considered to be good. For example, if the difference between the proportions of the two states is less than a preset threshold value, it can be determined that the proportions of the two states are not much different and the randomization quality is good.

[0138] In another embodiment, the present invention provides multiple methods to obtain the randomization quality of the written data corresponding to the first direction according to the proportion of N states. The following is explained by a specific example:

[0139] (1) Comparison method of the difference between the maximum and minimum state proportions in each bit value group:

[0140] The processor 211 first calculates the maximum difference of the proportions of N states in each bit value group:

[0141] The first bit value group: S0 accounts for 37.5%, S1 accounts for 62.5%, and the maximum difference = |62.5%-37.5%| = 25%.

[0142] The second bit value group: S0 accounts for 50.0%, S1 accounts for 50.0%, and the maximum difference = |50.0%-50.0%| = 0%.

[0143] The third bit value group: S0 accounts for 50.0%, S1 accounts for 50.0%, and the maximum difference = |50.0%-50.0%| = 0%.

[0144] The 4th bit value group: S0 accounts for 50.0%, S1 accounts for 50.0%, and the maximum difference = |50.0%-50.0%| = 0%.

[0145] The processor 211 may set a preset threshold, such as 20%. If the maximum difference of all bit value groups is not greater than the threshold, the randomization quality of the written data corresponding to the first direction is determined to be qualified. In this example, since the maximum difference (25%) of the first bit value group exceeds the preset threshold, the randomization quality is determined to be unqualified.

[0146] (2) State ratio interval distribution method: The processor 211 sets multiple state ratio interval ranges, for example:

[0147] The first interval: 0% to 25%; the second interval: 25% to 50%; the third interval: 50% to 75%; the fourth interval: 75% to 100%.

[0148] Then the processor 211 counts the distribution of the state proportion of each bit value group in each interval:

[0149] The first bit value group: S0 (37.5%) falls in the second interval, and S1 (62.5%) falls in the third interval.

[0150] The second bit value group: S0 (50.0%) falls within the third interval, and S1 (50.0%) falls within the third interval.

[0151] The third bit value group: S0 (50.0%) falls within the third interval, and S1 (50.0%) falls within the third interval.

[0152] The 4th bit value group: S0 (50.0%) falls within the third interval, and S1 (50.0%) falls within the third interval.

[0153] The processor 211 may set a determination rule: for example, if the state proportions exceeding a preset ratio (such as 75%) are all concentrated in the same interval, the randomization quality of the written data corresponding to the first direction is determined to be unqualified. In this example, 7 (a total of 8) state proportions fall in the third interval, exceeding 75%, so the randomization quality is determined to be unqualified.

[0154] These methods can be used alone or in combination to evaluate the randomization quality of the written data corresponding to the first direction. In this way, the present invention can effectively identify the situation where the bit state distribution is too concentrated or uneven. Through these different statistical methods, the processor 211 can comprehensively evaluate the randomization quality of each written data.

[0155] Embodiment 2: Introducing a benchmark ratio value.

[0156] In this embodiment, the concept of a benchmark ratio value is introduced and used to evaluate the randomization quality.

[0157] The base percentage value corresponding to a memory cell is 100% divided by the total number of corresponding bit states. For example, taking MLC (multi-level cell) as an example, X=2, N=2 2 =4, the base percentage is 100% / 4=25%.

[0158] Initially, the processor 211 obtains a plurality of bit values ​​of the write data. Here, it is assumed that the write data is "1001101110100011".

[0159] Next, the processor 211 obtains the state proportions of N bit states. In this example, N=4, indicating four bit states: 00, 01, 10, and 11.

[0160] Next, the processor 211 divides the number of each bit state by the total number of bits to obtain:

[0161] The percentage of bit state S0 (00): 3 / 8 = 37.5%

[0162] The percentage of bit state S1 (01): 2 / 8 = 25%

[0163] The percentage of bit state S2(10): 2 / 8 = 25%

[0164] The percentage of bit state S3 (11): 1 / 8 = 12.5%

[0165] Next, the processor 211 obtains a reference proportion value. Ideally, the state proportion of each of the four bit states should be equal, that is, 100% / 4=25%.

[0166] The following describes specific details of obtaining the quality of the randomization of the write data corresponding to the first direction according to the N state proportions and the reference proportion value.

[0167] In one embodiment, the processor 211 obtains N deviation values ​​between the N state proportions of each bit value group and the reference proportion value. The following is an explanation through a specific example:

[0168] Assume that the written data corresponds to 4 bit value groups in the first direction (M=4), each bit value group corresponds to two bit states (N=2), and the reference proportion is 50%.

[0169] The processor 211 calculates N deviation values ​​of the first bit value group: the deviation value of the bit state S0: |37.5%-50.0%|=12.5%; the deviation value of the bit state S1: |62.5%-50.0%|=12.5%.

[0170] The processor 211 calculates N deviation values ​​of the second bit value group: the deviation value of the bit state S0: |50.0%-50.0%|=0%; the deviation value of the bit state S1: |50.0%-50.0%|=0%.

[0171] The processor 211 calculates N deviation values ​​of the third bit value group: the deviation value of the bit state S0: |50.0%-50.0%|=0%; the deviation value of the bit state S1: |50.0%-50.0%|=0%.

[0172] The processor 211 calculates N deviation values ​​of the fourth bit value group: the deviation value of the bit state S0: |50.0%-50.0%|=0%; the deviation value of the bit state S1: |50.0%-50.0%|=0%.

[0173] After obtaining these deviation values, the processor 211 compares the deviation values ​​of each bit state in the M bit value groups to find the maximum deviation value:

[0174] (1) For bit state S0: Since the deviation values ​​in the M bit value groups are {12.5%, 0%, 0%, 0%}, the maximum deviation value of S0 is 12.5%.

[0175] (2) For bit state S1: Since the deviation values ​​in the M bit value groups are {12.5%, 0%, 0%, 0%}, the maximum deviation value of bit state S1 is 12.5%.

[0176] In this way, the processor 211 obtains N maximum deviation values ​​corresponding to N bit states (e.g., in this example, N=2, and the two maximum deviation values ​​corresponding to bit states S0 and S1 are 12.5% ​​and 12.5%). Assuming the preset threshold is 10%, since the maximum deviation values ​​(12.5%) of bit state S0 and bit state S1 are both greater than the preset threshold, the randomization quality of the written data corresponding to the first direction is determined to be unqualified. This means that in the first direction, the bit state distribution in at least one bit value group is too uneven.

[0177] When determining that the randomization quality of a write data is acceptable, the processor 211 may use the write data as the target write data.

[0178] In one embodiment, after the processor 211 obtains a target write data, it is not necessary to perform random verification operations on other write data to save system resources.

[0179] However, in another embodiment, the processor 211 may perform a randomization verification operation on all write data to find the randomized write data with qualified and best quality (e.g., the smallest maximum deviation value) as the target write data, thereby further improving the reliability and security of data storage in the storage device 20.

[0180] Please go back Figure 2 . After acquiring the target write data, then, in step S240, the processor 211 stores the target write data in multiple target storage units among the multiple storage units of the rewritable non-volatile memory module 220. In more detail, the processor 211 corresponds the physical addresses of multiple target storage units to the target write data, and updates the corresponding mapping information after the target write data is programmed to the physical address. In addition, this process may involve the wear leveling algorithm of the flash memory controller to ensure that the number of times the storage units are used is balanced and the service life of the storage device is extended.

[0181] On the other hand, the processor 211 generates and stores metadata related to the target write data, which metadata is associated with subsequent read and restore operations. In one embodiment, the metadata includes one or more of the following:

[0182] a. Randomization algorithm identifier: used to identify the randomization algorithm used when generating the target write data, for subsequent de-randomization operations.

[0183] b. Data mapping table: records the correspondence between data blocks and physical storage unit addresses.

[0184] c. Error Correction Code (ECC): used to detect and correct possible bit errors.

[0185] d. Timestamp: records the time when data is written, used for data version control and recovery.

[0186] e. Data length: records the length of the original data for subsequent de-randomization operations.

[0187] f. Checksum: used to verify data integrity.

[0188] In one embodiment, when the storage controller 210 receives a read instruction from the host system 10, the processor 211 performs the following steps to restore the original data:

[0189] (1) Parsing a read instruction: The processor 211 parses a read instruction from the host system 10 and determines a logical address range of data to be read.

[0190] (2) Address conversion: The processor 211 uses a logical-to-physical mapping table to convert a logical address into a corresponding physical address.

[0191] (3) Reading metadata: The processor 211 first reads metadata related to the target data. These metadata are usually stored in predefined special pages or blocks, including:

[0192] a. Randomization algorithm identifier

[0193] b. Data mapping table

[0194] c. Error Correction Code (ECC)

[0195] d. Data length

[0196] e. Checksum

[0197] (4) Reading randomized data: According to the data mapping table in the metadata, the processor 211 reads the randomized target write data from the corresponding physical address.

[0198] (5) Error checking and correction: The processor 211 uses the read ECC information to perform error checking on the data. If a correctable error is found, it is corrected. If an uncorrectable error is found, the data block is marked as an error and other recovery mechanisms are attempted.

[0199] (6) Data integrity verification: In one embodiment, the processor 211 also verifies the integrity of the read data using the stored checksum. If the check fails, it may be necessary to start a data recovery program or report an error to the host system.

[0200] (7) Determining a de-randomization algorithm: After obtaining the target write data after successful decoding, the processor 211 determines the de-randomization algorithm to be used according to the randomization algorithm identifier in the metadata.

[0201] (8) Performing a de-randomization operation: The processor 211 performs a de-randomization operation on the randomized data read. This process is the reverse process of the randomization operation during writing, and may include:

[0202] a. Reverse displacement operation

[0203] b. The inverse operation of the XOR operation

[0204] c. Reverse permutation operation

[0205] d. Use the same random seed to perform the reverse operation

[0206] (9) Data length adjustment: In one embodiment, the processor 21 may further trim the de-randomized data according to the original data length recorded in the metadata to ensure that the length of the recovered data is consistent with the original data.

[0207] (10) Data transmission: After acquiring the corresponding original data, the processor 211 transmits the restored original data to the host system 10 through the connection interface circuit 230 in response to the read instruction.

[0208] Through this detailed de-randomization process, the storage controller 210 can accurately restore the randomized target write data stored in the storage device 20 to the corresponding original data and safely transmit it to the host system 10. This process not only ensures the correct recovery of the data, but also includes steps such as error detection, correction and data integrity verification to improve the reliability and correctness of data reading. It should be noted that the randomization operation and the de-randomization operation can be implemented by a specific randomization circuit and a de-randomization circuit to implement the above-mentioned randomization / de-randomization algorithm. In addition, the randomization circuit and the de-randomization circuit can also be integrated into the same circuit unit.

[0209] Figure 5 FIG. 4 is a flow chart of a randomized verification operation according to an embodiment of the present invention.

[0210] Please refer to Figure 5 This embodiment describes a method for verifying the randomization quality of written data, which is applicable to a rewritable non-volatile memory module having multiple storage units. The method is executed by a processor of a storage controller and mainly includes the following steps:

[0211] In step S510, the processor 211 obtains 4 bit value groups (M=4) corresponding to the first direction of the write data. Since each storage unit can store 1 bit (X=1), each bit value corresponds to 2 bit states (N=2 1 =2). Assume that the contents of these 4 bit value groups are:

[0212] The first bit value group: "11100000";

[0213] The second bit value group: "11110001";

[0214] The third bit value group: "00011111";

[0215] The fourth bit value group: "00001111".

[0216] In step S520, the processor 211 calculates the bit state ratio of each bit value group:

[0217] (1) Bit state ratio of the first bit value group:

[0218] Bit state S0 percentage: 62.5%;

[0219] Bit state S1 percentage: 37.5%.

[0220] (2) Bit state ratio of the second bit value group:

[0221] Bit state S0 percentage: 25.0%;

[0222] Bit state S1 percentage: 75.0%.

[0223] (3) Bit state ratio of the third bit value group:

[0224] Bit state S0 percentage: 37.5%;

[0225] Bit state S1 percentage: 62.5%.

[0226] (4) Bit state ratio of the fourth bit value group:

[0227] Bit state S0 percentage: 75.0%;

[0228] Bit state S1 percentage: 25.0%.

[0229] Next, in step S530, the processor 211 obtains a reference ratio value based on the two bit states. In this example, the reference ratio value is 50% (100% / 2=50%).

[0230] Next, in step S540, the processor 211 calculates the deviation value between each bit state in each bit value group and the reference ratio value:

[0231] (1) Deviation value of the first bit value group:

[0232] Bit state S0 deviation value: |62.5%-50.0%|=12.5%;

[0233] Bit state S1 deviation value: |37.5%-50.0%|=12.5%.

[0234] (2) Deviation value of the second bit value group:

[0235] Bit state S0 deviation value: |25.0%-50.0%|=25.0%;

[0236] Bit state S1 deviation value: |75.0%-50.0%|=25.0%.

[0237] (3) Deviation value of the third bit value group:

[0238] Bit state S0 deviation value: |37.5%-50.0%|=12.5%;

[0239] Bit state S1 deviation value: |62.5%-50.0%|=12.5%.

[0240] (4) Deviation value of the fourth bit value group:

[0241] Bit state S0 deviation value: |75.0%-50.0%|=25.0%;

[0242] Bit state S1 deviation value: |25.0%-50.0%|=25.0%.

[0243] Next, in step S550, the processor 211 calculates the maximum deviation value of each bit state in the four bit value groups:

[0244] The four deviation values ​​of the bit state S0 are {12.5%, 25.0%, 12.5%, 25.0%}: the maximum deviation value of the bit state S0 is 25.0%.

[0245] The four deviation values ​​of the bit state S1 are {12.5%, 25.0%, 12.5%, 25.0%}: the maximum deviation value of the bit state S1 is 25.0%.

[0246] Next, in step S560, the processor 211 sets the preset threshold to 20%, and determines whether the two maximum deviation values ​​are both less than the preset threshold.

[0247] In step S580, since the maximum deviation values ​​(25.0%) of the bit state S0 and the bit state S1 are respectively greater than the preset threshold value (20%), the processor 211 determines that the randomization quality of the write data corresponding to the first direction is unqualified.

[0248] Through the above method, the present invention can not only evaluate the overall bit state distribution, but also identify serious deviations in specific bit value groups. This detailed evaluation method helps to early discover data distribution problems that may lead to reduced storage reliability, avoiding the defects of traditional methods that only focus on overall statistics and ignore local extreme cases.

[0249] The following further uses a complete embodiment to illustrate the randomized verification operation of the present invention.

[0250] In one embodiment, a rewritable non-volatile memory module 220 of a triple-level cell (TLC) is used as an example to illustrate the randomized verification operation. In the TLC architecture, each memory cell can store 3 bits (X=3), so there are 8 bit states (N=2 3 =8). In addition, it is further assumed that the three bit value groups corresponding to the first direction of the written data are to be verified.

[0251] The processor 211 first obtains the 8-bit state distribution of multiple storage cells corresponding to the first bit value group of the first direction of the written data:

[0252] The state proportion of bit state S0 is: 13.4%, the state proportion of bit state S1 is: 11.8%, the state proportion of bit state S2 is: 12.7%, the state proportion of bit state S3 is: 13.1%, the state proportion of bit state S4 is: 12.5%, the state proportion of bit state S5 is: 11.7%, the state proportion of bit state S6 is: 13.2%, and the state proportion of bit state S7 is: 11.6%.

[0253] Next, the processor 211 first obtains the 8-bit state distribution of the plurality of storage cells corresponding to the second bit value group of the first direction of the written data:

[0254] The state proportion of bit state S0 is: 12.2%, the state proportion of bit state S1 is: 12.4%, the state proportion of bit state S2 is: 13.3%, the state proportion of bit state S3 is: 12.1%, the state proportion of bit state S4 is: 12.6%, the state proportion of bit state S5 is: 12.0%, the state proportion of bit state S6 is: 12.8%, and the state proportion of bit state S7 is: 12.6%.

[0255] Next, the processor 211 first obtains the 8-bit state distribution of multiple storage cells corresponding to the third bit value group of the first direction of the written data:

[0256] The state proportion of bit state S0 is: 10.1%, the state proportion of bit state S1 is: 13.8%, the state proportion of bit state S2 is: 11.6%, the state proportion of bit state S3 is: 14.1%, the state proportion of bit state S4 is: 12.7%, the state proportion of bit state S5 is: 12.2%, the state proportion of bit state S6 is: 13.1%, and the state proportion of bit state S7 is: 12.4%.

[0257] The processor 211 calculates the deviation value of each bit state on each line with reference to the base ratio of 12.5%. Taking bit state S0 as an example:

[0258] The deviation value of the first bit value group corresponding to the bit state S0 is: |13.4%-12.5%|=0.9%;

[0259] The deviation value of the second bit value group corresponding to the bit state S0 is: |12.2%-12.5%|=0.3%;

[0260] The deviation value of the bit state S0 corresponding to the third bit value group is: |10.1%-12.5%|=2.4%.

[0261] Next, the processor 211 finds out that the maximum deviation value of the bit state S0 on all lines is 2.4%. Assuming the preset threshold is 3%, since 2.4% is less than 3%, it means that the distribution of the bit state S0 is qualified.

[0262] The processor 211 performs the same calculation and judgment on other bit states (S1 to S7). If the maximum deviation values ​​of all bit states are less than the preset threshold, the randomization verification of the first direction is qualified. Then the processor 211 performs the same verification process on the second direction and the third direction.

[0263] This method pays special attention to the distribution of each bit state on each line, which can effectively avoid the problem that the traditional method only looks at the overall average value and ignores the local extreme distribution. In addition, by verifying the distribution in three directions respectively, the present invention can more comprehensively evaluate the uniformity of data distribution in the three-dimensional structure and improve storage reliability.

[0264] Another example is used below to illustrate how to perform randomized verification operations based on multiple directions of a three-dimensional circuit structure.

[0265] In one embodiment, the processor 211 first verifies the first direction. Assume that the written data has 4 bit value groups (M=4) in the first direction, and each group includes 8 storage cells. In this example, each storage cell is a single-layer cell (SLC), so there are 2 bit states (N=2). When the processor 211 calculates that the maximum deviation values ​​of the bit state S0 and the bit state S1 are 18% and 17% respectively, and the preset threshold is 20%, it is determined that the randomization quality of the written data corresponding to the first direction is qualified.

[0266] Next, the processor 211 verifies the second direction. Assuming there are 3 bit value groups (P=3) in the second direction, the processor 211 calculates the state proportion of each bit value group:

[0267] The first bit value group: bit state S0 accounts for 45%; bit state S1 accounts for 55%.

[0268] The second bit value group: bit state S0 accounts for 52%; bit state S1 accounts for 48%.

[0269] The third bit value group: bit state S0 accounts for 47%; bit state S1 accounts for 53%.

[0270] The processor 211 calculates the deviation from the baseline ratio of 50% as:

[0271] The three deviation values ​​of bit state S0 are {5%, 2%, 3%}: the maximum deviation value of bit state S0 is 5%; the three deviation values ​​of bit state S1 are {5%, 2%, 3%}: the maximum deviation value of bit state S1 is 5%.

[0272] Since the two maximum deviation values ​​are both smaller than the preset threshold value of 20%, the processor 211 determines that the randomization quality of the second direction is qualified.

[0273] Finally, the processor 211 verifies the third direction. Assuming that there are 5 bit value groups (Q=5) in the third direction, after a similar calculation process, it is obtained that the maximum deviation value of the bit state S0 is 15%; the maximum deviation value of the bit state S1 is 16%.

[0274] These deviation values ​​are also all smaller than the preset threshold value of 20%, so the processor 211 determines that the randomization quality of the third direction is qualified.

[0275] Since the randomization qualities of the written data corresponding to the first direction, the second direction, and the third direction are all qualified, the processor 211 finally determines that the randomization quality of the written data is qualified.

[0276] However, in another embodiment, assuming that there are 5 bit value groups (Q=5) in the third direction, after a similar calculation process, it is obtained that: the maximum deviation value of the bit state S0 is 25%; the maximum deviation value of the bit state S1 is 16%. Since the maximum deviation value of the bit state S0 is greater than the preset threshold value of 20%, the processor 211 determines that the quality of randomization in the third direction is unqualified.

[0277] This multi-directional verification method overcomes the limitation of traditional technology that only focuses on a single direction. By simultaneously verifying the data distribution in three directions, the present invention can more comprehensively evaluate the degree of data randomization in the three-dimensional structure and effectively improve storage reliability.

[0278] In one embodiment, when the processor 211 determines that the randomization quality of the written data corresponding to the first direction is unqualified, further measures are taken to record the abnormal situation.

[0279] Assume that the written data corresponds to 4 bit value groups (M=4) in the first direction, each group contains 8 storage cells, and is a single-layer cell (SLC), so there are 2 bit states (N=2). The processor 211 has completed the maximum deviation value calculation for each bit state:

[0280] The four deviation values ​​of bit state S0 are {22%, 15%, 18%, 20%}: the maximum deviation value of bit state S0 is 22%; the four deviation values ​​of bit state S1 are {12%, 25%, 16%, 15%}: the maximum deviation value of bit state S1 is 25%.

[0281] When the preset threshold is set to 20%, the processor 211 finds that:

[0282] The maximum deviation value of bit state S0 (22%)>preset threshold (20%);

[0283] The maximum deviation value (25%) of the bit state S1 is greater than the preset threshold (20%).

[0284] Therefore, the processor 211 obtains the two abnormal maximum deviation values ​​(22% and 25%) and the corresponding abnormal bit states (bit state S0 and bit state S1).

[0285] Next, the processor 211 records the bit states whose maximum deviation value exceeds the preset threshold and the directions to which they belong: the first direction (such as the X direction); and the abnormal bit states in the first direction (bit state S0 and bit state S1). In another embodiment, the processor 211 further records the corresponding maximum deviation values ​​(such as 22% and 25%).

[0286] This recording mechanism enables the present invention to not only identify situations where randomization quality is unqualified, but also accurately locate the direction in which the problem occurs and the specific bit state, which helps to improve the randomization operation in a targeted manner later.

[0287] In one embodiment, when the processor 211 finds that the randomization quality of all written data is unqualified, the randomization operation is adjusted according to the recorded abnormal bit states and their corresponding directions.

[0288] Assume that the original data generates three written data after three different randomization operations, and the randomization verification results corresponding to the first direction are as follows:

[0289] (1) The first written data (generated by the randomization operation of the XOR operation): the maximum deviation value of the bit state S0 is 25% (in the second bit value group); the maximum deviation value of the bit state S1 is 23% (in the third bit value group).

[0290] (2) The second written data (generated by randomization operation of bit shift operation): the maximum deviation value of bit state S0 is 22% (in the first bit value group); the maximum deviation value of bit state S1 is 24% (in the fourth bit value group).

[0291] (3) The third written data (generated by the randomization operation of the permutation operation): the maximum deviation value of the bit state S0 is 26% (in the third bit value group); the maximum deviation value of the bit state S1 is 21% (in the second bit value group).

[0292] Since the randomization quality of all written data in the first direction is unqualified (the maximum deviation value exceeds the preset threshold value of 20%), the processor 211 can perform the following adjustments according to the recorded abnormal bit states and their distribution in the first direction, for example:

[0293] 1. In response to the abnormal bit state S0 of the second bit value group in the first write data, the processor 211 adjusts the random sequence of the XOR operation of the area.

[0294] 2. In view of the abnormality of the bit state S1 of the fourth bit value group in the second write data, the processor 211 increases the number of shift operations in the area.

[0295] 3. With respect to the abnormal bit state S0 of the third bit value group in the third write data, the processor 211 uses a more complex substitution table for this area.

[0296] After the adjustment, the processor 211 regenerates the write data and performs a randomized verification operation until the target write data that passes the verification is found.

[0297] After the above adjustment, the processor 211 regenerates three new write data and performs the randomization verification operation again. If any of the new write data passes the verification, the processor 211 can store the qualified write data as the target write data in multiple target storage units.

[0298] This adaptive adjustment mechanism enables the present invention to optimize the randomization operation according to specific abnormal situations, which not only improves the success rate of obtaining qualified written data, but also effectively avoids the problem of repeated uneven data distribution in a specific direction or specific position.

[0299] This embodiment also provides a computer program product, including a computer readable code, or a non-volatile computer readable storage medium carrying a computer readable code, when the computer readable code runs in a processor of a storage device, the processor in the storage device executes the steps of the above-mentioned data writing method. The computer program product can be implemented in hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium, and in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (Software Development Kit, SDK) and the like.

[0300] The data writing method and randomized verification operation proposed by the present invention have obvious technical effects in a non-volatile memory with a three-dimensional structure. By performing multiple randomization operations on the written data and executing the verification process based on multiple directions of the three-dimensional circuit architecture, the method can effectively improve the uniformity of data distribution in the memory.

[0301] Specifically, the method accurately quantifies the randomization quality of data by analyzing the state proportions of multiple bit value groups in each direction and the deviation values ​​from the benchmark proportion values. By comparing the maximum deviation value of each bit state in multiple bit value groups in the same direction with a preset threshold, the present invention can accurately determine whether the data distribution in each direction is uniform. Finally, only when the randomization quality of the written data in the three directions is qualified, the written data is determined to be usable for storing the original data.

[0302] When the randomization quality in a certain direction is found to be unqualified, the method will record the abnormal bit state in the direction where the deviation value exceeds the preset threshold. This targeted recording mechanism provides a clear basis for subsequent randomization operation adjustments. If the randomization quality of all written data is unqualified, the method can adjust the randomization operation according to the recorded abnormal bit state and its corresponding direction, regenerate the written data and verify it again to store qualified written data, thereby completing the storage of the original data.

[0303] Compared with the traditional method that only focuses on the overall data distribution, the present invention can more accurately evaluate the degree of data randomization in the three-dimensional structure by analyzing the local distribution characteristics of the bit value group in each direction. This multi-directional and multi-level verification method not only improves storage reliability, but also effectively avoids the problem of uneven data distribution in specific directions or local areas.

[0304] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data writing method for a rewritable non-volatile memory module having a plurality of storage units, characterized in that: include: Get raw data from the host system; Performing multiple randomization operations on the original data to obtain multiple write data; Based on multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, performing a randomization verification operation on each write data to obtain target write data from the multiple write data, wherein the randomization quality of the target write data is determined to be qualified; as well as The target write data is stored in a plurality of target storage units among the plurality of storage units.

2. The data writing method according to claim 1, characterized in that: Each randomization operation processes the original data using a different randomization algorithm, wherein the different randomization algorithms include at least one of the following: XOR operation, performing XOR operation on the original data and a plurality of predefined different random sequences; A shift operation, performing a plurality of different circular shifts or logical shifts on the original data; A permutation operation, changing the order of bits in the original data according to a plurality of predefined different permutation tables; Dynamic random seed operation, generating multiple different random seeds based on system time, data address or other system variables, and using the multiple random seeds and the original data to generate the multiple write data; as well as A grouping operation is performed to divide the original data into a plurality of sub-blocks, and different XOR operations, shift operations, permutation operations, and dynamic random seed operations are applied to the plurality of sub-blocks.

3. The data writing method according to claim 1, characterized in that: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data includes: Obtaining M bit value groups of the write data corresponding to a first direction of the multiple directions, wherein the multiple bit values ​​in each bit value group correspond to the multiple storage units in the first direction of the rewritable non-volatile memory module, and each bit value corresponds to one of N bit states, where N is 2X, and X is the number of bits that can be stored in each storage unit; According to the plurality of bit values ​​of each bit value group, obtaining N state proportions corresponding to the N bit states of each bit value group; and According to the proportions of the N states, a quality of the randomization of the written data corresponding to the first direction is obtained.

4. The data writing method according to claim 3, characterized in that: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data further includes: Based on the N bit states, obtaining a reference proportion value; and The quality of the randomization of the write data corresponding to the first direction is obtained according to the N state proportions and the reference proportion value.

5. The data writing method according to claim 4, characterized in that: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data further includes: Based on each bit value group, obtain N deviation values ​​between the N state proportions of each bit value group and the reference proportion value; According to the M deviation values ​​corresponding to the same bit state of the M bit value groups, a maximum of the M deviation values ​​is used as the maximum deviation value corresponding to the same bit state, thereby obtaining N maximum deviation values ​​corresponding to the N bit states; If the N maximum deviation values ​​are all not greater than a preset threshold, determining that the quality of the randomization of the written data corresponding to the first direction is qualified; If one of the N maximum deviation values ​​is greater than the preset threshold, it is determined that the quality of the randomization of the write data corresponding to the first direction is unqualified.

6. The data writing method according to claim 5, wherein the plurality of directions include the first direction, the second direction and the third direction, wherein: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data further includes: Obtaining P bit value groups corresponding to a second direction of the written data and N maximum deviation values ​​of the P bit value groups corresponding to the N bit states, so as to obtain the quality of the randomization corresponding to the second direction of the written data; Obtaining Q bit value groups corresponding to a third direction of the written data and N maximum deviation values ​​of the Q bit value groups corresponding to the N bit states, so as to obtain the quality of the randomization corresponding to the third direction of the written data; and If the qualities of the randomization of the written data corresponding to the first direction, the second direction, and the third direction are all qualified, it is determined that the quality of the randomization of the written data is qualified.

7. The data writing method according to claim 5, characterized in that: After determining that the quality of the randomization of the written data corresponding to the first direction is unqualified, the method further includes: Acquire one or more abnormal maximum deviation values ​​greater than the preset threshold value among the N maximum deviation values ​​and one or more abnormal bit states corresponding to the one or more abnormal maximum deviation values ​​among the N bit states; and The first direction and the one or more abnormal bit states corresponding to the first direction are recorded.

8. The data writing method according to claim 7, characterized in that: If the randomization qualities of the plurality of write data are all unqualified, the method further comprises: According to the one or more abnormal bit states and corresponding directions, adjusting the plurality of randomization operations to regenerate a plurality of new write data; and The randomized verification operation is performed again on each new write data to try to obtain the target write data, and then the target write data is stored in the plurality of target storage units.

9. A memory controller, adapted for use in a storage device equipped with a rewritable non-volatile memory module, wherein the storage device is electrically connected to a host system, characterized in that: The memory controller comprises: a memory interface control circuit, for electrically connecting to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of storage units; and a processor, electrically connected to the memory interface control circuit, wherein the processor is configured to: Get raw data from the host system; Performing multiple randomization operations on the original data to obtain multiple write data; Based on multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, performing a randomization verification operation on each write data to obtain target write data from the multiple write data, wherein the randomization quality of the target write data is determined to be qualified; and The target write data is stored in a plurality of target storage units among the plurality of storage units.

10. The memory controller according to claim 9, characterized in that: Each randomization operation processes the original data using a different randomization algorithm, wherein the different randomization algorithms include at least one of the following: XOR operation, performing XOR operation on the original data and a plurality of predefined different random sequences; A shift operation, performing a plurality of different circular shifts or logical shifts on the original data; A permutation operation, changing the order of bits in the original data according to a plurality of predefined different permutation tables; Dynamic random seed operation, generating multiple different random seeds based on system time, data address or other system variables, and using the multiple random seeds and the original data to generate the multiple write data; as well as A grouping operation is performed to divide the original data into a plurality of sub-blocks, and different XOR operations, shift operations, permutation operations, and dynamic random seed operations are applied to the plurality of sub-blocks.

11. The memory controller according to claim 9, wherein: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data includes: Obtaining M bit value groups of the write data corresponding to a first direction of the multiple directions, wherein the multiple bit values ​​in each bit value group correspond to the multiple storage units in the first direction of the rewritable non-volatile memory module, and each bit value corresponds to one of N bit states, where N is 2X, and X is the number of bits that can be stored in each storage unit; According to the multiple bit values ​​of each bit value group, obtain the N state proportions corresponding to the N bit states of each bit value group; According to the proportions of the N states, a quality of the randomization of the written data corresponding to the first direction is obtained.

12. The memory controller according to claim 11, wherein: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data further includes: Based on the N bit states, obtaining a reference proportion value; and The quality of the randomization of the write data corresponding to the first direction is obtained according to the N state proportions and the reference proportion value.

13. The memory controller according to claim 12, wherein: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data further includes: Based on each bit value group, obtain N deviation values ​​between the N state proportions of each bit value group and the reference proportion value; According to the M deviation values ​​corresponding to the same bit state of the M bit value groups, a maximum of the M deviation values ​​is used as the maximum deviation value corresponding to the same bit state, thereby obtaining N maximum deviation values ​​corresponding to the N bit states; If the N maximum deviation values ​​are all not greater than a preset threshold, determining that the quality of the randomization of the written data corresponding to the first direction is qualified; If one of the N maximum deviation values ​​is greater than the preset threshold, it is determined that the quality of the randomization of the write data corresponding to the first direction is unqualified.

14. The memory controller according to claim 13, wherein the plurality of directions include the first direction, the second direction and the third direction, wherein: Based on the multiple directions of the three-dimensional circuit architecture of the rewritable non-volatile memory module, the step of performing the randomization verification operation on each written data further includes: Obtaining P bit value groups corresponding to a second direction of the written data and N maximum deviation values ​​of the P bit value groups corresponding to the N bit states, so as to obtain the quality of the randomization corresponding to the second direction of the written data; Obtaining Q bit value groups corresponding to a third direction of the written data and N maximum deviation values ​​of the Q bit value groups corresponding to the N bit states, so as to obtain the quality of the randomization corresponding to the third direction of the written data; and If the qualities of the randomization of the written data corresponding to the first direction, the second direction, and the third direction are all qualified, it is determined that the quality of the randomization of the written data is qualified.

15. The memory controller according to claim 13, wherein: After determining that the quality of the randomization of the write data corresponding to the first direction is unqualified, the processor is further configured to: Acquire one or more abnormal maximum deviation values ​​greater than the preset threshold value among the N maximum deviation values ​​and one or more abnormal bit states corresponding to the one or more abnormal maximum deviation values ​​among the N bit states; and The first direction and the one or more abnormal bit states corresponding to the first direction are recorded.

16. The memory controller according to claim 15, characterized in that: If the randomization qualities of the plurality of write data are all unqualified, the processor is further configured to: According to the one or more abnormal bit states and corresponding directions, adjusting the plurality of randomization operations to regenerate a plurality of new write data; and The randomized verification operation is performed again on each new write data to try to obtain the target write data, and then the target write data is stored in the plurality of target storage units.

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