Method and device for reducing power consumption of solid state disk, equipment and storage medium

Abstract

The invention discloses a method, device and equipment for reducing power consumption of a solid state disk and a storage medium, and the method comprises the following steps: respectively carrying out time sequence parameter training at different temperatures under different frequency gears of a dynamic random access memory (DRAM) to obtain time sequence parameter training results corresponding to the different frequency gears; and selecting different frequency gears for switching based on the data volume interacted between the SSD and the DRAM of the current solid state disk so as to reduce the power consumption of the solid state disk. According to the method and the device, the working frequency of the DRAM can be dynamically switched within different temperature ranges according to the state of the current data volume, and the overall power consumption of the SSD is reduced under the condition that the optimal performance is ensured, so that the heating of the SSD is reduced, and the stability of a product is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of hard disk power consumption control, and in particular to a method, device, equipment and storage medium for reducing the power consumption of a solid state hard disk. Background Art

[0002] The current mainstream mid-to-high-end solid-state drives are generally composed of storage controllers, NAND Flash storage particles, DDR chips, and peripheral control circuits. The storage controller and DDR chip are connected through a high-speed bus (including data bus, address bus and command bus), and exchange commands through the JEDEC standard protocol. The DRAM used by SSDs at first was generally DDR3 / DDR3L, with an interface frequency of 667MHz. With the development of storage technology, the host interface speed of SSDs is getting higher and higher, forcing the DRAM interface rate of SSD storage controllers to exchange data to higher and higher rates. The current mainstream SSD controllers support DDR4 / LPDDR4X / DDR5, etc., and the interface speed has also increased from 667MHz, 800Mhz, 1200MHz, etc. to the current 2400 / 2800MHz.

[0003] The increase in data transmission rate also means higher power consumption of the interface circuit. The power consumption here has two parts: one is the DRAM interface control module on the controller side, and the other is the interface control module of the DRAM itself. However, in actual applications, the DRAM transmission rate does not need to be maintained in high-speed mode in many occasions. For example, in the field of data acquisition (such as monitoring and security), data writing is generally maintained at a continuous low speed. For another example, since SSDs generally have over-temperature protection, when the SSD temperature is too high, the amount of data received by the DRAM from the master control will also be greatly reduced, but at this time, the DRAM still operates at a higher frequency, resulting in unnecessary power consumption waste.

[0004] Therefore, how to dynamically switch the DRAM operating frequency within different temperature ranges according to the current data volume status to reduce SSD power consumption is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The main purpose of the present invention is to provide a method, device, equipment and storage medium for reducing the power consumption of a solid-state hard disk, which can dynamically switch the operating frequency of DRAM according to the current data volume within different temperature ranges, thereby reducing the overall power consumption of the SSD while ensuring optimal performance, thereby reducing the heat generation of the SSD and enhancing the stability of the product.

[0006] In a first aspect, the present application provides a method for reducing the power consumption of a solid state drive, the method comprising the steps of:

[0007] Perform timing parameter training at different temperatures at different frequency levels of the dynamic random access memory DRAM to obtain timing parameter training results corresponding to the different frequency levels;

[0008] Based on the amount of data currently interacting between the SSD and DRAM, different frequency gears are selected for switching to reduce the power consumption of the SSD.

[0009] In combination with the first aspect, as an optional implementation method, the amount of data interacted between the SSD and the DRAM per unit time is detected in real time;

[0010] When the amount of data interacted is less than a first set threshold, the DRAM frequency level is lowered;

[0011] When the amount of data interacted is greater than a second set threshold, the DRAM frequency gear is increased, wherein the second set threshold is greater than the first set threshold;

[0012] According to the adjusted DRAM frequency gear, the corresponding frequency gear is searched from the timing parameter training result, and the corresponding frequency gear is loaded and switched from the Nor Flash or NAND Flash key data area to cover the current frequency gear of the DRAM controller and DRAM.

[0013] In combination with the first aspect above, as an optional implementation method, access to DRAM is actively suspended, and the data to be saved in DRAM is temporarily saved in the SRAM area or NAND Flash. After the overwriting is completed, the temporarily stored data is loaded into DRAM to re-receive DRAM access requests.

[0014] In combination with the first aspect above, as an optional implementation manner, the data to be saved includes: a logical-to-physical mapping table in the SSD and codes and data running in the DRAM.

[0015] In combination with the first aspect, as an optional implementation method, different frequency gears of DRAM are selected based on the working range of DRAM;

[0016] Performing timing parameter training at different temperatures for each frequency level of the DRAM to obtain a plurality of different windows corresponding to each frequency level;

[0017] An overlapping area of ​​a plurality of different windows is selected, and the middle position point of the overlapping area window is used as the final timing parameter training result of each frequency gear.

[0018] In combination with the first aspect above, as an optional implementation manner, the timing parameters include: Drive strength / ODT of the controller, DQ / DQS delay parameters, Drive strength / ODT of the DRAM, CA training parameters and Vref training parameters.

[0019] In combination with the first aspect above, as an optional implementation method, the final timing parameter training result of each frequency gear is stored in the Nor Flash or NAND Flash key data area on the SSD.

[0020] In a second aspect, the present application provides a device for reducing the power consumption of a solid state drive, the device comprising:

[0021] A training module is used to perform timing parameter training at different temperatures under different frequency levels of the dynamic random access memory DRAM to obtain timing parameter training results corresponding to different frequency levels;

[0022] The processing module is used to select different frequency gears for switching based on the amount of data currently interacting between the solid-state drive SSD and the DRAM to reduce the power consumption of the solid-state drive.

[0023] In a third aspect, the present application further provides an electronic device, comprising: a processor; a memory, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the method described in any one of the first aspects is implemented.

[0024] In a fourth aspect, the present application further provides a computer-readable storage medium storing computer program instructions, which, when executed by a computer, enables the computer to execute any of the methods described in the first aspect.

[0025] The present application provides a method, device, equipment and storage medium for reducing the power consumption of a solid-state hard disk, wherein the method includes the steps of: performing timing parameter training at different temperatures under different frequency gears of a dynamic random access memory DRAM, and obtaining timing parameter training results corresponding to different frequency gears; based on the amount of data currently interacting between the solid-state hard disk SSD and the DRAM, selecting different frequency gears for switching to reduce the power consumption of the solid-state hard disk. The present application can dynamically switch the operating frequency of the DRAM according to the state of the current data volume within different temperature ranges, and reduce the overall power consumption of the SSD while ensuring optimal performance, thereby reducing the heat generation of the SSD and enhancing the stability of the product.

[0026] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0028] Figure 1 A flow chart of a method for reducing the power consumption of a solid state drive provided in an embodiment of the present application;

[0029] Figure 2 A schematic diagram of a method for reducing the power consumption of a solid state drive provided in an embodiment of the present application;

[0030] Figure 3 A schematic diagram of parameter training provided in an embodiment of the present application;

[0031] Figure 4 A schematic diagram of an electronic device provided in an embodiment of the present application;

[0032] Figure 5 A schematic diagram of a computer-readable program medium provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0034] Furthermore, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. Some of the blocks shown in the drawings are functional entities and do not necessarily correspond to physically or logically separate entities.

[0035] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings.

[0036] Reference Figure 1 , Figure 1 FIG. 1 is a flow chart of a method for reducing power consumption of a solid state hard disk provided by the present invention. Figure 1 As shown, the method comprises the steps of:

[0037] Step S101: Perform timing parameter training at different temperatures at different frequency levels of the dynamic random access memory DRAM to obtain timing parameter training results corresponding to the different frequency levels.

[0038] Based on the working range of DRAM, select different DRAM frequency levels;

[0039] Performing timing parameter training at different temperatures for each frequency level of the DRAM to obtain a plurality of different windows corresponding to each frequency level;

[0040] An overlapping area of ​​a plurality of different windows is selected, and the middle position point of the overlapping area window is used as the final timing parameter training result of each frequency gear.

[0041] The timing parameters include: Drive strength / ODT of the controller, DQ / DQS delay parameters, Drive strength / ODT of the DRAM, CA training parameters, and Vref training parameters.

[0042] Specifically, according to the DDR3 / DDR4 / DDR5 spec, you can select the frequency points corresponding to the following different speed bins, see Table 1:

[0043] Table 1

[0044] Freq.0 Freq.1 Freq.2 Freq.3 …… Freq.12 400Mhz 533Mhz 667Mhz 800Mhz …… 2800Mhz

[0045] Parameter training is performed at different temperatures at different frequency levels (it should be noted that different temperatures can be customized according to needs, for example, this application uses -20°C, 25°C and 70°C). Finally, the controller and DRAM timing parameters applicable to three temperature points at different frequency points are obtained, including the controller's Drive strength / ODT, DQ / DQS delay parameters, DRAM's Drive strength / ODT, CA training parameters and Vref training parameters. This step can ensure that the DRAM switches frequency parameters in any temperature range, and there will be no bit errors in the interface read and write signals. It should also be explained that Drivestrength is drive strength, and ODT (On-Die Termination) is a terminal technology integrated inside the memory chip (such as DDR SDRAM). It is used to improve signal integrity, reduce signal reflections and crosstalk, and thus improve the stability and reliability of data transmission between the memory module and the memory controller. DQ is a data queue. In SSDs, the data queue is an internal mechanism used by the controller to manage data transmission and command execution. "DQS" stands for "Data Strobe" or "Data Quality Signal". DQS is a critical signal used to synchronize data transfer between the memory and the memory controller. "CA" usually refers to "Command Address". In DDR SDRAM and its successors, CA is part of the memory address signal and is used to select a specific column in the memory. When "CA training parameters" are mentioned, this usually refers to a set of parameters used to optimize the command address signal during the memory training process.

[0046] It needs to be explained that parameter training is performed at different temperature points because the devices that send and receive signals are themselves affected by temperature, which is manifested in changes in signal amplitude and phase (that is, signal delay), changes in signal setup time and hold time. These changes will affect the signal transmission quality and the results of signal sampling and judgment.

[0047] The reason for signal parameter training is: assuming that the signal amplitude 1.2V represents a high level and 0V represents a low level, then when the signal is sampled, it can be judged as 1 if it is greater than 0.6V, and it can be judged as 0 if it is less than 0.6V. When sampling, the high level will last for a period of time, which is called the hold time of the signal. In theory, it is best to sample to the middle of the hold time window. There is a risk of bit error when sampling at the edge of the hold time. Then the process of finding the middle position of the hold time window is the process of parameter training. This process can be described as: by adjusting the delay register in the controller, sampling the signal once at a certain delay interval, and determining whether the data obtained by the sampling is correct. In this way, there will be multiple samples in the hold time window, and the corresponding data points with all correct points form a window. The parameters corresponding to the middle point of this window are selected to end the training.

[0048] In one embodiment, the final timing parameter training results of each frequency gear are stored in the Nor Flash or NAND Flash key data area on the SSD. That is, when the SSD is produced, the results are saved in the Nor Flash or NAND Flash key data area on the SSD to ensure security, wherein the Nor Flash key data area includes: Boot Block, Configuration Sector, Firmware Area and Parameter Storage. The NAND Flash key data area includes: Bad Block Table, Boot Area, ECC (Error Correction Code) Area, Reserved Area and Firmware Storage.

[0049] In one embodiment, the operating frequency of the DRAM is determined according to the user manual of the DRAM, which is generally between 400 MHz and 2800 MHz. The registers on the SSD are set to allow the DRAM to operate at a frequency of 400 MHz. Parameter training is performed at high temperature / normal temperature / low temperature to obtain three groups of parameter windows. The area window where the three groups of windows overlap is selected, and then the middle position point of the overlapping window is taken as the final parameter configuration point at 400 MHz.

[0050] What needs to be explained is that SDRAM: the full name is synchronous dynamic random-access memory, that is, synchronous dynamic memory. The more common ones are DDR3 / DDR4 / DDR5 and other DRAM (dynamic random access memory), also known as DDR chips.

[0051] Solid State Drive: The full name is Solid State Drive (English abbreviation: SSD), which is a data storage module composed of several NAND Flash chips, DDR chips, storage control chips and other devices.

[0052] Vref: The SSD controller and DRAM data interface use this level to determine data. Levels greater than or equal to Vref are considered logic 1, and levels less than Vref are considered logic 0.

[0053] Step S102: Based on the amount of data currently exchanged between the solid state drive SSD and the DRAM, different frequency gears are selected for switching to reduce the power consumption of the solid state drive.

[0054] Specifically, the amount of data interacting between the SSD and DRAM per unit time is detected in real time;

[0055] When the amount of data interacted is less than a first set threshold, the DRAM frequency level is lowered;

[0056] When the amount of data interacted is greater than a second set threshold, the DRAM frequency gear is increased, wherein the second set threshold is greater than the first set threshold;

[0057] According to the adjusted DRAM frequency gear, the corresponding frequency gear is searched from the timing parameter training result, and the corresponding frequency gear is loaded and switched from the Nor Flash or NAND Flash key data area to cover the current frequency gear of the DRAM controller and DRAM.

[0058] For ease of understanding, an example is given. The software running on the SSD detects in real time the amount of data sent to the DRAM per unit time (number of commands x amount of data carried by each command = total amount of data). For example, if the data transmission volume within 1 second is less than 500MB, the frequency is reduced by one gear. If it is greater than 2GB, the frequency is increased. According to the adjusted DRAM frequency gear, the corresponding frequency gear is searched from the timing parameter training result, and access to the DRAM is actively suspended. The data to be saved in the DRAM is temporarily saved in the SRAM area or NAND Flash, and the corresponding frequency gear is switched from the Nor Flash or NAND Flash key data area to overwrite the current frequency gear of the DRAM controller and DRAM. When the overwriting is completed, the temporarily stored data is loaded into the DRAM to receive the DRAM access request again.

[0059] That is to say, if the data transmission volume is less than 500MB, the frequency will be reduced by one gear, and if it is greater than 2GB, the frequency will be increased. When this condition is met, the SSD software actively suspends access to DRAM, and stores the data to be saved in DRAM (logical to physical mapping table in SSD, or NAND Flash), and then loads the switching frequency parameters from the Nor Flash or NAND Flash key data area to reinitialize the DRAM controller and DRAM with the new frequency parameters. After the initialization is completed, the previously stored data is loaded into DRAM, and finally the subsequent access requests to DRAM are received again.

[0060] It should be noted that the thresholds of 500M and 2GB are only used as examples, and the specific thresholds can be adjusted according to the transmission bandwidth of the DRAM on the current SSD.

[0061] In summary, the present application can dynamically switch the operating frequency of DRAM according to the current data volume within different temperature ranges, thereby reducing the overall power consumption of the SSD while ensuring optimal performance, thereby reducing the heat generation of the SSD and enhancing the stability of the product.

[0062] Reference Figure 2 , Figure 2 FIG. 1 is a schematic diagram of a device for reducing power consumption of a solid state hard disk provided by the present invention. Figure 2 As shown, the device comprises:

[0063] The training module 201 is used to perform timing parameter training at different temperatures under different frequency levels of the dynamic random access memory DRAM, and obtain the timing parameter training results corresponding to the different frequency levels.

[0064] Processing module 202: It is used to select different frequency gears for switching based on the amount of data currently interacting between the solid state drive SSD and the DRAM, so as to reduce the power consumption of the solid state drive.

[0065] Furthermore, in a possible implementation, the processing module is also used to detect in real time the amount of data interacted between the SSD and the DRAM per unit time;

[0066] When the amount of data interacted is less than a first set threshold, the DRAM frequency level is lowered;

[0067] When the amount of data interacted is greater than a second set threshold, the DRAM frequency gear is increased, wherein the second set threshold is greater than the first set threshold;

[0068] According to the adjusted DRAM frequency gear, the corresponding frequency gear is searched from the timing parameter training result, and the corresponding frequency gear is loaded and switched from the Nor Flash or NAND Flash key data area to cover the current frequency gear of the DRAM controller and DRAM.

[0069] Furthermore, in a possible implementation, the processing module is also used to actively suspend access to the DRAM, temporarily save the data that needs to be saved in the DRAM to the SRAM area or NAND Flash, and when the overwriting is completed, load the temporarily stored data to the DRAM to re-receive the DRAM access request.

[0070] Furthermore, in a possible implementation, the processing module is also used to determine the data to be saved, which includes: a logical to physical mapping table in the SSD and the code and data running in the DRAM.

[0071] Furthermore, in a possible implementation manner, the training module is further used to select different frequency gears of the DRAM based on the operating range of the DRAM;

[0072] Performing timing parameter training at different temperatures for each frequency level of the DRAM to obtain a plurality of different windows corresponding to each frequency level;

[0073] An overlapping area of ​​a plurality of different windows is selected, and the middle position point of the overlapping area window is used as the final timing parameter training result of each frequency gear.

[0074] Furthermore, in a possible implementation, the training module is also used to train timing parameters, where the timing parameters include: Drive strength / ODT of the controller, DQ / DQS delay parameters, Drive strength / ODT of the DRAM, CA training parameters, and Vref training parameters.

[0075] Furthermore, in a possible implementation manner, the training module is further configured to store the final timing parameter training result of each frequency gear in a Nor Flash or NAND Flash key data area on the SSD.

[0076] Reference Figure 3 , Figure 3 FIG. 4 is a schematic diagram of parameter training provided by the present invention. Figure 3 As shown:

[0077] Taking a signal with a high level of 1.2V as an example, when the signal level sampled by the signal receiving end is greater than 0.6V, it will be judged as a high level 1, otherwise it is a low level 0. Figure 3 , what is expected to be received is a high level 1, then sampling and judging within the sampling time range marked by the solid arrow will obtain a signal 1, and this range is also called a PASS window. Under different temperature conditions, since the signal is affected by external factors such as temperature, a PASS window corresponding to different temperatures will be obtained, such as a high temperature PASS window, a normal temperature PASS window, and a low temperature PASS window. The present invention will first take the overlapping area of ​​the three PASSwindows as the final PASS window, and finally take the middle sampling position of the final PASS window as the final parameter training result. Among them, the dotted arrow marks the point where the sampling decision will produce a bit error, because it is less than the decision level 0.6V, and the solid arrow indicates the point where the sampling decision is correct.

[0078] Refer to the following Figure 4 An electronic device 400 according to this embodiment of the present invention will be described. Figure 4 The electronic device 400 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0079] like Figure 4 As shown, the electronic device 400 is in the form of a general computing device. The components of the electronic device 400 may include but are not limited to: at least one processing unit 410, at least one storage unit 420, and a bus 430 connecting different system components (including the storage unit 420 and the processing unit 410).

[0080] The storage unit stores program codes, which can be executed by the processing unit 410, so that the processing unit 410 executes the steps according to various exemplary embodiments of the present invention described in the above “Embodiment Method” section of this specification.

[0081] The storage unit 420 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 421 and / or a cache memory unit 422 , and may further include a read-only memory unit (ROM) 423 .

[0082] The storage unit 420 may also include a program / utility 424 having a set (at least one) of program modules 425, such program modules 425 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0083] Bus 430 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0084] The electronic device 400 may also communicate with one or more external devices (e.g., keyboards, pointing devices, Bluetooth devices, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 400, and / or communicate with any device that enables the electronic device 400 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed via an input / output (I / O) interface 450. Furthermore, the electronic device 400 may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter 460. As shown, the network adapter 460 communicates with other modules of the electronic device 400 via a bus 430. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 400, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0085] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0086] According to the solution of the present disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the above method of the present specification is stored. In some possible implementations, various aspects of the present invention can also be implemented in the form of a program product, which includes a program code, and when the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps according to various exemplary implementations of the present invention described in the above "Exemplary Method" section of the present specification.

[0087] refer to Figure 5 As shown, a program product 500 for implementing the above method according to an embodiment of the present invention is described, which can adopt a portable compact disk read-only memory (CD-ROM) and include program code, and can be run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, a readable storage medium can be any tangible medium containing or storing a program, which can be used by or in combination with an instruction execution system, an apparatus or a device.

[0088] The program product may use any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0089] Computer readable signal media may include data signals propagated in baseband or as part of a carrier wave, in which readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Readable signal media may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0090] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the foregoing.

[0091] Program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0092] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0093] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

[0094] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

Claims

1. A method for reducing the power consumption of a solid state drive, characterized in that: include: Perform timing parameter training at different temperatures at different frequency levels of the dynamic random access memory DRAM to obtain timing parameter training results corresponding to the different frequency levels; Based on the amount of data currently interacting between the SSD and DRAM, different frequency gears are selected for switching to reduce the power consumption of the SSD.

2. The method according to claim 1, characterized in that The method of selecting different frequency gears for switching based on the amount of data currently interacting between the solid state drive SSD and the DRAM includes: Real-time detection of the amount of data exchanged between SSD and DRAM per unit time; When the amount of data interacted is less than a first set threshold, the DRAM frequency level is lowered; When the amount of data interacted is greater than a second set threshold, the DRAM frequency gear is increased, wherein the second set threshold is greater than the first set threshold; According to the adjusted DRAM frequency gear, the corresponding frequency gear is searched from the timing parameter training result, and the corresponding frequency gear is loaded and switched from the Nor Flash or NAND Flash key data area to cover the current frequency gear of the DRAM controller and DRAM.

3. The method according to claim 2, characterized in that After searching the corresponding frequency level from the timing parameter training result according to the adjusted DRAM frequency level, the method further includes: Actively suspend access to DRAM, temporarily save the data that needs to be saved in DRAM to the SRAM area or NAND Flash, and when the overwriting is completed, load the temporarily stored data to DRAM to receive DRAM access requests again.

4. The method according to claim 3, characterized in that include: The data to be saved include: a logic-to-physical mapping table in the SSD and codes and data running in the DRAM.

5. The method according to claim 1, characterized in that The timing parameter training at different temperatures is performed at different frequency levels of the dynamic random access memory DRAM to obtain the timing parameter training results corresponding to the different frequency levels, including: Based on the working range of DRAM, select different DRAM frequency levels; Performing timing parameter training at different temperatures for each frequency level of the DRAM to obtain a plurality of different windows corresponding to each frequency level; An overlapping area of ​​a plurality of different windows is selected, and the middle position point of the overlapping area window is used as the final timing parameter training result of each frequency gear.

6. The method according to claim 5, characterized in that include: The timing parameters include: Drive strength / ODT of the controller, DQ / DQS delay parameters, Drive strength / ODT of the DRAM, CA training parameters, and Vref training parameters.

7. The method according to claim 5, characterized in that Also includes: The final timing parameter training results of each frequency gear are stored in the Nor Flash or NAND Flash key data area on the SSD.

8. A device for reducing the power consumption of a solid state hard disk, characterized in that: include: A training module is used to perform timing parameter training at different temperatures under different frequency levels of the dynamic random access memory DRAM to obtain timing parameter training results corresponding to different frequency levels; The processing module is used to select different frequency gears for switching based on the amount of data currently interacting between the solid-state drive SSD and the DRAM to reduce the power consumption of the solid-state drive.

9. An electronic device, characterized in that: The electronic device comprises: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: The computer program instructions are stored therein, and when the computer program instructions are executed by a computer, the computer is caused to execute the method according to any one of claims 1 to 7.

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