SOT-MTJ-based true random number generator and control method thereof
Through the SOT-MTJ-based true random number generator, the random flip of the SOT-MTJ resistive state is achieved using the write current, which solves the problem of high and slow erasing power consumption of RRAM devices, and realizes the generation of true random number with higher speed and lower power consumption.
Patent Information
- Application Number
- CN202411928567.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-05-13
AI Technical Summary
The existing RRAM-based true random number generator has the problem of high erasing power consumption and slow speed, and cannot meet the needs of higher speeds and lower power consumption.
Using a true random number generator based on SOT-MTJ, a write current is applied to the bottom electrode of SOT-MTJ through a write drive unit, so that its resistive state is randomly flipped between the high-resistance state and the low-resistance state. The read amplifier reads the resistive state in the form of a voltage and outputs the comparison result with the reference voltage to complete the generation of the true random number.
Achieve higher erase speed and lower power consumption, suitable for high throughput, low power consumption true random number generators.
Smart Images
Figure CN119987718A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a true random number generator based on SOT-MTJ and a control method thereof. Background Art
[0002] True Random Number Generator (TRNG) is widely used in artificial intelligence, hardware security and other fields. High throughput, low area overhead and low power consumption are very important for TRNG. TRNG based on non-volatile memory has a simpler circuit structure and is easy to achieve TRNG's requirements for area, power consumption, throughput and other aspects.
[0003] At present, many TRNGs based on RRAM (Resistive Random Access Memory) have been proposed. RRAM is suitable as the entropy source of TRNG because of its high erase and write times, fast flip speed, and natural cycle-to-cycle dynamic randomness, which makes the entropy source extraction circuit very simple. However, the erase and write power consumption of RRAM devices is too high (hundreds of picojoules per bit), and the erase and write speed is too slow (hundreds of nanoseconds), which cannot meet the requirements of higher speed and lower power consumption. Summary of the invention
[0004] The purpose of the embodiments of the present disclosure is to provide a true random number generator based on SOT-MTJ and a control method thereof, so as to solve the problems of high power consumption and slow speed of entropy source erasing based on RRAM in the prior art.
[0005] The embodiments of the present disclosure adopt the following technical solution: a true random number generator based on SOT-MTJ, comprising: a random number generation unit, comprising at least one spin-orbit moment magnetic tunnel junction SOT-MTJ; a write drive unit, used to apply a write current to the bottom electrode of the SOT-MTJ so that the resistance state of the SOT-MTJ is randomly flipped between a high resistance state and a low resistance state; a read amplifier, used to read the resistance state of the SOT-MTJ in the form of a voltage and output a comparison result between the voltage and a reference voltage; an output unit, used to output a true random number according to the comparison result.
[0006] In some embodiments, the SOT-MTJ includes at least a bottom electrode, a free layer, a tunneling layer, a reference layer, and a pinned layer stacked in sequence from bottom to top, and a top electrode of the SOT-MTJ is disposed on a side of the pinned layer away from the bottom electrode.
[0007] In some embodiments, the first output terminal of the write driver unit is connected to one end of the bottom electrode through a write bit line, the second output terminal of the write driver unit is connected to the other end of the bottom electrode through a source-drain line, the top electrode of the SOT-MTJ is connected to the first input terminal of the read amplifier through a read bit line, and the second input terminal of the read amplifier is connected to a reference unit.
[0008] In some embodiments, when the write driver unit applies a write current to the bottom electrode of the SOT-MTJ, the write driver unit applies a write voltage to the bottom electrode through the write bit line, and the source and drain lines are grounded to form a write current in the bottom electrode.
[0009] In some embodiments, when the read amplifier reads the resistance state of the SOT-MTJ, the read amplifier provides a read voltage to the top electrode and collects the voltage across the SOT-MTJ through the read bit line.
[0010] In some embodiments, the reference unit has at least a reference resistor, and a resistance value of the reference resistor is smaller than a high-resistance state resistance value of the SOT-MTJ and larger than a low-resistance state resistance value of the SOT-MTJ.
[0011] In some embodiments, the read amplifier includes at least first to twenty-first transistors, a first comparator and a second comparator, and the reference unit includes at least a first reference resistor and a second reference resistor; wherein, the sources of the first to sixth transistors are connected to the working voltage of the read amplifier, the gates of the first to sixth transistors are connected to the degradation voltage, the drain of the first transistor is connected to the source of the seventh transistor, the drain of the second transistor is connected to the source of the eighth transistor, the drain of the third transistor is connected to the ninth transistor, the drain of the fourth transistor is connected to the source of the tenth transistor, the drain of the fifth transistor is connected to the source of the eleventh transistor, the drain of the sixth transistor is connected to the source of the twelfth transistor, the drain and gate of the seventh transistor, the drain of the eighth transistor, the gate of the ninth transistor are connected to the first reference node, the gate of the eighth transistor, the drain of the ninth transistor, the drain of the tenth transistor, the gate of the eleventh transistor and the drain of the fourteenth transistor are connected to the sampling node, the gate of the tenth transistor, the drain of the eleventh transistor, the gate and drain of the twelfth transistor, and the drain of the fifteenth transistor are connected to the second reference node, and the gates of the thirteenth to fifteenth transistors are connected to the clamping voltage , the source of the thirteenth transistor is connected to the drain of the sixteenth transistor, the source of the fourteenth transistor is connected to the drain of the seventeenth transistor, the source of the fifteenth transistor is connected to the drain of the eighteenth transistor, the gates of the sixteenth to eighteenth transistors are connected to the selection signal, the source of the sixteenth transistor is connected to one end of the first reference resistor, the source of the seventeenth transistor is connected to the top electrode, the source of the eighteenth transistor is connected to one end of the second reference resistor, the other end of the first reference resistor is connected to the drain of the nineteenth transistor, the bottom electrode is connected to the drain of the twentieth transistor, the other end of the second reference resistor is connected to the drain of the twenty-first transistor, the gates of the nineteenth to twenty-first transistors are connected to the bit line, and the sources of the nineteenth to twenty-first transistors are grounded; the positive input terminal of the first comparator is connected to the sampling node, the inverting input terminal of the first comparator is connected to the first reference node, the positive input terminal of the second comparator is connected to the sampling node, the inverting input terminal of the second comparator is connected to the second sampling node, the output terminals of the first comparator and the second comparator output levels with opposite phases, and the output terminal of the read amplifier is the output terminal of the first comparator or the second comparator.
[0012] In some embodiments, the output unit includes at least a D flip-flop, a D terminal of the D flip-flop is connected to the output terminal of the read amplifier, and outputs a true random number according to the comparison result under the control of a clock signal.
[0013] The disclosed embodiment also provides a control method for a true random number generator as described above, comprising: controlling a write drive circuit to apply a write current to a bottom electrode of a spin-orbit moment magnetic tunnel junction SOT-MTJ so that the resistance state of the SOT-MTJ randomly flips between a high resistance state and a low resistance state; driving a read amplifier to read out the resistance state of the SOT-MTJ in the form of a voltage, and outputting a comparison result between the voltage and a reference voltage; and collecting and outputting a true random number output by an output unit according to the comparison result.
[0014] The beneficial effects of the embodiments of the present disclosure are as follows: based on the magnetic domain reversal characteristics of the SOT-MTJ, the random reversal of the resistance state of the SOT-MTJ can be achieved only by applying a write current. After the writing is completed, the resistance state of the SOT-MTJ is read out by the read amplifier in the form of voltage, and the comparison result with the reference voltage is output to the output unit, thereby completing the generation of true random numbers, so that it has a higher erasing speed and lower power consumption, and can be applied to a true random number generator with high throughput and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0016] Figure 1 This is a schematic diagram of the structure of a true random number generator based on SOT-MTJ in the first embodiment of the present disclosure;
[0017] Figure 2 A schematic diagram of the hierarchical structure of the SOT-MTJ in the first embodiment of the present disclosure;
[0018] Figure 3 This is a schematic diagram of the principle of generating random numbers by the SOT-MTJ in the first embodiment of the present disclosure;
[0019] Figure 4 A schematic diagram of a circuit structure of a read amplifier in the first embodiment of the present disclosure;
[0020] Figure 5 Flow chart of a control method for a true random number generator in the second embodiment of the present disclosure. DETAILED DESCRIPTION
[0021] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will be combined with the drawings in one or more embodiments of this specification to clearly and completely describe the technical solutions in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this document.
[0022] True random number generators are widely used in artificial intelligence, hardware security and other fields. High throughput, low area overhead and low power consumption are very important for TRNG. TRNG based on non-volatile memory has a simpler circuit structure and is easy to achieve TRNG requirements in terms of area, power consumption, throughput and so on.
[0023] At present, many TRNGs based on RRAM have been proposed. RRAM is suitable as the entropy source of TRNG because of its high erase and write times, fast flip speed, and natural cycle-to-cycle dynamic randomness, which makes the entropy source extraction circuit very simple. However, the erase and write power consumption of RRAM devices is too high (hundreds of picojoules per bit), and the erase and write speed is too slow (hundreds of nanoseconds), which cannot meet the requirements of higher speed and lower power consumption.
[0024] In order to solve the above problems, the first embodiment of the present disclosure provides a true random number generator based on SOT-MTJ, and its structural diagram is shown as follows: Figure 1 As shown, it mainly includes a random number generation unit 10, a write driver unit 20, a read amplifier 30 and an output unit 40. Among them, the random number generation unit 10 includes at least one spin-orbit moment magnetic tunnel junction SOT-MTJ; the write driver unit 20 is used to apply a write current to the bottom electrode of the SOT-MTJ to randomly flip the resistance state of the SOT-MTJ between a high resistance state and a low resistance state; the read amplifier 30 is used to read the resistance state of the SOT-MTJ in the form of voltage and output the comparison result between the voltage and the reference voltage; the output unit 40 is used to output a true random number according to the comparison result.
[0025] In this embodiment, the random number generation unit 10 is mainly implemented by a spin-orbit moment magnetic tunnel junction SOT-MTJ device. For the SOT-MTJ, its hierarchical structure at least includes a bottom electrode, a free layer, a tunneling layer, a reference layer, and a pinning layer stacked in sequence from bottom to top, and a top electrode of the SOT-MTJ is arranged on a side of the pinning layer away from the bottom electrode, such as Figure 2As shown. Specifically, the overall hierarchical structure of the SOT-MTJ is prepared on the surface of the substrate SUB. The bottom electrode can also be called a heavy metal layer, which is made of heavy metal materials such as tungsten W. It is mainly used for current injection to generate spin-polarized current, and then generate spin-orbit torque through the tunnel junction to drive the magnetization reversal of the free layer, while realizing unipolar writing characteristics, thereby simplifying the overall circuit structure and reducing energy consumption; the free layer, tunnel layer, reference layer and pinned layer are the core hierarchical structures of the magnetic tunnel junction. Through the tunneling magnetoresistance effect, the antiparallel and parallel magnetic moment states are further translated into high and low resistance states that can be handled by the microelectronic circuit. , so as to complete the writing and reading operations of information. Conventional materials can be directly used in the preparation of each layer, such as magnesium oxide MgO as the tunneling layer material, cobalt iron boron CoFeB as the free layer and reference layer material, cobalt / platinum multilayer film [Co / Pt]n as the pinning layer material, and tungsten W, ruthenium Ru and other materials can be combined to prepare a protective layer on the pinning layer, and finally form a device with the following hierarchical structure: SUB / W / CoFeB / MgO / CoFeB / W / Co / [Pt / Co]3 / Pt / Co / Ru / Co / [Pt / Co]6 / Pt / W / Ru. At the same time, a top electrode is set on the top of the SOT-MTJ to realize the resistance state readout of the SOT-MTJ. The top electrode can be made of a metal material with good conductive properties.
[0026] Combination Figure 1 As shown, the first output end of the write driver unit 20 is connected to one end of the bottom electrode through the write bit line (WBL, Write BitLine), and the second output end of the write driver unit 20 is connected to the other end of the bottom electrode through the source drain line (SL, Source Line). Figure 1 The first input terminal of the read amplifier 30 is connected to the first input terminal of the read amplifier 30 through the read bit line (RBL), and the second input terminal of the read amplifier 30 is connected to the reference unit 31. The reference unit 31 is used to provide a reference resistor as a basis for the read amplifier 30 to read the resistance state of the SOT-MTJ. It should be noted that, in fact, for the write driver unit 20 and the read amplifier 30, they can be used to implement the writing and reading of multiple SOT-MTJs at the same time. For example, an MRAM memory formed by multiple SOT-MTJ devices arranged in an array, combined with the design of the word line WL, the bit line BL and the selection transistor in the array, and the selection of the SOT-MTJ by the word line signal and the bit line signal, can realize independent writing and reading control of the SOT-MTJ at any position, thereby realizing high-throughput random number generation.
[0027] In the actual implementation process, when the write driver unit 20 applies a write current to the bottom electrode of the SOT-MTJ, the write driver unit 20 applies a write voltage to the bottom electrode through the write bit line WBL, and the source drain line SL is grounded, so that a write current from left to right is formed in the bottom electrode. At this time, in the absence of conditions such as an external magnetic field to break the time reversal symmetry, a sufficiently large write current can achieve a 50% probability flip of the free layer of the SOT-MTJ, and this flip is independent of the previous resistance state of the SOT-MTJ. Figure 3 The schematic diagram of the principle of SOT-MTJ generating random numbers is shown in FIG. Figure 3 As shown, Heff represents the magnetization direction of the reference layer, m represents the current magnetization direction of the free layer, and SOT is the horizontal force formed when the bottom electrode applies a write current. Under the action of SOT, m is pulled to the horizontal direction, and the torque of SOT will become 0. At this time, if SOT is removed, m will spontaneously return to the upward or downward direction, so that the SOT-MTJ has a 50% probability of presenting a high resistance state and a 50% probability of presenting a low resistance state. It should be noted that the magnitude of the write current should at least exceed the critical flip current of the SOT-MTJ to ensure the random flip effect. The specific current magnitude of the critical flip current will vary according to the bottom electrode size, SOT-MTJ device characteristics, etc. Therefore, this embodiment does not limit the magnitude of the write current, and it can be set according to actual conditions.
[0028] After writing is completed, the read amplifier 30 provides a read voltage to the top electrode of the SOT-MTJ, and collects the voltage across the SOT-MTJ through the read bit line RBL. At this time, the voltage collected by the read amplifier is related to the resistance state of the SOT-MTJ. When the SOT-MTJ is in a high resistance state, the voltage collected by the read amplifier is large, and when the SOT-MTJ is in a low resistance state, the voltage collected by the read amplifier is small. In combination with the resistance difference of the SOT-MTJ in the high and low resistance states, the voltage value collected by the read amplifier is also significantly different. The reference unit 31 is used to provide a reference voltage to the read amplifier, which can specifically have a reference resistor. When collecting the voltage across the SOT-MTJ, the read amplifier simultaneously applies the same read voltage to the reference resistor, and collects the voltage across the reference resistor as the reference voltage. Since the reference resistor is known and the reference voltage is fixed, the read amplifier can output the comparison result Qm between the voltages according to the size relationship between the voltage of the SOT-MTJ and the reference voltage, and since the resistance state of the SOT-MTJ is randomly presented, the comparison result output by the read amplifier at this time is also random. In some embodiments, the resistance of the reference resistor can be set to be less than the high-resistance state resistance of the SOT-MTJ and greater than the low-resistance state resistance of the SOT-MTJ, so as to serve as a reference for distinguishing the high and low resistance states of the SOT-MTJ. During actual setting, more reference resistors can be set accordingly in combination with the circuit design of the read amplifier.
[0029] Figure 4 FIG. 2 shows a schematic diagram of a circuit structure of the read amplifier 30 in this embodiment. Figure 4 The read amplifier structure shown in FIG. 1 includes a first reference resistor R L and the second reference resistor R H The read amplifier 30 mainly includes the first to the twenty-first transistors, the first comparator S1 and the second comparator S2, and the specific structure is as follows: the source of the first to the sixth transistors is connected to the working voltage of the read amplifier, and the gate of the first to the sixth transistors is connected to the degradation voltage V Degen , the drain of the first transistor M1 is connected to the source of the seventh transistor M7, the drain of the second transistor M2 is connected to the source of the eighth transistor M8, the drain of the third transistor M3 is connected to the ninth transistor M9, the drain of the fourth transistor M4 is connected to the source of the tenth transistor M10, the drain of the fifth transistor M5 is connected to the source of the eleventh transistor M11, the drain of the sixth transistor M6 is connected to the source of the twelfth transistor M12, the drain and gate of the seventh transistor M7, the drain of the eighth transistor M8, and the gate of the ninth transistor M9 are connected to the drain of the thirteenth transistor M13, and the first reference node V ref- The gate of the eighth transistor M8, the drain of the ninth transistor M9, the drain of the tenth transistor M10, the gate of the eleventh transistor M11 and the drain of the fourteenth transistor M14 are connected to the sampling node V data The gate of the tenth transistor M10, the drain of the eleventh transistor M11, the gate and drain of the twelfth transistor M12, and the drain of the fifteenth transistor M15 are connected to the second reference node V ref+ , the gates of the thirteenth to fifteenth transistors are connected to the clamping voltage V clamp The source of the thirteenth transistor M13 is connected to the drain of the sixteenth transistor M16, the source of the fourteenth transistor M14 is connected to the drain of the seventeenth transistor M17, the source of the fifteenth transistor M15 is connected to the drain of the eighteenth transistor M18, the gates of the sixteenth to eighteenth transistors are connected to the selection signal MUX, the source of the sixteenth transistor M16 is connected to the first reference resistor R L The source of the seventeenth transistor M17 is connected to the top electrode, and the source of the eighteenth transistor M18 is connected to the second reference resistor R H One end of the first reference resistor R L The other end of the second reference resistor R is connected to the drain of the nineteenth transistor M19, the bottom electrode is connected to the drain of the twentieth transistor M20, and the H The other end of is connected to the drain of the 21st transistor M21, the gates of the 19th to 21st transistors are connected to the bit line WL, and the sources of the 19th to 21st transistors are grounded; the positive input end of the first comparator S1 is connected to the sampling node Vdata The inverting input terminal of the first comparator S1 is connected to the first reference node V ref- The non-inverting input terminal of the second comparator S2 is connected to the sampling node V data , the inverting input terminal of the second comparator is connected to the second sampling node V ref+ The output terminals of the first comparator S1 and the second comparator S2 output levels with opposite phases, which are D 0ut0 and D 0ut1 , the output end of the read amplifier is the output end of the first comparator or the second comparator.
[0030] When the read amplifier performs reading and comparison, the sampling node V is determined according to the resistance state of the SOT-MTJ. data The voltage at the first reference node V ref- and the second reference node V ref+ The voltage at the output is compared and amplified to output the complementary D 0ut0 Signal and D 0ut1 The signal is used to characterize the resistance state of the SOT-MTJ. Based on the random flipping of the SOT-MTJ, the comparison result Qm output by the read amplifier is also random. Finally, after being processed by the output unit, a true random number output is formed, completing the true random number generation process.
[0031] In this embodiment, the output unit 40 includes at least a D flip-flop, including at least a data input terminal (D terminal), a clock input terminal (CLK), and a complementary output terminal, which are Q and non- Q represents the current stored data state, and The D flip-flop has a memory function, and its output changes with the data input (D) at the rising or falling edge of the clock signal (CLK). Specifically, at a specific edge of the clock signal (usually the rising edge), if the D input is high, the 0 output becomes high; if the D input is low, the 0 output becomes low. The output end of the read amplifier 30 is connected to the D end of the D flip-flop, and random high and low levels are output to it. Then, under the control of the clock signal, the D flip-flop outputs a true random number in combination with the level of the comparison result Qm.
[0032] Based on the magnetic domain reversal characteristics of SOT-MTJ, this embodiment can realize random reversal of the resistance state of SOT-MTJ only by applying a write current. After writing, the read amplifier reads the resistance state of SOT-MTJ in the form of voltage, and outputs the comparison result with the reference voltage to the output unit to complete the generation of true random numbers, so that the power consumption of the true random number generator is reduced to picojoules per bit to sub-picojoules per bit, and the erasing speed is shortened to tens of nanoseconds to sub-nanoseconds, so that it can be applied to high-throughput, low-power true random number generators. In addition, by optimizing the preparation process of each level in SOT-MTJ, it can have better device characteristics, thereby achieving faster erasing and lower power consumption.
[0033] The second embodiment of the present disclosure provides a control method of the true random number generator provided by the first embodiment, and its flow chart is as follows: Figure 5 As shown, it mainly includes:
[0034] S10, controlling the write driving circuit to apply a write current to the bottom electrode of the spin-orbit moment magnetic tunnel junction SOT-MTJ, so that the resistance state of the SOT-MTJ is randomly flipped between a high resistance state and a low resistance state;
[0035] S20, driving the read amplifier to read the resistance state of the SOT-MTJ in the form of voltage, and outputting a comparison result between the voltage and a reference voltage;
[0036] S30, collecting and outputting the true random number output by the output unit according to the comparison result.
[0037] It should be noted that the above control method is used to schematically describe the control process of the true random number generator. In actual implementation, the number of SOT-MTJ devices can be multiple and arranged in an array. When any SOT-MTJ is actually controlled to output random numbers as the entropy source of TRNG, the SOT-MTJ currently used as the entropy source can be first located through the word line signal and the bit line signal, and then the write driver unit and the read amplifier can control the read and write of the SOT-MTJ. The write driver unit, the read amplifier and the output unit can be specifically controlled in combination with actual computing requirements, such as the application of write voltage, read voltage, and the application of D register clock signal, etc. This embodiment will not be described in detail.
[0038] In addition, the principle of SOT-MTJ outputting random numbers and the specific process of realizing true random number output as an entropy source of a true random number generator have been described in detail in the first embodiment, and will not be repeated here.
[0039] Based on the magnetic domain reversal characteristics of the SOT-MTJ, this embodiment can achieve random reversal of the resistance state of the SOT-MTJ by simply applying a write current. After writing is completed, the read amplifier reads the resistance state of the SOT-MTJ in the form of voltage, and outputs the comparison result with the reference voltage to the output unit, thereby completing the generation of true random numbers, so that it has a higher erase speed and lower power consumption, and can be applied to a high-throughput, low-power true random number generator.
[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A true random number generator based on SOT-MTJ, characterized in that: include: A random number generation unit includes at least one spin-orbit moment magnetic tunnel junction SOT-MTJ; A write driving unit, used for applying a write current to the bottom electrode of the SOT-MTJ, so that the resistance state of the SOT-MTJ is randomly flipped between a high resistance state and a low resistance state; A read amplifier, configured to read the resistance state of the SOT-MTJ in the form of a voltage and output a comparison result between the voltage and a reference voltage; An output unit is used to output a true random number according to the comparison result.
2. The true random number generator according to claim 1, characterized in that: The SOT-MTJ at least includes a bottom electrode, a free layer, a tunneling layer, a reference layer and a pinning layer stacked in sequence from bottom to top, and a top electrode of the SOT-MTJ is arranged on a side of the pinning layer away from the bottom electrode.
3. The true random number generator according to claim 2, characterized in that: The first output end of the write driver unit is connected to one end of the bottom electrode through a write bit line, the second output end of the write driver unit is connected to the other end of the bottom electrode through a source-drain line, the top electrode of the SOT-MTJ is connected to the first input end of the read amplifier through a read bit line, and the second input end of the read amplifier is connected to a reference unit.
4. The true random number generator according to claim 3, characterized in that: When the write driver unit applies a write current to the bottom electrode of the SOT-MTJ, the write driver unit applies a write voltage to the bottom electrode through the write bit line, and the source-drain line is grounded, so that a write current is formed in the bottom electrode.
5. The true random number generator according to claim 3, characterized in that: When the read amplifier reads the resistance state of the SOT-MTJ, the read amplifier provides a read voltage to the top electrode and collects the voltage across the SOT-MTJ through the read bit line.
6. The true random number generator according to claim 3, characterized in that: The reference unit at least has a reference resistor, and a resistance value of the reference resistor is smaller than a high-resistance state resistance value of the SOT-MTJ and larger than a low-resistance state resistance value of the SOT-MTJ.
7. The true random number generator according to claim 3, characterized in that: The read amplifier includes at least first to twenty-first transistors, a first comparator and a second comparator, and the reference unit includes at least a first reference resistor and a second reference resistor; Among them, the sources of the first to sixth transistors are connected to the working voltage of the read amplifier, the gates of the first to sixth transistors are connected to the degradation voltage, the drain of the first transistor is connected to the source of the seventh transistor, the drain of the second transistor is connected to the source of the eighth transistor, the drain of the third transistor is connected to the ninth transistor, the drain of the fourth transistor is connected to the source of the tenth transistor, the drain of the fifth transistor is connected to the source of the eleventh transistor, the drain of the sixth transistor is connected to the source of the twelfth transistor, the drain and gate of the seventh transistor, the drain of the eighth transistor, and the gate of the ninth transistor are connected to the first reference node, the gate of the eighth transistor, the drain of the ninth transistor, the drain of the tenth transistor, the gate of the eleventh transistor, and the drain of the fourteenth transistor are connected to the sampling node, and the gate of the tenth transistor, the drain of the eleventh transistor, and the gate of the twelfth transistor are connected to the sampling node. The top electrode and the drain of the fifteenth transistor are connected to the second reference node, the gates of the thirteenth to fifteenth transistors are connected to the clamping voltage, the source of the thirteenth transistor is connected to the drain of the sixteenth transistor, the source of the fourteenth transistor is connected to the drain of the seventeenth transistor, the source of the fifteenth transistor is connected to the drain of the eighteenth transistor, the gates of the sixteenth to eighteenth transistors are connected to the selection signal, the source of the sixteenth transistor is connected to one end of the first reference resistor, the source of the seventeenth transistor is connected to the top electrode, the source of the eighteenth transistor is connected to one end of the second reference resistor, the other end of the first reference resistor is connected to the drain of the nineteenth transistor, the bottom electrode is connected to the drain of the twentieth transistor, the other end of the second reference resistor is connected to the drain of the twenty-first transistor, the gates of the nineteenth to twenty-first transistors are connected to the bit line, and the sources of the nineteenth to twenty-first transistors are grounded; A non-inverting input terminal of the first comparator is connected to the sampling node, an inverting input terminal of the first comparator is connected to the first reference node, a non-inverting input terminal of the second comparator is connected to the sampling node, an inverting input terminal of the second comparator is connected to the second sampling node, output terminals of the first comparator and the second comparator output levels with opposite phases, and an output terminal of the read amplifier is an output terminal of the first comparator or the second comparator.
8. The true random number generator according to any one of claims 1 to 7, characterized in that: The output unit at least includes a D flip-flop, a D terminal of the D flip-flop is connected to the output terminal of the read amplifier, and outputs a true random number according to the comparison result under the control of a clock signal.
9. A control method for a true random number generator as claimed in any one of claims 1 to 8, characterized in that: include: Controlling a write drive circuit to apply a write current to a bottom electrode of a spin-orbit moment magnetic tunnel junction SOT-MTJ so that the resistance state of the SOT-MTJ is randomly flipped between a high resistance state and a low resistance state; driving a read amplifier to read out the resistance state of the SOT-MTJ in the form of a voltage, and outputting a comparison result between the voltage and a reference voltage; The acquisition output unit outputs a true random number according to the comparison result.