Pseudo-random sequence generation circuit and pseudo-random sequence generation method for processor

Abstract

The invention relates to a pseudorandom sequence generation circuit and a pseudorandom sequence generation method for a processor. Based on the invention, the shift deduction circuit of the processor can deduce to obtain the shift deduction result of the plurality of single-bit registers after the linear feedback shift of the specified shift times, and the shift deduction circuit can use the shift deduction result to complete the shift jump of the plurality of single-bit registers after the linear feedback shift of the specified shift times at one time. In addition, the shift deduction result can also comprise each output register value of the output bit registers configured in the plurality of single-bit registers in the linear feedback shift process of the specified shift times. Therefore, each output register value of the output bit register obtained in one time in the shift deduction result can be respectively used as the corresponding bit of the pseudo-random sequence to be output in parallel, so that the parallel output of the pseudo-random sequence can be realized, and the working frequency required for generating the pseudo-random sequence in the processor can be reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a pseudo-random sequence generation circuit for a processor, a pseudo-random sequence generation method for a processor, and a processor. Background Art

[0002] The processor can use a linear feedback shift register (LFSR) to generate a pseudo-random sequence. The pseudo-random sequence has multiple bits, and the multiple bits of the pseudo-random sequence are serially generated by the linear feedback shift register, that is, the linear feedback shift register can only generate one bit of the pseudo-random sequence in one working clock cycle.

[0003] The operating frequency of the linear feedback shift register to generate the pseudo-random sequence needs to match the data rate of the processor transmitting the pseudo-random sequence. If the transmission rate of the processor is high, the operating frequency of the linear feedback shift register used to generate the pseudo-random sequence for the processor will inevitably increase accordingly, and may even exceed the level that is difficult to achieve with the manufacturing process of the processor. For example, the transmission rate of the processor is 16Gbps, and the pseudo-random sequence includes 16 bits. In this case, the operating frequency of the linear feedback shift register used to serially generate the pseudo-random sequence for the processor needs to reach 16GHz, and the manufacturing process of the processor is difficult to meet such a high operating frequency.

[0004] Therefore, how to reduce the operating frequency required to generate a pseudo-random sequence in a processor has become a technical problem to be solved in the relevant technology. Summary of the invention

[0005] Embodiments of the present application provide a pseudo-random sequence generation circuit for a processor, a pseudo-random sequence generation method for a processor, and a processor, which are helpful to reduce the operating frequency required for generating a pseudo-random sequence in the processor.

[0006] In one embodiment of the present application, a pseudo-random sequence generation circuit for a processor is provided, comprising: A register group, comprising a plurality of single-bit registers; wherein one of the plurality of single-bit registers is designated as an output bit register in a set linear feedback shift topology; Shift deduction circuit for: Based on pre-configured shift prediction information, shift deduction results of the multiple single-bit registers after completing the linear feedback shift of the specified shift times are determined; wherein the shift prediction information is determined based on the linear feedback shift topology, the specified shift times are determined by the set bit number of the pseudo-random sequence, and the shift deduction results include: the update register value of the last linear feedback shift of each single-bit register in the multiple single-bit registers in the specified shift times, and the output register value of each linear feedback shift of the output bit register in the specified shift times; Based on the shift deduction result, the synchronous update of the multiple single-bit registers and the parallel output of the pseudo-random sequence are realized; wherein the synchronous update is used to synchronously update the multiple single-bit registers to the updated register value of the last linear feedback shift in the specified number of shifts, and the parallel output of the pseudo-random sequence includes: outputting the output register value of each linear feedback shift of the output bit register in the specified number of shifts as the corresponding bit of the pseudo-random sequence in parallel.

[0007] In some examples, optionally, the shift prediction information is used to characterize: an iterative logical relationship between an updated register value of each single-bit register among the multiple single-bit registers at any linear feedback shift and an initial register value of at least one associated single-bit register; wherein the at least one associated single-bit register is predetermined among the multiple single-bit registers by performing shift deduction of the arbitrary linear feedback shift based on the linear feedback shift topology; the shift deduction circuit is specifically used to determine the shift deduction result in the following manner: determining the shift deduction result based on the shift prediction information and the initial register value of the at least one associated single-bit register.

[0008] In some examples, optionally, the shift prediction information includes multiple iterative logic relationship tables corresponding to different numbers of linear feedback shifts; wherein each iterative logic relationship table in the multiple iterative logic relationship tables is used to characterize: the iterative logical relationship between the updated register value of the linear feedback shift number corresponding to each single-bit register in the multiple single-bit registers in the iterative logic relationship table and the initial register value of at least one associated single-bit register; the at least one associated single-bit register is pre-determined in the multiple single-bit registers by using the shift deduction of the arbitrary number of linear feedback shifts based on the linear feedback shift topology; the shift deduction circuit is specifically used to determine the shift deduction result in the following manner: based on the lookup table operation of the multiple iterative logic relationship tables and the initial register value of the at least one associated single-bit register, determine the shift deduction result.

[0009] In some examples, optionally, the first lookup table hit object of the lookup table operation with the specified shift number as the index includes: the iterative logical relationship table corresponding to the last linear feedback shift in the specified shift number among the multiple iterative logical relationship tables; the first lookup table result of the lookup table operation on the first lookup table hit object includes: the iterative logical relationship between the updated register value of each linear feedback shift of the output bit register except the last one in the specified shift number and the initial register value of the at least one associated single-bit register; the process of the shift deduction circuit determining the shift deduction result includes: determining the updated register value of each single-bit register among the multiple single-bit registers after completing the last linear feedback shift in the specified shift number based on the first lookup table result and the initial register value of the at least one associated single-bit register.

[0010] In some examples, optionally, each output register value of the output bit register includes, in sequence: the initial register value of the output bit register, and the updated register value of each linear feedback shift of the output bit register except the last one in the specified shift number; the second lookup table hit object of the lookup table operation with the specified shift number as the index includes: the iterative logical relationship table of each linear feedback shift except the last one in the specified shift number in sequence in the multiple iterative logical relationship tables; the second lookup table result of the lookup table operation on the first lookup table hit object includes: the iterative logical relationship between the initial register value of the output bit register and the updated register value of each linear feedback shift of the output bit register except the last one in the specified shift number; the process of the shift deduction circuit determining the shift deduction result includes: determining each output register value of the output bit register based on the second lookup table result and the initial register value of the at least one associated single-bit register.

[0011] In some examples, optionally, each iterative logical relationship table in the multiple iterative logical relationship tables includes: an operational polynomial corresponding to each single-bit register in the multiple single-bit registers; wherein, any operational polynomial included in each iterative logical relationship table in the multiple iterative logical relationship tables is used to characterize: the iterative logical relationship between the updated register value of the single-bit register corresponding to the operational polynomial at the linear feedback shift number corresponding to the iterative logical relationship table and the initial register value of the at least one associated single-bit register.

[0012] In some examples, optionally, the cycle period of the linear feedback shift of the plurality of single-bit registers is 2M -1 , M represents the total number of registers of the plurality of single-bit registers, and the total number of the plurality of iterative logic relationship tables is less than or equal to 2 M-1 .

[0013] In some examples, optionally, an information storage circuit is also included to store the shift prediction information.

[0014] In some examples, optionally, the shift deduction circuit is also used to receive a pseudo-random sequence generation instruction; wherein the pseudo-random sequence generation instruction is used to indicate the set number of bits of the pseudo-random sequence.

[0015] In another embodiment of the present application, a pseudo-random sequence generation method for a processor is provided, the processor comprising a register group, the register group comprising a plurality of single-bit registers, one of the plurality of single-bit registers being designated as an output bit register in a set linear feedback shift topology, and the pseudo-random sequence generation method comprising: Based on pre-configured shift prediction information, shift deduction results of the multiple single-bit registers after completing the linear feedback shift of the specified shift times are determined; wherein the shift prediction information is determined based on the linear feedback shift topology, the specified shift times are determined by the set bit number of the pseudo-random sequence, and the shift deduction results include: the update register value of the last linear feedback shift of each single-bit register in the multiple single-bit registers in the specified shift times, and the output register value of each linear feedback shift of the output bit register in the specified shift times; Based on the shift deduction result, the synchronous update of the multiple single-bit registers and the parallel output of the pseudo-random sequence are realized; wherein the synchronous update is used to synchronously update the multiple single-bit registers to the updated register value of the last linear feedback shift in the specified number of shifts, and the parallel output of the pseudo-random sequence includes: outputting the output register value of each linear feedback shift of the output bit register in the specified number of shifts as the corresponding bit of the pseudo-random sequence in parallel.

[0016] In some examples, optionally, the shift prediction information is used to characterize: an iterative logical relationship between an updated register value of each single-bit register among the multiple single-bit registers at any number of linear feedback shifts and an initial register value of at least one associated single-bit register; wherein the at least one associated single-bit register is predetermined among the multiple single-bit registers by performing shift deduction of the arbitrary number of linear feedback shifts based on the linear feedback shift topology; determining the shift deduction results of the multiple single-bit registers after completing the linear feedback shift for a specified number of shifts based on the pre-configured shift prediction information includes: determining the shift deduction result based on the shift prediction information and the initial register value of the at least one associated single-bit register.

[0017] In some examples, optionally, the shift prediction information includes multiple iterative logic relationship tables corresponding to different numbers of linear feedback shifts; wherein each iterative logic relationship table in the multiple iterative logic relationship tables is used to characterize: the iterative logical relationship between the updated register value of the linear feedback shift number corresponding to each single-bit register in the iterative logic relationship table and the initial register value of the at least one associated single-bit register; the at least one associated single-bit register is pre-determined among the multiple single-bit registers by performing shift deduction of the arbitrary number of linear feedback shifts based on the linear feedback shift topology; the shift deduction results of the multiple single-bit registers after completing the linear feedback shift of the specified number of shifts based on the pre-configured shift prediction information are determined, including: determining the shift deduction results based on a lookup table operation on the multiple iterative logic relationship tables and the initial register value of the at least one associated single-bit register.

[0018] In some examples, optionally, the first lookup table hit object of the lookup table operation with the specified shift number as the index includes: the iterative logical relationship table of the last linear feedback shift in the specified shift number in the multiple iterative logical relationship tables; the first lookup table result of the lookup table operation on the first lookup table hit object includes: the iterative logical relationship between the updated register value of the last linear feedback shift of each single-bit register in the multiple single-bit registers in the specified shift number and the initial register value of the at least one associated single-bit register; the shift deduction result is determined based on the lookup table operation on the multiple iterative logical relationship tables and the initial register value of the at least one associated single-bit register, including: determining the updated register value of the last linear feedback shift of each single-bit register in the multiple single-bit registers in the specified shift number based on the first lookup table result and the initial register value of the at least one associated single-bit register.

[0019] In some examples, optionally, each output register value of the output bit register includes, in sequence: the initial register value of the output bit register, and the updated register value of each linear feedback shift of the output bit register except the last one in the specified shift number; the second lookup table hit object indexed by the lookup table operation includes: the iterative logical relationship tables of the multiple iterative logical relationship tables corresponding to each linear feedback shift except the last one in the specified shift number; the second lookup table result of the lookup table operation on the second lookup table hit object includes: the iterative logical relationship between the updated register value of each linear feedback shift of the output bit register except the last one in the specified shift number and the initial register value of the at least one associated single-bit register; the shift deduction result is determined based on the lookup table operation on the multiple iterative logical relationship tables and the initial register value of the at least one associated single-bit register, including: determining each output register value of the output bit register based on the second lookup table result and the initial register value of the at least one associated single-bit register.

[0020] In some examples, optionally, each iterative logical relationship table in the multiple iterative logical relationship tables includes: an operational polynomial corresponding to each single-bit register in the multiple single-bit registers; wherein, any operational polynomial included in each iterative logical relationship table in the multiple iterative logical relationship tables is used to characterize: the iterative logical relationship between the updated register value of the single-bit register corresponding to the operational polynomial at the linear feedback shift number corresponding to the iterative logical relationship table and the initial register value of the at least one associated single-bit register.

[0021] In some examples, optionally, the cycle period of the linear feedback shift of the plurality of single-bit registers is 2 M -1 , M represents the total number of registers of the plurality of single-bit registers, and the total number of the plurality of iterative logic relationship tables is less than or equal to 2 M-1 .

[0022] In another embodiment of the present application, a processor is provided, comprising the pseudo-random sequence generation circuit as described above.

[0023] Based on the embodiment of the present application, the processor may include a register group and a shift deduction circuit, wherein a shift relationship based on a preset linear feedback shift topology may exist between multiple single-bit registers in the register group, and the shift deduction circuit may deduce the shift deduction results of the linear feedback shift of multiple single-bit registers after a specified number of shifts, and the shift deduction circuit may use the shift deduction results to complete the shift jump of multiple single-bit registers after the linear feedback shift of the specified number of shifts at one time, and the shift deduction results may also include the output register values ​​of each time of the output bit register configured in the multiple single-bit registers during the linear feedback shift of the specified number of shifts. Among them, since the specified number of shifts of the linear feedback shift corresponds to the set number of bits of the pseudo-random sequence, the output register values ​​of each time of the output bit register obtained in the shift deduction results at one time can be respectively output in parallel as the corresponding bits of the pseudo-random sequence, thereby realizing the parallel output of the pseudo-random sequence. Furthermore, compared to a linear feedback shift register that generates a pseudo-random sequence serially, the scheme for generating a pseudo-random sequence in parallel based on shift deduction in the embodiment of the present application helps to reduce the operating frequency required to generate a pseudo-random sequence in a processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following drawings are only used to illustrate and explain the present application, and do not limit the scope of the present application: Figure 1 This is an exemplary structural diagram of a pseudo-random sequence generation circuit for a processor in an embodiment of the present application; Figure 2 It is a schematic diagram of the principle of a linear feedback shift topology applicable to a register group in an embodiment of the present application; Figure 3 It is a schematic diagram of the principle of another linear feedback shift topology applicable to the register group in the embodiment of the present application; Figure 4 A schematic diagram of the deduction principle of a pseudo-random sequence generation circuit for a processor in an embodiment of the present application; Figure 5It is a schematic diagram of the deduction principle of the pseudo-random sequence generation circuit for the processor based on the lookup table in an embodiment of the present application; Figure 6 A schematic diagram of an example of a linear feedback shift topology set for a register group in an embodiment of the present application; Figure 7 The figure is a schematic diagram of an exemplary flow chart of a pseudo-random sequence generation method for a processor in an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and examples.

[0026] Figure 1 Schematic diagram of an exemplary structure of a pseudo-random sequence generation circuit for a processor in an embodiment of the present application. Figure 1 In an embodiment of the present application, a pseudo-random sequence generation circuit for a processor may include a register group 10, an information storage circuit 20, and a shift deduction circuit 30.

[0027] Illustratively, in an embodiment of the present application, the register group 10 may include a plurality of (eg, M) single-bit registers Reg_1 to Reg_M, where M is a positive integer greater than 1.

[0028] Exemplarily, in an embodiment of the present application, the register values ​​of the plurality of single-bit registers Reg_1 to Reg_M may have a shift relationship based on a preset linear feedback shift topology, and one of the plurality of single-bit registers Reg_1 to Reg_M (e.g., the single-bit register Reg_M) may be designated as an output bit register in the set linear feedback shift topology. The shift relationship based on the linear feedback shift topology may mean that the update change of the register values ​​of the plurality of single-bit registers Reg_1 to Reg_M and the output register value generated by the output bit register Reg_M due to the linear feedback shift all conform to the shift change rule in the linear feedback shift topology, and the plurality of single-bit registers Reg_1 to Reg_M may not need to actually undergo multiple shift iterations of the register values ​​according to the operating frequency. For example, there is no need to create real electrical connections between multiple single-bit registers Reg_1~Reg_M according to the linear feedback shift topology, and the multiple single-bit registers Reg_1~Reg_M can be independently electrically connected to the shift deduction circuit 30. In this case, it can be considered that the register group 10 (that is, the multiple single-bit registers Reg_1~Reg_M) and the shift deduction circuit 30 are connected through a parallel bus.

[0029] Figure 2This is a schematic diagram of the principle of a linear feedback shift topology applicable to the register group in the embodiment of the present application. Figure 2 In an embodiment of the present application, it is assumed that one register Reg_1 among multiple single-bit registers Reg_1 to Reg_M is designated as an input bit register in a linear feedback shift topology, and another register Reg_M is designated as an output bit register in a linear feedback shift topology. In this case, multiple single-bit registers Reg_1 to Reg_M can be sequentially connected in series in a step-by-step arrangement direction from the input bit register Reg_1 to the output bit register Reg_M, and each single-bit register Reg_k (k is a positive integer greater than or equal to 1 and less than or equal to M) among the multiple single-bit registers Reg_1 to Reg_M is also connected to a function operation circuit. The function operation circuit is used to perform logical operations such as XOR operations on the register values ​​D_1 to D_M of the multiple single-bit registers Reg_1 to Reg_M based on a preset logical operation function F (D_1, D_2, ..., D_M), and the output end of the function operation circuit for generating the operation result can be connected to the input bit register Reg_1. For example, Figure 2 The linear feedback shift topology shown is similar to the Galois topology model applied to the linear feedback shift register in the related art.

[0030] If based on Figure 2 The linear feedback shift topology shown is applied to a linear feedback shift register. Then, the actual shift process that occurs in any working clock cycle includes: The operation result obtained by performing a logical operation on the register values ​​D_1~D_M of the multiple single-bit registers Reg_1~Reg_M in the previous working clock cycle using the logical operation function F(D_1, D_2, ..., D_M) can be used as the register value V1 of the input bit register Reg_1 in the current working clock cycle; The register value D_k of each single-bit register Reg_k except the output bit register Reg_M among the multiple single-bit registers Reg_1~Reg_M can be shifted to the subsequent single-bit register Reg_k+1 on the side where the output bit register Reg_M is located, where k is a positive integer greater than or equal to 1 and less than or equal to M-1, that is, the register value of the single-bit registers Reg_2~Reg_M is updated to "D_k+1=D_k"; The register value D_M of the output bit register Reg_M in the previous working clock cycle can be output as the output register value D_out.

[0031] In the embodiments of the present application, Figure 2The function operation circuit in FIG. 1 and the connection between the multiple single-bit registers Reg_1 to Reg_M are indicated by dashed lines, which means that the pseudo-random sequence generation circuit for the processor may not include Figure 2 The function operation circuit shown in FIG. 1 may not have a sequential series connection relationship between the multiple single-bit registers Reg_1 to Reg_M. In this case, the update changes of the register values ​​D_1 to D_M of the multiple single-bit registers Reg_1 to Reg_M, and the output register value D_out generated by the output bit register Reg_M due to the linear feedback shift, can still meet the following conditions: Figure 2 The shift change rule in the linear feedback shift topology shown in the figure, and based on the shift deduction of the shift deduction circuit 30, the update change of the register values ​​D_1~D_M of multiple single-bit registers Reg_1~Reg_M after multiple shifts, and the multiple outputs of the output register value D_out continuously occurring due to the multiple linear feedback shifts of the output bit register Reg_M can be completed at one time in one working clock cycle, rather than being completed one by one through multiple working clock cycles like a linear feedback shift register.

[0032] Figure 3 This is a schematic diagram of another linear feedback shift topology applicable to the register group in the embodiment of the present application. Figure 3 In the embodiment of the present application, it is assumed that one register Reg_1 among the multiple single-bit registers Reg_1~Reg_M is designated as an input bit register in the linear feedback shift topology, and another register Reg_M is designated as an output bit register in the linear feedback shift topology. In this case, in the direction of step-by-step arrangement from the input bit register Reg_1 to the output bit register Reg_M, any two adjacent single-bit registers Reg_k~Reg_k+1 among the multiple single-bit registers Reg_1~Reg_M can be connected through an exclusive OR operation circuit (indicated by the symbol "⊕" marked with the character "XOR" in the figure), and the output bit register Reg_M is also connected to the exclusive OR operation circuit between any two adjacent single-bit registers Reg_k~Reg_k+1, and the exclusive OR operation circuit between any two adjacent single-bit registers Reg_k~Reg_k+1 is used to perform an exclusive OR operation using the register value D_k of the previous stage single-bit register Reg_k and the register value D_M of the output bit register Reg_M, and the operation result of the exclusive OR operation circuit between any two adjacent single-bit registers Reg_k~Reg_k+1 is used to output to the next stage single-bit register Reg_k+1. For example, Figure 3 The linear feedback shift topology shown is similar to an Xorshift (exclusive OR shift) topology model applied to a linear feedback shift register in the related art.

[0033] If based on Figure 3 The linear feedback shift topology shown is applied to a linear feedback shift register. Then, the actual shift process that occurs in any working clock cycle includes: The register value D_M of the output bit register Reg_M in the previous working clock cycle can be used as the register value V1 of the input bit register Reg_1 in the current working clock cycle; The register value D_k of each single-bit register Reg_k except the output bit register Reg_M among the multiple single-bit registers Reg_1~Reg_M can be shifted to the subsequent single-bit register Reg_k+1 on the side where the output bit register Reg_M is located through an exclusive OR operation circuit, where k is a positive integer greater than or equal to 1 and less than or equal to M-1, that is, the register value of the single-bit registers Reg_2~Reg_M is updated to "D_k+1=D_k XOR D_M"; The register value D_M of the output bit register Reg_M in the previous working clock cycle can be output as the output register value D_out.

[0034] In the embodiments of the present application, Figure 3 The XOR operation circuit in FIG. 1 and the connection between the multiple single-bit registers Reg_1 to Reg_M are indicated by dashed lines, which means that the pseudo-random sequence generation circuit for the processor may not include Figure 3 In addition, there may be no connection relationship between the multiple single-bit registers Reg_1 to Reg_M through the exclusive OR operation circuit. In this case, the update changes of the register values ​​D_1 to D_M of the multiple single-bit registers Reg_1 to Reg_M, and the output register value D_out generated by the output bit register Reg_M due to the linear feedback shift, can still meet the following conditions: Figure 3 The shift change rule in the linear feedback shift topology shown in the figure, and based on the shift deduction of the shift deduction circuit 30, the update change of the register values ​​D_1~D_M of multiple single-bit registers Reg_1~Reg_M after multiple shifts, and the multiple outputs of the output register value D_out of the output bit register Reg_M due to multiple linear feedback shifts can be completed at one time in one working clock cycle, rather than being completed one by one through multiple working clock cycles like a linear feedback shift register.

[0035] In the embodiments of the present application, Figure 2 and Figure 3The linear feedback shift topology shown is intended to facilitate understanding of the shift relationship between the register values ​​of multiple single-bit registers Reg_1~Reg_M based on the linear feedback shift topology, and is not intended to make unnecessary restrictions on the update changes of the register values ​​D_1~D_M of the multiple single-bit registers Reg_1~Reg_M, and the rules of the output register value D_out generated by the output bit register Reg_M due to the linear feedback shift. For example, any linear feedback shift topology that meets the following conditions can be applied to the embodiments of the present application: the feedback source in the linear feedback shift includes the register value D_M of the output bit register Reg_M, and the update of the register value D_1 of the input bit register Reg_1 is associated with the register value D_M of the output bit register Reg_M.

[0036] Exemplarily, in an embodiment of the present application, the information storage circuit 20 may be used to store pre-configured shift prediction information. The shift prediction information is determined based on a linear feedback shift topology set for a plurality of single-bit registers Reg_1 to Reg_M, and the shift prediction information may be used to characterize: the update changes of register values ​​D_1 to D_M of the plurality of single-bit registers Reg_1 to Reg_M based on the linear feedback shift topology, and the rule of the output register value D_out generated by the output bit register Reg_M due to the linear feedback shift based on the linear feedback shift topology.

[0037] Exemplarily, in an embodiment of the present application, in an embodiment of the present application, the pre-configured shift prediction information can be used to specifically characterize: the iterative logical relationship between the updated register value D_i_j of each single-bit register Reg_i in a plurality of single-bit registers Reg_1 to Reg_M at any linear feedback shift (i.e., the jth linear feedback shift of the single-bit register Reg_i starting from its initial register value D_i_0) and the initial register value of at least one associated single-bit register in the plurality of single-bit registers Reg_1 to Reg_M (i.e., the iterative logical relationship between the updated register value D_i_j of the single-bit register Reg_i and the initial register value of at least one associated single-bit register). Wherein, i is a positive integer greater than or equal to 1 and less than or equal to M, and j is a positive integer greater than or equal to 1 and used to represent any number of times.

[0038] Exemplarily, in an embodiment of the present application, at least one associated single-bit register among the multiple single-bit registers Reg_1~Reg_M can be predetermined among the multiple single-bit registers Reg_1~Reg_M by shift deduction of any number of linear feedback shifts starting from an initial register value D_i_0 based on a pre-set linear feedback shift topology.

[0039] Exemplarily, in an embodiment of the present application, the value range of any number represented by j may be less than or equal to the maximum number of shifts that can be supported by the shift deduction of the shift deduction circuit 30 .

[0040] For example, in the embodiment of the present application, the cycle period of the linear feedback shift of the plurality of single-bit registers Reg_1 to Reg_M (ie, the cycle period during which the output register value D_out of the output bit register Reg_M is not repeated) may be 2 M-1 , and the maximum number of shifts supported by the shift deduction circuit 30 may be less than or equal to the cycle period 2 M -1 .

[0041] Exemplarily, in an embodiment of the present application, the specified shift number N may be determined by the set bit number Q of the pseudo-random sequence to be generated, the specified shift number N and the set bit number Q are both positive integers greater than 1, the set bit number Q may be P times the specified shift number N, and P is a positive integer greater than or equal to 1. For example, the specified shift number N may be equal to the set bit number Q, or may be half of the set bit number Q.

[0042] For example, in an embodiment of the present application, the set bit number Q of the pseudo-random sequence indicated by the pseudo-random sequence generation instruction may be limited to be less than the cycle period 2. M-1 , and the specified shift number N can be limited to be less than or equal to the maximum shift number that the shift deduction of the shift deduction circuit 30 can support.

[0043] Exemplarily, in an embodiment of the present application, the shift deduction circuit 30 can be used to implement shift deduction in the following manner: based on the pre-configured shift prediction information stored in the information storage circuit 20, determine the shift deduction result after multiple single-bit registers Reg_1~Reg_M complete the linear feedback shift of a specified shift number N.

[0044] Exemplarily, in an embodiment of the present application, the shift deduction circuit 30 may be used to receive a pseudo-random sequence generation instruction. The pseudo-random sequence generation instruction may be used to indicate the set bit number Q of the pseudo-random sequence, and the pseudo-random sequence generation instruction may also be used to trigger the shift deduction circuit 30 to perform shift deduction on the register group 10 (i.e., multiple single-bit registers Reg_1 to Reg_M) to determine the shift deduction result. That is, the shift deduction circuit 30 may trigger the shift deduction on the register group 10 (i.e., multiple single-bit registers Reg_1 to Reg_M) in response to the pseudo-random sequence generation instruction, and determine the specified number of shifts N of the linear feedback shift required for the shift deduction triggered in response to the pseudo-random sequence generation instruction.

[0045] Exemplarily, in an embodiment of the present application, the initial register value D_i_0 of each single-bit register Reg_i among the multiple single-bit registers Reg_1~Reg_M before the start of the first linear feedback shift in the specified shift number N can also be considered as the register value when the shift deduction circuit 30 is triggered to perform shift deduction (that is, triggered to perform determination of the shift deduction result).

[0046] Exemplarily, in an embodiment of the present application, the shift deduction circuit 30 can be specifically used to determine the shift deduction result in the following manner: based on pre-configured shift prediction information (for example, shift prediction information stored in the information storage circuit 20) and an initial register value of at least one associated single-bit register predetermined among the multiple single-bit registers Reg_1~Reg_M, determine the shift deduction result for the register group 10 (i.e., multiple single-bit registers Reg_1~Reg_M).

[0047] Figure 4 This is a schematic diagram of the deduction principle of the pseudo-random sequence generation circuit used for the processor in the embodiment of the present application. Figure 4 In an embodiment of the present application, the shift deduction circuit 30 can concurrently (or synchronously) read the current register values ​​of the multiple single-bit registers Reg_1 to Reg_M as the initial register values ​​D_1_0 to D_M_0 of the multiple single-bit registers Reg_1 to Reg_M when being triggered to perform shift deduction on the register group 10 (i.e., the multiple single-bit registers Reg_1 to Reg_M). In addition, in an embodiment of the present application, the shift deduction circuit 30 can query the pre-configured shift prediction information in the information storage circuit 20 when concurrently (or synchronously) reading the initial register values ​​D_1_0 to D_M_0 of the multiple single-bit registers Reg_1 to Reg_M.

[0048] For example, in the embodiments of the present application, Figure 4 As shown, based on the initial register values ​​D_1_0 to D_M_0 of the multiple single-bit registers Reg_1 to Reg_M read concurrently (or synchronously), and the query result of the shift prediction information (such as the iterative logic relationship described above), the shift deduction result determined by the shift deduction circuit 30 may specifically include: Update register values ​​{D_1_N, D_2_N, ..., D_M_N} of the last (i.e., Nth) linear feedback shift of the plurality of single-bit registers Reg_1 to Reg_M in a specified number of shifts (i.e., N times), including an update register value D_i_N of the last (i.e., Nth) linear feedback shift of each single-bit register Reg_i in the plurality of single-bit registers Reg_1 to Reg_M in a specified number of shifts (i.e., N times); and, The output register values ​​{D_out_1, D_out_2, ..., D_out_N} of each linear feedback shift (i.e., the 1st to Nth linear feedback shifts, a total of N times) of the output bit register Reg_M in the specified shift times (i.e., N times), wherein the output register value D_out_ j of any one (i.e., the jth) linear feedback shift of the output bit register Reg_M in the specified shift times (i.e., N times) may be the previous register value of the output bit register Reg_M before the (i.e., the jth) linear feedback shift.

[0049] Exemplarily, in an embodiment of the present application, the previous register value of the output bit register Reg_M before the first (i.e., the case where j is equal to 1) linear feedback shift in the specified shift number (i.e., N times) may be the initial register value D_M_0 of the output bit register Reg_M before the first linear feedback shift in the specified shift number (i.e., N times) starts (i.e., when the shift deduction circuit 30 is triggered to perform shift deduction); the previous register value of the output bit register Reg_M before each linear feedback shift starting from the second time (i.e., the case where j is greater than 1) in the specified shift number (i.e., N times) may be the updated register values ​​D_M_1~D_M_N-1 of each linear feedback shift (i.e., the 1st to N-1st linear feedback shifts) of the output bit register Reg_M in the specified shift number (i.e., N times) except the last time (i.e., the Nth time). Thus, each output register value {D_out_1, D_out_2, ..., D_out_N} of the output bit register Reg_M may include, in sequence: the initial register value D_M_0 of the output bit register Reg_M before the first linear feedback shift in the specified shift number (i.e., N times) begins (i.e., when the shift deduction circuit 30 is triggered to perform shift deduction), and the updated register values ​​D_M_1 to D_M_N-1 of each linear feedback shift (i.e., the 1st to N-1st linear feedback shift) of the output bit register Reg_M in the specified shift number (i.e., N times) except the last one (i.e., the Nth time).

[0050] Exemplarily, in an embodiment of the present application, the shift deduction circuit 30 may also be used to: based on the determined shift deduction result, realize synchronous update of multiple single-bit registers Reg_1 to Reg_M and parallel output of a pseudo-random sequence PRS.

[0051] For example, in the embodiments of the present application, Figure 4As shown, the synchronous update of multiple single-bit registers Reg_1~Reg_M by the shift deduction circuit 30 can be used to: synchronously update (or synchronously assign) multiple single-bit registers Reg_1~Reg_M to the updated register values ​​D_1_N~D_M_N of the last (i.e., Nth) linear feedback shift of each single-bit register Reg_1~Reg_M in a specified number of shifts (i.e., N times), that is, synchronously update the initial register values ​​D_1_0~D_M_0 of multiple single-bit registers Reg_1~Reg_M directly (or once) to the updated register values ​​D_1_N~D_M_N of the last (i.e., Nth) linear feedback shift of each single-bit register Reg_1~Reg_M in a specified number of shifts (i.e., N times). That is, each single-bit register Reg_i among the multiple single-bit registers Reg_1~Reg_M can directly (or once) jump from the initial register value D_i_0 to the updated register value D_i_N of the last (i.e., Nth) linear feedback shift of the single-bit register Reg_i in the specified number of shifts (i.e., N times).

[0052] For example, in the embodiments of the present application, Figure 4 As shown, the parallel output process of the pseudo-random sequence PRS implemented by the shift deduction circuit 30 may include: using the output register values ​​{D_out_1, D_out_2, ..., D_out_N} (i.e., D_M_0 and D_M_1 to D_M_N-1) of each linear feedback shift of the output bit register Reg_M in a specified shift number (i.e., N times) as Q bits of the pseudo-random sequence PRS ( Figure 4 The corresponding bits in the diagram are output in parallel, taking the specified shift number N being equal to the set bit Q as an example.

[0053] Based on an embodiment of the present application, a processor may include a register group 10 and a shift deduction circuit 30. A shift relationship based on a preset linear feedback shift topology may exist between multiple single-bit registers Reg_1~Reg_M in the register group 10, and the shift deduction circuit 30 may directly deduce the shift deduction results of the linear feedback shift of the multiple single-bit registers Reg_1~Reg_M after a specified number of shifts. Wherein: a plurality of single-bit registers Reg_1~Reg_M can be synchronously updated to updated register values ​​D_1_N~D_M_N of linear feedback shift after a specified number of shifts (i.e., N times) by using the shift deduction result, so that the plurality of single-bit registers can complete the shift jump of the linear feedback shift of the specified number of shifts at one time (for example, within one working clock cycle); the specified number of shifts (i.e., N times) of the linear feedback shift corresponds to the set number of bits Q of the pseudo-random sequence, and the shift deduction result can also include the output register values ​​D_out_1~D_out_N (i.e., D_M_0 and D_M_1~ D_M_N-1) of the output bit register Reg_M configured in the plurality of single-bit registers Reg_1~Reg_M during the process of the linear feedback shift of the specified number of shifts. Therefore, the output register values ​​D_out_1~D_out_N (i.e., D_M_0 and D_M_1~ D_M_N-1) of the output bit register Reg_M are D_M_N-1) can be respectively output in parallel as the corresponding bits of the pseudo-random sequence (for example, output in parallel within one working clock cycle), thereby realizing the parallel output of the pseudo-random sequence PRS. Furthermore, compared with the linear feedback shift register that generates the pseudo-random sequence serially, the scheme of generating the pseudo-random sequence in parallel based on shift deduction in the embodiment of the present application helps to reduce the operating frequency required for generating the pseudo-random sequence in the processor.

[0054] For example, if the transmission rate of the processor can be 16 Gbps, the pseudo-random sequence includes 16 bits, and the specified number of shift deductions is 16 times, then the pseudo-random sequence generation circuit in the embodiment of the present application can generate a 16-bit pseudo-random sequence in parallel in one working clock cycle. In this case, the operating frequency of the pseudo-random sequence generation circuit in the embodiment of the present application for generating pseudo-random sequences in parallel for the processor may only require 1 GHz, which is lower than the 16 GHz required by the linear feedback shift register.

[0055] For another example, if the transmission rate of the processor can be 16 Gbps, the pseudo-random sequence includes 16 bits, and the specified number of shift deductions is 8 times, then the pseudo-random sequence generation circuit in the embodiment of the present application can successively generate two groups of 8-bit sequence segments of the pseudo-random sequence in parallel through two working clock cycles. In this case, the pseudo-random sequence generation circuit in the embodiment of the present application is used to generate pseudo-random sequences in parallel for the processor. The working frequency may only need 2 GHz, which is still lower than the 16 GHz required by the linear feedback shift register.

[0056] Figure 5 This is a schematic diagram of the deduction principle of the pseudo-random sequence generation circuit for the processor based on the lookup table in the embodiment of the present application. Figure 5 In an embodiment of the present application, the pre-configured shift prediction information stored in the information storage circuit 20 may include a plurality of iterative logic relationship tables {TBL} corresponding to linear feedback shifts of different shift times j. Each of the plurality of iterative logic relationship tables {TBL} is used to characterize: an iterative logic relationship between an updated register value D_i_ j of each single-bit register Reg_i in the plurality of single-bit registers Reg_1 to Reg_M at the linear feedback shift times j corresponding to the iterative logic relationship table (i.e., the jth time of the single-bit register Reg_i starting from its initial register value D_i_0) and the initial register value of at least one associated single-bit register predetermined in the plurality of single-bit registers Reg_1 to Reg_M (i.e., an iterative logic relationship between an updated register value D_i_ j of the single-bit register Reg_i and the initial register value of at least one associated single-bit register).

[0057] Exemplarily, in an embodiment of the present application, each iterative logic relationship table TBL_j in a plurality of iterative logic relationship tables {TBL} includes: an operation polynomial F(i, j) corresponding to each single-bit register Reg_i in a plurality of single-bit registers Reg_1~Reg_M respectively; wherein, any operation polynomial F(i, j) included in each iterative logic relationship table TBL_j in a plurality of iterative logic relationship tables {TBL} is used to characterize: an iterative logic relationship between an updated register value D_i_j of a single-bit register Reg_i corresponding to the operation polynomial F(i, j) in a plurality of single-bit registers Reg_1~Reg_M at a linear feedback shift number j (i.e., the jth time of the single-bit register Reg_i starting from its initial register value D_i_0) corresponding to the iterative logic relationship table and an initial register value of at least one associated single-bit register predetermined in the plurality of single-bit registers Reg_1~Reg_M (i.e., an iterative logic relationship between an updated register value D_i_j of the single-bit register Reg_i and an initial register value of at least one associated single-bit register).

[0058] Exemplarily, in an embodiment of the present application, for any operation polynomial F(i, j) included in each iterative logic relationship table TBL_ j in the multiple iterative logic relationship tables {TBL}, the operation terms included therein are used to characterize the initial register value of at least one associated single-bit register predetermined in the multiple single-bit registers Reg_1~Reg_M. Therefore, any operation polynomial F(i, j) included in each iterative logic relationship table TBL_ j in the multiple iterative logic relationship tables {TBL} can be used to indicate the initial register value of at least one associated single-bit register predetermined in the multiple single-bit registers Reg_1~Reg_M.

[0059] For example, in the embodiment of the present application, as described above, the cycle period of the linear feedback shift of the plurality of single-bit registers Reg_1 to Reg_M (ie, the cycle period during which the output register value D_out of the output bit register Reg_M does not repeat) may be 2 M-1 Therefore, the total number T of multiple iterative logical relationship tables {TBL} can be less than or equal to 2 M-1 .

[0060] Exemplarily, in an embodiment of the present application, the total number T of the multiple iterative logic relationship tables {TBL} can represent the maximum number of shifts that can be supported by the shift deduction of the shift deduction circuit 30, and the specified number of shifts N can be limited to be less than or equal to the total number T of the multiple iterative logic relationship tables {TBL}. In this case, the value range of the linear feedback shift number j can be expressed as a positive integer greater than or equal to 1 and less than or equal to T.

[0061] Exemplarily, in an embodiment of the present application, the shift deduction circuit 30 can be specifically used to determine the shift deduction result in the following manner: based on a lookup-table operation on multiple iterative logic relationship tables {TBL} and an initial register value of at least one associated single-bit register predetermined among multiple single-bit registers Reg_1~Reg_M, the shift deduction result is determined.

[0062] Exemplarily, in an embodiment of the present application, in order to determine the updated register values ​​D_1_N~D_M_N of the last (i.e., Nth) linear feedback shift of each single-bit register Reg_1~Reg_M in the shift deduction result in a specified number of shifts (i.e., N times), the first lookup table hit object indexed by the specified number of times N of the shift deduction circuit 30 may include: an iterative logical relationship table TBL_N corresponding to the last (i.e., Nth) linear feedback shift in the specified number of shifts (i.e., N times) in multiple iterative logical relationship tables {TBL}.

[0063] Exemplarily, in an embodiment of the present application, the first lookup table result of the lookup table operation performed by the shift deduction circuit 30 for the first lookup table hit object may include: the iterative logical relationship between the updated register value D_i_N of the last (i.e., Nth) linear feedback shift of each single-bit register Reg_i in the plurality of single-bit registers Reg_1~Reg_M in the specified number of shifts (i.e., N times) and the initial register value of at least one associated single-bit register predetermined in the plurality of single-bit registers Reg_1~Reg_M (i.e., the iterative logical relationship between the updated register value D_i_N of the single-bit register Reg_i and the initial register value of at least one associated single-bit register). For example, the iterative logical relationship may be represented by the operational polynomials F(1, N)~F(M, N) in the iterative logical relationship table TBL_N.

[0064] Exemplarily, in an embodiment of the present application, the process of the shift deduction circuit 30 determining the shift deduction result using the first lookup table result may include: determining the update register value D_1_N~D_M_N of the last (i.e., Nth) linear feedback shift of each single-bit register Reg_1~Reg_M in a specified number of shifts (i.e., N times) based on the first lookup table result and the initial register value of at least one associated single-bit register predetermined in the plurality of single-bit registers Reg_1~Reg_M. That is, the update register value D_1_N~D_M_N of the last (i.e., Nth) linear feedback shift of each single-bit register Reg_1~Reg_M in a specified number of shifts (i.e., N times) can be determined by substituting the initial register value of at least one associated single-bit register predetermined in the plurality of single-bit registers Reg_1~Reg_M into the operational polynomials F(1, N)_1~F(M, N) in the first lookup table result that characterize the iterative logical relationship corresponding to each single-bit register Reg_1~Reg_M.

[0065] Exemplarily, in an embodiment of the present application, in order to determine the output register values ​​{D_out_1, D_out_2, ..., D_out_N} (i.e., D_M_0 and D_M_1~D_M_N-1) of each linear feedback shift of the output bit register Reg_M in a specified shift number (i.e., N times), the shift deduction circuit 30 may include a second lookup table hit object indexed by the specified number N, which may include: multiple iterative logic relationship tables {TBL} that correspond in sequence to each (i.e., 1st to N-1st) linear feedback shift except the last one in the specified shift number (i.e., N times) TBL_1~TBL_N-1.

[0066] Exemplarily, in an embodiment of the present application, the second lookup table result of the lookup table operation performed by the shift deduction circuit 30 for the second lookup table hit object may include: the iterative logical relationship between the updated register values ​​D_M_1~D_M_N-1 of the output bit register Reg_M in each (i.e., the 1st to N-1st) linear feedback shift except the last time in the specified shift times (i.e., N times) and the initial register value of at least one associated single-bit register predetermined in the plurality of single-bit registers Reg_1~Reg_M (i.e., the iterative logical relationship between each of the updated register values ​​D_M_1~D_M_N-1 of the output bit register Reg_M and the initial register value of at least one associated single-bit register. For example, these iterative logical relationships may be represented by the operational polynomials F(M, 1)~F(M, N-1) in the iterative logical relationship tables TBL_1~TBL_N-1, respectively.

[0067] Exemplarily, in an embodiment of the present application, the process of the shift deduction circuit 30 determining the shift deduction result using the second lookup table result may include: determining the output register values ​​{D_out_1, D_out_2, ..., D_out_N} of each linear feedback shift of the output bit register Reg_M in a specified shift number (i.e., N times) based on the second lookup table result and the initial register value of at least one associated single-bit register predetermined in the plurality of single-bit registers Reg_1 to Reg_M. Among them, the first output register value D_out_1 of the output bit register Reg_M is the initial register value D_M_0 of the output bit register Reg_M, and the subsequent output register values ​​D_out_2 to D_out_N of the output bit register Reg_M can be determined by sequentially substituting the initial register value of at least one associated single-bit register predetermined in the plurality of single-bit registers Reg_1 to Reg_M into the operational polynomials F(M, 1) to F(M, N-1) representing the iterative logical relationship in the second lookup table result.

[0068] Figure 6 Schematic diagram of a linear feedback shift topology example set for a register group in an embodiment of the present application. Figure 6 In the linear feedback shift topology example shown in FIG. 1 , the total number of registers M of the plurality of single-bit registers Reg_1 to Reg_M is 23. In this case, in the case Figure 6 In the linear feedback shift topology example shown, the single-bit registers Reg_2 and Reg_3, Reg_5 and Reg_6, Reg_8 and Reg_9, Reg_16 and Reg_17, and Reg_21 and Reg_22 among the multiple single-bit registers Reg_1 to Reg_23 are connected through an exclusive OR operation circuit (indicated by the symbol "⊕" marked with the character "XOR" in the figure), the output bit register Reg_23 is also connected to the exclusive OR operation circuit, and the remaining adjacent single-bit registers among the multiple single-bit registers Reg_1 to Reg_23 are all directly connected.

[0069] For example, in the embodiment of the present application, taking the maximum number of shifts supported by the shift deduction circuit 30 as 16 as an example, the multiple single-bit registers Reg_1 to Reg_23 are based on the following: Figure 6 The shifting rules of the linear feedback shifting topology example shown can be referred to in Tables 1 to 16 listed below. Tables 1 to 16 correspond to the 1st to 16th linear feedback shifting times, respectively, and each of Tables 1 to 16 includes three table items.

[0070] Exemplarily, in the embodiment of the present application, the first column of each table in Table 1 to Table 16 represents: the updated register value D_i_j of the plurality of single-bit registers Reg_1 to Reg_23 at the linear shift number j corresponding to the table.

[0071] Exemplarily, in the embodiment of the present application, the second column of each table in Table 1 to Table 16 represents: the shift logic relationship between the update register value D_i_ j of the linear shift number j corresponding to the multiple single-bit registers Reg_1~Reg_23 in the table and the previous register value of the associated single-bit register before the linear shift number j corresponding to the table (i.e., j-1 times). Among them, in the second column of each table in Table 1 to Table 16, the operation polynomial G(i, j) of the previous register value of the associated single-bit register may be included, which has an equivalent relationship with the update register value D_i_ j of the corresponding single-bit register Reg_i, so that the equivalent relationship between the operation polynomial G(i, j) in the second column and the update register value D_i_ j can represent the shift logic relationship between the update register value D_i_ j and the previous register value of the associated single-bit register. In addition, the symbol "^" is used in the operation polynomial G(i, j) in the second column of each table in Table 1 to Table 16 to represent an exclusive OR operation.

[0072] Exemplarily, in the embodiment of the present application, the third column of each table in Table 1 to Table 16 represents: the iterative logical relationship between the update register value D_i_ j of the linear shift number j corresponding to the multiple single-bit registers Reg_1~Reg_23 in the table and the initial register value of the associated single-bit register before the first linear feedback shift. Among them, in the third column of each table in Table 1 to Table 16, the operation polynomial F(i, j) of the initial register value of the associated single-bit register may be included, and there is an equivalent relationship with the update register value D_i_ j of the corresponding single-bit register Reg_i, so that the iterative logical relationship between the update register value D_i_ j and the initial register value of the associated single-bit register is represented by the equivalent relationship between the operation polynomial in the third column and the update register value D_i_ j. In addition, the symbol "^" is used in the operation polynomial in the third column of each table in Table 1 to Table 16 to represent an exclusive OR operation.

[0073] Exemplarily, in an embodiment of the present application, the operational polynomial F(i, j) corresponding to each single-bit register Reg_i in the third column of each table in Tables 1 to 16 can be determined by iterating step by step with the operational polynomial G(i, j) corresponding to each single-bit register Reg_i in the second column of the previous table. For example, the operational polynomial F(i, 8) corresponding to each single-bit register Reg_i in the third column of Table 8 can be substituted into the operational polynomial G(i, 1) corresponding to the single-bit register Reg_i in the second column of Table 1 into the operational polynomial G(i, 2) corresponding to the single-bit register Reg_i in the second column of Table 2, and then the substitution result is further substituted into the operational polynomial G(i, 3) corresponding to the single-bit register Reg_i in the second column of Table 3, and then substituted into the operational polynomial G(i, 8) corresponding to the single-bit register Reg_i in the second column of Table 8 step by step, thereby obtaining the operational polynomial F(i, j) corresponding to the single-bit register Reg_i in the second column of Table 8. That is, the operational polynomial G(i, j) in the second column of each of Tables 1 to 16 is intended to represent the shift logic relationship between the register values ​​of the current and previous linear feedback shifts of multiple single-bit registers Reg_1~Reg_23, so that, through the step-by-step iteration of the shift logic relationship between the register values ​​of the current and previous linear feedback shifts, the operational polynomial F(i, j) in the third column for characterizing the iterative logic relationship between the last linear feedback shift and the initial register value can be obtained.

[0074] Illustratively, in an embodiment of the present application, 16 iterative logic relationship tables TBL_1 to TBL_16 in the plurality of iterative logic relationship tables {TBL} may include the third columns of Tables 1 to 16 in sequence.

[0075] Table 1:

[0076] Table 2:

[0077] Table 3:

[0078] Table 4:

[0079] Table 5:

[0080] Table 6:

[0081] Table 7:

[0082] Table 8:

[0083] Exemplarily, in an embodiment of the present application, if the specified shift number N is 8, then the multiple single-bit registers Reg_1 to Reg_23 can be synchronously updated according to the corresponding operation polynomials F(1, 8) to F(23, 8) in the third column of Table 8. At the same time (for example, within one working clock cycle), among the 8 bits of the pseudo-random sequence output in parallel: Bit 1: Initial register value D_23_0 of output bit register Reg_23; 2nd position: the operation polynomial F(23, 1)=D_22_0 in Table 1; The third position: the operation polynomial F(23, 2)=D_21_0^D_23_0 in Table 2; 4th position: the operation polynomial F(23, 3)=D_20_0^D_22_0 in Table 3; 5th digit: the operation polynomial F(23, 4)=D_19_0^D_21_0^D_23_0 in Table 4; The sixth position: the operation polynomial F(23, 5)=D_18_0^D_20_0^D_22_0 in Table 5; 7th position: the operation polynomial F(23, 6)=D_17_0^D_19_0^D_21_0^D_23_0 in Table 6; Bit 8: Operation polynomial F(23, 7)=D_16_0^D_23_0^D_18_0^D_20_0^D_22_0 in Table 7.

[0084] Table 9:

[0085] Table 10:

[0086] Table 11:

[0087] Table 12:

[0088] Table 13:

[0089] Table 14:

[0090] Table 15:

[0091] Table 16:

[0092] Exemplarily, in an embodiment of the present application, if the specified shift number N is 16, then the multiple single-bit registers Reg_1 to Reg_23 can be synchronously updated according to the corresponding operation polynomials F(1, 16) to F(23, 16) in the third column of Table 16. At the same time (for example, within one working clock cycle), among the 16 bits of the pseudo-random sequence output in parallel: Bit 1: Initial register value D_23_0 of output bit register Reg_23; 2nd position: the operation polynomial F(23, 1)=D_22_0 in Table 1; The third position: the operation polynomial F(23, 2)=D_21_0^D_23_0 in Table 2; 4th position: the operation polynomial F(23, 3)=D_20_0^D_22_0 in Table 3; 5th digit: the operation polynomial F(23, 4)=D_19_0^D_21_0^D_23_0 in Table 4; The sixth position: the operation polynomial F(23, 5)=D_18_0^D_20_0^D_22_0 in Table 5; 7th position: the operation polynomial F(23, 6)=D_17_0^D_19_0^D_21_0^D_23_0 in Table 6; 8th bit: Operation polynomial F(23, 7)=D_16_0^D_23_0^D_18_0^D_20_0^D_22_0 in Table 7; The 9th position: the operation polynomial F(23, 8) in Table 8, that is: D_15_0^D_22_0^D_17_0^D_19_0^D_21_0^D_23_0; The 10th digit: the operation polynomial F(23, 9) in Table 9, that is: D_14_0^D_21_0^D_16_0^D_18_0^D_20_0^D_22_0; 11th bit: The operation polynomial F(23, 10) in Table 10, that is: D_13_0^D_20_0^D_15_0^D_17_0^D_19_0^D_21_0^D_23_0; The 12th bit: the operation polynomial F(23, 11) in Table 11, that is: D_12_0^D_19_0^D_14_0^D_16_0^D_23_0^D_18_0^D_20_0^D_22_0; The 13th bit: the operation polynomial F(23, 12) in Table 12, that is: D_11_0^D_18_0^D_13_0^D_15_0^D_22_0^D_17_0^D_19_0^D_21_0^D_23_0; 14th bit: The operation polynomial F(23, 13) in Table 13, that is: D_10_0^D_17_0^D_12_0^D_14_0^D_21_0^D_16_0^D_18_0^D_20_0^D_22_0; 15th bit: The operation polynomial F(23, 14) in Table 14, that is: D_9_0^D_16_0^D_11_0^D_13_0^D_20_0^D_15_0^D_17_0^D_19_0^D_21_0; 16th bit: The operation polynomial F(23, 15) in Table 15, that is: D_8_0^D_15_0^D_10_0^D_12_0^D_19_0^D_14_0^D_16_0^D_18_0^D_20_0.

[0093] It is understandable that the above examples are only for more intuitive understanding of the deduction principle implemented by the shift deduction circuit 30 based on the lookup table operation of the shift prediction information, and are not intended to make unnecessary limitations on the specific definition of the iterative logical relationship represented by the shift prediction information. That is, the iterative logical relationship represented by the shift prediction information can be represented by an operational polynomial whose operation method is not limited to the XOR operation, or other forms not limited to the operational polynomial.

[0094] In an embodiment of the present application, a pseudo-random sequence generation method for a processor is also provided, and a processor applicable to the pseudo-random sequence generation method may include a register group, the register group may include multiple single-bit registers, and one of the multiple single-bit registers may be designated as an output bit register in a set linear feedback shift topology.

[0095] Figure 7 FIG. 1 is an exemplary flow chart of a pseudo-random sequence generation method for a processor in an embodiment of the present application. Figure 7 In an embodiment of the present application, the pseudo-random sequence generation method may include: S710: Based on pre-configured shift prediction information, determine shift deduction results of multiple single-bit registers of the processor after completing linear feedback shifts of a specified number of shifts; wherein the shift prediction information is determined based on a linear feedback shift topology set for the multiple single-bit shift registers, the specified number of shifts of the linear feedback shift is determined by the set number of bits of the pseudo-random sequence, and the determined shift deduction results include: an updated register value of the last linear feedback shift of each single-bit register in the multiple single-bit registers in the specified number of shifts, and each output register value of each linear feedback shift of the output bit register in the specified number of shifts; S730: Based on the determined shift deduction result, realize the synchronous update of multiple single-bit registers and the parallel output of pseudo-random sequence; wherein, the synchronous update of multiple single-bit registers is used to synchronously update multiple single-bit registers to the updated register value of the last linear feedback shift in the specified shift number, and the parallel output of the pseudo-random sequence includes: outputting the output register value of each linear feedback shift of the output bit register in the specified shift number as the corresponding bit of the pseudo-random sequence in parallel.

[0096] Based on the above process of the embodiment of the present application, the shift deduction results of the linear feedback shift of the multiple single-bit registers of the processor after the specified shift times can be directly deduced. Among them: the multiple single-bit registers can be synchronously updated to the updated register values ​​of the linear feedback shift after the specified shift times using the shift deduction results, so that the multiple single-bit registers can complete the shift jump of the linear feedback shift of the specified shift times at one time (for example, within one working clock cycle); the specified shift times (i.e., N times) of the linear feedback shift corresponds to the set bit number of the pseudo-random sequence, and the shift deduction results can also include the output register values ​​of each time of the output bit register configured in the multiple single-bit registers during the linear feedback shift of the specified shift times, so that the output register values ​​of each time of the output bit register can be respectively output in parallel as the corresponding bits of the pseudo-random sequence (for example, output in parallel within one working clock cycle), thereby realizing the parallel output of the pseudo-random sequence. Furthermore, compared to a linear feedback shift register that generates a pseudo-random sequence serially, the scheme for generating a pseudo-random sequence in parallel based on shift deduction in the embodiment of the present application helps to reduce the operating frequency required to generate a pseudo-random sequence in a processor.

[0097] Exemplarily, in an embodiment of the present application, the shift prediction information based on which S710 performs shift deduction can be used to characterize: the iterative logical relationship between the updated register value of each single-bit register in a plurality of single-bit registers from any number of linear feedback shifts (i.e., any number of times starting from its initial register value) and the initial register value of at least one associated single-bit register; wherein, at least one associated single-bit register can be pre-determined among a plurality of single-bit registers by performing shift deduction of any number of linear feedback shifts based on a linear feedback shift topology. In this case, S710 can specifically include: determining the shift deduction results of a plurality of single-bit registers of the processor after completing a specified number of linear feedback shifts based on the pre-configured shift prediction information and the initial register value of at least one associated single-bit register.

[0098] Exemplarily, in an embodiment of the present application, the shift prediction information based on which S710 performs shift deduction may include multiple iterative logic relationship tables corresponding to different linear feedback shift times, respectively; wherein each iterative logic relationship table in the multiple iterative logic relationship tables may be used to characterize: the iterative logic relationship between the updated register value of each single-bit register in the multiple single-bit registers corresponding to the linear feedback shift times in the iterative logic relationship table and the initial register value of at least one associated single-bit register. In this case, S710 may specifically include: based on the lookup table operation of the multiple iterative logic relationship tables and the initial register value of at least one associated single-bit register, determining the shift deduction results of the multiple single-bit registers of the processor after completing the linear feedback shift of the specified shift times.

[0099] Exemplarily, in an embodiment of the present application, the first lookup table hit object of the lookup table operation performed by S710 with the specified shift number as the index may include: the iterative logical relationship table of the last linear feedback shift in the specified shift number in the multiple iterative logical relationship tables. In this case, the first lookup table result of the lookup table operation on the first lookup table hit object may include: the iterative logical relationship between the updated register value of the last linear feedback shift of each single-bit register in the multiple single-bit registers in the specified shift number and the initial register value of at least one associated single-bit register. Furthermore, the process of determining the shift deduction result based on the lookup table operation on the multiple iterative logical relationship tables and the initial register value of at least one associated single-bit register by S710 may include: determining the updated register value of the last linear feedback shift of each single-bit register in the specified shift number based on the first lookup table result and the initial register value of at least one associated single-bit register.

[0100] Exemplarily, in an embodiment of the present application, each output register value of the output bit register may include in sequence: the initial register value of the output bit register, and the update register value of each linear feedback shift of the output bit register except the last one in the specified shift times. Therefore, in an embodiment of the present application, the second lookup table hit object of the lookup table operation performed by S710 with the specified shift times as the index may include: the iterative logical relationship table of each linear feedback shift except the last one in the specified shift times in a plurality of iterative logical relationship tables. In this case, the second lookup table result of the lookup table operation on the second lookup table hit object may include: the iterative logical relationship between the update register value of each linear feedback shift of the output bit register except the last one in the specified shift times and the initial register value of at least one associated single-bit register. Furthermore, the process of determining the shift deduction result based on the lookup table operation on the plurality of iterative logical relationship tables and the initial register value of at least one associated single-bit register may include: determining each output register value of the output bit register based on the second lookup table result and the initial register value of at least one associated single-bit register.

[0101] Exemplarily, in an embodiment of the present application, each iterative logic relationship table in a plurality of iterative logic relationship tables may include: an operational polynomial corresponding to each single-bit register in a plurality of single-bit registers; wherein, any operational polynomial included in each of the plurality of iterative logic relationship tables may be used to characterize: an iterative logical relationship between an updated register value of the single-bit register corresponding to the operational polynomial at the number of linear feedback shifts corresponding to the iterative logic relationship table and an initial register value of at least one associated single-bit register.

[0102] Exemplarily, in an embodiment of the present application, the cycle period of the linear feedback shift of the plurality of single-bit registers is 2 M-1 , M represents the total number of registers of the plurality of single-bit registers, and the total number of the plurality of iterative logic relationship tables is less than or equal to 2 M-1 , and the total number of multiple iterative logic relationship tables can be used to characterize the maximum number of shifts that the pseudo-random sequence can support based on the lookup table method.

[0103] In an embodiment of the present application, a processor is further provided, which may include the pseudo-random sequence generation circuit as described in the above embodiment.

[0104] Exemplarily, in an embodiment of the present application, the processor may refer to any device with processing capability, for example, the processor may be any one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), a NPU (Neural Network Processing Unit), a DPU (Deep Learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose computing on Graphics Processing Units).

[0105] Exemplarily, in an embodiment of the present application, the processor may include at least two chiplets, and the pseudo-random sequences generated in parallel by the pseudo-random sequence generation circuit may be used for verification of transmission communication between the chiplets.

[0106] Exemplarily, in an embodiment of the present application, at least two core particles of the processor may transmit a communication data packet through a physical layer channel, any one of the at least two core particles that is a sender of the communication data packet includes a pseudo-random sequence generation circuit, and another core particle of the at least two core particles that is a receiver of the communication data packet may include an analog receiving circuit, the analog receiving circuit is used to receive the communication data packet by sampling the physical layer channel based on analog deskew, and the pseudo-random sequence concurrently output by the pseudo-random sequence generation circuit is used to verify the analog deskew. For example, the core particle that is a receiver of the communication data packet among the at least two core particles may use the pseudo-random sequence transmitted through the physical layer channel and received by sampling based on analog deskew to determine whether there is a residual deviation that has not been corrected by analog deskew.

[0107] It can be understood that, in the embodiments of the present application, the various parts of the contents exemplified can be in an "and / or" relationship. In this article, the meaning of "and / or" refers to the contexts connected by it, which can be in a common limiting relationship of "and", or can also be in an alternative limiting relationship of "or". Therefore, the various parts of the contents with an "and / or" relationship can be understood as including different combinations of situations in which "and / or" between each two parts of the contents respectively represents a common limiting relationship of "and" or an alternative limiting relationship of "or", and this combination of different situations can be considered to be basically equivalent to the limiting scope of "at least one of the parts".

[0108] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A pseudo-random sequence generating circuit for a processor, characterized in that: include: A register group, comprising a plurality of single-bit registers; wherein one of the plurality of single-bit registers is designated as an output bit register in a set linear feedback shift topology; Shift deduction circuit for: Based on pre-configured shift prediction information, shift deduction results of the multiple single-bit registers after completing the linear feedback shift of the specified shift times are determined; wherein the shift prediction information is determined based on the linear feedback shift topology, the specified shift times are determined by the set bit number of the pseudo-random sequence, and the shift deduction results include: the updated register value of the last linear feedback shift of each single-bit register in the multiple single-bit registers in the specified shift times, and the output register value of each linear feedback shift of the output bit register in the specified shift times; Based on the shift deduction result, the synchronous update of the multiple single-bit registers and the parallel output of the pseudo-random sequence are realized; wherein the synchronous update is used to synchronously update the multiple single-bit registers to the updated register value of the last linear feedback shift in the specified number of shifts, and the parallel output of the pseudo-random sequence includes: outputting the output register value of each linear feedback shift of the output bit register in the specified number of shifts as the corresponding bit of the pseudo-random sequence in parallel.

2. The pseudo-random sequence generating circuit according to claim 1, characterized in that: The shift prediction information is used to characterize: an iterative logical relationship between an updated register value of each single-bit register in the plurality of single-bit registers in any linear feedback shift and an initial register value of at least one associated single-bit register; wherein the at least one associated single-bit register is predetermined in the plurality of single-bit registers by performing a shift deduction of the arbitrary linear feedback shift based on the linear feedback shift topology; The shift deduction circuit is specifically used to determine the shift deduction result in the following manner: determine the shift deduction result based on the shift prediction information and the initial register value of the at least one associated single-bit register.

3. The pseudo-random sequence generating circuit according to claim 1, characterized in that: The shift prediction information includes a plurality of iterative logic relationship tables corresponding to different linear feedback shift times respectively; wherein each of the plurality of iterative logic relationship tables is used to characterize: an iterative logic relationship between an updated register value of each single-bit register in the plurality of single-bit registers corresponding to the linear feedback shift times in the iterative logic relationship table and an initial register value of at least one associated single-bit register; the at least one associated single-bit register is pre-determined in the plurality of single-bit registers by performing a shift deduction of any number of linear feedback shifts based on the linear feedback shift topology; The shift deduction circuit is specifically used to determine the shift deduction result in the following manner: determining the shift deduction result based on a table lookup operation on the multiple iterative logic relationship tables and the initial register value of the at least one associated single-bit register.

4. The pseudo-random sequence generating circuit according to claim 3, characterized in that: The first lookup table hit object indexed by the lookup table operation includes: an iterative logic relationship table corresponding to the last linear feedback shift in the specified shift number among the multiple iterative logic relationship tables; The first lookup table result of the lookup table operation on the first lookup table hit object includes: an iterative logical relationship between an updated register value of the last linear feedback shift of each single-bit register of the plurality of single-bit registers in the specified number of shifts and the initial register value of the at least one associated single-bit register; The process of the shift deduction circuit determining the shift deduction result includes: based on the first lookup table result and the initial register value of the at least one associated single-bit register, determining the updated register value of each single-bit register among the multiple single-bit registers after completing the last linear feedback shift in the specified number of shifts.

5. The pseudo-random sequence generating circuit according to claim 3, characterized in that: The output register values ​​of the output bit register include: the initial register value of the output bit register, and the update register value of each linear feedback shift of the output bit register except the last one in the specified shift times; The second lookup table hit object indexed by the lookup table operation includes: the iterative logic relationship tables of the multiple iterative logic relationship tables that correspond to the linear feedback shifts of the specified shift times except the last one; The second lookup table result of the lookup table operation on the second lookup table hit object includes: an iterative logical relationship between the update register value of each linear feedback shift of the output bit register except the last one in the specified number of shifts and the initial register value of the at least one associated single-bit register; The process of the shift deduction circuit determining the shift deduction result includes: determining each output register value of the output bit register based on the second lookup table result and the initial register value of the at least one associated single-bit register.

6. The pseudo-random sequence generating circuit according to claim 3, characterized in that: Each of the multiple iterative logic relationship tables includes: an operation polynomial corresponding to each single-bit register in the multiple single-bit registers; wherein, any operation polynomial included in each of the multiple iterative logic relationship tables is used to characterize: the iterative logical relationship between the updated register value of the single-bit register corresponding to the operation polynomial at the corresponding number of linear feedback shifts and the initial register value of the at least one associated single-bit register.

7. The pseudo-random sequence generating circuit according to claim 3, characterized in that: The cycle period of the linear feedback shift of the plurality of single-bit registers is 2 M-1 , M represents the total number of registers of the plurality of single-bit registers, and the total number of the plurality of iterative logic relationship tables is less than or equal to 2 M-1 .

8. A pseudo-random sequence generation method for a processor, characterized in that: The processor includes a register group, the register group includes a plurality of single-bit registers, one of the plurality of single-bit registers is designated as an output bit register in a set linear feedback shift topology, and the pseudo-random sequence generation method includes: Based on pre-configured shift prediction information, shift deduction results after the multiple single-bit registers complete the linear feedback shift of the specified shift times are determined; wherein the shift prediction information is determined based on the linear feedback shift topology, the specified shift times are determined by the set bit number of the pseudo-random sequence, and the shift deduction results include: the updated register value of the last linear feedback shift of each single-bit register in the multiple single-bit registers in the specified shift times, and the output register value of each linear feedback shift of the output bit register in the specified shift times; Based on the shift deduction result, the synchronous update of the multiple single-bit registers and the parallel output of the pseudo-random sequence are realized; wherein the synchronous update is used to synchronously update the multiple single-bit registers to the updated register value of the last linear feedback shift in the specified number of shifts, and the parallel output of the pseudo-random sequence includes: outputting the output register value of each linear feedback shift of the output bit register in the specified number of shifts as the corresponding bit of the pseudo-random sequence in parallel.

9. The method for generating a pseudo-random sequence according to claim 8, characterized in that: The shift prediction information is used to characterize: an iterative logical relationship between an updated register value of each single-bit register in the plurality of single-bit registers in any linear feedback shift and an initial register value of at least one associated single-bit register; wherein the at least one associated single-bit register is predetermined in the plurality of single-bit registers by performing a shift deduction of the arbitrary linear feedback shift based on the linear feedback shift topology; The method of determining the shift deduction result after the multiple single-bit registers complete the linear feedback shift of the specified shift times based on the pre-configured shift prediction information includes: determining the shift deduction result based on the shift prediction information and the initial register value of the at least one associated single-bit register.

10. A processor, characterized in that: The method comprises the pseudo-random sequence generating circuit as claimed in any one of claims 1 to 7.

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