Virtual prototype platform branch prediction method, device, equipment and medium

Abstract

The present application relates to a branch prediction method, apparatus, device and medium for a virtual prototype platform. The method comprises: calling a preset scoring strategy, wherein a branch jump direction predictor in a branch prediction model predicts the jump direction of the current branch instruction based on a memory address corresponding to the current branch instruction; if the current branch instruction is in a jump state, a branch jump address predictor in the branch prediction model adopts a preset scoring strategy to predict a program counter address to be jumped corresponding to the current branch instruction based on a memory address corresponding to the current branch instruction; if the current branch instruction is in a non-jump state, a branch jump address predictor determines a program counter address of the next instruction of the current branch instruction based on a memory address corresponding to the current branch instruction, thereby completing branch prediction of the virtual prototype platform; the present application significantly improves the coverage of branch prediction, making the functional verification of the virtual prototype platform more comprehensive.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a virtual prototype platform branch prediction method, a corresponding device, an electronic device, and a computer-readable storage medium. Background Art

[0002] With the rapid development of modern computing technology, CPU design is becoming increasingly complex, and market demands for faster time to market are also increasing. Driven by Gordon Moore's predictions about technological advancement, CPU integration is constantly increasing, and performance requirements are also rising. To remain competitive in the fiercely competitive market, CPU design and development cycles must be significantly shortened while ensuring high performance and reliability. The traditional hardware-first, software-later design process is no longer able to meet the demands of rapid iteration. Therefore, electronic system-level (ESL) design methodologies have become a key technology to address this issue. By building virtual prototypes early in the design process, design teams can achieve collaborative development of hardware and software. This approach not only accelerates CPU design cycles but also enables more comprehensive testing and verification early in the design process, significantly improving design efficiency and product quality. Therefore, virtual prototyping technology plays a vital role in CPU design, enabling designers to identify and resolve potential issues before actual product manufacturing, effectively driving the rapid development and innovation of CPU technology.

[0003] Branch prediction research has been ongoing for decades, primarily focusing on predicting the direction of conditional branches, as this aspect often represents the primary source of mispredictions. It is a fundamental means of ensuring smooth execution of the processor instruction flow, efficiency, and performance optimization. By effectively utilizing data such as PC values ​​and history information, a range of branch prediction algorithms have been developed to prevent pipeline stalls and other behaviors caused by branch mispredictions. Among high-accuracy branch predictors, the TAGE branch predictor is one of the most important, named for its use of the geometric length of history markers for branch prediction. Due to its high prediction accuracy and balanced resource consumption, it is frequently used in processor branch prediction optimization. The TAGE-SC-L branch prediction model, proposed by André Seznec in 2011 and an extension of the TAGE branch prediction technique, is an advanced branch prediction technique currently used in CPU design. However, verification of these high-accuracy branch prediction algorithms has been limited to rapid evaluation in simulators or verification on actual processors. Such models have not yet been fully functionally verified in virtual prototyping (VP) platforms at the electronic system level (ESL).

[0004] To sum up, the TAGE-SC-L branch prediction model in the existing technology has not yet been fully functionally verified on the virtual prototype (VP) platform at the electronic system level (ESL). In order to solve this problem, the applicant has made corresponding explorations. Summary of the Invention

[0005] The purpose of this application is to solve the above problems and provide a virtual prototype platform branch prediction method, corresponding device, electronic device and computer-readable storage medium.

[0006] In order to meet the various objectives of this application, this application adopts the following technical solutions:

[0007] A virtual prototype platform branch prediction method proposed to meet one of the purposes of this application includes:

[0008] In response to the branch prediction instruction of the virtual prototype platform, the instruction simulator in the CPU core structure is triggered to send the memory address corresponding to the current branch instruction to the preset branch prediction model during the decoding stage;

[0009] Invoking a preset scoring strategy, a branch jump direction predictor in the branch prediction model predicts a jump direction of the current branch instruction based on a memory address corresponding to the current branch instruction, wherein the jump direction includes a first jump direction and a second jump direction, the first jump direction indicating that the current branch instruction is in a jump state, and the second jump direction indicating that the current branch instruction is in a non-jump state;

[0010] If the current branch instruction is in a jump state, the branch jump address predictor in the branch prediction model uses a preset scoring strategy to predict the address of the program counter to be jumped corresponding to the current branch instruction according to the memory address corresponding to the current branch instruction;

[0011] If the current branch instruction is in a non-jump state, the branch jump address predictor determines the program counter address of the next instruction of the current branch instruction according to the memory address corresponding to the current branch instruction;

[0012] An actual jump result of the current branch instruction is determined in the CPU core structure, and the actual jump result is sent to a branch jump direction predictor in the branch prediction model to update the branch prediction model to complete branch prediction of the virtual prototype platform.

[0013] Optionally, the basic network architecture of the branch prediction model is an improved TAGE-SC-L branch prediction model, and the improved TAGE-SC-L branch prediction model is constructed by a TAGE-SC-L branch predictor that introduces a scoring strategy and a perceptron.

[0014] Optionally, after the step of triggering the instruction simulator in the CPU core structure to send the memory address corresponding to the current branch instruction to a preset branch prediction model, the following steps are included:

[0015] Calling a preset scoring strategy to initialize initial scoring variables corresponding to the main predictor, the statistical correction predictor, and the cyclic predictor;

[0016] If the prediction result corresponding to any branch predictor matches its corresponding actual result, its corresponding prediction score increases by 1; if the prediction result of any branch predictor does not match its actual result, its corresponding prediction score is set to 0;

[0017] Compare the first prediction score corresponding to the main predictor, the second prediction score corresponding to the statistical correction predictor, and the third prediction score corresponding to the loop predictor. If the third prediction score corresponding to the loop predictor is greater than the first prediction score corresponding to the main predictor and the second prediction score corresponding to the statistical correction predictor, take the third prediction result corresponding to the loop predictor as the final prediction result.

[0018] Optionally, after comparing the first prediction score corresponding to the main predictor, the second prediction score corresponding to the statistically corrected predictor, and the third prediction score corresponding to the loop predictor, and if the third prediction score corresponding to the loop predictor is greater than the first prediction score corresponding to the main predictor and the second prediction score corresponding to the statistically corrected predictor, then taking the third prediction result corresponding to the loop predictor as the final prediction result, the method further includes:

[0019] If the second prediction score corresponding to the statistically corrected predictor is greater than the first prediction score corresponding to the main predictor, the second prediction result corresponding to the statistically corrected predictor is used as the final prediction result; otherwise, the first prediction result corresponding to the main predictor is selected as the final prediction result;

[0020] If the first condition flag corresponding to the statistical correction predictor is not equal to 1, the determination includes: if the second condition flag corresponding to the loop predictor is equal to 1, selecting the third prediction result corresponding to the loop predictor as the final prediction result; otherwise, selecting the first prediction result corresponding to the main predictor as the final prediction result;

[0021] If the first condition flag corresponding to the statistical correction predictor is equal to 1, directly selecting the optimal branch predictor selected based on the preset scoring strategy;

[0022] The above steps are executed in a loop and the prediction result of the final selected branch predictor is returned.

[0023] Optionally, the master predictor includes a base table and multiple tag tables, wherein the base table is indexed by a program counter address, and the tag table is indexed by hashing history information of a variable geometric history length with the program counter address to obtain a prediction result, and if no tag table hits, the prediction result of the base table is selected;

[0024] Otherwise, the prediction result of the tag table with the longest history length is selected from all the hit tag tables as the final prediction direction.

[0025] Optionally, the CPU core structure includes a four-stage pipeline of instruction fetch, decoding, execution and write-back.

[0026] Optionally, in the decoding stage, calling the get_prediction() function in the branch jump direction predictor in the branch prediction model to predict the jump direction of the current branch instruction according to the memory address corresponding to the current branch instruction;

[0027] In the execution phase, the preset update_predictor() function is called to send the actual jump result to the branch jump direction predictor in the branch prediction model.

[0028] A virtual prototype platform branch prediction device provided for another purpose of the present application includes:

[0029] a memory address sending module, configured to respond to a branch prediction instruction of the virtual prototype platform, triggering the instruction simulator in the CPU core structure to send a memory address corresponding to the current branch instruction to a preset branch prediction model during the decoding phase;

[0030] a jump direction prediction module, configured to call a preset scoring strategy, wherein a branch jump direction predictor in the branch prediction model predicts a jump direction of the current branch instruction based on a memory address corresponding to the current branch instruction, wherein the jump direction includes a first jump direction and a second jump direction, the first jump direction indicating that the current branch instruction is in a jump state, and the second jump direction indicating that the current branch instruction is in a non-jump state;

[0031] The to-be-jumped address prediction module is configured to, if the current branch instruction is in a jump state, use a preset scoring strategy by the branch jump address predictor in the branch prediction model to predict the to-be-jumped program counter address corresponding to the current branch instruction based on the memory address corresponding to the current branch instruction;

[0032] a program counter address determination module configured to, if the current branch instruction is in a non-jump state, determine the program counter address of the next instruction of the current branch instruction based on the memory address corresponding to the current branch instruction by the branch jump address predictor;

[0033] A branch prediction model update module is configured to determine an actual jump result of the current branch instruction in the CPU core structure, and send the actual jump result to a branch jump direction predictor in the branch prediction model to update the branch prediction model to complete the branch prediction of the virtual prototype platform.

[0034] An electronic device provided to meet another purpose of the present application includes a central processing unit and a memory, wherein the central processing unit is used to call and run a computer program stored in the memory to execute the steps of the virtual prototype platform branch prediction method described in the present application.

[0035] A computer-readable storage medium is provided to meet another purpose of the present application, which stores a computer program implemented according to the virtual prototype platform branch prediction method in the form of computer-readable instructions. When the computer program is called and executed by a computer, the steps included in the corresponding method are executed.

[0036] Compared with the prior art, the present application addresses the problem that the TAGE-SC-L branch prediction model in the prior art has not yet been fully functionally verified on the virtual prototype (VP) platform at the electronic system level (ESL). The applicant has made corresponding explorations to solve this problem. The present application includes but is not limited to the following beneficial effects:

[0037] First, this application defines an improved branch prediction model based on a virtual prototype platform architecture, which has more comprehensive functional verification. This technology introduces a branch prediction model based on a virtual prototype, which can more comprehensively test and evaluate the functions of the branch prediction algorithm through simulation and verification during the design phase. The virtual prototype can provide more verification and optimization opportunities for various branch prediction scenarios, thereby ensuring that the final prediction model is more accurate and reliable.

[0038] Secondly, this application uses the higher-level hardware description language SystemC to design the branch prediction algorithm module, which results in faster simulation speed. Using a higher-level hardware description language for design makes the simulation of the branch prediction algorithm module more efficient. The SystemC language supports hardware-level parallelization and abstract modeling. Compared with traditional low-level languages, it can simulate faster, reduce design and verification cycles, and improve development efficiency.

[0039] Third, this application adopts a new scoring strategy to design the TAGE-SC-LS model, which has higher prediction accuracy. By introducing a new scoring strategy to design the TAGE-SC-LS model, the accuracy of branch prediction is significantly improved. The scoring strategy can allocate scores to different historical patterns, making the TAGE model more accurate in capturing complex branch patterns.

[0040] Fourthly, this application integrates the perceptron with the TAGE-SC-L branch predictor by introducing a scoring strategy, and designs the TAGE-SC-LP model with higher prediction coverage. By integrating the scoring strategy with the perceptron, the design of the TAGE-SC-LP model is further optimized, and the coverage of branch prediction is significantly improved. The perceptron is an algorithm based on machine learning, which can adjust the prediction strategy through dynamic learning, so that the model can cover more types of branch patterns, enhancing the adaptability and generalization ability of the model. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0042] Figure 1 Schematic diagram of the flow of the virtual prototype platform branch prediction method in an embodiment of the present application;

[0043] Figure 2 This is an exemplary architecture of an improved branch prediction model based on a virtual prototype platform in an embodiment of the present application;

[0044] Figure 3 This is an exemplary structure of the main predictor in the embodiment of the present application;

[0045] Figure 4 is an exemplary structure of the original TAGE-SC-L branch prediction model in the embodiments of this application;

[0046] Figure 5 This is a principle block diagram of a branch prediction device for a virtual prototype platform in an embodiment of the present application;

[0047] Figure 6 Schematic diagram of the structure of the computer device in the embodiment of the present application. DETAILED DESCRIPTION

[0048] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and are not to be construed as limiting the present application.

[0049] It will be understood by those skilled in the art that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. The term "and / or" used herein includes all or any units and all combinations of one or more associated listed items.

[0050] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0051] It will be understood by those skilled in the art that the terms "client," "terminal," and "terminal device" as used herein include both devices that are wireless signal receivers, i.e., devices that only have wireless signal receivers without transmission capabilities, and devices that have receiving and transmitting hardware capable of two-way communication over a two-way communication link. Such devices may include: cellular or other communication devices such as personal computers and tablet computers, which have single-line displays, multi-line displays, or cellular or other communication devices without multi-line displays; PCS (Personal Communications Service), which may combine voice, data processing, fax, and / or data communication capabilities; PDA (Personal Digital Assistant), which may include a radio frequency receiver, a pager, Internet / Intranet access, a web browser, a notepad, a calendar, and / or a GPS (Global Positioning System) receiver; and conventional laptop and / or palmtop computers or other devices, which have and / or include a radio frequency receiver. As used herein, the terms "client," "terminal," or "terminal device" may be portable, transportable, or installed in a vehicle (air, sea, and / or land), or may be adapted and / or configured to operate locally and / or in a distributed manner at any other location on Earth and / or in space. As used herein, the terms "client," "terminal," or "terminal device" may also refer to a communication terminal, an Internet terminal, or a music / video playback terminal, such as a PDA, an MID (Mobile Internet Device), and / or a mobile phone with music / video playback capabilities, or may include a smart TV, a set-top box, or other device.

[0052] The hardware referred to by names such as "server", "client", and "service node" in this application is essentially an electronic device with capabilities equivalent to those of a personal computer. It is a hardware device that has the necessary components revealed by the von Neumann principle, such as a central processing unit (including an arithmetic unit and a controller), a memory, an input device, and an output device. Computer programs are stored in its memory, and the central processing unit loads the program stored in the external memory into the internal memory for execution, executes the instructions in the program, and interacts with the input and output devices to complete specific functions.

[0053] It should be noted that the concept of "server" referred to in this application can also be extended to server clusters. Based on the network deployment principles understood by those skilled in the art, the servers described should be logically divided. In physical space, these servers can be independent of each other but callable through interfaces, or integrated into a single physical computer or a computer cluster. Those skilled in the art should understand this flexibility and should not use it to constrain the implementation of the network deployment method of this application.

[0054] Unless expressly specified, one or more technical features of the present application can be deployed on a server for implementation and accessed by a client through a remote call to obtain an online service interface provided by the server, or can be directly deployed and run on a client for implementation.

[0055] Unless expressly specified otherwise, the neural network models referenced or may be referenced in this application may be deployed on a remote server and remotely called on the client, or may be deployed and directly called on a client with sufficient device capabilities. In some embodiments, when it runs on the client, its corresponding intelligence may be obtained through transfer learning to reduce the requirements for the client's hardware operating resources and avoid excessive occupation of the client's hardware operating resources.

[0056] Unless explicitly specified, the various data involved in this application can be stored remotely on a server or on a local terminal device, as long as they are suitable for being called by the technical solution of this application.

[0057] Those skilled in the art should be aware that although the various methods of this application are described based on the same concept and thus exhibit commonality, unless otherwise specified, these methods can be independently executed. Similarly, the various embodiments disclosed in this application are all based on the same inventive concept. Therefore, concepts with the same expression, as well as concepts that are appropriately transformed for convenience despite different expression, should be understood as equivalent.

[0058] Unless expressly stated to be mutually exclusive, the various embodiments disclosed in this application may be cross-combined with the relevant technical features of the various embodiments to flexibly construct new embodiments, as long as such combination does not deviate from the creative spirit of this application and can meet the needs of the prior art or resolve certain deficiencies in the prior art. Those skilled in the art should be aware of such flexibility.

[0059] See also Figure 1 In one embodiment, the virtual prototype platform branch prediction method of the present application includes:

[0060] Step S10: responding to the branch prediction instruction of the virtual prototype platform, triggering the instruction simulator in the CPU core structure to send the memory address corresponding to the current branch instruction to the preset branch prediction model during the decoding stage;

[0061] The virtual prototype platform branch prediction model architecture in the terminal device can respond to the virtual prototype platform branch prediction instruction, triggering the instruction simulator in the CPU core structure to send the memory address corresponding to the current branch instruction to the preset branch prediction model during the decoding stage; wherein, the basic network architecture of the branch prediction model is an improved TAGE-SC-L branch prediction model, and the improved TAGE-SC-L branch prediction model is constructed by a TAGE-SC-L branch predictor that introduces a scoring strategy and a perceptron.

[0062] Step S20: calling a preset scoring strategy, wherein the branch jump direction predictor in the branch prediction model predicts the jump direction of the current branch instruction according to the memory address corresponding to the current branch instruction, wherein the jump direction includes a first jump direction and a second jump direction, the first jump direction indicates that the current branch instruction is in a jump state, and the second jump direction indicates that the current branch instruction is in a non-jump state;

[0063] Step S30: If the current branch instruction is in a jump state, the branch jump address predictor in the branch prediction model uses a preset scoring strategy to predict a program counter address to be jumped corresponding to the current branch instruction based on the memory address corresponding to the current branch instruction;

[0064] Step S40: If the current branch instruction is in a non-jump state, the branch jump address predictor determines a program counter address of the next instruction of the current branch instruction according to the memory address corresponding to the current branch instruction;

[0065] Step S50: determining the actual jump result of the current branch instruction in the CPU core structure, and sending the actual jump result to the branch jump direction predictor in the branch prediction model to update the branch prediction model to complete the branch prediction of the virtual prototype platform.

[0066] In some embodiments, the main predictor includes a base table and multiple tag tables, wherein the base table is indexed by a program counter address, and the tag table indexes the prediction result by performing a hash operation on history information of a variable-length geometric history length and the program counter address. If no tag table hits, the prediction result of the base table is selected; otherwise, the prediction result of the tag table with the longest history length is selected from all the hit tag tables as the final prediction direction.

[0067] In some embodiments, in the decoding stage, the get_prediction() function in the branch jump direction predictor in the branch prediction model is called to predict the jump direction of the current branch instruction based on the memory address corresponding to the current branch instruction; in the execution stage, the preset update_predictor() function is called to send the actual jump result to the branch jump direction predictor in the branch prediction model.

[0068] Specifically, see Figure 2 , Figure 2 This is an exemplary architecture of an improved branch prediction model based on a virtual prototype platform in an embodiment of the present application. The virtual prototype platform branch prediction method of the present application can be implemented based on the improved branch prediction model architecture of the virtual prototype platform. The virtual prototype platform branch prediction model architecture includes a CPU core structure and a branch prediction model structure, wherein: Figure 2 The left side shows the CPU core structure, which is implemented through the instruction simulator (ISS). The CPU core can be configured with the RV32IM instruction set or the RV64IM instruction set, including a four-stage pipeline: instruction fetch (IF), decode (ID), execute (EX) and write back (WB). Figure 2 The right side is the branch prediction model structure. The CPU core structure is interconnected with the CPU core through its operating logic in the pipeline. It includes a branch jump direction predictor and a branch jump address predictor (BTB).

[0069] The operating principle of the improved branch prediction model architecture based on the virtual prototype platform of this application is as follows:

[0070] The improved TAGE-SC-L branch prediction model of this application is integrated into the pipeline model of the CPU core architecture. During the decode (ID) phase, the branch instruction and PC address are identified. The branch instruction is passed to the execute (EX) phase for computation, and the PC address is passed to the branch prediction model. The get_prediction() function in the branch prediction model receives the PC address and determines whether the instruction should jump. The branch prediction state table is used to store prediction information.

[0071] The branch jump address predictor (BTB is used to predict the jump target address of the branch instruction. It outputs the program counter address (PC address) to be jumped. Jump_PC_addr represents the program counter address to be jumped and the program counter address (PC address) of the next instruction of the current branch instruction. Branch PC addr+4 represents the program counter address of the next instruction of the current branch instruction.

[0072] For each branch instruction, the branch prediction model predicts two directions (PredDir): jump or no jump. If the jump is taken, the program counter address to jump to (Jump_PC_addr) is sent to the instruction fetch (IF) stage. Otherwise, the program counter address of the next instruction (Branch PC addr+4) is sent to the instruction fetch (IF) stage. In the instruction simulator (ISS), execution of the branch instruction is not interrupted. During the execute (EX) stage, the actual jump result (Actual_result) is sent to the update_predictor() function to update the branch predictor state.

[0073] In some embodiments, the present application uses a higher-level abstraction hardware description language SystemC to design a high-accuracy branch prediction model, and uses a scoring strategy to design an improved TAGE-SC-L branch prediction model with higher accuracy than the original TAGE-SC-L branch prediction model, which is named TAGE-SC-LS branch prediction model, where TAGE is the main predictor, SC represents the statistical correction predictor, L represents the loop predictor, and S represents the scoring strategy.

[0074] See also Figure 3 , Figure 3 As an exemplary structure of the master predictor (TAGE), the master predictor (TAGE) can capture a wide range of dynamic branch patterns in branch prediction. The master predictor (TAGE) consists of a base table (Base) and multiple tag tables. The base table is indexed by the PC value, and the tag table uses a hash operation of history information of variable geometric history length and PC value to index the prediction result. If there is no tag table hit, the prediction result of the Base table is selected; otherwise, the prediction result of the tag table with the longest history length is selected from all the hit tag tables as the final prediction direction. Although the master predictor (TAGE) can capture many branch patterns and has strong adaptability, the master predictor (TAGE) is not effective when processing some irregular loop bodies. The loop predictor provides a solution. When a loop body with a fixed number of iterations is detected and the confidence exceeds the threshold, the prediction result of the loop predictor will be selected as the final output. In addition, for branch patterns with statistical regularities, the performance of the main predictor (TAGE) and the loop predictor (L) is poor. The statistical correction predictor can solve this problem. It can invert the prediction result of the main predictor (TAGE) as the final output result when the confidence of the main predictor (TAGE) is low.

[0075] See also Figure 4 , Figure 4The exemplary structure of the original TAGE-SC-L branch prediction model is shown. Generally speaking, the selection priority of the prediction results of the three branch predictors in the TAGE-SC-L branch predictor, namely the main predictor (TAGE), the statistical correction predictor (SC) and the loop predictor (L), is loop predictor (L), statistical correction predictor (SC), and main predictor (TAGE). The higher priority loop predictor (L) sometimes overrides the result of the SC predictor.

[0076] In order to give full play to the potential of the statistically corrected predictor (SC), the improved TAGE-SC-L branch prediction model of this application introduces a scoring strategy. The pseudo code of the scoring strategy is as follows:

[0077]

[0078] From the pseudo code of the above scoring strategy, it can be seen that Score_TAGE represents the first prediction score corresponding to the main predictor, Score_SC represents the second prediction score corresponding to the statistical correction predictor, Score_loop represents the third prediction score corresponding to the loop predictor, Pred_TAGE represents the first prediction result corresponding to the main predictor, Pred_SC represents the second prediction result corresponding to the statistical correction predictor, Pred_LP represents the third prediction result corresponding to the loop predictor, Actual_result represents the actual execution result of the branch instruction, PredDir_Select represents the best branch predictor result selected based on the score strategy, PredDir represents the final selected branch prediction result, use_sc represents the first conditional flag corresponding to the statistical correction predictor, and use_loop represents the second conditional flag corresponding to the loop predictor.

[0079] From the pseudo code of the above scoring strategy, we can see that the scoring strategy of this application adopts the following mechanism:

[0080] The main predictor (TAGE), statistical correction predictor (SC) and loop predictor (L) are respectively assigned a scoring parameter, which includes Score_TAGE, Score_SC and Score_loop, where Score_TAGE represents the first prediction score corresponding to the main predictor, Score_SC represents the second prediction score corresponding to the statistical correction predictor, and Score_loop represents the third prediction score corresponding to the loop predictor. If the jump direction predicted by each of them is the same as the actual jump direction, the corresponding score is increased by one, otherwise it is reduced by one. When it is set to 0, the prediction results of the main predictor (TAGE) and the loop predictor (L) are selected according to the original logic in the original TAGE-SC-L branch prediction model; when SC is valid, the present application applies a scoring strategy to the original TAGE-SC-L predictor and selects the jump direction of the predictor with the highest score as the final prediction result.

[0081] In a specific embodiment, after the step of triggering the instruction simulator in the CPU core structure to send the memory address corresponding to the current branch instruction to the preset branch prediction model, the method includes:

[0082] Step S201: calling a preset scoring strategy to initialize initial scoring variables corresponding to the main predictor, the statistical correction predictor, and the cyclic predictor;

[0083] Step S202: If the prediction result corresponding to any branch predictor matches its corresponding actual result, its corresponding prediction score is increased by 1; if the prediction result of any branch predictor does not match its actual result, its corresponding prediction score is set to 0;

[0084] Step S203: Compare the first prediction score corresponding to the main predictor, the second prediction score corresponding to the statistical correction predictor, and the third prediction score corresponding to the loop predictor. If the third prediction score corresponding to the loop predictor is greater than the first prediction score corresponding to the main predictor and the second prediction score corresponding to the statistical correction predictor, use the third prediction result corresponding to the loop predictor as the final prediction result.

[0085] After comparing the first prediction score corresponding to the main predictor, the second prediction score corresponding to the statistically corrected predictor, and the third prediction score corresponding to the loop predictor, and if the third prediction score corresponding to the loop predictor is greater than the first prediction score corresponding to the main predictor and the second prediction score corresponding to the statistically corrected predictor, taking the third prediction result corresponding to the loop predictor as the final prediction result, the method further includes:

[0086] Step S2001: If the second prediction score corresponding to the statistically corrected predictor is greater than the first prediction score corresponding to the main predictor, the second prediction result corresponding to the statistically corrected predictor is used as the final prediction result; otherwise, the first prediction result corresponding to the main predictor is selected as the final prediction result;

[0087] Step S2002: If the first condition flag corresponding to the statistical correction predictor is not equal to 1, the determination includes: if the second condition flag corresponding to the loop predictor is equal to 1, selecting the third prediction result corresponding to the loop predictor as the final prediction result; otherwise, selecting the first prediction result corresponding to the main predictor as the final prediction result;

[0088] Step S2003: If the first condition flag corresponding to the statistical correction predictor is equal to 1, directly selecting the optimal branch predictor selected based on the preset scoring strategy;

[0089] Step S2004: Execute the above steps in a loop and return the prediction result of the branch predictor finally selected.

[0090] In a further embodiment, since the TAGE-SC-LS branch prediction model of the present application has a low prediction accuracy in scenarios of long dependencies and nonlinear recognition, and the perceptron (P) is considered to be an effective method to improve the prediction accuracy, the perceptron (P) uses a perceptron for branch prediction, which is represented by a weight vector, which indicates the correlation between different branches. In order to provide coverage of more diverse program behaviors, we combine TAGE-SC-LS with the perceptron (P) through a scoring strategy to obtain a more optimized branch prediction model TAGE-SC-LSP, which is the final improved TAGE-SC-L branch prediction model of the present application, and it further improves the accuracy of branch prediction.

[0091] As can be seen from the above embodiments, compared with the prior art, the present application addresses the problem that the TAGE-SC-L branch prediction model in the prior art has not yet been fully functionally verified on the virtual prototype (VP) platform at the electronic system level (ESL). To address this problem, the present applicant has made corresponding explorations. The present application includes but is not limited to the following beneficial effects:

[0092] First, this application defines an improved branch prediction model based on a virtual prototype platform architecture, which has more comprehensive functional verification. This technology introduces a branch prediction model based on a virtual prototype, which can more comprehensively test and evaluate the functions of the branch prediction algorithm through simulation and verification during the design phase. The virtual prototype can provide more verification and optimization opportunities for various branch prediction scenarios, thereby ensuring that the final prediction model is more accurate and reliable.

[0093] Secondly, this application uses the higher-level hardware description language SystemC to design the branch prediction algorithm module, which results in faster simulation speed. Using a higher-level hardware description language for design makes the simulation of the branch prediction algorithm module more efficient. The SystemC language supports hardware-level parallelization and abstract modeling. Compared with traditional low-level languages, it can simulate faster, reduce design and verification cycles, and improve development efficiency.

[0094] Third, this application adopts a new scoring strategy to design the TAGE-SC-LS model, which has higher prediction accuracy. By introducing a new scoring strategy to design the TAGE-SC-LS model, the accuracy of branch prediction is significantly improved. The scoring strategy can allocate scores to different historical patterns, making the TAGE model more accurate in capturing complex branch patterns.

[0095] Fourthly, this application integrates the perceptron with the TAGE-SC-L branch predictor using a scoring strategy to design the TAGE-SC-LP model, which achieves higher prediction coverage. By integrating the scoring strategy with the perceptron, the design of the TAGE-SC-LP model is further optimized, improving branch prediction coverage. The perceptron is a machine learning-based algorithm that can dynamically adjust its prediction strategy, allowing the model to cover a wider variety of branch patterns and enhancing its adaptability and generalization capabilities.

[0096] See also Figure 5A virtual prototype platform branch prediction device is provided to meet one of the purposes of the present application, including a memory address sending module 1100, a jump direction prediction module 1200, a to-be-jumped address prediction module 1300, a program counter address determination module 1400, and a branch prediction model update module 1500. The memory address sending module 1100 is configured to respond to a virtual prototype platform branch prediction instruction, triggering the instruction simulator in the CPU core structure to send the memory address corresponding to the current branch instruction to a preset branch prediction model during the decoding stage; the jump direction prediction module 1200 is configured to call a preset scoring strategy, and the branch jump direction predictor in the branch prediction model predicts the jump direction of the current branch instruction based on the memory address corresponding to the current branch instruction, wherein the jump direction includes a first jump direction and a second jump direction, the first jump direction indicating that the current branch instruction is in a jump state, and the second jump direction indicating that the current branch instruction is in a non-jump state; the to-be-jumped address prediction module 1300 is configured to, if the current branch instruction is in a jump state, The branch jump address predictor in the branch prediction model adopts a preset scoring strategy to predict the program counter address to be jumped corresponding to the current branch instruction based on the memory address corresponding to the current branch instruction; the program counter address determination module 1400 is configured so that if the current branch instruction is in a non-jump state, the branch jump address predictor determines the program counter address of the next instruction of the current branch instruction based on the memory address corresponding to the current branch instruction; the branch prediction model update module 1500 is configured to determine the actual jump result of the current branch instruction in the CPU core structure, and send the actual jump result to the branch jump direction predictor in the branch prediction model to update the branch prediction model to complete the branch prediction of the virtual prototype platform.

[0097] Based on any embodiment of this application, please refer to Figure 6 Another embodiment of the present application further provides an electronic device, which can be implemented by a computer device, such as Figure 6As shown, a schematic diagram of the internal structure of a computer device. The computer device includes a processor, a computer-readable storage medium, a memory, and a network interface connected via a system bus. Among them, the computer-readable storage medium of the computer device stores an operating system, a database, and computer-readable instructions, and the database may store a control information sequence, and when the computer-readable instructions are executed by the processor, the processor may implement a virtual prototype platform branch prediction method. The processor of the computer device is used to provide computing and control capabilities to support the operation of the entire computer device. The memory of the computer device may store computer-readable instructions, and when the computer-readable instructions are executed by the processor, the processor may execute the virtual prototype platform branch prediction method of the present application. The network interface of the computer device is used to connect and communicate with a terminal. Those skilled in the art will understand that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0098] In this embodiment, the processor is used to execute Figure 5 The memory stores the program code and various data required to execute the specific functions of each module in the virtual prototype platform branch prediction device. The network interface is used to transmit data between user terminals or servers. The memory in this embodiment stores the program code and data required to execute all modules in the virtual prototype platform branch prediction device of this application. The server can call the server's program code and data to execute the functions of all modules.

[0099] The present application also provides a storage medium storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors execute the steps of the virtual prototype platform branch prediction method described in any embodiment of the present application.

[0100] The present application also provides a computer program product, including a computer program / instruction, which, when executed by one or more processors, implements the steps of the virtual prototype platform branch prediction method described in any embodiment of the present application.

[0101] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments of the present application can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above-mentioned embodiments of the method. The aforementioned storage medium can be a computer-readable storage medium such as a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0102] The above description is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A virtual prototype platform branch prediction method, characterized in that: include: In response to a branch prediction instruction of the virtual prototype platform, the instruction simulator in the CPU core structure is triggered to send the memory address corresponding to the current branch instruction to a preset branch prediction model during the decoding stage, wherein the basic network architecture of the branch prediction model is an improved TAGE-SC-L branch prediction model, and the improved TAGE-SC-L branch prediction model is constructed by a TAGE-SC-L branch predictor that introduces a scoring strategy and a perceptron, and the TAGE-SC-L branch predictor includes a main predictor, a statistical correction predictor, and a loop predictor; the perceptron uses a perceptron for branch prediction, and the perceptron is represented by a weight vector, and the weight vector indicates the correlation between different branches; calling a preset scoring strategy so that a branch jump direction predictor in the branch prediction model predicts a jump direction of the current branch instruction based on a memory address corresponding to the current branch instruction, wherein the jump direction includes a first jump direction and a second jump direction, the first jump direction indicating that the current branch instruction is in a jump state, and the second jump direction indicating that the current branch instruction is in a non-jump state, wherein the preset scoring strategy includes initializing initial score variables corresponding to the main predictor, the statistical correction predictor, and the loop predictor; if a prediction result corresponding to any branch predictor matches its corresponding actual result, then increasing its corresponding prediction score by 1; if a prediction result of any branch predictor does not match its actual result, then setting its corresponding prediction score to 0; comparing the first prediction score corresponding to the main predictor, the second prediction score corresponding to the statistical correction predictor, and the third prediction score corresponding to the loop predictor; and if the third prediction score corresponding to the loop predictor is greater than the first prediction score corresponding to the main predictor and the second prediction score corresponding to the statistical correction predictor, then using the third prediction result corresponding to the loop predictor as the final prediction result; If the current branch instruction is in a jump state, the branch jump address predictor in the branch prediction model uses a preset scoring strategy to predict the address of the program counter to be jumped corresponding to the current branch instruction according to the memory address corresponding to the current branch instruction; If the current branch instruction is in a non-jump state, the branch jump address predictor determines the program counter address of the next instruction of the current branch instruction according to the memory address corresponding to the current branch instruction; An actual jump result of the current branch instruction is determined in the CPU core structure, and the actual jump result is sent to a branch jump direction predictor in the branch prediction model to update the branch prediction model to complete branch prediction of the virtual prototype platform.

2. The virtual prototype platform branch prediction method according to claim 1, characterized in that: The master predictor includes a base table and multiple tag tables, wherein the base table is indexed by a program counter address, and the tag table is indexed by hashing history information of variable geometric history length and the program counter address to obtain a prediction result. If no tag table hits, the prediction result of the base table is selected. Otherwise, the prediction result of the tag table with the longest history length is selected from all the hit tag tables as the final prediction direction.

3. The virtual prototype platform branch prediction method according to claim 1, characterized in that: The CPU core structure includes a four-stage pipeline of instruction fetch, decoding, execution and write-back.

4. The virtual prototype platform branch prediction method according to any one of claims 1 to 3, characterized in that: In the decoding stage, the get_prediction() function in the branch jump direction predictor in the branch prediction model is called to predict the jump direction of the current branch instruction according to the memory address corresponding to the current branch instruction; During the execution phase, the preset update_predictor() function is called to send the actual jump result to the branch jump direction predictor in the branch prediction model.

5. A virtual prototype platform branch prediction device, characterized in that: include: a memory address sending module configured to respond to a branch prediction instruction of the virtual prototype platform and trigger an instruction simulator in the CPU core structure to send a memory address corresponding to the current branch instruction to a preset branch prediction model during a decoding phase, wherein the basic network architecture of the branch prediction model is an improved TAGE-SC-L branch prediction model, the improved TAGE-SC-L branch prediction model being constructed by a TAGE-SC-L branch predictor that introduces a scoring strategy and a perceptron, the TAGE-SC-L branch predictor including a main predictor, a statistically corrected predictor, and a loop predictor; the perceptron using a perceptron for branch prediction, the perceptron being represented by a weight vector that indicates the correlation between different branches; a jump direction prediction module configured to invoke a preset scoring strategy so that a branch jump direction predictor in the branch prediction model predicts a jump direction of the current branch instruction based on a memory address corresponding to the current branch instruction, wherein the jump direction includes a first jump direction and a second jump direction, the first jump direction indicating that the current branch instruction is in a jump state, and the second jump direction indicating that the current branch instruction is in a non-jump state, wherein the preset scoring strategy is to initialize initial score variables corresponding to the main predictor, the statistical correction predictor, and the loop predictor; if a prediction result corresponding to any branch predictor matches its corresponding actual result, then the corresponding prediction score is increased by 1; if a prediction result of any branch predictor does not match its actual result, then the corresponding prediction score is set to 0; compare the first prediction score corresponding to the main predictor, the second prediction score corresponding to the statistical correction predictor, and the third prediction score corresponding to the loop predictor; and if the third prediction score corresponding to the loop predictor is greater than the first prediction score corresponding to the main predictor and the second prediction score corresponding to the statistical correction predictor, then use the third prediction result corresponding to the loop predictor as the final prediction result; The to-be-jumped address prediction module is configured to, if the current branch instruction is in a jump state, use a preset scoring strategy by the branch jump address predictor in the branch prediction model to predict the to-be-jumped program counter address corresponding to the current branch instruction based on the memory address corresponding to the current branch instruction; a program counter address determination module configured to, if the current branch instruction is in a non-jump state, determine the program counter address of the next instruction of the current branch instruction based on the memory address corresponding to the current branch instruction by the branch jump address predictor; A branch prediction model update module is configured to determine an actual jump result of the current branch instruction in the CPU core structure, and send the actual jump result to a branch jump direction predictor in the branch prediction model to update the branch prediction model to complete the branch prediction of the virtual prototype platform.

6. An electronic device comprising a central processing unit and a memory, characterized in that: The central processing unit is configured to call and run a computer program stored in the memory to execute the steps of the method according to any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that It stores a computer program implemented according to the method described in any one of claims 1 to 4 in the form of computer-readable instructions, and when the computer program is called and executed by a computer, the steps included in the corresponding method are executed.

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