Storage block protection

Abstract

Systems, devices, and methods related to memory bank protection are described. A number of errors within a single bank may be determined and the determined number may be used to further determine whether to access other banks to correct the determined number. The bank protection described herein may prevent a single bank of a memory die from becoming a single point of fault (SPOT).

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with an application date of May 18, 2022, application number 202280033754.X, and invention name “Memory Body Protection”. Technical Field

[0003] The present disclosure relates generally to semiconductor memories and methods, and more particularly to apparatus, systems, and methods for memory bank protection. Background Art

[0004] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), etc. Non-volatile memory can provide persistent data by saving stored data when power is not supplied and can include NAND flash memory, NOR flash memory, and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0005] The memory device may be coupled to a host (e.g., a host computing device) to store data, commands, and / or instructions for use by the host when the computer or electronic system is operating. For example, during operation of a computing or other electronic system, data, commands, and / or instructions may be transferred between the host and the memory device. Summary of the invention

[0006] One aspect of the present application relates to an apparatus comprising: a first group of memory bodies of a memory device, the first group of memory bodies comprising: a first portion configured to store host data; and a second portion configured to store error detection data indicating a number of errors in corresponding ones of the first group of memory bodies and exceeding a threshold number; and a second group of memory bodies of the memory device, the second group of memory bodies configured to store error correction data to correct a number of errors in corresponding ones of the first group of memory bodies and exceeding the threshold number.

[0007] Another aspect of the present application relates to a device comprising: a group of storage bodies configured to store data corresponding to a first stripe, wherein the first stripe further comprises: a first portion of the group of storage bodies configured to store first host data; and a second portion of the group of storage bodies configured to store first error correction data to correct the number of errors in the first host data; and the group of storage bodies further configured to store data corresponding to a second stripe, wherein the second stripe further comprises: a third portion of the group of storage bodies configured to store second host data; and a fourth portion of the group of storage bodies configured to store second error correction data.

[0008] Another aspect of the present application relates to a method, comprising: performing an error detection operation on first host data retrieved from a first storage body in a group of storage bodies using first error detection data; and in response to the error detection operation indicating a number of errors within the first host data that exceeds a threshold number, performing an error correction operation using the following data: first error correction data for correcting the number of errors that exceeds the threshold number; and second host data retrieved from one or more storage bodies in the group of storage bodies that are different from the first storage body. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of an apparatus in the form of a computing system including a host and a memory device according to several embodiments of the present disclosure.

[0010] Figure 2 An example memory die including a memory bank configured for storing error correction / detection data is illustrated in accordance with several embodiments of the present disclosure.

[0011] Figure 3 Examples illustrating how error correction / detection data may be spread among memory banks in accordance with several embodiments of the present disclosure.

[0012] Figure 4 Examples illustrating how error correction / detection data may be spread among memory banks in accordance with several embodiments of the present disclosure.

[0013] Figure 5 An example bank protection scheme is described in which error correction / detection data spans multiple memory dies in accordance with several embodiments of the present disclosure.

[0014] Figure 6 is a flow chart representing an example method for memory bank protection according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] Systems, devices, and methods related to storage body protection are described. Data protection and recovery schemes are often an important aspect of RAS (reliability, availability, and serviceability) associated with memory systems. Such schemes can provide a "chip-killing" capability, where the memory system can operate normally even if a constituent chip (e.g., a memory die) is damaged; thereby avoiding a situation where one of the chips becomes a single point of failure (SPOF) for the memory system. Typically, the chip-killing capability is provided by a "redundant array of independent disks (RAID)" scheme, which allows data recovery of a damaged chip by reading all constituent chips of the memory system.

[0016] This RAID scheme provides a chip-hunting capability, however, it may introduce unnecessary delays when implemented in a memory system where failures frequently occur in specific memory locations at a granularity smaller than the die level. For example, a memory die (e.g., a DRAM die) that includes multiple banks of memory cells typically experiences a failure in a single constituent bank. Therefore, a chip-hunting capability that prevents a single memory die from becoming a SPOF treats the failure of a single bank as a failure of the die, which will trigger a read of multiple dies each time a single bank fails.

[0017] In contrast, the embodiments described herein are directed to providing a storage body protection scheme that avoids each constituent storage body from becoming a SPOF of a memory die. Therefore, the storage body protection scheme provided by the embodiments of the present disclosure avoids instances in which data recovery of a failed storage body requires reading all memory dies of a memory system unless a particular die is completely damaged (e.g., non-functional), which will improve the overall performance of the memory system. Compared to previous RAS schemes, various embodiments of the present disclosure can provide benefits such as reduced overhead because a single storage body can be used for parity data (e.g., RAID parity) rather than, for example, an entire die in some previous "chip hunting" methods. Moreover, in some embodiments, the parity stripe used to protect the storage body is within a single die; therefore, operations related to the parity scheme (e.g., reading, writing, and recovery in a failure situation) involve a single die on a single channel, which can provide simpler management than a RAID recovery scheme that operates across multiple dies and / or channels. Moreover, because various embodiments involve a single die, a storage body recovery mechanism (e.g., CRC+RAID) can be implemented on the die rather than via a controller outside the die.

[0018] In the following detailed description of the present disclosure, reference is made to the accompanying drawings, which form a part of the present disclosure and in which are shown by way of illustration how one or more embodiments of the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present disclosure, and it is to be understood that other embodiments may be utilized and process, electrical and structural changes may be made without departing from the scope of the present disclosure.

[0019] As used herein, designators such as "N," "M," and the like, particularly with respect to element numbers in the drawings, indicate that a number of the designated particular feature may be included. It should also be understood that the terminology used herein is only used to describe specific embodiments and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" may include both singular and plural referents unless the context clearly indicates otherwise. Additionally, "several," "at least one," and "one or more" (e.g., several memory banks) may refer to one or more memory banks, while "a plurality" is intended to refer to more than one such thing.

[0020] In addition, the word "may" is used throughout this application to mean permission (e.g., possibility, ability) rather than mandatory (e.g., must). The term "include" and its derivatives mean "include (but not limited to)". As the context requires, the terms "coupled" and "coupled" mean physically connected directly or indirectly or used to access and move (transmit) commands and / or data.

[0021] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, 221 may refer to Figure 2 Element "21" in , and similar elements in Figure 3 321. A group or more similar elements or components may be collectively referred to herein by a single element symbol. For example, multiple reference elements 221-1 to 221-M may be collectively referred to as 221. It should be understood that the elements shown in various embodiments herein may be added, exchanged and / or eliminated to provide several additional embodiments of the present disclosure. In addition, the proportions and / or relative scales of the elements provided in the figures are intended to illustrate certain embodiments of the present disclosure and should not be considered as intended to be limiting.

[0022] Figure 1 is a block diagram of an apparatus in the form of a computing system 100 including a system controller 110 and a memory device 120 according to several embodiments of the present disclosure. As used herein, the memory device 120, the control circuitry 140, the memory banks 121-1, 121-2, ..., 121-N, and / or the memory array 130 may also be individually considered as a "device".

[0023] The system controller 110 is coupled (e.g., connected) to the memory device 120. The system controller 110 may be an external controller, such as a memory controller of a memory subsystem, such as, for example, a dual in-line memory module (DIMM) or a solid state drive (SSD). In embodiments where the system controller 110 is a memory controller of a memory subsystem, the memory controller 110 may be coupled to one or more processors, such as a CPU.

[0024] System controller 110 may include logic circuitry (e.g., logic 160) that may be used to generate ECC data based on data received from a host. Logic circuitry 160 may operate based on various types of error correction / detection data, such as Hamming codes, Reed-Solomon (RS) codes, Bose-Chaudhuri-Hokwenheim (BCH) codes, cyclic redundancy check (CRC) codes, Gray codes, Reed-Muller codes, Gopal codes, and Denniston codes, among others. The error correction / detection data generated using error correction / detection component 105 may be written to multiple dies (e.g., memory die 120), such as in conjunction with Figure 5 Further description / clarification.

[0025] In various embodiments, the system controller 110 may be further coupled to a host system ( Figure 1 The system 100 may include a single integrated circuit or a host, and the system controller 110 and the memory device 120 may be on the same integrated circuit. The system 100 may be, for example, a server system and / or a high performance computing (HPC) system and / or a portion thereof.

[0026] Memory device 120 (eg, memory die) may include a number of memory banks 121-1, 121-2, ..., 121-N (eg, collectively referred to as memory bank 121), which may include memory array 130 (including multiple rows and columns of memory cells) and sensing circuitry 150. Although Figure 1 1 shows a single memory device 120, the system controller 110 may be coupled to multiple memory devices (eg, dies) 120 via multiple channels. Figure 1 1, but each of the memory banks 121 may include control circuitry (e.g., a memory bank processor) to control and / or orchestrate the execution of memory operations in response to instructions received from the control circuitry 140. In some embodiments, each of the memory banks 121 may be individually addressable, for example, by the control circuitry 140.

[0027] For clarity, system 100 has been simplified to focus on features that are particularly relevant to the present disclosure. Memory array 130 may be a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a NAND flash array, and / or a NOR flash array, among other types of arrays. Array 130 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as data lines or digit lines).

[0028] like Figure 1 , memory device 120 may include address circuitry 142 to latch address signals provided by I / O circuitry 144 via a combined data / address bus 156, such as an external I / O bus connected to system controller 110. I / O circuitry 144 may include an internal I / O bus. For example, the internal I / O bus may transfer data between memory banks and I / O pins, such as DRAM DQs.

[0029] Memory device 120 may include address circuitry 142 to latch address signals for data provided by I / O circuitry 144 via input / output "I / O" circuitry 156 (e.g., data bus and / or address bus) (e.g., provided to external ALU circuitry and DRAM DQ via local I / O lines and global I / O lines). Address signals are received by address circuitry 142 and decoded by row decoder 146 and column decoder 152 to access memory array 130. Data may be read from memory array 130 by sensing voltage and / or current changes on sense lines (digit lines) using sense circuitry 150. Sense circuitry 150 may read and latch a page (e.g., row) of data from memory array 130. I / O circuitry 144 may be used for bidirectional data communication with system controller 110 via data bus 156 (e.g., 64-bit wide data bus). Write circuitry 148 may be used to write data to memory array 130.

[0030] The control circuitry 140 (e.g., bank control logic and sequencer) may decode signals (e.g., commands) provided by the control bus 154 from the system controller 110. These signals may include chip enable signals, write enable signals, and / or address latch signals, which may be used to control operations performed on the memory array 130, including data sensing, data storage, data movement (e.g., copying, transferring, and / or transmitting data values), data writing, and / or data erasing operations, among other operations. In various embodiments, the control circuitry 140 may be responsible for executing instructions from the system controller 110 and accessing the memory array 130. The control circuitry 140 may be a state machine, a sequencer, or some other type of controller.

[0031] The control circuit system 140 may further include an error correction / detection component 105 and utilize the error correction / detection component 105 to generate ECC data based on data received from the host and / or system controller 110. The error correction / detection component 105 may operate based on various types of error correction / detection data, such as Hamming codes, Reed-Solomon (RS) codes, Bose-Chaudhuri-Hokwenheim (BCH) codes, cyclic redundancy check (CRC) codes, Gray codes, Reed-Muller codes, Gopal codes, and Denniston codes, among others. The error correction / detection data generated using the error correction / detection component 105 may be written to the memory bank 121 in various ways, such as in combination with Figures 2 to 6 Further description / clarification.

[0032] The error correction / detection component 105 of the control circuit system 140 may be configured to perform error correction / detection operations using error correction / detection data stored in the memory array 130. The error correction / detection operations performed by using the error correction / detection component 105 may provide multiple levels of error correction / detection capabilities for errors within the memory array 130. For example, a first level (of multiple levels) of error correction / detection capabilities may be provided using error correction data stored in one memory bank (e.g., memory bank 121) to correct a number of errors that equals or does not exceed a threshold number and using error detection data stored in the same memory bank to indicate whether there are still errors remaining in the same memory bank even after a previously performed error correction operation (e.g., a first error correction operation). If it is indicated that there are still errors even after a previously performed error correction operation, then a second level (of multiple levels) of error correction / detection capabilities may be provided. The second level of error correction / detection capabilities may be provided by performing another error correction operation (e.g., a second error correction operation) using error correction data stored in a dedicated memory bank and / or portion of a memory bank.

[0033] In some embodiments, the first error correction operation (e.g., performed to provide a first level of error correction capability) and the second error correction operation (e.g., performed to provide a second level of error correction capability) may be performed at different processing resources. For example, the first error correction operation may be performed at a corresponding memory bank processor, while the second error correction operation may be performed at a system processor / controller, such as control circuit system 140.

[0034] Figure 2 An example memory die 220 is illustrated including memory banks 221-1, ..., 221-M configured to store error correction / detection data according to several embodiments of the present disclosure. Memory bank 221 is similar to a memory bank 221 in conjunction with Figure 1 Memory banks 121 are illustrated / described. Memory banks 221 may be those memory banks coupled to the same channel and included within a single memory die, such as memory die 220. Memory die 220 may be a DRAM die and memory banks 221 may include DRAM cells.

[0035] The memory banks 221-1, ..., 221-(M-1) may be configured to store host data (e.g., Figure 1 , 221-(M-1)-1. In some embodiments, the corresponding portions 221-1-1, ..., 221-(M-1)-1 of the memory banks 221-1, ..., 221-(M-1) may further include error correction data for correcting a number of errors in the corresponding ones of the memory banks 221-1, ..., 221-(M-1) that is equal to or does not exceed a threshold number. For example, a number of errors in the memory bank 221-1 that is equal to or does not exceed a threshold number may be corrected using the error correction data stored in the portion 221-1-1.

[0036] The memory bank 221 may be configured to store error detection data in its respective portions 221-1-2, ..., 221-M-2. Although the embodiment is not limited thereto, the error detection data may be CRC data. The error detection data (e.g., CRC) may be used to indicate the number of errors exceeding a threshold number within a corresponding one of a page (e.g., a row of memory cells) of the memory bank 221. For example, an error detection operation performed using the error detection data stored in the portion 221-1-2 may indicate whether a page of the memory bank 221-1 still has errors even after an error correction operation performed using the error correction data stored in the portion 221-1-1. The error detection operation indicating that errors still exist within the memory bank 221-1 further indicates that the memory bank 221-1 initially contained a number of errors exceeding a threshold number within the memory bank 221-1.

[0037] The memory bank 221-M may be configured to store error correction data in its portion 221-M-1 for correcting a number of errors exceeding a threshold number that cannot be corrected using the error correction data stored in a corresponding one of the portions 221-1-1, ..., 221-(M-1)-1 (e.g., within a corresponding one of the memory banks 221-1, ..., 221-(M-1)). In some embodiments, the error correction data for correcting a number of errors exceeding the threshold number may be parity data (e.g., RAID parity).

[0038] Performing an error correction operation using error correction data (e.g., parity data) that may be stored in memory bank 221-M involves reading the error correction data from memory bank 221-M and other host data stored in memory banks 221-1, ..., 221-(M-1) (e.g., other than the host data stored in the particular memory bank indicated as having the number or errors). For example, if it is determined that the host data read from memory bank 221-1 (e.g., data stored in a page of the corresponding memory bank) still contains errors that cannot be corrected by an error correction operation performed using error correction data stored in portion 221-1-1 of memory bank 221-1, then the data stored in memory bank 221-1 may be recovered by reading the error correction data stored in memory bank 221-M and other corresponding host data from memory banks 221-2, ..., 221-(M-1). For example, an XOR of data read from "good" memory banks 221-2, ..., 221-(M-1) with error correction data read from memory bank 221-M may be used to correct (eg, recover) erroneous data read from memory bank 221-1.

[0039] Figure 2 Stripes 222 (e.g., parity stripes) spanning memory banks 221-1, ..., 221-M are described. For example, stripes 222 may include / correspond to data stored in one or more rows of memory cells in each of memory banks 221-1, ..., 221-M. One or more rows within each of the memory banks corresponding to the same stripe (e.g., stripe 222) may be referred to as "stripes." Error correction operations described herein (e.g., performed using parity data) may be performed in units of stripes (e.g., stripe 222). For example, error correction data stored in memory bank 221-M and corresponding to a particular stripe (e.g., stripe 222) corresponds to error correction data previously generated based on host data corresponding to the same stripe. Therefore, an error correction operation for correcting a number of errors exceeding a threshold number involves reading the error correction data of the stripe as well as the host data (good data) of the stripe. In some embodiments, a stripe may correspond to data in a single row (e.g., a single DRAM page) of memory cells in a corresponding one of the memory banks.

[0040] In some embodiments, the memory bank 221 may be a DRAM memory bank and include DRAM cells. In this example, compared to NAND whose erase operation is performed in units of blocks (and write operations are performed in units of pages), read and write operations can be performed on the memory bank 221 independently of the erase operation. For example, in a NAND memory device, a block typically stores data pages corresponding to multiple stripes. Therefore, even updating data corresponding to one of the stripes and stored in a single page of the block requires erasing all pages of the block, which will further require rewriting data corresponding to other stripes of the block. On the other hand, updating the host data (corresponding to one of the stripes of the stripe) according to a DRAM memory bank (such as the memory bank 221) does not require rewriting the host data corresponding to other stripes of the stripe and / or other stripes.

[0041] Assuming that memory die 220 includes 64 memory banks (e.g., memory bank 221), Figure 2 The example illustrated in may have a parity overhead of approximately 1.58% (1 / 63). For example, the ratio of the number of memory banks (e.g., memory bank 221-M) configured to store error correction data for correcting a number of errors exceeding a threshold number to the number of memory banks (e.g., 221-1, ..., 221-(M-1)) configured to store host data is 1 / 63.

[0042] In some embodiments, the error detection data may be stored in a single row (e.g., a single DRAM page) of memory cells (of the corresponding ones of the portions 221-1-2, ..., 221-M-2). In this example, the error detection data stored in the single row of memory cells (which may be the unit of a single read operation of the DRAM array) may be used to perform an error detection operation on data corresponding to any one of the multiple stripes (of the corresponding ones of the portions 221-1-1, ..., 221-M-1). Thus, compared to those methods in which the corresponding error correction / detection data of the multiple stripes is stored in a separate location (which requires performing multiple read operations to read the error correction / detection data from each of the locations), the error detection data may be stored in a single row of memory cells (e.g., a single DRAM page) of memory cells. In this example, the error detection data stored in the single row of memory cells (which may be the unit of a single read operation of the DRAM array) may be used to perform an error detection operation on data corresponding to any one of the multiple stripes (of the corresponding ones of the portions 221-1-1, ..., 221-M-1). Figure 2 (and combined Figures 3 to 6 ) The illustrated embodiment of reading data corresponding to multiple stripes from the same memory bank involves reading error detection data from the same memory bank no more than once (a single read operation may be performed to read error detection data for multiple read operations performed to read data corresponding to the multiple stripes).

[0043] Although embodiments are not limited in this regard, the threshold quantities described herein may correspond to a single error. Figure 2In the embodiment described in , the error correction data stored in portions 221-1-1, ..., 221-M-1 can correct a single error, and the error correction data stored in storage body 221-M can correct multiple errors (e.g., more than a single error) within one or more storage bodies 221-1, ..., 221-(M-1).

[0044] The operational roles of storage banks (e.g., storage bank 221) may be occasionally / periodically swapped to balance the number of accesses across the storage banks and to avoid "hot spots" and to prevent one storage bank from being accessed more frequently than other storage banks. For example, it has been previously described that storage banks 221-1, ..., 221-(M-1) are configured to store host data, while storage bank 221-M is configured to store error correction data (e.g., parity data). In order to avoid storage banks 221-1, ..., 221-(M-1) being accessed more frequently than storage bank 221-M (because host data is likely to be accessed more frequently than multi-channel error correction data), at some point, one of the storage banks 221-1, ..., 221-(M-1) may be reconfigured to store error correction data, while storage bank 221-M may be reconfigured to store host data.

[0045] In a non-limiting example, an example device (eg Figure 1 The computing system 100 or memory device 120 described in the specification may include a first group of memory banks (e.g., memory banks 221-1, ..., 221-(M-1)) of memory dies (e.g., memory die 220). The first group of memory banks may include a first portion (e.g., portion 221-1-1, ..., 221-(M-1)-1) configured for host data and a second portion (e.g., portion 221-1-2, ..., 221-M-2) configured for error detection data indicating a number of errors exceeding a threshold number in a corresponding one of the first group of memory banks. The device may further include a second group of memory banks (e.g., memory bank 221-M) of memory dies configured for error correction data to correct a number of errors exceeding a threshold number in a corresponding one of the first group of memory banks. In some embodiments, the error detection data includes cyclic redundancy check (CRC) data. In addition, the first group of memory banks and the second group of memory banks may include dynamic random access memory (DRAM) cells.

[0046] In some embodiments, a memory die may include a plurality of groups of stripes (e.g., stripe 222). Each of the plurality of groups of stripes may include a respective row group of memory cells from each of the first and second groups of memory banks. In this example, the apparatus may further include control circuitry (e.g., coupled to the first group of memory banks and the second group of memory banks of the memory die) Figure 1140 described in detail in the accompanying drawings). The control circuitry may be configured to read host data from a first portion of one of the memory banks of the first group and corresponding to one of the plurality of stripes and to perform an error detection operation on the read host data using error detection data stored in a second portion of one of the memory banks of the first group. The control circuitry may be further configured to perform an error correction operation using at least error correction data stored in a memory bank of the second group and corresponding to one of the plurality of stripes in response to the error detection operation indicating that a number of errors within one of the memory banks of the first group exceeds a threshold number.

[0047] Continuing with the above example, the control circuit system may be further configured to perform an error correction operation on one of the memory banks of the first group using error correction data stored in a first portion of one of the memory banks of the first group before performing an error detection operation on a portion of the host data using error detection data stored in one of the memory banks of the first group to correct a number of errors within one of the memory banks of the first group that is equal to or does not exceed a threshold number.

[0048] Figure 3 An example is illustrated of how error correction / detection data may be distributed among memory banks 321 - 1 , . . . , 321 - 8 according to several embodiments of the present disclosure. Figure 3 The memory bank 321 described in Figure 1 and 2 1 and 2. For example, memory bank 321 may be those memory banks coupled to the same channel and include DRAM cells. Figure 3 Although not illustrated in FIG. 1 , each memory bank 321 may further store error detection data (eg, CRC) to indicate that the number of errors exceeds a threshold number, such as a single error. Figure 3 Eight memory banks are illustrated, but embodiments are not limited to a particular number of memory banks that a single memory die may include.

[0049] like Figure 3 As described in the foregoing, the memory bank 321 can be further divided into zones. As used herein, the term "zone" refers to a group of rows of memory cells that span multiple memory banks. For example, Figure 3, the row groups of memory cells 325-1-1, ..., 325-8-1 from the memory banks 321-1, ..., 321-8 can be referred to as the zone 323-1; the row groups of memory cells 325-1-2, ..., 325-8-2 from the memory banks 321-1, ..., 321-8 can be referred to as the zone 323-2; the row groups of memory cells 325-1-3, ..., 325-8-3 from the memory banks 321-1, ..., 321-8 can be referred to as the zone 323-3; the row groups of memory cells 325-1-4, ..., 325-8-4 from the memory banks 321-1, ..., 321-8 can be referred to as the zone 323- 4; the row groups of memory cells 325-1-5, ..., 325-8-5 respectively from the storage bodies 321-1, ..., 321-8 may be referred to as zone 323-5; the row groups of memory cells 325-1-6, ..., 325-8-6 respectively from the storage bodies 321-1, ..., 321-8 may be referred to as zone 323-6; the row groups of memory cells 325-1-7, ..., 325-8-7 respectively from the storage bodies 321-1, ..., 321-8 may be referred to as zone 323-7; and the row groups of memory cells 325-1-8, ..., 325-8-8 respectively from the storage bodies 321-1, ..., 321-8 may be referred to as zone 323-8.

[0050] The error correction data for correcting the number of errors exceeding the threshold is evenly distributed across the memory banks 321, so that each zone 323 can store the error correction data in only one of the memory banks 321. Figure 3 It is illustrated that the region 323-1 stores the error correction data in the memory bank 321-8 (e.g., the row group of the memory cell 325-1-8); the region 323-2 stores the error correction data in the memory bank 321-7 (e.g., the row group of the memory cell 325-2-7); the region 323-3 stores the error correction data in the memory bank 321-6 (e.g., the row group of the memory cell 325-3-6); and the region 323-4 stores the error correction data in the memory bank 321-5 (e.g., the row group of the memory cell 325-4-5). Zone 323-5 stores error correction data in memory bank 321-4 (e.g., a row group of memory cell 325-5-4); zone 323-6 stores error correction data in memory bank 321-3 (e.g., a row group of memory cell 325-6-3); zone 323-7 stores error correction data in memory bank 321-2 (e.g., a row group of memory cell 325-7-2); and zone 323-8 stores error correction data in memory bank 321-1 (e.g., a row group of memory cell 325-8-1). Figure 2Compared to the example described in which error correction data is stored in only one of the memory banks 221 (e.g., memory bank 221-M), evenly distributing the error correction data across memory banks 321 can balance the number of accesses across memory banks 321 to avoid "hot spots" by preventing one memory bank from being accessed more frequently than other memory banks.

[0051] An error correction operation for correcting a number of errors exceeding a threshold number (e.g., a single error) may be performed in stripe units using error correction data (e.g., parity data) stored in one of the memory banks 321 of each zone 323, such as in combination with Figure 3 Description. For example, if it is determined that host data read from a row of memory cells of group 325-1-1 of memory bank 321-1 and corresponding to a particular stripe contains a number of errors exceeding a threshold number that cannot be corrected by an error correction operation previously performed to correct a number of errors equal to or not exceeding the threshold number, then the data may be recovered by reading the error correction data stored in a corresponding row of memory cell group 325-8-1 of memory bank 321-8 (corresponding to the same stripe as the row of memory cells of group 325-1-1) and other host data from a corresponding row of memory cells of each of memory cell row groups 325-2-1, ..., 325-7-1 of memory banks 321-2, ..., 321-7 (corresponding to the same stripe as the row of memory cells of memory cell row group 325-1-1). Although embodiments are not limited thereto, the threshold number described herein may correspond to a single error.

[0052] Also like combining Figure 2 In the description, the operational roles of a memory bank (e.g., memory bank 321) with respect to a zone (e.g., zone 323) may be occasionally / periodically swapped to balance the number of accesses across the memory banks and avoid "hot spots" and prevent one memory location (e.g., zone) from being accessed more frequently than other memory locations (e.g., zones). For example, one of the row groups of memory cells of a memory bank configured to store error correction data for a particular zone may be reconfigured to store host data, while a row group of memory cells of a different memory bank (which is configured to store host data) may be reconfigured to store error correction data for a particular zone (to correct a number of errors exceeding a threshold number).

[0053] Figure 4 An example is illustrated of how error correction / detection data may be spread among a bank 421 of a memory die 420 having error correction / detection data for a sub-region 427 in accordance with several embodiments of the present disclosure. Figure 4 The memory bank 421 and the area 423 described in Figure 2321 and region 323 are respectively illustrated in FIG. For example, memory bank 421 may be those memory banks coupled to the same channel and include DRAM cells. Although Figure 4 Although not illustrated in the figure, each memory bank 421 may further store error detection data (eg, CRC) for indicating the number of errors exceeding a threshold number (eg, a single error) within the corresponding memory bank 421. Figure 4 Eight banks and regions are illustrated, but embodiments are not limited to a particular number of banks / regions that a single memory die may include.

[0054] like Figure 4 As described in FIG. 4 , region 423 may be further divided into sub-regions. For example, Figure 4 It is explained that one or more rows of memory cells from each of the memory banks 421 and in the area 423-1 may constitute corresponding ones in the sub-areas 427-1-1, ..., 427-1-8; one or more rows of memory cells from each of the memory banks 421 and in the area 423-2 may constitute corresponding ones in the sub-areas 427-2-1, ..., 427-2-8; one or more rows of memory cells from each of the memory banks 421 and in the area 423-3 may constitute corresponding ones in the sub-areas 427-3-1, ..., 427-3-8; one or more rows of memory cells from each of the memory banks 421 and in the area 423-4 may constitute corresponding ones in the sub-areas 427-4-1, ..., 427-4-8. one or more rows of memory cells from each of the memory bodies 421 and within the zone 423-5 may constitute corresponding ones in the sub-zones 427-5-1, ..., 427-5-8; one or more rows of memory cells from each of the memory bodies 421 and within the zone 423-6 may constitute corresponding ones in the sub-zones 427-6-1, ..., 427-6-8; one or more rows of memory cells from each of the memory bodies 421 and within the zone 423-7 may constitute corresponding ones in the sub-zones 427-7-1, ..., 427-7-8; and one or more rows of memory cells from each of the memory bodies 421 and within the zone 423-8 may constitute corresponding ones in the sub-zones 427-8-1, ..., 427-8-8.

[0055] Error correction data (e.g., parity data) used to correct the number of errors exceeding a threshold may be evenly distributed across memory banks 421 and regions 423, such that each sub-region 427 may include error correction data from only one of memory banks 421. Figure 4It is illustrated that sub-area 427-1-1 stores error correction data in storage body 421-8; sub-area 427-1-2 stores error correction data in storage body 421-7; sub-area 427-1-3 stores error correction data in storage body 421-6; sub-area 427-1-4 stores error correction data in storage body 421-5; sub-area 427-1-5 stores error correction data in storage body 421-4; sub-area 427-1-6 stores error correction data in storage body 421-3; sub-area 427-1-7 stores error correction data in storage body 421-2; and sub-area 427-1-8 stores error correction data in storage body 421-1.

[0056] An error correction operation for correcting a number of errors exceeding a threshold number (e.g., a single error) may be performed in stripe units using error correction data (e.g., parity data) stored in one of the memory banks 421 of each sub-area 427, such as in combination with Figure 2 For example, if it is determined that host data read from a row of memory cells of sub-area 427-1-1 of memory bank 421-1 and corresponding to a particular stripe contains a number of errors exceeding a threshold number that cannot be corrected by an error correction operation previously performed to correct a number of errors equal to or not exceeding the threshold number, then data stored in a row of memory cells of a row group of memory cells 427-1-1 may be recovered by reading error correction data stored in a row of memory cells of sub-area 427-1-8 of memory bank 421-8 and corresponding rows of memory cells from each of sub-areas 427-1-2, ..., 427-1-7 of memory banks 421-2, ..., 421-7 and other host data corresponding to the same stripe. Although embodiments are not limited thereto, the threshold number described herein may correspond to a single error.

[0057] Also like combining Figure 2 and 3 In the description, the operational roles of memory banks (e.g., memory bank 421) with respect to a sub-region (e.g., sub-region 427) may be occasionally / periodically swapped to balance the number of accesses across the memory banks and avoid "hot spots" and prevent one memory location (e.g., a sub-region) from being accessed more frequently than other memory locations. For example, one of the row groups of memory cells of a memory bank configured to store error correction data for a particular sub-region may be reconfigured to store host data, while a row group of memory cells of a different memory bank (which is configured to store host data) may be reconfigured to store error correction data for the particular sub-region.

[0058] In a non-limiting example, an example system (eg Figure 1 The computing system 100 or memory device 120 described in the figure may include a memory die (eg, Figure 3and 4 A group of memory banks (e.g., memory die 320 / 420, respectively, as described in Figure 3 and 4 Each of the memory banks of the memory die may include a first portion configured to store error correction data for correcting a number of errors exceeding a threshold number within a respective memory bank and a second portion configured to store error detection data for indicating a number of errors exceeding a threshold number within a respective one of the groups of memory banks. The groups of memory banks may be coupled to the same channel.

[0059] In some embodiments, the memory die is a DRAM die. In this example, the second portion corresponds to a row of DRAM memory cells of a corresponding one of the memory bank groups. In some embodiments, each of the memory bank groups of the memory die may further include a third portion configured to store host data used to generate error correction data stored in the first portion of the memory bank group.

[0060] In some embodiments, the error correction data may include multiple portions of error correction data that are evenly distributed across groups of memory banks such that each of the multiple portions of error correction data is stored in a memory bank and row of memory cells of a different group of memory banks than other portions of the multiple portions of error correction data (e.g., row groups of memory cells 325-8-1, 325-7-2, 325-6-3, 325-5-4, 325-4-5, 325-3-6, 325-2-7, and 325-1-8). In some embodiments, the error correction data includes parity data.

[0061] In some embodiments, a memory die includes multiple groups of stripes (e.g. Figure 2 and 5 Each of the plurality of groups of stripes may include a respective row group of memory cells from each of the first and second groups of memory banks. Furthermore, the plurality of groups of stripes may store respective portions of the error correction data in locations corresponding to different memory banks of the first and second groups of memory banks.

[0062] In some embodiments, the system may further include control circuitry coupled to the memory bank groups (eg, Figure 1140 described in the accompanying drawings). The control circuit system may be configured to perform an error detection operation on one of the memory bank groups using error detection data stored in one of the memory bank groups to indicate that a number of errors in one of the memory bank groups exceeds a threshold number. The control circuit system may be further configured to perform a read operation on the memory bank group to retrieve error correction data stored in a first portion of each of the memory bank groups in response to the error detection operation indicating that the number of errors in one of the memory bank groups exceeds the threshold number. The control circuit system may be further configured to perform an error correction operation on the memory bank group to correct the number of errors in one of the memory bank groups exceeding the threshold number using the error correction data retrieved from the first portion of each of the memory bank groups.

[0063] Figure 5 An example memory bank protection scheme in which error correction / detection data spans multiple memory dies 520-1, ..., 520-P according to several embodiments of the present disclosure is described. The memory dies 520 are similar to the memory dies 520-1, ..., 520-P respectively. Figure 2 , 3 4. For example, each memory die 520 may be a DRAM die. The memory bank 521 may include DRAM cells. The memory die 520 may be coupled to different channels. In addition, the memory bank 521 is similar to the memory die 220, 320 and / or 420 respectively combined with the memory die 220, 320 and / or 420. For example, the memory die 520 may each be a DRAM die. The memory bank 521 may include DRAM cells. The memory die 520 may be coupled to different channels. In addition, the memory bank 521 is similar to the memory die 220, 320 and / or 420 respectively combined with the memory die 220, 320 and / or 420 Figure 2 , 3 4 and the memory banks 221, 321 and / or 421 described above. The memory bank 521 may include DRAM cells. Figure 5 The described error correction / detection operations may be performed by a system controller, for example in conjunction with Figure 1 The system controller 110 is illustrated.

[0064] The memory banks 521-1, ..., 521-Q of the memory dies 520-1, ..., 520-(P-1) and the memory banks 521-1, ..., 521-(Q-1) of the memory die 520-P can store host data (e.g., Figure 1) is stored in corresponding locations, for example, in corresponding portions 521-1-1, ..., 521-Q-1 of storage bodies 521-1, ..., 521-Q of memory die 520-1, ..., 520-(P-1) and / or in portions 521-1-1, ..., 521-(Q-1)-1 of storage bodies 521-1, ..., 521-(Q-1) of memory die 520-P. In some embodiments, corresponding portions 521-1-1, ..., 521-Q-1 of memory banks 521-1, ..., 521-Q of memory die 520-1, ..., 520-(P-1) and / or corresponding portions 521-1-1, ..., 521-(Q-1)-1 of memory banks 521-1, ..., 521-(Q-1) of memory die 520-P may further include error correction data for correcting a number of errors within corresponding ones of the memory banks 521 that is equal to or does not exceed a threshold number.

[0065] Each memory bank 521 may store error detection data in its corresponding portion 521-1-2, ..., 521-Q-2. Although the embodiment is not limited thereto, the error detection data may include CRC data. Error detection data (e.g., CRC) may be used to indicate that the number of errors in the corresponding one of the memory banks 521 exceeds a threshold number. For example, if the memory bank 521-1 of the memory die 520-1 still has errors even after an error correction operation performed using the error correction data stored in the portion 521-1-1 of the memory bank 521-1 of the memory die 520-1, then the error detection operation performed using the error detection data stored in the portion 521-1-2 of the memory die 520-1 may indicate that there are still errors in the memory bank 521-1 of the memory die 520-1. In some embodiments, each portion 521-1-2, ..., 521-Q-2 of each memory die 520-1, ..., 520-P may correspond to a single row of memory cells.

[0066] The memory bank 521-Q of the memory die 520-P may include error correction data in its portion 521-Q-1 for correcting a number of errors exceeding a threshold number that cannot be corrected using error correction data stored in the portions 521-1-1, ..., 521-Q-1 of the memory die 520-1, ..., 520-(P-1) and / or the portions 521-1-1, ..., 521-(Q-1)-1 of the memory die 520-P (e.g., within the memory banks 521-1, ..., 521-Q of the memory die 520-1, ..., 520-(P-1) and / or the memory banks 521-1, ..., 521-(Q-1) of the memory die 520-P. In some embodiments, the error correction data for correcting the number of errors exceeding the threshold number may be parity data. Although embodiments are not limited thereto, the threshold number described herein may correspond to a single error.

[0067] A stripe may include data stored in one or more rows of memory cells (e.g., stripes) of each of the memory banks 521-1, ..., 521-Q of the memory dies 520-1, ..., 520-P. For example, a stripe 522 may include / correspond to host data stored in one or more rows of memory cells of the memory banks 521-1, ..., 521-Q of the memory dies 520-1, ..., 520-(P-1) and the memory banks 521-1, ..., 521-(Q-1) of the memory die 520-P and error correction data stored in one or more rows of memory cells of the memory bank 521-Q of the memory die 520-P, such as Figure 5 Thus, an error correction operation may be performed on host data stored in one of the stripes of stripe 522 (to correct a number of errors exceeding a threshold number) by reading the error correction data of stripe 522 (of memory bank 521-Q of memory die 520-P) and host data of the other stripes of stripe 522.

[0068] The operational roles of banks / die (e.g., banks 521 and / or memory die 520) may be occasionally / periodically swapped to balance the number of accesses across banks and avoid "hot spots" and prevent one bank from being accessed more frequently than other banks / die. For example, it has been previously described that banks 521-Q of memory die 520-P are configured to store error correction data (e.g., parity data), while other banks 521 are configured to store host data. Thus, at a certain moment, one of banks 521 of memory die 520-1, ..., 520-(P-1) and banks 521-1, ..., 521-(Q-1) may be reconfigured to store error correction data, while banks 521-Q of memory die 520-P are reconfigured to store host data.

[0069] Assuming that each of memory dies 520 includes 64 memory banks (e.g., memory bank 521), Figure 5 The example illustrated in can have an overhead of approximately 0.048%. For example, the ratio of the number of memory banks configured for storing error correction data for correcting a number of errors exceeding a threshold number (e.g., memory bank 521-Q of memory die 520-P) to the number of memory banks configured for storing host data (e.g., memory banks 521-1, ..., 521-Q of memory die 520-1, ..., 520-(P-1) and memory banks 521-1, ..., 521-(Q-1) of memory die 520-P) is 1 / 2047 (approximately 0.048%).

[0070] In a non-limiting example, an example system (eg Figure 1 The computing system 100 or memory device 120 illustrated in the embodiment of the present invention may include a first number of memory dies (e.g., memory dies 520-1, ..., 520-(P-1)) in a group of memory dies (e.g., memory dies 520). Each of the memory dies in the first group may include multiple memory banks (e.g., memory banks 521-1, ..., 521-Q) and each of the multiple memory banks may include a first portion (e.g., portion 521-1-1, ..., 521-Q-1) configured to store host data and a second portion (e.g., portion 521-1-2, ..., 521-Q-2) configured to store error detection data indicating that the number of errors in the corresponding one of the multiple memory banks exceeds a threshold number. The system may further include a second memory die (e.g., memory die 520-P) in the group of memory dies. The second memory die may include multiple memory banks (e.g., memory banks 521-1, ..., 521-Q). One of the plurality of memory banks, such as memory bank 521-Q, may be configured to store error correction data to correct a number of errors exceeding a threshold number within the plurality of memory banks of the first number of memory dies and the second die.

[0071] In some embodiments, other memory banks of the plurality of memory banks of the second memory die (e.g., memory banks 521-1, ..., 521-(Q-1)) may be configured to store host data. In some embodiments, the memory dies of the first number of memory dies and the second memory die may be coupled to different channels. In some embodiments, each of the plurality of memory banks of the second memory die may be configured to store error detection data for indicating that a number of errors within a corresponding one of the plurality of memory banks of the second memory die exceeds a threshold number.

[0072] Figure 66 is a flow chart representing an example method 631 for memory bank protection according to several embodiments of the present disclosure. The method 631 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 631 is performed by Figure 1 1 and 12. The control circuit system 140 and / or system controller 110 described in the embodiment of the present invention are executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the processes may be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0073] At block 632, method 631 may include performing a process of ... Figures 2 to 5 A group of memory banks (eg, each of which is associated with a memory die 220, 320, 420, and / or 520) of the illustrated memory die 220, 320, 420, and / or 520 Figures 2 to 5 A memory bank in the illustrated memory banks 221, 321, 421 and / or 521) performs a read operation to retrieve first host data of a page of memory cells from a memory bank of a memory bank group and error detection data of a different page of memory cells from a memory bank of the group.

[0074] At block 634, method 631 may include performing an error detection operation on first host data retrieved from the memory cell page of the memory bank of the group using the error detection data. In some embodiments, method 631 may include performing an error correction operation on host data retrieved from the memory cell page of the memory bank of the group using error correction data stored in the memory bank of the group to correct a number of errors that equals or does not exceed a threshold number before performing the error detection operation on the host data retrieved from the memory cell page of the memory bank of the group.

[0075] At block 636, method 631 may include reading second host data of corresponding memory cell pages from other memory banks of the group and error correction data stored in at least one of the group in response to indicating via the error detection operation that the number of errors within the first host data exceeds a threshold number; and

[0076] At block 638 , the method 631 may include performing an error correction operation using the second host data retrieved from the corresponding memory cell page of the other memory bank and the error correction data retrieved from at least one of the groups to correct the number of errors exceeding the threshold number.

[0077] In some embodiments, method 631 may include receiving a write request to write different host data to a memory cell page of a memory bank of the group. In this example, method 631 may further include writing the different host data to the memory cell page without erasing other memory cell pages of the memory bank of the group.

[0078] In some embodiments, method 631 may include generating error correction data based on the different host data and the second host data in response to receiving a write request. In this example, method 631 may further include writing the generated error correction data to at least one of the groups.

[0079] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It should be understood that the above description is by way of illustration and not by way of limitation. A person skilled in the art will understand the combination of the above embodiments and other embodiments not explicitly described herein after reviewing the above description. The scope of one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the attached claims and the full scope of equivalents authorized by such claims.

[0080] In the Detailed Description, some features are grouped together in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure must use more features than are expressly recited in each claim. Rather, as the appended claims reflect, the inventive subject matter has less than all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. A device comprising: A first group of memory banks (221-1, ..., 221-(M-1)) of a memory device (120; 220; 320; 420; 520-1, ..., 520-P), the first group of memory banks comprising: A first portion (221-1-1, ..., 221-(M-1)-1) configured to store host data; and a second portion (221-1-2, ..., 221-M-2) configured to store error detection data indicating a number of errors exceeding a threshold number within a corresponding one of the memory banks of the first group; and A second group of memory banks (221-M) of the memory device is configured to store error correction data to correct a number of errors within respective ones of the first group of memory banks that exceed the threshold number.

2. The apparatus of claim 1, wherein the memory device comprises a plurality of groups of stripes (222; 522), each of the plurality of groups of stripes comprising a respective group (325) of memory cells from each of the first and second groups of memory banks.

3. The apparatus according to claim 2, wherein: A memory bank in the second group of memory banks is configured to store error correction data corresponding to a first stripe (222, 522); and Different ones of the second group of memory banks are configured to store error correction data corresponding to a second stripe (222, 522).

4. The apparatus according to claim 2, wherein: A first group of memory cells is distributed across the first group of memory banks and the second group of memory banks, the first group of memory cells being configured to store data corresponding to the first stripe; and A second group of memory cells is distributed across the first group of memory banks and the second group of memory banks, the second group of memory cells being configured to store data corresponding to the second stripe.

5. A device comprising: A group of memory banks (121-1, ..., 121-N; 221-1, ..., 221-M; 321-1, ..., 321-8; 521-1, 521-Q) configured to store data corresponding to a first stripe (222, 522), wherein the first stripe further comprises: a first portion of a memory bank of the group configured to store first host data; and a second portion of the memory bank of the group configured to store first error correction data to correct a number of errors in the first host data; and The memory banks of the group are further configured to store data corresponding to a second stripe (222, 522), wherein the second stripe further comprises: a third portion of the memory bank of the group configured to store second host data; and A fourth portion of the memory bank of the group is configured to store second error correction data.

6. The apparatus according to claim 5, wherein: The second portion of the memory banks of the group corresponds to a first memory bank (221-1, ..., 221-(M-1)) of the memory banks of the group; and The fourth portion of the memory banks of the group corresponds to the second memory bank (221-1, ..., 221-(M-1)) among the memory banks of the group.

7. The apparatus of claim 5, wherein: The second portion of the group of memory banks further includes a plurality of portions distributed across the group of memory banks, the plurality of portions configured to store the first error correction data.

8. The apparatus of claim 7, wherein the plurality of portions respectively correspond to different memory banks in the memory banks of the group.

9. The apparatus of claim 7, wherein: The plurality of portions respectively correspond to different groups of memory cells of the group of memory banks; and Each of the plurality of portions corresponds to a row of DRAM memory cells.

10. A method comprising: performing an error detection operation on first host data retrieved from a first memory bank in a group of memory banks (221-1, ..., 221-(M-1)) using the first error detection data; and In response to the error detection operation indicating a number of errors within the first host data that exceeds a threshold number, performing an error correction operation using: first error correction data for correcting the number of errors exceeding the threshold number; and Second host data is retrieved from one or more memory banks in the group of memory banks different from the first memory bank.

11. The method of claim 10, further comprising, prior to performing the error correction operation, performing a read operation on the one or more memory banks in the group of memory banks to: retrieving the second host data from a second memory bank in the group of memory banks; and The first error correction data is retrieved from a third memory bank of the group of memory banks.

12. The method according to claim 10, further comprising: performing an error detection operation on third host data retrieved from a second memory bank of the group of memory banks using the second error detection data; and In response to the error detection operation indicating a number of errors within the third host data that exceeds a threshold number, an error correction operation is performed using: second error correction data for correcting the number of errors exceeding the threshold number; and Fourth host data is retrieved from one or more memory banks in the group of memory banks different from the second memory bank.

13. The method according to claim 12, further comprising: performing a read operation on a first group of memory cells of the first memory bank to retrieve the first host data before performing the error detection operation on the first host data; and Prior to performing the error detection operation on the first host data, a read operation is performed on a second group of memory cells of the first memory bank to retrieve the first host data.

14. The method of claim 13, further comprising performing a read operation on a first group of memory cells of one or more memory banks to retrieve the second host data or the first error correction data before performing the error detection operation on the first host data.

15. The method of claim 13, further comprising performing a read operation on a second group of memory cells of the one or more memory banks to retrieve the fourth host data or the second error correction data before performing the error detection operation on the third host data.

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