Program debugging method and device, electronic equipment and storage medium

Abstract

The invention provides a program debugging method, and relates to the technical field of artificial intelligence, in particular to the technical fields of chips, heterogeneous programs, program debugging and the like. According to the specific implementation scheme, in response to a received notification corresponding to a preset event, at least one to-be-executed command is provided for simulation equipment through a command naming pipeline, the simulation equipment comprises a simulation processor, the simulation processor is a simulation artificial intelligence processor, and the simulation processor is connected with the simulation processor; the preset event is an event occurring in the process of simulating the processor to execute the to-be-debugged program; at least one simulation execution result corresponding to the at least one command to be executed is received via the result naming pipeline. The invention further provides a program debugging device, electronic equipment and a storage medium.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, and in particular to the technical fields of chips, heterogeneous programs, and program debugging. More specifically, the present disclosure provides a program debugging method, device, electronic device, and storage medium. Background Art

[0002] With the development of artificial intelligence technology, the application of heterogeneous computing is increasing. Heterogeneous computing can use different types of processors to jointly perform computing tasks, which can give full play to the characteristics of different processors and is widely used in fields such as high-performance computing. Summary of the invention

[0003] The present disclosure provides a program debugging method, apparatus, device and storage medium.

[0004] According to one aspect of the present disclosure, a program debugging method is provided, the method comprising: in response to receiving a notification corresponding to a preset event, providing at least one command to be executed to a simulation device via a command named pipe, wherein the simulation device comprises a simulation processor, the simulation processor is a simulated artificial intelligence processor, and the preset event is an event occurring during the execution of a program to be debugged by the simulation processor; and receiving at least one simulation execution result corresponding to the at least one command to be executed via a result named pipe.

[0005] According to another aspect of the present disclosure, a program debugging method is provided, the method comprising: in response to determining that a preset event occurs, sending a notification corresponding to the preset event via a notification named channel; in response to receiving at least one command to be executed via a command named pipe, executing at least one command to be executed using a simulation processor of a simulation device to obtain at least one simulation execution result, wherein the simulation processor is a simulation artificial intelligence processor; and sending at least one simulation execution result corresponding to the at least one command to be executed via a result named pipe.

[0006] According to another aspect of the present disclosure, a program debugging device is provided, which includes: a first providing module, used to provide at least one command to be executed to a simulation device via a command named pipe in response to receiving a notification corresponding to a preset event, wherein the simulation device includes a simulation processor, the simulation processor is a simulated artificial intelligence processor, and the preset event is an event occurring during the execution of a program to be debugged by the simulation processor; a first receiving module, used to receive at least one simulation execution result corresponding to at least one command to be executed via a result named pipe.

[0007] According to another aspect of the present disclosure, a program debugging device is provided, which includes: a first sending module, used to send a notification corresponding to the preset event via a notification named channel in response to determining that a preset event occurs; a first execution module, used to execute at least one command to be executed using a simulation processor of a simulation device in response to receiving at least one command to be executed via a command named pipe, and obtain at least one simulation execution result, wherein the simulation processor is a simulation artificial intelligence processor; a second sending module, used to send at least one simulation execution result corresponding to at least one command to be executed via a result named pipe.

[0008] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method provided according to the present disclosure.

[0009] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided. The computer instructions are used to cause a computer to execute the method provided according to the present disclosure.

[0010] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the method provided according to the present disclosure is implemented.

[0011] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0013] Figure 1 is a schematic diagram of an exemplary system architecture of an application program debugging method and apparatus according to an embodiment of the present disclosure;

[0014] Figure 2 is a flowchart of a program debugging method according to an embodiment of the present disclosure;

[0015] Figure 3 is a flowchart of a program debugging method according to an embodiment of the present disclosure;

[0016] Figure 4 is a schematic diagram of a debugging process and a debugged process according to an embodiment of the present disclosure;

[0017] Figure 5is a schematic diagram of an execution flow of a communication function according to an embodiment of the present disclosure;

[0018] Figure 6 is a block diagram of a program debugging device according to an embodiment of the present disclosure;

[0019] Figure 7 is a block diagram of a program debugging device according to an embodiment of the present disclosure; and

[0020] Figure 8 The present invention is a block diagram of an electronic device capable of applying an application debugging method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0022] Different types of processors can include central processing units (CPUs) and artificial intelligence processors. Artificial intelligence processors can be various processors such as general-purpose graphics processing units (GPGPUs), tensor processing units (TPUs), and neural network processing units (NPUs). Heterogeneous computing devices can include host and device ends. The host end can include a central processing unit. The device end can include an artificial intelligence processor. Heterogeneous computing can produce significant advantages in cost, performance, and power consumption. However, when developing heterogeneous programs, it is necessary to develop programs that run on the host end and also to develop programs that run on the device end. As a result, the development of heterogeneous programs is more difficult.

[0023] During the program development process, the program needs to be debugged. Heterogeneous programs can be debugged based on printing, tracing, and hardware debuggers, but it is difficult to achieve effective debugging. For example, the debugging method based on printing cannot dynamically observe the dynamic execution of heterogeneous programs, and the code of the heterogeneous programs needs to be modified and additional printing code needs to be added. However, modifying the code of the heterogeneous program may destroy the original error (bug), making it difficult to reproduce the error. For another example, the debugging method based on tracing can output information about all instructions on all device ends, but it cannot be directly associated with the source code, and developers need to manually map instructions to source code. If too much information is output, a lot of manpower is required to map the information and filter effective information. For another example, the debugging method based on the hardware debugger is limited by the debugging function of the hardware. If the hardware development is completed or frozen, the debugging capability of the hardware is basically formed, and the debugging function cannot be dynamically expanded according to the needs of developers. The hardware debugger also needs to add debugging support at the driver layer and encapsulate the hardware interface for the hardware debugger to use.

[0024] Therefore, in order to improve the debugging efficiency of heterogeneous programs, the present disclosure provides a program debugging method, which will be described below.

[0025] Figure 1 is a schematic diagram of an exemplary system architecture that can be used for application debugging method and device according to an embodiment of the present disclosure. It should be noted that: Figure 1 What is shown is merely an example of a system architecture to which the embodiments of the present disclosure can be applied, in order to help those skilled in the art understand the technical content of the present disclosure, but it does not mean that the embodiments of the present disclosure cannot be used in other devices, systems, environments or scenarios.

[0026] like Figure 1 As shown, the system architecture 100 according to this embodiment may include a first terminal device 101, a second terminal device 102, a third terminal device 103, a network 104 and a server 105. The network 104 is used to provide a medium for a communication link between the first terminal device 101, the second terminal device 102, the third terminal device 103 and the server 105. The network 104 may include various connection types, such as wired and / or wireless communication links, etc. It can be understood that the first terminal device to the third terminal device are different from the above-mentioned device end, and the device end is part of a heterogeneous computing device. The first terminal device to the third terminal device can be a heterogeneous computing device or a homogeneous computing device.

[0027] The user can use the first terminal device 101, the second terminal device 102, and the third terminal device 103 to interact with the server 105 through the network 104 to receive or send messages, etc. The first terminal device 101, the second terminal device 102, and the third terminal device 103 can be various electronic devices with display screens and supporting web browsing, including but not limited to smart phones, tablet computers, laptop portable computers, desktop computers, etc.

[0028] The server 105 may be a server that provides various services, such as a background management server (only as an example) that provides support for websites browsed by users using the first terminal device 101, the second terminal device 102, and the third terminal device 103. The background management server may analyze and process the received data such as user requests, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal device.

[0029] It should be noted that the program debugging method provided in the embodiment of the present disclosure can generally be executed by the server 105. Accordingly, the program debugging device provided in the embodiment of the present disclosure can generally be set in the server 105. The program debugging method provided in the embodiment of the present disclosure can generally be executed by a terminal device. Accordingly, the program debugging device provided in the embodiment of the present disclosure can generally be set in a terminal device. The program debugging method provided in the embodiment of the present disclosure can also be executed by a server or server cluster that is different from the server 105 and can communicate with the first terminal device 101, the second terminal device 102, the third terminal device 103 and / or the server 105. Correspondingly, the program debugging device provided in the embodiment of the present disclosure can also be set in a server or server cluster that is different from the server 105 and can communicate with the first terminal device 101, the second terminal device 102, the third terminal device 103 and / or the server 105.

[0030] It can be understood that the above describes the system architecture of the present disclosure, and the following will describe the method of the present disclosure.

[0031] Figure 2 is a flowchart of a program debugging method according to an embodiment of the present disclosure.

[0032] like Figure 2 As shown, the method 210 may include operations S211 to S212. It can be understood that the method 210 may be executed by a debugging process among multiple processes.

[0033] In operation S211 , in response to receiving a notification corresponding to a preset event, at least one to-be-executed command is provided to a simulation device via a command named pipe.

[0034] In the disclosed embodiment, the simulated device may be simulated by a simulator. The simulator may also be referred to as an emulator. The simulated device may include a simulated processor. It is understood that the simulated processor is a part of the simulated device simulated by the simulator. The simulator runs in the debugged process. The debugging process is a process different from the above-mentioned debugging process.

[0035] In the embodiment of the present disclosure, the simulated processor may be a simulated artificial intelligence processor, which may be a simulated general purpose graphics processor, a simulated tensor processor, or a simulated neural network processor.

[0036] In the disclosed embodiment, a named pipe may be used to communicate with a simulated device. The simulated device may be communicated with based on multiple named pipes. The multiple named pipes may include a command named pipe. The command may be provided to the simulated device via the command named pipe.

[0037] In the embodiment of the present disclosure, the command to be executed may include multiple sub-commands. For example, the command to be executed may cause the simulation device to return the status information of the simulation device.

[0038] In the disclosed embodiment, the preset event may be an event occurring during the execution of the program to be debugged by the simulation processor. The program to be debugged may be: a program running on the device in the heterogeneous program. For example, the preset event may be that a breakpoint of the program to be debugged is triggered.

[0039] In operation S212, at least one simulation execution result corresponding to at least one to-be-executed command is received via a result named pipe.

[0040] In the embodiment of the present disclosure, the information returned by the simulation device can be received via the result named pipe. The information returned by the simulation device can include the above-mentioned state information, simulation execution results, etc.

[0041] Through the disclosed embodiments, the simulator simulates a simulated device to execute the program to be debugged, and the simulator can be used to debug heterogeneous programs when the real hardware device does not support hardware debugging or does not support the required debugging function. Communication with the simulated device can be achieved through named pipes, and information can be obtained and commands can be sent from the simulated device. In this way, heterogeneous programs can be debugged comprehensively and accurately, and the efficiency of program debugging can be fully improved.

[0042] It can be understood that the above description of the named pipes of the present disclosure is combined with the command named pipe and the result named pipe. However, the present disclosure is not limited thereto, and the multiple named pipes may also include a notification named pipe, which will be described below.

[0043] In some embodiments, the notification corresponding to the preset event may be received via a notification named pipe. For example, after the preset event occurs, the simulation device may send the notification corresponding to the preset event to the debugging process via the notification named pipe.

[0044] It can be understood that the method of the present disclosure is described above in conjunction with a debugging process, and the method of the present disclosure will be described below in conjunction with a debugged process.

[0045] Figure 3 is a schematic diagram of a program debugging method according to an embodiment of the present disclosure.

[0046] like Figure 3 As shown, the method 320 may include operations S321 to S323. It can be understood that the method 320 may be executed by a debugged process among multiple processes.

[0047] In operation S321, in response to determining that a preset event occurs, a notification corresponding to the preset event is sent via a notification named pipe.

[0048] In the disclosed embodiment, the preset event may be an event that occurs when the simulation processor of the simulation device executes the program to be debugged. For example, when the simulation processor executes to a breakpoint of the program to be debugged, it may be determined that the preset event occurs. Next, a notification may be sent to the debugging process via a notification named pipe. The debugging process may perform the above operation S211 and provide at least one instruction to be executed to the simulation device via a command named pipe.

[0049] In operation S322, in response to receiving at least one command to be executed via the command named pipe, the at least one command to be executed is executed using a simulation processor of the simulation device to obtain at least one simulation execution result.

[0050] In the embodiment of the present disclosure, the simulation processor is a simulation artificial intelligence processor. It can be understood that the above description of the simulation device, simulation processor and simulator is also applicable to the present embodiment, and the present disclosure will not repeat them here.

[0051] In operation S323, at least one simulation execution result corresponding to the at least one to-be-executed command is sent via the result named pipe.

[0052] Through the disclosed embodiments, the simulator simulates a simulated device to execute the program to be debugged, and the simulator can be used to debug heterogeneous programs when the real hardware device does not support hardware debugging or does not support the required debugging function. Through the named pipe, the simulated device can receive commands from the debugging process, send information to the debugging process, and obtain commands. In this way, heterogeneous programs can be debugged comprehensively and accurately, and the efficiency of program debugging can be fully improved.

[0053] It can be understood that the method of the present disclosure is described above in conjunction with the debugging process and the debugged process respectively, and the method of the present disclosure will be further described below in conjunction with the debugging process and the debugged process.

[0054] Figure 4 It is a schematic diagram of a debugging process and a debugged process according to an embodiment of the present disclosure.

[0055] like Figure 4 As shown, the debugging process p410 can execute the above method 210, and the debugged process p420 can execute the above method 320. The debugged process p420 can send a notification corresponding to a preset event to the debugging process p410 via a notification named pipe. In order to handle the preset event, the debugging process p410 can send one or more commands to the debugged process p420 via a command named pipe. After receiving one or more commands, the debugged process p420 can execute the one or more commands to obtain one or more results. Next, via the result named pipe, the debugged process p420 can send one or more results to the debugging process p410. Through the embodiment of the present disclosure, multiple named pipes are used as a communication method between the debugging process and the debugged process, without the need to use additional inter-process communication means. After determining the file path of the named pipe, full-duplex communication can be achieved, and efficient communication can be easily achieved.

[0056] It can be understood that the above text describes the method of the present disclosure in combination with the debugging process and the debugged process, and the following text will further describe multiple named pipes of the present disclosure.

[0057] In some embodiments, multiple named pipes can be implemented as communication functions. The communication functions of the present disclosure will be described below in conjunction with the debugged process.

[0058] Figure 5 It is a schematic diagram of the execution flow of a communication function according to an embodiment of the present disclosure.

[0059] like Figure 5 As shown, when a preset event occurs, the debugged process can call a communication function to send a notification corresponding to the preset event via a notification named pipe. Next, operations S5211 to S5212 can be performed.

[0060] In operation S5211, the communication exit flag is set to an invalid value.

[0061] For example, the invalid value may be 0, and the value of the communication exit mark may be set to 0. When the communication exit mark is an invalid value, the communication between the debugging process and the debugged process may be maintained. That is, the debugging process may monitor the notification named pipe and the result named pipe. The debugged process may monitor the command named pipe.

[0062] In operation S5212, it is determined whether the communication exit flag is a valid value.

[0063] For example, in response to determining that the communication exit flag is a valid value, operation S524 may be performed. The valid value may be 1.

[0064] For example, in response to determining that the communication exit flag is not a valid value, the command named pipe may continue to be monitored to receive the command provided by the debugging process. This will be described below in conjunction with operations S5221 to S5225.

[0065] In operation S5221, a command is received via a command named pipe.

[0066] In operation S5222, the command is parsed to obtain the type of the command. For example, different types of commands may include a to-be-executed command and a communication exit command.

[0067] In operation S5223, it is determined whether the command is a communication exit command.

[0068] For example, in response to determining that the command is a communication exit command, operation S5224 may be performed.

[0069] For example, in response to determining that the command is not a communication exit command, operation S5225 may be performed.

[0070] In operation S5224, the communication exit flag is set to a valid value. Next, the process may return to operation S5212. Operation S5212 is performed again, and in response to determining that the communication exit flag is a valid value, operation S524 may be performed to end the communication.

[0071] In operation S5225, the command is executed by the simulation processor to obtain a simulation result. For example, if the command is a to-be-executed command, the to-be-executed command can be executed to obtain a simulation execution result.

[0072] Next, operation S523 may be performed to send the simulation result via the result naming channel. For example, the simulation result may be provided to the debugging process via the result naming channel. Next, the process may return to operation S5212.

[0073] In operation S524, the communication is ended. For example, the communication function may be exited.

[0074] It can be understood that the above text describes multiple named pipes of the present disclosure in conjunction with communication functions, and the following text will describe different preset events of the present disclosure.

[0075] In some embodiments, the preset event may be a first preset event. The first preset event may be that the simulation processor starts to execute the program to be debugged. For example, a user may set one or more breakpoints in the program to be debugged. The debugging process may generate debugging information based on the one or more breakpoints set by the user. The debugging information may indicate the location of the breakpoint of the program to be debugged.

[0076] In some embodiments, the program to be debugged may correspond to a plurality of initial instructions. For example, after the code of the program to be debugged is compiled, a plurality of initial instructions may be obtained.

[0077] In some embodiments, the initial instruction may be processed according to the data in one or more first simulation registers. For example, an initial instruction may be an addition instruction. The addition instruction may perform an addition operation according to the data in two first simulation registers to obtain an addition operation result. The addition operation result may be written into another first simulation register. It is understood that the initial instruction is an addition instruction, which is only an example, and the initial instruction may be various types of instructions, and the present disclosure does not limit this.

[0078] In some embodiments, the method 320 may further include: loading the program to be debugged into the simulation storage unit of the simulation device. Next, when the program to be debugged starts to be executed, it may be determined that a first preset event occurs.

[0079] In some embodiments, in some implementations of the above operation S321, in response to determining that the first preset event occurs, a notification corresponding to the first preset event is sent via a notification named pipe. For example, the debugged process can call the above communication function to send a notification corresponding to the first preset event via the notification named pipe and establish communication with the debugging process.

[0080] In some embodiments, the method 320 may further include sending program address information of the program to be debugged in the simulation storage unit via the result named pipe. For example, the program address information may indicate the starting address of the program to be debugged in the simulation storage unit.

[0081] In some embodiments, the method 210 may further include, in response to receiving a notification corresponding to a first preset event via a notification named pipe, obtaining program address information of the program to be debugged in the simulated storage unit via a result named pipe. Parse the debugging information of the function of the program to be debugged to obtain at least one offset value. The offset value corresponds to a breakpoint. Determine at least one breakpoint address information based on the program address information and the at least one offset value. For example, the start address and the offset value of the program to be debugged in the simulated storage unit are added to determine the breakpoint address information of the breakpoint. The breakpoint address information may indicate the address of the breakpoint in the simulated storage unit.

[0082] In some embodiments, in some implementations of the above operation S211, at least one command to be executed may be provided to the simulation device via a command named pipe.

[0083] In some embodiments, at least one command to be executed may include a first command to be executed. The first command to be executed may instruct the simulation processor to save at least one initial instruction related to the breakpoint of the program to be debugged and add a virtual trap instruction at the breakpoint. The virtual trap instruction may block the execution of the program to be debugged. For example, the program to be debugged may include multiple initial instructions. There may be one or more initial instructions at the breakpoint. When setting a breakpoint, the user may determine one or more initial instructions related to the breakpoint from the one or more initial instructions at the breakpoint. For another example, the virtual trap instruction may implement the function of the trap instruction without a hardware debugger. The simulator may simulate a virtual trap instruction that is consistent with the simulation processor and has no conflict. Through the disclosed embodiment, the user can set a program breakpoint in the program running on the simulation device, and obtain the location and context information of the breakpoint, which can effectively improve the debugging efficiency.

[0084] In some embodiments, at least one command to be executed may further include a second command to be executed. The second command to be executed may instruct the analog device to adjust or return status information of the analog device. The status information may include one or more first status sub-information and one or more second status sub-information. The first status sub-information may characterize the state of the first register of the initial instruction. The second status sub-information may characterize the state of the analog storage unit.

[0085] In some embodiments, in some implementations of the above operation S322, executing at least one command to be executed using a simulation processor of a simulation device, and obtaining a simulation execution result includes: executing a first command to be executed using a simulation processor to save at least one initial instruction related to a breakpoint of a program to be debugged and adding a virtual trap instruction at the breakpoint to obtain a first simulation execution result. Executing a second command to be executed using a simulation processor to obtain a second simulation execution result. The first simulation execution result may indicate that virtual trap instructions have been added at all breakpoints of the program to be debugged. The second simulation execution result may include the above-mentioned status information. For example, if the second command to be executed indicates returning status information of one or more first simulation registers, the second simulation execution result may include one or more first status sub-information corresponding to the one or more first simulation registers. The first status sub-information may include information such as the capacity and number of the first simulation register. For another example, if the second command to be executed indicates adjusting the first simulation register of the initial instruction, the second simulation execution result may include the first status sub-information, and the first status sub-information may indicate: the number of the first simulation register of the adjusted initial instruction.

[0086] In some embodiments, in some implementations of the above operation S323, at least one simulation execution result corresponding to at least one to-be-executed command may be sent via a result named pipe. For example, a first simulation execution result and a second simulation execution result may be sent via a result named pipe.

[0087] In some embodiments, in some implementations of the above operation S212, at least one simulation execution result corresponding to at least one to-be-executed command may be received via a result named pipe. For example, a first simulation execution result and a second simulation execution result may be received via a result named pipe.

[0088] It is understandable that multiple different second to-be-executed instructions can be provided to the debugged process multiple times, and multiple second simulation execution results can be received multiple times. In addition, during the debugging process, if the user believes that the program to be debugged can be started, the first communication exit command can be provided to the debugged process using the debugging process, which will be explained below.

[0089] In some embodiments, the method 210 may further include: providing a first communication exit command to the simulation device via a command named pipe. The first communication exit command may instruct the simulation processor to end communication or to start executing the program to be debugged.

[0090] In some embodiments, the above method 320 may also include: in response to receiving a first communication exit command via a command named pipe, executing the first communication exit command to execute the program to be debugged using a simulated processor. For example, after executing the first communication exit command, the current communication between the debugged process and the debugging process may be terminated. Through the disclosed embodiment, after executing the first communication exit command, the simulated processor of the debugged process may execute multiple initial instructions of the program to be debugged, and may simulate the operation of the program according to user needs, which helps to improve the debugging efficiency of the program.

[0091] It can be understood that the method of the present disclosure is described above in conjunction with the first preset event, and the method of the present disclosure will be described below in conjunction with the second preset event.

[0092] In some embodiments, the second preset event may be that a target breakpoint in the program to be debugged is triggered. The target breakpoint is one of at least one breakpoint of the program to be debugged.

[0093] In some embodiments, the analog device includes at least one of an analog storage unit, a first analog register, and a second analog register. The above description of the analog storage unit and the first analog register is also applicable to this embodiment, and the disclosure will not repeat them here.

[0094] In some embodiments, when executing the initial instruction, the simulation processor obtains the initial instruction according to the simulation address in the second simulation register. For example, the data stored in the second simulation register may be a simulation address. Based on the simulation address in the second simulation register, the simulation processor may obtain an initial instruction. After the simulation processor obtains an initial instruction based on the current simulation address in the second simulation register, the second simulation register will be updated. The updated second simulation register stores the post-simulation address so that the simulation register obtains another initial instruction. In one example, the second simulation register may be a simulated program counter (PC) register.

[0095] In some embodiments, the simulation processor has multiple execution modes. The multiple execution modes include a first execution mode. The simulation processing in the first execution mode can continuously execute multiple initial instructions. For example, as described above, a virtual trap instruction is added at the breakpoint. In the first execution mode, after the simulation processor continuously executes multiple initial instructions, it executes the virtual trap instruction, and it can be determined that the second preset event occurs. In addition, after the simulation processor executes the virtual trap instruction, the simulation processor is in a blocked state and stops executing the initial instruction.

[0096] In some embodiments, in some implementations of the above operation S321, in response to determining that the second preset event occurs, a notification corresponding to the second preset event is sent via a notification named pipe. For example, when determining that the second preset event occurs, the debugged process can call the above communication function to establish communication with the debugging process, so as to send a notification corresponding to the second preset event to the debugging process via the notification named pipe, so that the debugging process processes the second preset event this time.

[0097] In some embodiments, in some implementations of the above operation S211, in response to receiving a notification corresponding to the second preset event via the notification named pipe, at least one to-be-executed command is provided to the simulation device via the command named pipe. For example, the at least one to-be-executed command may include one or more second to-be-executed commands.

[0098] In some embodiments, in some implementations of the above operation S322, in response to receiving at least one command to be executed via a command named pipe, the at least one command to be executed is executed using a simulation processor to obtain at least one simulation execution result. For example, the at least one command to be executed may include one or more second commands to be executed. The at least one simulation execution result may include at least one second simulation execution result. It is understood that the above description of the second command to be executed and the second simulation execution result is also applicable to the present embodiment, and the present disclosure will not repeat them here.

[0099] In some embodiments, in some implementations of the above operation S323, at least one simulation execution result is sent via a result named pipe. For example, at least one simulation execution result may be sent to a debugging process.

[0100] In some embodiments, in some implementations of the above operation S212, the debugging process may obtain at least one simulation execution result via a result named pipe.

[0101] It is understandable that after the breakpoint is triggered, the current state of the simulation device can be queried, printed, and adjusted based on the second command to be executed. Next, some ways of continuing to execute the program to be debugged will be described.

[0102] In some embodiments, the method 210 may further include: storing at least one initial instruction associated with the target breakpoint in a first buffer of the simulation storage unit. Writing the simulation address of the initial instruction in the first buffer into the second simulation register. For example, the user may provide indication information for continuing execution. Based on the indication information, the debugging process may call the storage allocation interface of the simulation storage unit to allocate a storage area as the first buffer. As described above, at least one initial instruction associated with the breakpoint is saved. After the breakpoint is triggered, the breakpoint may be used as a target breakpoint. At least one initial instruction associated with the target breakpoint may be stored in the first buffer. And writing the simulation address of the initial instruction in the first buffer into the second simulation register, so that the simulation processor can execute the initial instruction in the first buffer after resuming execution. Through the embodiment of the present disclosure, storing one or more initial instructions at the breakpoint into the first buffer, and writing the simulation address of the initial instruction into the second simulation register, the simulation processor may execute one or more initial instructions at the breakpoint, which is helpful for reproducing the instructions at the breakpoint. If there is an error in the instruction at the breakpoint, accurate error reproduction may be achieved, and debugging efficiency may be improved.

[0103] In some embodiments, the multiple execution modes of the simulation processor may further include a second execution mode. The simulation processor in the second execution mode may stop executing the initial instruction after executing a preset number of initial instructions. For example, the preset number may be 1. In the second execution mode, the simulation processor may trigger blocking after executing 1 instruction and stop executing subsequent initial instructions. The second execution mode may also be referred to as a single-step execution mode.

[0104] In some embodiments, the method 210 may further include providing a first switching instruction to the simulation device via a command named pipe, so that the simulation processor switches from the first execution mode to the second execution mode.

[0105] In some embodiments, the above method 320 may further include: in response to receiving a first switching command via a command named pipe, executing the first switching command using a simulation processor to switch from a first execution mode to a second execution mode. It is understood that after executing the first switching command, a simulation result representing the switch to the second execution mode may be generated, and the simulation result may be sent via a result named pipe to improve the stability and robustness of the simulation device. It is also understood that after executing the first switching command, a simulation result representing the switch to the second execution mode may not be generated, and the present disclosure does not limit this.

[0106] In some embodiments, the method 210 may further include: providing the second communication exit command to the simulation device via a command named pipe, so that the simulation processor obtains the initial instruction according to the simulation address of the second simulation register. The debugging process may send the second communication exit command to the debugged process.

[0107] In some embodiments, the method 320 may further include: in response to receiving a second communication exit command via a command named pipe, executing the second communication exit command to use the simulation processor to obtain the initial instruction according to the simulation address in the second simulation register. For example, after the debugged process receives the second communication exit command, the communication with the debugging process may be terminated. Next, the simulation processor of the debugged process may obtain the initial instruction according to the simulation address in the second simulation register, and execute the initial instruction.

[0108] It can be understood that the method of the present disclosure is described above in conjunction with the second preset event, and the method of the present disclosure will be further described below in conjunction with the third preset event.

[0109] In some embodiments, the third preset event may be that the simulation processor in the second execution mode has executed a preset number of initial instructions. For example, as described above, after terminating the communication with the debugging process, the simulation processor in the second execution mode may execute the initial instructions in the first buffer. Taking the preset number as 1 as an example, after executing 1 initial instruction, the simulation processor stops executing, and it can be determined that the third preset event occurs.

[0110] In some embodiments, in some implementations of the above operation 321, in response to determining that the third preset event occurs, a notification corresponding to the third preset event is sent via a notification named pipe. For example, the debugged process can call the above communication function to send a notification corresponding to the third preset event via a notification named pipe.

[0111] In some embodiments, in some implementations of the above operation S211, in response to receiving a notification corresponding to the third preset event via the notification named pipe, the notification corresponding to the third preset event can be displayed on the visual interface. Via the command named pipe, the user input command can be provided as the third command to be executed to the simulation device. For example, the user input command can instruct the simulation device to return or adjust the state information of the simulation device. The user input command can be similar to the second command to be executed.

[0112] In some embodiments, in some implementations of the above operation S322, in response to receiving a third command to be executed via a command named pipe, the third command to be executed is executed by using a simulation processor to obtain a third simulation execution result.

[0113] In some embodiments, in some implementations of the above operation S323, the third simulation execution result is sent via a result named pipe. For example, the third simulation execution result can be sent to a debugging process.

[0114] In some embodiments, in some implementations of the above operation S212, the third simulation execution result is received via a result named pipe. For example, the debugging process may receive the third simulation execution result via the result named pipe.

[0115] In some embodiments, the method 210 may further include providing a third communication exit command to the simulation device via a command named pipe. The third communication command may instruct the simulation device to end the communication and continue to execute the initial instruction in the first buffer in the second execution mode.

[0116] In some embodiments, the method 320 may further include, in response to receiving a third communication exit command via the command named pipe, executing the third communication exit command to end the communication. Next, the simulation processor may continue to execute the initial instruction in the first buffer in the second execution mode. It is understood that during the execution of the initial instruction in the first buffer, the third preset event may occur multiple times.

[0117] It can be understood that after the last initial instruction in the first buffer is executed in the second execution mode, the second execution mode can be switched to the first execution mode, which will be explained below.

[0118] In some embodiments, the method 210 may further include providing a second switching command to the simulation device via a command named pipe, so that the simulation processor switches from the second execution mode to the first execution mode. For example, the second switching command may be provided to the simulation device.

[0119] In some embodiments, the method 320 may further include, in response to receiving a second switching command via a command named pipe, executing the second switching command using the simulation processor to switch the simulation processor from the second execution mode to the first execution mode.

[0120] In some embodiments, the above method 210 may further include writing the simulation address of the initial instruction after the target breakpoint into a second simulation register. For example, a virtual trap instruction is provided at the target breakpoint. The simulation address of the initial instruction after the virtual trap instruction may be written into the second simulation register. Next, after exiting the communication with the debugging process, the simulation processing in the first execution mode may obtain the initial instruction according to the simulation address in the second simulation register to continue executing the program to be debugged until the program to be debugged is executed or the next virtual trap instruction is executed. Through the embodiments of the present disclosure, the execution of the program to be debugged may be resumed from the breakpoint to continue subsequent debugging.

[0121] It can be understood that the above description uses the example of executing the initial instruction in the first buffer in the second execution mode to illustrate the present disclosure. Before executing the initial instruction in the first buffer, the second switching instruction can also be provided to the simulation device so that the simulation processing continuously processes the initial instruction in the first buffer in the first execution mode to speed up the debugging efficiency.

[0122] It can be understood that the above description uses the third preset event occurring after the second preset event as an example to illustrate the present disclosure. However, the present disclosure is not limited thereto. After the second preset event occurs, the first switching instruction may not be provided to the simulation device, and the second communication exit command may be provided to the simulation device, so that the simulation processor continues to execute the program to be debugged.

[0123] It can be understood that the method of the present disclosure is described above, and the device of the present disclosure will be described below.

[0124] Figure 6 is a block diagram of a program debugging device according to an embodiment of the present disclosure.

[0125] like Figure 6 As shown, the device 610 may include a first providing module 611 and a first receiving module 612 .

[0126] The first providing module 611 is used to provide at least one to-be-executed command to the simulation device via a command named pipe in response to receiving a notification corresponding to a preset event. The simulation device includes a simulation processor, the simulation processor is a simulation artificial intelligence processor, and the preset event is an event that occurs during the simulation processor executing the program to be debugged.

[0127] The first receiving module 612 is configured to receive at least one simulation execution result corresponding to at least one to-be-executed command via a result named pipe.

[0128] In some embodiments, notifications are received via a notification named pipe.

[0129] In some embodiments, the preset event is a first preset event, and the first preset event is that the simulated processor starts to execute the program to be debugged.

[0130] In some embodiments, at least one command to be executed includes a first command to be executed, which is used to instruct the simulation processor to save at least one initial instruction related to the breakpoint of the program to be debugged and add a virtual trap instruction at the breakpoint, and the virtual trap instruction is used to block the execution of the program to be debugged.

[0131] In some embodiments, the simulation device further includes a simulation storage unit. The device further includes: an acquisition module, which is used to obtain program address information of the program to be debugged in the simulation storage unit via a result named pipe. A parsing module, which is used to parse the debugging information corresponding to the program to be debugged to obtain at least one offset value, and the offset value corresponds to a breakpoint. A determination module, which is used to determine at least one breakpoint address information according to the program address information and the at least one offset value.

[0132] In some embodiments, the apparatus further includes: a second providing module, configured to provide a first communication exit command to the simulation device via a command named pipe, wherein the first communication exit command is configured to instruct the simulation processor to execute the program to be debugged.

[0133] In some embodiments, the simulation device further includes at least one of a simulation storage unit, a first simulation register, and a second simulation register. The initial instruction of the program to be debugged is used to process according to the data in the first simulation register. When executing the initial instruction of the program to be debugged, the simulation processor obtains the initial instruction according to the simulation address in the second simulation register. The multiple execution modes of the simulation processor include a first execution mode and a second execution mode. The simulation processor in the first execution mode continuously executes multiple initial instructions, and the simulation processor in the second execution mode stops executing the initial instruction after executing a preset number of initial instructions.

[0134] In some embodiments, the preset event is a second preset event, the second preset event is that a target breakpoint in the program to be debugged is triggered, and the target breakpoint is one of at least one breakpoint of the program to be debugged.

[0135] In some embodiments, at least one command to be executed includes a second command to be executed, and the second command to be executed is used to instruct the simulation device to adjust or return the status information of the simulation device, and the status information includes at least one of first status sub-information and second status sub-information, and the first status sub-information is used to characterize the state of the first simulation register of the initial instruction, and the second status sub-information is used to characterize the state of the simulation storage unit.

[0136] In some embodiments, the apparatus further comprises: a storage module, configured to store at least one initial instruction associated with the target breakpoint in a first buffer of the simulation storage unit; a first writing module, configured to write the simulation address of the initial instruction in the first buffer into the second simulation register; and a third providing module, configured to provide the first switching command to the simulation device via a command named pipe, so that the simulation processor switches from the first execution mode to the second execution mode.

[0137] In some embodiments, the apparatus further comprises: a fourth providing module, configured to provide the second communication exit command to the simulation device via a command named pipe, so that the simulation processor obtains the initial instruction according to the simulation address in the second simulation register.

[0138] In some embodiments, the preset event is a third preset event, and the third preset event is that the simulation processor in the second execution mode has executed a preset number of initial instructions. The simulation processor switches to the second execution mode after the target breakpoint of the program to be debugged is triggered, and the target breakpoint is one of at least one breakpoint of the program to be debugged.

[0139] In some embodiments, the first providing module includes: a display submodule for displaying a notification corresponding to the third preset event on the visual interface; and a providing submodule for providing the user input command as the third to-be-executed command to the simulation device via a command named pipe.

[0140] In some embodiments, the apparatus further includes: a fifth providing module, configured to provide a second switching command to the simulation device via a command named pipe, so that the simulation processor switches from the second execution mode to the first execution mode.

[0141] In some embodiments, the apparatus further comprises: a second writing module, configured to write a simulation address of an initial instruction after a target breakpoint into a second simulation register.

[0142] It can be understood that the above describes the device corresponding to the debugging process, and the following describes the device corresponding to the debugged process.

[0143] Figure 7 is a block diagram of a program debugging device according to an embodiment of the present disclosure.

[0144] like Figure 7 As shown, the device 720 may include a first sending module 721 , a first execution module 722 , and a second sending module 723 .

[0145] The first sending module 721 is configured to send a notification corresponding to the preset event via a notification named channel in response to determining that a preset event occurs.

[0146] The first execution module 722 is used to execute the at least one to-be-executed command using a simulation processor of the simulation device in response to receiving at least one to-be-executed command via the command named pipe, and obtain at least one simulation execution result. The simulation processor is a simulation artificial intelligence processor.

[0147] The second sending module 723 is used to send at least one simulation execution result corresponding to at least one to-be-executed command via a result named pipe.

[0148] In some embodiments, the preset event is a first preset event, and the first preset event is that the simulated processor starts to execute the program to be debugged.

[0149] In some embodiments, at least one command to be executed includes a first command to be executed. The first execution module includes: a first execution submodule, which is used to execute the first command to be executed using a simulation processor to save at least one initial instruction related to the breakpoint of the program to be debugged and add a virtual trap instruction at the breakpoint to obtain a first simulation execution result. The first simulation execution result is used to indicate that virtual trap instructions have been added at all breakpoints of the program to be debugged, and the virtual trap instruction is used to block the execution of the program to be debugged.

[0150] In some embodiments, the simulation device further comprises a simulation storage unit. The apparatus further comprises: a third sending module, configured to send program address information of the program to be debugged in the simulation storage unit via a result named pipe.

[0151] In some embodiments, the apparatus further comprises: a second execution module for executing the first communication exit command in response to receiving the first communication exit command via the command named pipe, so as to execute the program to be debugged using the simulated processor.

[0152] In some embodiments, the simulation device further includes at least one of a simulation storage unit, a first simulation register, and a second simulation register. The initial instruction of the program to be debugged is used to process according to the data in the first simulation register. When executing the initial instruction of the program to be debugged, the simulation processor obtains the initial instruction according to the simulation address in the second simulation register. The multiple execution modes of the simulation processor include a first execution mode and a second execution mode. The simulation processor in the first execution mode continuously executes multiple initial instructions, and the simulation processor in the second execution mode stops executing the initial instruction after executing a preset number of initial instructions.

[0153] In some embodiments, the preset event is a second preset event, the second preset event is that a target breakpoint in the program to be debugged is triggered, and the target breakpoint is one of at least one breakpoint of the program to be debugged.

[0154] In some embodiments, at least one command to be executed includes a second command to be executed. The first execution module includes: a second execution submodule, which is used to execute the second command to be executed using the simulation processor to obtain a second simulation execution result. The second simulation execution result includes state information of the simulation device, and the state information includes at least one of first state sub-information and second state sub-information, the first state sub-information is used to characterize the state of the first simulation register of the initial instruction, and the second state sub-information is used to characterize the state of the simulation storage unit.

[0155] In some embodiments, the device further includes: a third execution module for executing the first switching command using the simulation processor in response to receiving the first switching command via the command named pipe, so that the simulation processor switches from the first execution mode to the second execution mode.

[0156] In some embodiments, the device further comprises: a fourth execution module for executing the second communication exit command in response to receiving the second communication exit command via the command named pipe, so that the simulation processor obtains the initial instruction according to the simulation address in the second simulation register.

[0157] In some embodiments, the preset event is a third preset event, and the third preset event is that the simulation processor in the second execution mode has executed a preset number of initial instructions. The simulation processor switches to the second execution mode after the target breakpoint of the program to be debugged is triggered, and the target breakpoint is one of the programs to be debugged.

[0158] In some embodiments, it also includes: a fifth execution module, which is used to execute the second switching command using the simulation processor in response to receiving the second switching command via the command named pipe, so that the simulation processor switches from the second execution mode to the first execution mode.

[0159] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0160] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0161] Figure 8A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0162] like Figure 8 As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 to a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0163] A number of components in the device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0164] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSP), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as program debugging methods. For example, in some embodiments, the program debugging method may be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the program debugging method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to execute the program debugging method in any other appropriate manner (for example, by means of firmware).

[0165] Various embodiments of the systems and techniques described above herein may be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard parts (ASSPs), system on chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0166] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0167] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media may include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories, read-only memories, erasable programmable read-only memories (EPROM) or flash memories, optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0168] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a cathode ray tube (CRT) display or a liquid crystal display (LCD)) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0169] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a Local Area Network (LAN), a Wide Area Network (WAN), and the Internet.

[0170] A computer system may include clients and servers. Clients and servers are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship to each other.

[0171] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0172] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A program debugging method, comprising: In response to receiving a notification corresponding to a preset event, providing at least one to-be-executed command to a simulation device via a command named pipe, wherein the simulation device includes a simulation processor, the simulation processor is a simulation artificial intelligence processor, and the preset event is an event occurring during the execution of the program to be debugged by the simulation processor; At least one simulation execution result corresponding to at least one of the to-be-executed commands is received via a result named pipe.

2. The method according to claim 1, wherein: The notifications are received via the notification named pipe.

3. The method according to claim 1, wherein: The preset event is a first preset event, and the first preset event is that the simulation processor starts to execute the program to be debugged.

4. The method according to claim 3, wherein: At least one of the commands to be executed includes a first command to be executed, which is used to instruct the simulation processor to save at least one initial instruction related to the breakpoint of the program to be debugged and add a virtual trap instruction at the breakpoint, and the virtual trap instruction is used to block the execution of the program to be debugged.

5. The method according to claim 4, wherein: The simulation device also includes a simulation storage unit, The method further comprises: Obtaining program address information of the program to be debugged in the simulation storage unit via the result named pipe; Parsing debugging information corresponding to the program to be debugged to obtain at least one offset value, wherein the offset value corresponds to one of the breakpoints; At least one breakpoint address information is determined according to the program address information and at least one of the offset values.

6. The method according to claim 3, further comprising: A first communication exit command is provided to the simulation device via the command named pipe, wherein the first communication exit command is used to instruct the simulation processor to execute the program to be debugged.

7. The method according to claim 1, wherein: The analog device further includes at least one of an analog storage unit, a first analog register, and a second analog register, The initial instruction of the program to be debugged is used to be processed according to the data in the first simulation register. When executing the initial instruction of the program to be debugged, the simulation processor obtains the initial instruction according to the simulation address in the second simulation register. The multiple execution modes of the simulation processor include a first execution mode and a second execution mode. The simulation processor in the first execution mode continuously executes multiple initial instructions, and the simulation processor in the second execution mode stops executing initial instructions after executing a preset number of initial instructions.

8. The method according to claim 7, wherein: The preset event is a second preset event, the second preset event is that a target breakpoint in the program to be debugged is triggered, and the target breakpoint is one of at least one breakpoint of the program to be debugged.

9. The method according to claim 3 or 8, wherein: At least one of the pending commands includes a second pending command, and the second pending command is used to instruct the simulation device to adjust or return the status information of the simulation device, and the status information includes at least one of first status sub-information and second status sub-information, the first status sub-information is used to characterize the status of the first simulation register of the initial instruction, and the second status sub-information is used to characterize the status of the simulation storage unit.

10. The method according to claim 8, further comprising: storing at least one initial instruction associated with the target breakpoint in the first buffer of the emulation storage unit; Writing the simulated address of the initial instruction in the first buffer into the second simulated register; A first switching command is provided to the simulation device via the command named pipe, so that the simulation processor switches from the first execution mode to the second execution mode.

11. The method according to claim 10, further comprising: A second communication exit command is provided to the simulation device via the command named pipe, so that the simulation processor obtains an initial instruction according to the simulation address in the second simulation register.

12. The method according to claim 7, wherein: The preset event is a third preset event, and the third preset event is that the simulation processor in the second execution mode has executed the preset number of initial instructions. The simulation processor switches to the second execution mode after the target breakpoint of the program to be debugged is triggered, and the target breakpoint is one of at least one breakpoint of the program to be debugged.

13. The method according to claim 11, wherein: Providing at least one to-be-executed command to the simulation device via the command named pipe comprises: Displaying a notification corresponding to the third preset event on a visual interface; The user input command is provided to the simulation device as a third command to be executed via the command named pipe.

14. The method according to claim 10 or 13, further comprising: A second switching command is provided to the simulation device via the command named pipe, so that the simulation processor switches from the second execution mode to the first execution mode.

15. The method according to claim 13, further comprising: The simulated address of the initial instruction after the target breakpoint is written into the second simulated register.

16. A program debugging method, comprising: In response to determining that a preset event occurs, sending a notification corresponding to the preset event via a notification named channel; In response to receiving at least one to-be-executed command via the command named pipe, executing at least one of the to-be-executed commands using a simulation processor of a simulation device to obtain at least one simulation execution result, wherein the simulation processor is a simulation artificial intelligence processor; At least one simulation execution result corresponding to at least one of the to-be-executed commands is sent via a result named pipe.

17. The method according to claim 16, wherein: The preset event is a first preset event, and the first preset event is that the simulation processor starts to execute the program to be debugged.

18. The method according to claim 17, wherein: At least one of the pending commands includes a first pending command, The using a simulation processor of a simulation device to execute at least one of the commands to be executed to obtain at least one simulation execution result comprises: The first to-be-executed command is executed using the simulation processor to save at least one initial instruction related to the breakpoint of the program to be debugged and add a virtual trap instruction at the breakpoint to obtain a first simulation execution result, wherein the first simulation execution result is used to indicate that the virtual trap instruction has been added at all breakpoints of the program to be debugged, and the virtual trap instruction is used to block the execution of the program to be debugged.

19. The method according to claim 17, wherein: The simulation device also includes a simulation storage unit, The method further comprises: The program address information of the program to be debugged in the simulation storage unit is sent via the result named pipe.

20. The method of claim 17, further comprising: In response to receiving a first communication exit command via the command named pipe, the first communication exit command is executed to execute the program to be debugged using the simulation processor.

21. The method according to claim 16, wherein: The analog device further includes at least one of an analog storage unit, a first analog register, and a second analog register, The initial instruction of the program to be debugged is used to be processed according to the data in the first simulation register. When executing the initial instruction of the program to be debugged, the simulation processor obtains the initial instruction according to the simulation address in the second simulation register. The multiple execution modes of the simulation processor include a first execution mode and a second execution mode. The simulation processor in the first execution mode continuously executes multiple initial instructions, and the simulation processor in the second execution mode stops executing the initial instructions after executing a preset number of the initial instructions.

22. The method according to claim 21, wherein: The preset event is a second preset event, the second preset event is that a target breakpoint in the program to be debugged is triggered, and the target breakpoint is one of at least one breakpoint of the program to be debugged.

23. The method according to claim 22, wherein: At least one of the pending commands includes a second pending command, The using a simulation processor of a simulation device to execute at least one of the commands to be executed to obtain at least one simulation execution result comprises: The second command to be executed is executed by the simulation processor to obtain a second simulation execution result, wherein the second simulation execution result includes status information of the simulation device, and the status information includes at least one of first status sub-information and second status sub-information, the first status sub-information is used to characterize the status of the first simulation register of the initial instruction, and the second status sub-information is used to characterize the status of the simulation storage unit.

24. The method according to claim 23, further comprising: In response to receiving a first switch command via the command named pipe, the first switch command is executed by the simulation processor so that the simulation processor switches from the first execution mode to the second execution mode.

25. The method according to claim 24, further comprising: In response to receiving a second communication exit command via the command named pipe, executing the second communication exit command causes the emulation processor to fetch an initial instruction according to the emulation address in the second emulation register.

26. The method according to claim 21, wherein: The preset event is a third preset event, and the third preset event is that the simulation processor in the second execution mode has executed the preset number of initial instructions. The simulation processor switches to the second execution mode after the target breakpoint of the program to be debugged is triggered, and the target breakpoint is one of the programs to be debugged.

27. The method according to claim 25 or 26, wherein: Also includes: In response to receiving a second switch command via the command named pipe, the second switch command is executed by the simulation processor so that the simulation processor switches from the second execution mode to the first execution mode.

28. A program debugging device, comprising: A first providing module is configured to provide at least one to-be-executed command to a simulation device via a command named pipe in response to receiving a notification corresponding to a preset event, wherein the simulation device includes a simulation processor, the simulation processor is a simulation artificial intelligence processor, and the preset event is an event occurring during the execution of the program to be debugged by the simulation processor; The first receiving module is used to receive at least one simulation execution result corresponding to at least one of the to-be-executed commands via a result named pipe.

29. The device according to claim 28, wherein The notifications are received via the notification named pipe.

30. A program debugging device, comprising: A first sending module, configured to send a notification corresponding to the preset event via a notification named channel in response to determining that a preset event occurs; A first execution module is configured to, in response to receiving at least one to-be-executed command via a command named pipe, execute at least one to-be-executed command using a simulation processor of a simulation device to obtain at least one simulation execution result, wherein the simulation processor is a simulation artificial intelligence processor; The second sending module is used to send at least one simulation execution result corresponding to at least one of the to-be-executed commands via a result named pipe.

31. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 27.

32. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 27.

33. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 27.

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