ZYNQ-based multifunctional analog instrument test acquisition card and data processing method

Abstract

The invention discloses a multifunctional analog instrument acquisition card based on a ZYNQ-7000 chip and a data processing method. The acquisition card takes a ZYNQ-7000 series main control chip as a core, a PS end is responsible for data storage and network transmission, and a PL end covers a data acquisition module, a data output module, a data cache module and the like. A four-channel single-channel ADC circuit is adopted for data acquisition, and the data is cached and converted by FIFO and then transmitted to a PS end by DMA; the signal output module generates an analog signal according to an instruction of the upper computer; high-speed and stable data transmission is realized by means of multi-channel DMA; the Ethernet module guarantees communication with an upper computer. By utilizing the unique architecture of the ZYNQ chip and combining the cooperative operation of each functional module, the system has the advantages of modularization, high precision, high-speed processing, expandability and the like, effectively solves many defects of an existing data acquisition system, can be widely applied to analog signal acquisition and processing in multiple fields, improves the efficiency and precision of data acquisition and processing, and has a great market application prospect.

Description

Technical Field

[0001] The present invention relates to the technical field of data output and acquisition, and in particular to a multifunctional analog instrument test acquisition card based on ZYNQ and a data processing method. Background Art

[0002] Zynq is an innovative chip. Unlike traditional FPGAs, it is a chip with a programmable system-on-chip. Its full name is Zynq-7000 All Programmable SoC, which is tightly integrated with a dual-core ARM Cortex-A9 processor and a traditional field programmable gate array (FPGA) logic component. This unique architecture enables Zynq to excel in meeting the stringent requirements of complex embedded systems for high performance, low power consumption, and multi-core processing capabilities. Based on the SoC characteristics of the ARM processor, Zynq has powerful capabilities in processing complex algorithms, control logic, and communicating with external devices. At the same time, with the programmability of FPGA, it can flexibly implement various hardware acceleration functions, such as high-speed data processing and interface customization.

[0003] In recent years, my country's integrated circuit industry has developed rapidly, covering multiple links such as design, manufacturing, packaging, and testing. Among them, the testing link runs through the entire industry chain and is crucial. In the integrated circuit manufacturing stage, each component needs to be accurately tested to ensure that its performance meets the requirements; after the packaging is completed, the circuit board must be fully functional and parameter tested to ensure product quality. The position of automated testing technology in the integrated circuit industry is becoming increasingly prominent. It not only significantly improves the detection efficiency, but also greatly enhances the accuracy of the detection. As the first step in information processing, data acquisition has become increasingly important with technological progress and has been widely used in many fields. In addition, as various applications continue to increase their requirements for data quality, the accuracy required by the data acquisition system is becoming increasingly demanding, which has brought challenges and created opportunities for the development of data acquisition technology.

[0004] However, the existing data acquisition system has limitations in the single-chip solution and problems with the coordination between FPGA, ARM and DSP. In the current technical field, many companies' automated production lines often use hardware solutions with single-chip microcomputers as the main control chip to realize the acquisition function. Although this solution is low-cost, it has obvious defects. Due to the relatively weak processing power of the single-chip microcomputer, its acquisition speed is severely limited by the operating speed and processing cycle of the processor, which makes it difficult to meet the demand for high-speed signal acquisition. In addition, the traditional parallel transmission bus interface is widely used in this solution, but this type of interface has problems such as weak signal anti-interference ability and slow data transmission speed, and cannot adapt to the task of acquiring large amounts of data signals.

[0005] Due to the particularity of its circuit design, FPGA has extremely strong parallel processing capabilities, but in terms of data processing, its performance is slightly inferior to that of ARM and DSP, and its logic design is complex and the development cost is high. In order to make up for their respective shortcomings, the processors are often used to work together. However, the separate processing architecture of FPGA and ARM or DSP adopted by most acquisition systems currently not only leads to a significant increase in costs, but also makes the circuit design extremely complicated. At the same time, different processors require different development platforms, which significantly prolongs the development cycle and is not conducive to the rapid iteration and application of products.

[0006] In addition, there are many system defects in using a single multi-channel acquisition ADC. Although some designs have abandoned the traditional acquisition system and selected the Zynq-7000 series SoC produced by Xilinx, which integrates FPGA and ARM internally, as the main control chip, the efficiency has been improved to a certain extent. However, most of these systems use a single multi-channel acquisition ADC to realize the data acquisition function. In actual work, the collected multi-channel analog signals need to switch the circuit, and after each circuit switch, it is necessary to wait for the sampling circuit to stabilize in order to obtain a stable signal voltage. As the system sampling time increases, the errors at the time of acquisition of each analog signal will gradually accumulate and become larger and larger, which is extremely unfavorable for the subsequent analysis and processing after data acquisition, and may lead to problems such as inaccurate analysis results and poor processing effects.

[0007] The data transmission method of ZYNQ heterogeneous chips also has disadvantages. Xilinx's ZYNQ heterogeneous chips consist of an FPGA core and an ARM core. When interacting between FPGA and ARM, if the traditional interrupt or query data transmission method is used, the ARM core will frequently participate in the control of every instruction in the system, which will greatly reduce the system transmission efficiency. Moreover, under this data transmission method, the data transmission speed between ARM and FPGA is slow and unstable, which cannot meet the application scenarios with high real-time requirements, and seriously restricts the overall performance and application scope of the system. Summary of the invention

[0008] In view of the above-mentioned problems existing in the prior art, the present invention aims to provide a multifunctional analog instrument test acquisition card and data processing method based on ZYNQ, and is committed to designing a strictly synchronous data generation and acquisition device with the characteristics of modularization, high-speed processing, large-capacity storage, low power consumption, and flexible and scalable, and matching corresponding data processing methods, so as to effectively overcome the defects of the prior art and meet the urgent needs of various fields for high-precision and high-efficiency data acquisition and processing.

[0009] In order to solve the above technical problems, this application provides the following technical solutions:

[0010] A ZYNQ-based analog instrument circuit test acquisition card adopts the ZYNQ-7000 series main control chip. The PS end of the main control chip is responsible for the storage of raw data and network data transmission, including ARM hard core, large-capacity DDR3 storage and TCP Ethernet; the PL end is responsible for data acquisition, output and caching, including:

[0011] The data acquisition module adopts a four-way single-channel ADC acquisition circuit. The ADC chip is AD9280, with a maximum conversion rate of 32MSPS and a data bit width of 8bit. It integrates a sample-and-hold amplifier and a power reference source. Single-ended input or differential input can be selected according to actual needs. The data acquisition module is used to serialize the collected parallel data, cache and align the data with the help of the FIFO module, convert it into AXI-Stream stream data, and transmit it to the PS end through DMA;

[0012] The signal output module is mainly composed of DDS, including phase accumulator, phase modulator, waveform data table ROM, AD9708 converter, which is used to receive the waveform data generated by the host computer and convert it into analog signal for signal output;

[0013] FIFO buffer module, built on RAM, has the feature of first-in-first-out, does not require address lines, can cache data efficiently, and its writing and reading are carried out under clock control;

[0014] The data transmission module includes a DMA control unit. The DMA control unit is designed with four channels. Each channel independently receives different AXI-Stream data streams and uses a FIFO to cache the data streams. The ARM core can initialize the DMA control unit and assign different interrupt numbers to each channel. The data directly accesses the specified address unit of the DDR memory through the S2MM interface. The DMA adopts the Direct direct transmission mode. The length register bit width of the buffer area Buffer is 23 bits, and the address bit width is 32 bits. The DMA's s_axi_lite_aclk adopts the 50MHz clock frequency of the ZYNQ GP interface, and the m_axi__s2mm interface adopts the 100MHz clock frequency of the ZYNQ HP interface. The reset adopts the Global low-level reset;

[0015] Ethernet module, ZYNQ as Client, PC as Server, using Xilinx's embedded development environment SDK, select lwip protocol as Ethernet protocol stack, first initialize the Ethernet lwip protocol stack, then initialize the TCP configuration parameters, network address, port number, and storage space, and transmit the data of the four channels to the host computer through channel traversal. After the data transmission of each channel is completed, the Tcp_Flag signal is pulled high. Before transmission, the network port connection function is used to make the ZYNQ end actively initiate a TCP connection request to the PC end and complete the three-way handshake to establish a TCP network connection.

[0016] The present invention is based on the multifunctional analog instrument test acquisition card of ZYNQ, which is based on the ZYNQ-7000 series main control chip. The PS end of the main control chip is responsible for the storage of raw data and network data transmission, and its components include ARM hard core, large-capacity DDR3 storage and TCP Ethernet. The PL end focuses on data acquisition, output and cache work, covering key components such as ADC, DAC, signal output module, data acquisition module, FIFO cache module, etc.

[0017] The present invention also provides an analog instrument circuit test data acquisition method based on ZYNQ, an analog instrument circuit test signal output method based on ZYNQ, and an analog instrument circuit test data transmission method based on ZYNQ.

[0018] in:

[0019] Data acquisition module

[0020] A four-way single-channel ADC acquisition circuit is used, and the ADC chip selected is AD9280. The chip has a maximum conversion rate of up to 32MSPS and a data bit width of 8bit. It integrates a sample-and-hold amplifier and a power reference source, and can flexibly select single-ended input or differential input according to the actual application scenario. When working, the data acquisition module first collects the input data of the analog instrument circuit to obtain parallel data. Then, with the help of the FIFO module, these parallel data are cached and aligned to match the data bit width, and then converted into AXI-Stream stream data. Finally, the converted data is accurately transmitted to the PS end through DMA transmission.

[0021] Signal output module

[0022] It is mainly composed of DDS (digital synthesizer), and its internal structure includes important components such as phase accumulator, phase modulator, waveform data table ROM, AD9708 converter, etc. This module can receive various waveform data generated by the host computer, such as sine wave, square wave, sawtooth wave, etc. The host computer first converts the generated waveform data into a COE file in the memory format, and then sets the signal parameters and sends the data through Ethernet. After receiving the data, the signal output module of the acquisition card writes it into the waveform data table ROM, and then the data is read from the ROM, and the digital signal is accurately converted into an analog signal by the AD9708 digital-to-analog converter, and finally the signal is output.

[0023] FIFO buffer module

[0024] Built on RAM, it has the remarkable feature of first-in-first-out (FIFO) and can work efficiently without address lines. Its write and read operations are performed under the precise control of the clock. When the write enable (wr_en) signal is pulled high, the data (din) begins to be written into the FIFO; when the read enable (rd_en) signal is pulled high, the FIFO begins to read the data and outputs the read data in the next clock cycle. FIFO also has multiple status signals, such as full means full, almost_full means almost full, wr_ack means write operation response, over_flow means overflow, valid means the read data is valid, almost_empty means almost empty, empty means empty, and underflow means read empty. These status signals can indicate the cache status of the FIFO in real time, providing an important reference for the stable operation of the system.

[0025] Data transmission module

[0026] The core component is the DMA control unit, which is carefully designed with four channels. Each channel receives different AXI-Stream data streams independently and is equipped with a FIFO to cache the data streams. The ARM core can fully initialize the DMA control unit, including assigning a unique interrupt number to each channel and setting various parameters of the DMA engine, such as the address of the channel DMA engine, the memory address of the sent data, the length of the data to be sent, and the DMA transmission direction. DMA uses the Direct direct transmission mode, and the length register width of its buffer area Buffer is set to 23 bits and the address width is 32 bits to match the AXI bus (ZYNQ is a 32-bit bus width). The DMA's s_axi_lite_aclk uses the 50MHz clock frequency of the ZYNQ GP interface, the m_axi__s2mm interface uses the 100MHz clock frequency of the ZYNQ HP interface, and the reset uses the Global low-level reset method. Eight-way DMA requires eight DMA interrupts. Through a Connect IP core, four DMA interrupts are cleverly integrated into one data, and then connected to the IRQ_F2P interrupt interface of the ZYNQ core to ensure the efficiency and stability of data transmission.

[0027] Ethernet Module

[0028] In the present invention, ZYNQ acts as the Client, and the PC host computer acts as the Server. The embedded development environment SDK of Xilinx is adopted, and the lwip protocol is selected as the Ethernet protocol stack. First, the Ethernet lwip protocol stack is initialized, and then the TCP configuration parameters, network address, port number, storage space, etc. are carefully initialized. During the data transmission process, the channel traversal method is adopted to transmit the data of the four channels in the acquisition card to the host computer in sequence and in an orderly manner. Before each channel data transmission, the network port connection function tcp_client_connect is used to make the ZYNQ end actively initiate a TCP connection request to the PC host computer, and complete the three-way handshake process of the TCP connection. After the TCP network connection is successfully established, data transmission begins. After the data transmission of each channel is completed, the Tcp_Flag signal is pulled high to indicate the smooth progress of the Ethernet transmission.

[0029] Compared with the prior art, the multifunctional analog instrument test acquisition card and data processing method based on ZYNQ of the present invention have at least the following beneficial effects:

[0030] 1. The present invention adopts a modular design concept, and each functional module is independent of each other but works together. This design method makes the system highly extensible, and functional modules can be easily added or modified according to actual needs without large-scale changes to the entire system, effectively reducing the cost of system upgrades and maintenance and extending the product life cycle.

[0031] 2. Advantages of four-way single-channel ADC acquisition circuit

[0032] The four-way single-channel ADC acquisition circuit effectively avoids the signal delay problem caused by the circuit switching process compared to the traditional multi-channel acquisition ADC. This design ensures the accuracy and real-time performance of data acquisition, and provides a reliable data basis for subsequent data processing and analysis. At the same time, the ADC does not require additional complex software design, and can run automatically by simply connecting to the corresponding clock, which greatly simplifies the development process, improves development efficiency, and reduces development costs.

[0033] 3. Multi-channel DMA technology improves system performance

[0034] The system innovatively adopts multi-channel DMA technology to establish a direct data transmission channel between memory and memory, memory and peripherals. During the data transmission process, the data transmission of the memory mapping space can be completed without the frequent participation of the ARM core. The multi-channel DMA can simultaneously transmit multiple channels of data in real time and at high speed, allowing the ARM-side central processing unit to focus on signal processing and system function control, significantly improving the overall performance of the system and enhancing the system's real-time response capability.

[0035] 4. Advantages of customization based on AXI4 bus

[0036] This system is customized based on the AXI4 bus, and the number of transmission channels can be flexibly customized according to actual needs. It supports fixed-point high-speed transmission of data with a maximum bit width of 32 bits, and has strong compatibility, and can support DMA packet transmission of data from different channels with variable length and address. This flexible transmission method can effectively adapt to diverse data transmission needs and improve the system's data processing capabilities and transmission efficiency.

[0037] 5. Leverage Zynq’s existing DDR storage resources

[0038] Without using peripheral resources, ZYNQ's existing DDR storage resources are fully utilized to greatly improve the transmission and storage capabilities of multiple types of data. This not only reduces the dependence on external storage devices, reduces system cost and complexity, but also increases the speed of data storage and access, further improving the overall performance of the system.

[0039] The multifunctional analog instrument test acquisition card and data processing method based on ZYNQ of the present invention will be further described below in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 The overall system design block diagram of the multifunctional analog instrument test acquisition card based on ZYNQ of the present invention;

[0041] Figure 2 This is a flow chart of the data acquisition module of the multifunctional analog instrument test acquisition card based on ZYNQ of the present invention;

[0042] Figure 3 This is a flow chart of the data output module of the multifunctional analog instrument test acquisition card based on ZYNQ of the present invention;

[0043] Figure 4 This is a timing diagram of writing the FIFO standard of the multifunctional analog instrument test acquisition card based on ZYNQ of the present invention;

[0044] Figure 5 It is a timing diagram of the FIFO standard reading operation of the multifunctional analog instrument test acquisition card based on ZYNQ of the present invention;

[0045] Figure 6 It is a schematic diagram of the four-channel DMA design of the multifunctional analog instrument test acquisition card based on ZYNQ of the present invention;

[0046] Figure 7 This is a flow chart of the data transmission module of the multifunctional analog instrument test acquisition card based on ZYNQ of the present invention;

[0047] Figure 8 The present invention is a flowchart of the Ethernet module of the multifunctional analog instrument test acquisition card based on ZYNQ. DETAILED DESCRIPTION

[0048] In the ZYNQ-based analog instrument circuit test acquisition card of the present invention, data processing mainly covers core links such as data acquisition, transmission and storage, and each link closely cooperates and is deeply integrated with the overall system architecture.

[0049] like Figure 1As shown, it is a system overall design block diagram of the multifunctional analog instrument test acquisition card based on ZYNQ of the present invention. It mainly includes the connection relationship between the PS end and the PL end of the ZYNQ main control chip, including the connection mode between the ARM hard core, DDR3 storage, TCP Ethernet, ADC, DAC, signal output module, data acquisition module, FIFO cache module, DMA control unit and other components. The PS end of the ZYNQ-7000 series main control chip is responsible for the storage of raw data and network data transmission, including ARM hard core, large-capacity DDR3 storage and TCP Ethernet; the PL end is responsible for data acquisition, output and caching.

[0050] The main structure of the multifunctional analog instrument test acquisition card based on ZYNQ of the present invention is now described as follows in conjunction with the accompanying drawings:

[0051] 1. Clock management

[0052] In the overall programming of ZYNQ, based on Figure 1 The system architecture shown in the figure is very important for the clock management program on the PL side. This system is based on the XC7Z020 core board, which provides a variety of clock sources such as a 50MHz crystal oscillator. When the FPGA is working, the clock is accurately managed by calling the matching IP core. Figure 1 As can be seen in the figure, each module has a close connection with the clock source. For example, the data acquisition module and the signal output module all rely on accurate clock signals to coordinate their work. By reasonably allocating and regulating the clock, it is ensured that each module can obtain the required clock frequency, so that each module can work stably at an appropriate speed, thereby strictly ensuring the clock synchronization of the entire test board system. For example, the ADC chip AD9280 in the data acquisition module requires a clock signal of a specific frequency to drive it to work at a maximum conversion rate of 32MSPS. The clock management program can accurately provide this signal to avoid data acquisition errors or performance degradation caused by inaccurate clock frequency.

[0053] 2. Data acquisition module,

[0054] A four-way single-channel ADC acquisition circuit is used. The ADC chip is AD9280, with a maximum conversion rate of 32MSPS and a data bit width of 8bit. It integrates a sample-and-hold amplifier and a power reference source. Single-ended input or differential input can be selected according to actual needs. The operating voltage range is 2.7V-5.5V. The data acquisition module is used to serialize the collected parallel data, cache and align the data with the help of the FIFO module, convert it into AXI-Stream stream data, and transmit it to the PS end through DMA;

[0055] Specifically, see Figure 1 , Figure 2,Include:

[0056] 1) ADC configuration and data collection (see Figure 1 )

[0057] The data acquisition module uses the AD9280 chip for data acquisition. Figure 1 First, the registers of AD9280 are properly configured through ARM to determine its working mode (single-ended or differential input) and other parameters. Then, AD9280 collects the input data of the analog instrument circuit according to the set maximum conversion rate of 32MSPS and 8-bit data width to obtain parallel data. In this process, according to Figure 1 The connection relationship between the data acquisition module and the ADC is that the data flows from the analog instrument circuit into the ADC and then enters the subsequent processing flow of the data acquisition module.

[0058] 2) Data caching and conversion (see Figure 1 , Figure 2 )

[0059] The collected parallel data is sent to the FIFO module for buffering and alignment. Figure 2 The data acquisition module flow chart shows the operation flow of data in the FIFO module. Under the control of the clock signal, the FIFO module manages data in order according to the first-in-first-out principle. When data is written to the FIFO, the write enable signal (wr_en) is pulled high at the corresponding clock edge, and the data is stored in the FIFO in sequence. At the same time, the FIFO module monitors its cache status to prevent data overflow (judged by the over_flow signal). When data needs to be read, the read enable signal (rd_en) is pulled high, and the FIFO outputs the cached data in sequence and converts it into AXI-Stream stream data. Figure 1 It can be seen that the FIFO module plays a bridge role in data caching and format conversion between the data acquisition module and the DMA control unit, ensuring that the data can smoothly enter the DMA transmission link.

[0060] 3) DMA transfer (see Figure 1 , Figure 2 , Figure 6 , Figure 7 )

[0061] The converted AXI-Stream data is transferred to the PS via DMA. Figure 6 and Figure 7 , the DMA control unit assigns an interrupt number to each channel and sets related parameters under the initialization of the ARM core. Figure 1It can be seen that data is read from FIFO by DMA, and then accurately transmitted to the DDR3 storage on the PS side through the S2MM interface according to the preset address unit. During the transmission process, DMA strictly follows the Direct transmission mode to ensure efficient and stable data transmission. For example, Figure 7 The whole process of DMA engine initialization, interrupt initialization, parameter configuration and DMA transmission startup is shown in detail in Figure 1 The paths in which the data acquisition module transmits data to the PS end through DMA correspond to each other, ensuring the accuracy of data from acquisition to storage.

[0062] 3. Signal output module (see Figure 1 , Figure 3 )

[0063] The signal output module is mainly composed of DDS, including phase accumulator, phase modulator, waveform data table ROM, AD9708 converter, which is used to receive any waveform data with a width of 8 bits and a depth of 256 generated by the host computer, such as sine wave, square wave, sawtooth wave and other waveforms, and convert them into COE files in memory format. The host computer sets signal parameters and sends data through Ethernet. After the data is written into ROM, the digital signal is converted into an analog signal by the AD9708 digital-to-analog converter and then the signal is output;

[0064] 1) Host computer data preparation

[0065] like Figure 1 As shown in the figure, the host computer generates specific waveform data as needed, such as sine wave, square wave or sawtooth wave, etc. The generated waveform data is converted into a COE file in the memory format. Then, the host computer sets the signal parameters such as waveform frequency, amplitude, etc. through Ethernet, and sends the COE file data to the acquisition card. Figure 1 As can be seen in the figure, the host computer and the signal output module of the acquisition card establish a connection through the Ethernet module to achieve data transmission and interaction.

[0066] 2) Data writing and conversion output

[0067] See also Figure 1 , Figure 3 After the signal output module of the acquisition card receives the data, it writes it into the waveform data table ROM. Figure 3 The data output module flow chart shows that the writing process is managed by the control logic inside the DDS to ensure that the data is accurately stored in the ROM. When the output signal is required, the data is read from the ROM, processed by the phase accumulator, phase modulator and other components in turn, and finally converted into an analog signal by the AD9708 digital-to-analog converter and output to an external device or circuit. Figure 1In the figure, the connection relationship between the components inside the signal output module shows the complete path of data from receiving data from the host computer to the final output of the analog signal. The components work together to complete the signal output function.

[0068] 4. FIFO buffer module implementation

[0069] See also Figure 4 , Figure 5 ,FIFO cache module, is built on RAM, has the characteristics of first-in-first-out, does not require address lines, can cache data efficiently, and its writing and reading are carried out under clock control, data is written when the write enable is pulled high, and data is read when the read enable is pulled high, and has a corresponding status signal to indicate the cache status;

[0070] The FIFO buffer module is built on RAM in hardware design. Figure 4 It can be seen from the write timing diagram of the FIFO standard that the write enable (wr_en) and read enable (rd_en) signals are pulled high or low by the system control logic according to the data transmission requirements. When there is data to be cached, the write enable signal is pulled high at the rising edge (or falling edge, depending on the specific design) of the clock, and the data is written to the FIFO bit by bit under the control of the clock. At the same time, the logic circuit inside the FIFO monitors the cache status in real time, such as judging whether it is about to be full through the full and almost_full signals, so that the system can take corresponding measures, such as suspending data writing or performing data transfer operations. When reading data, refer to Figure 5 The timing diagram of the FIFO standard read operation is as follows. The read enable signal is pulled high, and the FIFO outputs the data in sequence under the control of the clock. At the same time, the valid signal indicates the validity of the output data. The almost_empty and empty signals help the system determine whether the FIFO is about to be read empty or is empty, avoiding data errors caused by empty read operations. Figure 4 and Figure 5 The timing diagram in the figure shows in detail the precise operation timing of the FIFO cache module during data writing and reading, providing a reliable basis for the system in data cache management.

[0071] 5. Implementation of data transmission module

[0072] Please combine Figure 1 , Figure 6 , Figure 7, the data transmission module includes a DMA control unit. The DMA control unit is designed with four channels. Each channel independently receives different AXI-Stream data streams and uses a FIFO to cache the data streams. The ARM core can initialize the DMA control unit and assign different interrupt numbers to each channel. The data directly accesses the specified address unit of the DDR memory through the S2MM interface. The DMA adopts the Direct direct transmission mode. The length register bit width of the buffer area Buffer is 23 bits, and the address bit width is 32 bits. The DMA's s_axi_lite_aclk adopts the 50MHz clock frequency of the ZYNQ GP interface, and the m_axi__s2mm interface adopts the 100MHz clock frequency of the ZYNQ HP interface. The reset adopts the Global low-level reset;

[0073] 1) DMA control unit initialization

[0074] See also Figure 6 , Figure 7 , when the system starts, the ARM core fully initializes the DMA control unit. Figure 6 The four-channel DMA design assigns different interrupt numbers to the four channels. For example, channel 1 is assigned interrupt number 5, channel 2 is assigned interrupt number 6, etc., to ensure that after the data transmission of each channel is completed, an interrupt notification can be accurately sent to the ARM core. Then, refer to Figure 7 , set the parameters of the DMA engine, including the address of each channel DMA engine, such as the DMA engine address of channel 1 is set to 0x20000000, the memory address of the sent data is the data storage address of the corresponding channel of the data acquisition module, the length of the data to be sent is determined according to the actual amount of collected data, and the DMA transmission direction, etc. Figure 6 The connection relationship between the DMA control unit and each channel FIFO buffer and DDR memory can be clearly seen, which provides an intuitive reference for parameter setting and ensures the accuracy of the initialization process.

[0075] 2) Data transmission process

[0076] Combination Figure 1 , Figure 6 , Figure 7 It can be seen that when the AXI-Stream data stream of the data acquisition module is input to the AD9208_Stream IP core at the front end of each channel of the DMA control unit, combined with Figure 6 These IP cores convert the data format into the AXI-Stream data format supported by the AXI4 bus and store it in the corresponding FIFO buffer. Figure 7The ARM core starts the DMA sending instruction, and the DMA control unit drives the data from the FIFO buffer to the specified address unit of the DDR memory through the S2MM interface according to the preset parameters. Figure 6 It can be seen that DMA uses Direct transfer mode, and the length register width of its buffer Buffer is 23 bits, and the address width is 32 bits to match the AXI bus (ZYNQ has a 32-bit bus width). DMA's s_axi_lite_aclk uses the 50MHz clock frequency of the ZYNQ GP interface, and the m_axi__s2mm interface uses the 100MHz clock frequency of the ZYNQ HP interface. The reset uses the Global low-level reset method. Eight-way DMA requires eight DMA interrupts. Four DMA interrupts are integrated into one data through a Connect IP core, and then connected to the IRQ_F2P interrupt interface of the ZYNQ core. This integration process is Figure 6 It is clearly displayed in the system to ensure the efficiency and accuracy of interrupt processing during data transmission and to ensure stable data transmission in the system.

[0077] 6. Ethernet module implementation

[0078] Combination Figure 1 , Figure 8 It can be seen that in the Ethernet module, ZYNQ is used as the Client and the PC host computer is used as the Server. The embedded development environment SDK of Xilinx is used, and the lwip protocol is selected as the Ethernet protocol stack. The Ethernet lwip protocol stack is initialized first, and then the TCP configuration parameters, network address, port number, and storage space are initialized. The data of the four channels are transmitted to the host computer through channel traversal. After the data transmission of each channel is completed, the Tcp_Flag signal is pulled high. Before transmission, the network port connection function is used to make the ZYNQ end actively initiate a TCP connection request to the PC end and complete the three-way handshake to establish a TCP network connection.

[0079] 1) Ethernet communication link establishment

[0080] Combination Figure 8 After running Xilinx's embedded development environment SDK on the ZYNQ platform, according to Figure 8The Ethernet module flow chart first initializes the Ethernet lwip protocol stack. During the initialization process, set the relevant parameters of the network layer, such as the IP address is set to 192.168.0.100, the subnet mask is set to 255.255.255.0, the gateway is 192.168.0.1, etc. At the same time, initialize the TCP configuration parameters, including setting the port number to 8888, the timeout retransmission number to 3 times, etc., and initialize the storage space, and allocate a certain amount of memory space for data caching according to the estimated data transmission volume. Figure 1 The position of the Ethernet module in the entire system architecture can be seen in the figure. It serves as a communication bridge between the acquisition card and the host computer. These initialization parameters lay the foundation for establishing a stable Ethernet connection.

[0081] 2) Data transmission is progressing in an orderly manner

[0082] Combination Figure 1 , Figure 8 When data is transmitted, according to Figure 8 The channel traversal method starts from channel 1 of the acquisition card. Before each channel data is transmitted, the network port connection function tcp_client_connect is used to enable the ZYNQ end to actively initiate a TCP connection request to the PC host computer as the server, and complete the three-way handshake to establish a TCP network connection. For example, during the first handshake, the ZYNQ end sends a SYN packet to the host computer, and the host computer returns a SYN+ACK packet after receiving it. The ZYNQ end then sends an ACK packet to complete the connection establishment. After the connection is established, the data of channel 1 begins to be transmitted, and when the transmission is completed, the Tcp_Flag signal is pulled high. After the host computer detects the signal, it prepares to receive the data of the next channel, and the cycle continues until the data of all four channels are transmitted. Figure 1 In the figure, the data interaction path between the Ethernet module and other modules of the acquisition card and the host computer is demonstrated, which ensures the accurate and efficient transmission of data between the acquisition card and the host computer through Ethernet, realizing the Ethernet communication function of the system.

[0083] Combine the following Figure 1 , Figure 2 , Figure 6 , Figure 7 The implementation process of the data processing module is described in detail:

[0084] In the analog instrument circuit test acquisition card based on ZYNQ of the present invention, data processing mainly covers core links such as data acquisition, transmission and storage. Each link works closely together and is deeply integrated with the overall system architecture. The implementation process is described in detail below with reference to the accompanying drawings.

[0085] 1. Data Collection and Preliminary Processing

[0086] like Figure 1 , Figure 2 As shown in the figure, the data acquisition module is the source of data inflow, and its operation process is closely linked to the overall system architecture. Figure 1 It can be seen that the data acquisition module is connected to a four-way single-channel ADC acquisition circuit (the ADC chip is AD9280). The ADC chip can flexibly select single-ended or differential input mode within the operating voltage range based on its own characteristics, and collect the input data of the analog instrument circuit at a maximum conversion rate of 32MSPS and a data bit width of 8bit to obtain parallel data.

[0087] Reference Figure 2 The data acquisition module flow chart is shown in Figure 1. The collected parallel data is then sent to the FIFO module for caching and alignment processing. In the FIFO module, when the write enable (wr_en) signal is pulled high at the corresponding clock edge (based on the system clock setting, in coordination with the overall clock management), the data is written bit by bit into the FIFO under the precise control of the clock signal. At the same time, the FIFO module continuously monitors the cache status through the internal logic circuit, and uses status signals such as full and almost_full to determine the data cache status to prevent data overflow. For example, when the almost_full signal is valid, the system can suspend data acquisition or adjust the data flow according to the preset strategy to ensure the stability of the data cache.

[0088] When data needs to be read, the read enable (rd_en) signal is pulled high, and the FIFO outputs the cached data in sequence and converts it into AXI-Stream data. This conversion process prepares the format for subsequent data transmission to the PS end through DMA, allowing data to flow efficiently within the system.

[0089] 2. Data transmission and DMA control

[0090] like Figure 1 , Figure 6 , Figure 7 As shown in the figure, after being converted into AXI-Stream data, the data enters the data transmission module, and the core component DMA control unit begins to play a key role. Figure 6 The four-channel DMA design architecture, the four channels of the DMA control unit independently receive different AXI-Stream data streams, and are each equipped with a FIFO to cache the data stream.

[0091] When the system starts, the ARM core fully initializes the DMA control unit (such as Figure 7First, different interrupt numbers are carefully assigned to the four channels. For example, interrupt number 10 is assigned to channel 1, and interrupt number 11 is assigned to channel 2. This measure ensures that after the data transmission of each channel is completed, an interrupt notification can be accurately sent to the ARM core, so that the ARM core can know the data transmission status in time and perform subsequent processing.

[0092] Then set the various parameters of the DMA engine, including the address of each channel DMA engine. For example, the DMA engine address of channel 1 is set to 0x30000000, the memory address of the sent data is the data storage address of the corresponding channel of the data acquisition module, the length of the data to be sent is determined based on the actual amount of collected data, and the DMA transmission direction is clearly defined as from FIFO cache to DDR memory.

[0093] When the AXI-Stream data stream of the data acquisition module is input to the AD9208_Stream IP core at the front end of each channel of the DMA control unit ( Figure 6 The positions and connections are clearly shown in the figure. These IP cores convert the data format into the AXI-Stream data format supported by the AXI4 bus and store it in the corresponding FIFO buffer. Then, the ARM core starts the DMA send instruction, and the DMA control unit drives the data from the FIFO buffer to the specified address unit of the DDR memory through the S2MM interface according to the preset parameters.

[0094] During the transmission process, DMA uses the Direct transmission mode. The length register width of its buffer Buffer is 23 bits and the address width is 32 bits to match the AXI bus (ZYNQ has a 32-bit bus width). DMA's s_axi_lite_aclk uses the 50MHz clock frequency of the ZYNQ GP interface, and the m_axi__s2mm interface uses the 100MHz clock frequency of the ZYNQ HP interface. The reset uses the Global low-level reset method. Eight-way DMA requires eight DMA interrupts. Four DMA interrupts are integrated into one data through a Connect IP core, and then connected to the IRQ_F2P interrupt interface of the ZYNQ core ( Figure 6 The integration and connection process is presented in detail) to ensure the efficiency and accuracy of interrupt processing during data transmission and to ensure stable data transmission in the system.

[0095] 3. Data storage and system collaboration

[0096] The data transferred by DMA is finally stored in the DDR3 memory on the PS side. Figure 1It can be seen that DDR3 storage is closely connected with ARM hard core and Ethernet module, etc. During data storage, ARM core can further process or manage the stored data according to system requirements, such as classifying, marking or performing preliminary data analysis operations.

[0097] At the same time, the stored data can interact with the host computer through the Ethernet module. When the host computer has a data acquisition demand, the system can read the corresponding data from the DDR3 storage according to the host computer instructions and transmit the data to the host computer through the Ethernet module. This process involves a series of operations such as the initialization of the Ethernet module, the establishment of the TCP connection, and data transmission (as described in the previous Ethernet module implementation process), and works in conjunction with the data processing module to achieve the complete life cycle management of the data in the entire system, from collection, transmission, storage to interaction with the host computer, ensuring that the system can efficiently and accurately complete the processing task of the analog instrument circuit test data.

[0098] The embodiments described above are merely descriptions of preferred implementation modes of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

[0099] Abbreviations

[0100]

[0101]

Claims

1. A multifunctional analog instrument test acquisition card based on ZYNQ, including a ZYNQ-7000 series main control chip, characterized in that: The main control chip has a PS end and a PL end, wherein the PS end is responsible for the storage of original data and network data transmission, and includes an ARM hard core, a large-capacity DDR3 storage and a TCP Ethernet; The PL side is responsible for data collection, output and caching; The data acquisition module uses a four-way single-channel ADC acquisition circuit. The ADC chip is AD9280, which has a maximum conversion rate of 32MSPS and a data bit width of 8bit. It also integrates a sample-and-hold amplifier and a power reference source. It can select single-ended or differential input mode according to actual needs. This module is used to cache, align and convert the collected parallel data into AXI-Stream stream data through the FIFO module, and then transmit it to the PS end through DMA; The signal output module is mainly composed of DDS, including phase accumulator, phase modulator, waveform data table ROM, AD9708 digital-to-analog converter, which is used to receive the waveform data generated by the host computer and convert it into analog signal for output; FIFO buffer module, built on RAM, has first-in-first-out characteristics and does not require address lines, and can perform efficient data writing and reading operations under clock control; The data transmission module is equipped with a DMA control unit, which has four channels. Each channel independently receives different AXI-Stream data streams and uses a FIFO cache. The ARM core can initialize the DMA control unit and assign different interrupt numbers. The data directly accesses the specified address unit of the DDR memory through the S2MM interface. The DMA adopts the Direct direct transmission mode. The length register bit width of its buffer area Buffer is 23 bits and the address bit width is 32 bits. The s_axi_lite_aclk adopts the 50MHz clock frequency of the ZYNQGP interface, and the m_axi__s2mm interface adopts the 100MHz clock frequency of the ZYNQ HP interface. The reset is a Global low-level reset. The Ethernet module uses ZYNQ as the Client and the PC as the Server. It uses the lwip protocol stack in Xilinx's embedded development environment SDK. It first initializes the Ethernet lwip protocol stack, then completes the initialization of TCP configuration parameters, network address, port number and storage space, and transmits the data of the four channels to the host computer through channel traversal. Before each channel data is transmitted, a TCP connection request is initiated to the PC through the network port connection function tcp_client_connect and a three-way handshake is completed to establish a connection. After the transmission is completed, the Tcp_Flag signal is pulled high.

2. The multifunctional analog instrument test acquisition card based on ZYNQ according to claim 1 is characterized in that: The ZYNQ-7000 series main control chip works on the XC7Z020 core board and manages the clock by calling the matching IP core to ensure that each module operates at the required clock frequency and ensure the clock synchronization of the entire test board system.

3. The multifunctional analog instrument test acquisition card based on ZYNQ according to claim 1 is characterized in that: In the data acquisition module, register configuration is performed through ARM, all the channel data collected are sorted in sequence and stored in FIFO, and then DMA is used to read the data in FIFO and transmit it to the PS end DDR3.

4. The multifunctional analog instrument test acquisition card based on ZYNQ according to claim 1 is characterized in that: The DMA control unit front end is equipped with a pre-written AD9208_Stream IP core for each channel, which is used to convert data into the AXI-Stream stream data format supported by the AXI4 bus.

5. The ZYNQ-based analog instrument circuit test acquisition card according to claim 1, characterized in that: Eight-way DMA requires eight DMA interrupts. Use a Connect IP core to integrate four DMA interrupts into one data, and then connect it to the IRQ_F2P interrupt interface of the ZYNQ core.

6. The ZYNQ-based analog instrument circuit test acquisition card according to claim 1, characterized in that: The multi-channel DMA initializes four cache spaces for storing data frames, with an initial address at 128MB of memory, 4MB of cache space at a time, and a total of 16MB of cache space is initialized.

7. A ZYNQ-based analog instrument circuit test data acquisition method, characterized in that: The following steps are involved: The input data of the analog instrument circuit is collected using a four-way single-channel ADC acquisition circuit, where the ADC chip is AD9280. The chip selects single-ended input or differential input according to actual needs within the operating voltage range, collects data at a maximum conversion rate of 32MSPS, has a data bit width of 8 bits, and has an internal integrated sampling and holding amplifier and power reference source; The collected parallel data is cached and aligned with the help of FIFO module, so that the data bit width is matched and then converted into AXI-Stream stream data; The AXI-Stream data is transmitted to the DDR3 storage on the PS side through the DMA control unit. The four channels of the DMA control unit receive different AXI-Stream data streams respectively. Each channel uses a FIFO for cache. The DMA adopts the Direct transmission mode. After the ARM core initializes the DMA control unit and assigns the interrupt number, the data is transmitted through the S2MM interface according to the preset address unit. The length register width of the buffer area Buffer is 23 bits, and the address width is 32 bits. The DMA's s_axi_lite_aclk adopts the 50MHz clock frequency of the ZYNQ GP interface, and the m_axi__s2mm interface adopts the 100MHz clock frequency of the ZYNQ HP interface. The reset adopts the Global low-level reset.

8. A ZYNQ-based analog instrument circuit test signal output method, characterized in that: The following steps are involved: The host computer generates waveform data and converts it into a COE file in memory format; The host computer sets the signal parameters through Ethernet and sends the COE file data to the ZYNQ-based analog instrument circuit test acquisition card; The signal output module in the acquisition card receives the data and writes it into the waveform data table ROM. The module is composed of DDS, including phase accumulator, phase modulator, waveform data table ROM, and AD9708 digital-to-analog converter; After the data is read from the ROM, the AD9708 digital-to-analog converter converts the digital signal into an analog signal and outputs the signal.

9. A ZYNQ-based analog instrument circuit test data transmission method, characterized in that: The following steps are involved: In the ZYNQ-based analog instrument circuit test acquisition card, the DMA control unit receives the AXI-Stream data stream from the data acquisition module, where each channel front end of the DMA control unit is equipped with an AD9208_Stream IP core to convert the data into the AXI-Stream data format supported by the AXI4 bus; The ARM core initializes the DMA control unit, including assigning different interrupt numbers to each channel and setting the parameters of the DMA engine, which include the address of the channel DMA engine, the memory address of the data to be sent, the length of the data to be sent, and the DMA transfer direction; According to the set parameters, the DMA control unit directly transfers the data of multiple channels to the specified address unit in the DDR memory through the S2MM interface. The interrupts of the eight-way DMA are integrated through the Connect IP core and connected to the IRQ_F2P interrupt interface of the ZYNQ core. During the transmission process, DMA adopts the Direct transmission mode. The length register width of the buffer area Buffer is 23 bits, and the address width is 32 bits. The DMA's s_axi_lite_aclk adopts the 50MHz clock frequency of the ZYNQ GP interface, and the m_axi__s2mm interface adopts the 100MHz clock frequency of the ZYNQ HP interface. The reset adopts the Global low-level reset.

10. A ZYNQ-based analog instrument circuit testing Ethernet communication method, characterized in that: The following steps are involved: In the ZYNQ-based analog instrument circuit test acquisition card, using Xilinx's embedded development environment SDK, select the lwip protocol as the Ethernet protocol stack, and initialize the Ethernet lwip protocol stack; Initialize TCP configuration parameters, network address, port number, and storage space; The data of the four channels in the acquisition card are transmitted to the host computer in sequence through channel traversal. Before the data transmission of each channel, the network port connection function tcp_client_connect is used to enable the ZYNQ end to actively initiate a TCP connection request to the PC host computer as the Server, and complete the three-way handshake of the TCP connection to establish a TCP network connection. After the data transmission of each channel is completed, the Tcp_Flag signal is pulled high.

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